Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a memory cell constituted by a FinFET having a split-gate type MONOS structure, the FinFET having a plurality of source regions formed in a plurality of fins, and the plurality of source regions being commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions being commonly connected by a bit line contact, and the FinFET constitutes a 1-bit memory cell.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-207061, filed on November 15, 2019, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to semiconductor devices, and more particularly to techniques applicable to semiconductor devices including transistors with fin structures. Background Technology

[0004] Flash memory, or EEPROM (Electrically Erasable Programmable Read-Only Memory), has been widely used as non-volatile memory in MCUs (Microcontroller Units). These memory devices have a conductive floating gate electrode surrounded by an oxide film or a trapped dielectric film beneath the gate electrode of a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor), and are configured to use the charge accumulation state in the floating gate or trapped dielectric film as stored information and to read it out as the threshold of the transistor. The trapped dielectric film mentioned here is a dielectric film capable of accumulating charge, and examples include silicon nitride films. By injecting charge into the charge accumulation film and releasing charge from the charge accumulation film to shift the threshold of the MISFET, the MISFET can be used as non-volatile memory. This flash memory is also known as a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) transistor. Furthermore, split-gate memory cells using MONOS transistors as memory transistors and further adding control transistors have been widely used.

[0005] Furthermore, transistors with fin structures are known as field-effect transistors, which can achieve improved operating speed, reduced leakage current and power consumption, and miniaturization of semiconductor devices. A fin-structured transistor (FinFET) is, for example, a semiconductor device configured to have a semiconductor layer protruding on a semiconductor substrate as a channel region and a gate electrode formed across the protruding semiconductor layer.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2006-41354

[0008] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2017-45860

[0009] Patent document 1 discloses a split-gate memory cell with a MONOS transistor.

[0010] Patent document 2 discloses a technique for forming a MONOS transistor as a transistor with a fin structure. Summary of the Invention

[0011] A split-gate memory cell with a MONOS transistor that uses hot carriers to write and erase information is configured to perform reading of stored information as the read current value changes by changing the threshold of the memory transistor by trapping negatively charged electrons or positively charged holes in a charge storage layer (also referred to as a charge accumulation layer), which is formed below the memory gate electrode.

[0012] Because split-gate memory cells use a split-gate structure, in which a transistor with a control gate and a transistor with a memory gate are connected in series, they are called split-gate charge-trapping memory cells.

[0013] When an n-type MOSFET is used in a transistor with a control gate, increasing the amount of holes stored by injecting holes into the charge storage layer and lowering the threshold voltage of the transistor with the memory gate is effective in increasing the read current. Conversely, to bring the transistor into a high threshold state, a large number of electrons are needed to compensate for the large number of holes stored in the charge storage layer. Therefore, to achieve a constant read current while promoting the miniaturization of memory cells, the amount of injected charge per unit channel needs to be increased.

[0014] However, to increase the amount of charge injected during writing and erasing of memory cells, a high electric field is required, but this leads to a degradation of the transistor's rewrite durability and charge storage characteristics, which is of great concern in the operation of memory cells. For example, according to the inventors' research based on the present invention, such as Figure 4A and 4B As shown, when the electric field during rewriting is high (high electric field writing), a greater degradation in rewrite durability and charge storage characteristics is observed compared to the case of a low electric field (low electric field writing). Note that in Figure 4A In the diagram, the number of rewrites and the number of rewrite pulses represent the number of rewrites, with the numbers increasing relatively in the direction indicated by the arrows. Additionally, in... Figure 4B In this context, charge storage time represents the relative increase of time in the direction indicated by the arrow, and threshold change represents the relative change (deterioration) of the threshold in the direction indicated by the arrow.

[0015] When FinFETs are used as transistors for memory cells for the purpose of miniaturizing memory cells, field concentration is likely to occur at the tips or corners of the fins, which are protruding semiconductor layers on a semiconductor substrate, and are locally subjected to extremely high electric fields, since the transistors are configured to have a three-dimensional structure. Therefore, it is foreseeable that the degradation of rewrite endurance and charge storage characteristics will become more severe.

[0016] Other objects and novel features will become clear from the description and accompanying drawings in this specification.

[0017] The following is a brief summary of the typical embodiments disclosed in this application.

[0018] According to one embodiment, a semiconductor device includes a memory cell composed of a FinFET having a split-gate MONOS structure, and a 1-bit memory cell is formed by a FinFET using multiple fins. Furthermore, the trenches formed between the multiple fins of the FinFET constituting the same memory cell are formed to be deeper than the trenches formed between the fins of the FinFET constituting another.

[0019] The information rewrite characteristics of a memory cell composed of a FinFET having a split-gate MONOS structure can be improved by using a semiconductor device according to one embodiment. Attached Figure Description

[0020] Figure 1A This is a schematic planar layout diagram showing the active region and gate region of a MOSFET with a planar structure studied by the inventors of this invention;

[0021] Figure 1B This is a schematic planar layout diagram showing the active region and gate region of the 3D FinFET structure studied by the inventors of this invention;

[0022] Figure 2 This is a cross-sectional view showing the main parts of the split-gate MONOS memory cell studied by the inventors of this invention;

[0023] Figure 3 This is a bias condition diagram illustrating an example of the bias conditions applied during operation of a split-gate MONOS using a FinFET according to one embodiment.

[0024] Figure 4A This is a graph showing the correlation between the number of rewrites and the number of rewrite pulses in high and low electric fields, as studied by the inventors of this invention;

[0025] Figure 4BThis is a graph showing the correlation between charge storage time and threshold change in high and low electric fields, as studied by the inventors of this invention.

[0026] Figure 5 This is a circuit diagram illustrating the configuration of a memory module according to an embodiment;

[0027] Figure 6 This is a planar layout diagram showing a split-gate MONOS using a FinFET according to an embodiment;

[0028] Figure 7 It is shown that... Figure 6 A cross-sectional view of the main part of the unit cell UC corresponding to line AA in the diagram;

[0029] Figure 8 It is shown Figure 7 Cross-sectional view of the main part of the comparative example;

[0030] Figure 9 This is a cross-sectional view showing the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate type MONOS according to an embodiment;

[0031] Figure 10 It shows the next step. Figure 9 Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0032] Figure 11 It shows the next step. Figure 10 Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0033] Figure 12 It shows the next step. Figure 11 Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0034] Figure 13 It shows the next step. Figure 12 Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0035] Figure 14A It shows the next step. Figure 13 Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0036] Figure 14B It is shown that... Figure 14AA cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0037] Figure 15A It shows the next step. Figure 14A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0038] Figure 15B It is shown that... Figure 15A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0039] Figure 16A It shows the next step. Figure 15A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0040] Figure 16B It is shown that... Figure 16A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0041] Figure 17A It shows the next step. Figure 16A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0042] Figure 17B It is shown that... Figure 17A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0043] Figure 18A It shows the next step. Figure 17A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0044] Figure 18B It is shown that... Figure 18A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0045] Figure 19A It shows the next step. Figure 18A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0046] Figure 19B It is shown that... Figure 19A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0047] Figure 20A It means to continue Figure 19ACross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0048] Figure 20B It is shown that... Figure 20A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0049] Figure 21A It shows the next step. Figure 20A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0050] Figure 21B It is shown that... Figure 21A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0051] Figure 22A It means to continue Figure 21A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0052] Figure 22B It is shown that... Figure 22A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0053] Figure 23A It means to continue Figure 22A Cross-sectional views of the main parts of the manufacturing process of a memory cell using a FinFET with a split-gate MONOS;

[0054] Figure 23B It is shown that... Figure 23A A cross-sectional view of the main part corresponding to the single-point chain line CC in the diagram;

[0055] Figure 24 This is a cross-sectional view showing the main parts of a method for manufacturing a first modified semiconductor device according to an embodiment;

[0056] Figure 25 It shows the next step. Figure 24 Cross-sectional views of the main parts in the manufacturing method; and

[0057] Figure 26 This is a plan view showing the structure of a second modified semiconductor device according to an embodiment. Detailed Implementation

[0058] The semiconductor device according to the embodiments will be described in detail with reference to the accompanying drawings. Note that in the specification and drawings, the same components or corresponding components are indicated by the same reference numerals, and repeated descriptions thereof will be omitted. Moreover, embodiments and each modification may be suitably combined at least partially with each other. Furthermore, in some cases, to facilitate reading of the drawings, diagonals indicating that the cross-section is not hollow may be omitted in the cross-sectional view. If the cross-section is hollow, this fact is obviously described in the specification.

[0059] Furthermore, in the accompanying drawings used in the embodiments, shading has been omitted in some cases to facilitate viewing. The symbols "-" and "" are used. + "" indicates the relative concentration of impurities of type n conductivity or type p conductivity. For example, in the case of type n impurities, the impurity concentration is determined according to "n". -- “、”n - “、”n”、”n + "and"n ++ The order of "" becomes higher.

[0060] (First Embodiment)

[0061] Before describing the semiconductor device according to the first embodiment in detail, the advantages of a memory cell composed of a plurality of FinFETs having multiple fins arranged in parallel will be described. For 1 bit of information, by using multiple fins arranged in parallel, the channel width is effectively improved, and the amount of charge injected per unit channel during writing and erasing of the memory cell is reduced, thereby greatly improving the rewrite endurance and charge storage characteristics of the memory cell.

[0062] Figure 1A A schematic planar layout is shown, illustrating the active region AR and gate region GR of a typical planar MOSFET. On the other hand, Figure 1B A schematic planar layout is shown, illustrating the active region FAR and gate region GR2 of a typical FinFET.

[0063] exist Figure 1A In the planar MOSFET shown, the effective channel width corresponds to the channel width W1, which is the width of the semiconductor layer (difference diffusion layer) used as the active region AR. On the other hand, in Figure 1B In the FinFET shown, assuming the fin height is H FN At that time, the effective channel width is determined by the fin height H. FN The value is obtained by adding twice the fin width W2.

[0064] For example, when a cell pitch (fin pitch) PC2, which is half the cell pitch (fin pitch) PC1, is achieved using patterning techniques such as advanced lithography (e.g., dual patterning), the effective cell pitch in a planar MOSFET is half the cell pitch PC1. On the other hand, the effective cell pitch in a FinFET is achieved by adjusting the fin height H. FN The value is obtained by adding four times the fin width W2 to twice the fin width W2.

[0065] Here, when the unit spacing PC2 and the fin height H FN When set to the same value, since the effective channel width is obtained by adding twice the cell pitch PC2 to twice the fin width W2, more than four times the channel width can be ensured compared to the case of planar MOSFETs. Therefore, it can be seen that using FinFETs with multiple fins to configure memory cells is very effective in suppressing the amount of charge injected per unit area into the charge trapping film.

[0066] Furthermore, although described later, the effective channel width can be increased by increasing the effective fin height in the region sandwiched between multiple fins (in other words, reducing the height of the isolation area between the multiple fins). With such a configuration, rewrite endurance and charge storage characteristics can be improved because, in addition to increasing the number of fins, the channel area that can be controlled by the memory gate electrode can also be expanded.

[0067] Next, we will refer to Figure 2 Describe the memory cell structure of a MONOS transistor. The memory cell MC includes a control gate CG used as a word line WL, a memory gate MG used as write and erase electrodes, and an array of elements arranged on one side of the control gate CG and consisting of n... + The drain region DR formed by the diffusion layer and the n-type diffusion layer are arranged on one side of the memory gate MG. + The source region SR is formed by the diffusion layer. The control gate CG controls the p-type channel formation layer CGC below the control gate CG formed on the surface of the p-type substrate PSUB through the field effect via the field dielectric film GI, and the memory gate MG controls the n-type channel MGC below the memory gate MG via the charge trapping film CTF.

[0068] Additionally, a predetermined potential is supplied to each of the drain region DR, source region SR, p-type substrate PSUB, and memory gate MG via bit line BL, source line SL, substrate potential line VSUB, and sub-word line SWL. Normally, the source and drain names are used according to the direction of channel carrier flow; however, due to the asymmetric structure of the split-gate MONOS, for convenience, the source and drain names are used here as electrode names for a specific diffusion layer. Therefore, depending on the operating mode, carriers can flow from the drain electrode to the source electrode.

[0069] In a split-gate MONOS, during writing, electrons are injected into the charge trapping film by a vertical electric field using SSI (source-side injection). During erasure, holes are injected into the charge trapping film by accelerating the holes generated by interband tunneling at the end of the diffusion layer (source) using the horizontal electric field of the MG channel.

[0070] Figure 3 It shows having Figure 2 The diagram illustrates the operating modes of a typical memory cell in a split-gate MONOS structure. In the corresponding operation, the bias conditions at the terminals are... Figure 3 Table A above is represented by symbols such as ground potential GND and power supply voltage Vcc, while... Figure 3 Table B below uses a voltage of 1.5V as an example to illustrate specific voltages (in V) in the device. Because writing uses a source-side injection method, and the hot carrier electrons generated in the channel are injected into the charge trapping film, the channels of the selection transistor and memory transistor enter the on-state and are subjected to a high memory gate voltage VMG.

[0071] On the other hand, since holes are generated by interband tunneling through the electric field between the source line SL and the memory gate MG during erasure, a negative memory gate voltage VMG is applied. The generated holes are accelerated by the electric field to be injected into the charge trapping film, thereby performing erasure. In the read operation, the operation of the non-volatile memory cell is obtained by setting the source line SL to ground potential, setting the bit line BL to power supply voltage, applying the power supply voltage to the control gate CG, selecting the transistor to enter the on state, and reading the charge trapping state of the memory gate MG as the magnitude of the current value. In the first embodiment, an important objective is to reduce the bias VMG(V) of the memory gate MG during write. mgp ).

[0072] Next, we will refer to Figure 5 and Figure 6A detailed description of the semiconductor device according to the first embodiment will be provided. First, typical operation in configuring a non-volatile memory array using a semiconductor device having a split-gate MONOS structure will be described.

[0073] Figure 5 A typical array configuration is shown. Figure 5 An example of a non-volatile memory module is shown, and an equivalent circuit diagram is shown illustrating the connection relationship of four memory cells MC out of a plurality of memory cells MC.

[0074] Each control gate CG is electrically connected to the word line driver circuit WLD for controlling the gate CG, each memory gate MG is electrically connected to the memory gate driver circuit MGD for the memory gate MG, the source region SR is electrically connected to the source line driver circuit SLD for the source line, and the drain region DR is electrically connected to the bit line driver circuit BLD for the bit line. Additionally, a predetermined potential is applied to the semiconductor substrate PSUB via the substrate voltage circuit VSUBGN.

[0075] Figure 6 It shows Figure 5 An example of a planar layout for a memory cell array is shown. Figure 6 It shows the relationship with the Figure 5 The planar layout of the two memory cells surrounded by the dashed line MC is shown.

[0076] In addition, Figure 6 In the diagram, the portion surrounded by the dashed line UC indicates a unit cell UC corresponding to a memory cell, and the unit cell UC includes a first fin FN1 and a second fin FN2 extending in a first direction X in the plan view, a memory gate MG and a control gate CG extending in a second direction Y in the plan view, a source line contact SLC commonly connected to the source regions formed in the first fin FN1 and the second fin FN2, and a bit line contact BLC commonly connected to the drain regions formed in the first fin FN1 and the second fin FN2.

[0077] Figure 7 It shows the relationship with Figure 6 The cross-sectional structure corresponding to the single-point chainline AA in the diagram. For example... Figure 7 As shown, a feature of the semiconductor device according to the first embodiment is that the height of the upper surface of the isolation region STI in the region sandwiched between the two fins FN1 and FN2 is lower than the height of the upper surface of the isolation region STI located outside the fins FN1 and FN2.

[0078] from Figure 7It is evident that the region to be an effective channel consists of two regions, such as the dual-gate control region DGR sandwiched in the middle by the memory gate MG, and the single-gate control region SGR. The single-gate control region SGR is controlled by a portion of the memory gate MG located in the region sandwiched between the two fins FN1 and FN2, thus increasing the effective channel width.

[0079] For example, when the charge trapping membrane (CTF) is composed of a stack of silicon oxide, silicon nitride, and silicon oxide films with a thickness of 20 nm, the upper surface of the isolation region STI between fins FN1 and FN2 should be formed 20 nm lower than the upper surface of the isolation region STI outside fins FN1 and FN2. Compared to the dual-gate control region (DGR), the single-gate control region (SGR) is slightly inferior in terms of the controllability of the memory gate (MG), but since current drive force is preferred over switching operation in charge accumulation memory, it is important to increase the effective channel width.

[0080] For comparison, Figure 8 A comparative example is shown, in which the height of the upper surface of the isolation region STI in the region sandwiched between the two fins FN1 and FN2 is equal to the height of the isolation region STI located outside fins FN1 and FN2.

[0081] exist Figure 8 In the structure shown, in the lower part of fins FN1 and FN2, the two sides of the fins are only sandwiched in the middle by charge trapping films. In other words, since the substrate PSUB constituting the lower part of fins FN1 and FN2 has a region where the memory gate MG cannot be placed, the field effect of the memory gate MG is difficult to act on the channel in this region, and it is difficult to achieve good controllability.

[0082] Note that in the first embodiment, the operation of a memory cell with an NMOS control gate selection transistor has been described using the operation of a memory cell in a split-gate MONOS structure. However, in a memory cell with a PMOS selection transistor, the same effect as described above for NMOS can be obtained by reversing the positive and negative signs of the bias condition.

[0083] Next, we will refer to Figures 9 to 24 A method for manufacturing a semiconductor device according to a first embodiment is described.

[0084] like Figure 9As shown, a silicon oxide film 10, a silicon nitride film 20, and an amorphous carbon layer 30 are sequentially formed on a semiconductor substrate PSUB made of p-type silicon, and the amorphous carbon layer 30 is patterned using a resist pattern via, for example, a selective etching process. Subsequently, a silicon nitride film 40 is formed on the semiconductor substrate PSUB to cover the amorphous carbon layer 30.

[0085] Next, anisotropic etching is performed on the silicon nitride film 40 to form spacers 40 formed from the silicon nitride film, such as... Figure 10 As shown.

[0086] Next, the amorphous carbon layer 30 is removed, and the upper surface of the semiconductor substrate PSUB is selectively etched using spacer 40 as a mask, thereby forming a structure as shown in the image. Figure 11 The image shows multiple fins (FN) made of silicon.

[0087] Next, an insulating film, such as a silicon oxide film, is deposited on the entire surface of the semiconductor substrate PSUB, and the silicon oxide film is etched back using a CMP (chemical mechanical polishing) method, thereby forming an isolation region STI to fill the space between the fins FN, as shown. Figure 12 As shown.

[0088] Next, for example, using a resist pattern as a mask, selective etching is performed on the insulating film IF buried in the space between the fins FN, thereby forming a structure as shown below. Figure 13 The isolation region STI is shown. The isolation region STI includes a first isolation region STIL disposed between the first fin FN1 and the second fin FN2 and having a lower upper surface height, and a second isolation region STIH disposed outside the first fin FN1 and the second fin FN2 and having a higher upper surface height. The upper surface height of the first isolation region STIL is set at a position that, compared to the upper surface height of the second isolation region STIH, is lower than the film thickness tCTF of the charge trapping film CTF (see [reference]). Figure 8 The corresponding thickness.

[0089] For example, when the charge trapping film to be formed later is formed by a stack of silicon oxide, silicon nitride and silicon oxide films and their film thickness is set to 20 nm, selective etching of the insulating film IF is performed such that the upper surface of the first isolation region STIL is 20 nm lower than the upper surface of the second isolation region STIH.

[0090] As mentioned above, by until Figure 13 The processing is completed as an isolation structure used to form the basic structure of FinFET. Note that the description of the manufacturing method after the isolation structure is completed is as follows: Figure 6The manufacturing method for the portion corresponding to the cross-sectional structure of the single-point chain line BB in the shown planar layout continues. Note that, with Figures 14A to 23A The cross section corresponding to each single-point chain CC in the diagram is respectively located at... Figures 14B to 23B As shown in the image.

[0091] like Figure 14A and 14B As shown, fins FN1 and FN2 are formed in Figure 6 It extends in the first direction X.

[0092] Next, after performing a process to remove the native oxide film on the silicon surface on the sidewalls of the fin FN by wet etching, as... Figure 15A and Figure 15B As shown, a gate dielectric film 50 is formed to cover the main surface of the fin FN. A gate material 60 is deposited on the gate dielectric film 50 as a material for forming the control gate CG, and then the upper surface of the gate material 60 is planarized by CMP. For example, a silicon oxide film is used as the gate dielectric film 50, and polysilicon is used as the gate material 60. The gate material 60 can be a stacked structure of polysilicon and metal films such as titanium nitride.

[0093] Next, after patterning the gate material 60 using photolithography and etching techniques, as follows: Figure 16A and Figure 16B As shown, the gate material 60 is processed perpendicularly to the semiconductor substrate PSUB through selective etching to form the control gate CG. At this time, the sides of the fin are fully exposed through over-etching.

[0094] Next, the silicon nitride film (insulating film) 20 and silicon oxide film (insulating film) 10, which serve as the cover layers on the exposed fin FN, are removed using an etching technique to obtain... Figure 17A The structure shown in 17B.

[0095] Next, as Figure 18A and Figure 18B As shown, a charge trapping film (CTF) is formed on the finned fin (FN). The charge trapping film CTF can be formed, for example, by a stacked structure of silicon oxide films, silicon nitride films, and silicon oxide films. Note that as materials for the charge trapping film CTF, a stacked structure of silicon oxide films, hafnium oxide films, aluminum oxide films, hafnium silicate films, and aluminum silicate films can be used.

[0096] Next, a gate material, made of polysilicon, is deposited as the memory gate MG on the entire surface of the semiconductor substrate PSUB, including the control gate CG, using a CVD method. The gate material is then anisotropically etched to form a spacer structure 70 on the sidewalls of the control gate CG. Figure 19A and Figure 19B As shown. In this anisotropic etching, over-etching corresponding to the height of the fin is performed, so that the gate material of the memory gate MG is not left on the side of the fin FN.

[0097] Next, after selectively removing the spacer structure 70 formed between the control gates CG, the charge trapping film is selectively removed, such as... Figure 20A and Figure 20B As shown. The charge trapping film can be selectively removed via wet etching using a spacer structure 70 remaining on one side of the control gate CG as a mask. In this state, using the spacer structure 70 and the control gate CG as a mask for impurity introduction, n-type impurities NI (e.g., arsenic) are selectively ion-implanted into the fin FN, thereby forming n-type impurities in the fin FN. + Type source pole regions SR and n + Type Drain Region DR.

[0098] Next, a silicon oxide film of approximately 500 nm is deposited over the entire surface of the semiconductor substrate PSUB, and the silicon oxide film is polished by CMP to planarize the top of the control gate CG and the memory gate MG, and an interlayer insulating film 80 is formed to fill the area excluding the control gate CG and the memory gate MG, as shown. Figure 21A and 21B As shown.

[0099] Next, a silicon oxide film is formed over the entire surface of the semiconductor substrate PSUB using, for example, a CVD method, thereby forming an interlayer insulating film 90. Subsequently, contact holes are formed in the interlayer insulating films 90 and 80, and bit line contacts (BLCs) and source line contacts (SLCs) made of a metallic material such as tungsten are formed to fill the contact holes. Figure 22A and Figure 22B As shown. Figure 6 As shown, the bit line contact BLC is electrically connected to the drain region DR in each of the two fins (FN1, FN2) arranged at a predetermined interval, thereby forming a common drain. Furthermore, as... Figure 6 As shown, the source line contact SLC is electrically connected to the source region SR formed in each of the two fins (FN1, FN2), thereby forming a common source.

[0100] Next, a silicon oxide film is formed over the entire surface of the semiconductor substrate PSUB using, for example, a CVD method, thereby forming an interlayer insulating film 100. Subsequently, contact holes are formed in the interlayer insulating film 100, and bit lines BL made of a metallic material such as copper are formed to electrically connect the bit lines BL to bit line contacts BLC, such as... Figure 23A and Figure 23B As shown. Through the above series of processes, a product with... Figure 6 The semiconductor device shown is a split-gate MONOS structure.

[0101] (First revision)

[0102] In the first embodiment, the fins formed on the semiconductor substrate PSUB have a uniform height, but fins with substantially different heights (in other words, trenches with different depths) can be formed by using a so-called dual patterning process.

[0103] For example, in Figure 10 Following the process shown, an amorphous carbon layer 30 and spacers 40S are used as a mask to etch the semiconductor substrate PSUB, thereby forming trenches 110 with a predetermined depth, as shown. Figure 24 As shown. For example, when the thickness of the charge trapping film CTF is 20 nm, a 20 nm substrate etching is performed.

[0104] Next, as Figure 25 As shown, after removing the amorphous carbon layer 30, spacers 40S are used as a mask to etch the semiconductor substrate PSUB, thereby alternately forming trenches 120 and 130 of different depths for each fin FN. Since fin structures with substantially different heights can be formed by forming trenches 120 and 130 of different depths, a uniform isolation thickness can be maintained, thereby improving the reliability of the device isolation characteristics.

[0105] The invention described above is based on specific embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0106] (Second revision)

[0107] For example, such as Figure 26 As shown, the bit line BL can be arranged to be shifted by half a cycle relative to the bit line contact BLC. In this case, the charge storage characteristics can be improved because it can be ensured that the fins do not overlap with the bit line BL.

Claims

1. A semiconductor device having a split-gate MONOS structure, the semiconductor device comprising: Semiconductor substrate, having a main surface; The first fin, being a part of the semiconductor substrate, is formed to selectively protrude from the main surface of the semiconductor substrate and extend in a first direction in the plan view; The second fin, being a part of the semiconductor substrate, is formed to selectively protrude from the main surface of the semiconductor substrate and is formed along the first fin at a predetermined interval from the first fin; An isolation region is formed on the main surface of the semiconductor substrate and is formed to have an upper surface at a lower position compared to the positions of the upper surfaces of the first fin and the second fin; A control gate is formed to sandwich each of the first and second fins via a gate dielectric film and to extend in a second direction in the plan view, the second direction intersecting the first direction, the gate dielectric film being formed on the surfaces of the first and second fins; A memory gate is formed to sandwich each of the first and second fins via a charge trapping film and extends adjacent to the control gate in a plan view, the charge trapping film being formed on the surfaces of the first and second fins; The first source region and the second source region are formed in the first fin and the second fin, respectively, and are located on one side of the split gate structure, which is composed of the control gate and the memory gate; as well as The first drain region and the second drain region are formed in the first fin and the second fin, respectively, and are located on the other side of the split gate structure. The first source region and the second source region constitute a common source, which is electrically connected through a source line contact. The first drain region and the second drain region constitute a common drain, which is electrically connected through a bit line contact. The control gate, the memory gate, the common source, and the common drain constitute a 1-bit memory cell. The isolation area comprises a first portion and a second portion. In a plan view, the first portion is arranged between the first fin and the second fin, and the second portion is arranged outside the first fin and the second fin. The upper surface of the first portion is lower than the upper surface of the second portion in the thickness direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, The upper surface of the second portion has almost the same height as the upper surface of the charge trapping film, which is formed on the first portion of the isolation region.

3. The semiconductor device according to claim 2, The charge trapping film is composed of the following stacked films: a first silicon oxide film, a silicon nitride film formed on the first silicon oxide film, and a silicon oxide film formed on the silicon nitride film.

4. A semiconductor device, comprising: The first memory cell is formed in a first region of a semiconductor substrate, has a split-gate MONOS structure, and is composed of a first FinFET; The second memory cell is formed in a second region of the semiconductor substrate that is different from the first region, has a split-gate MONOS structure, and is composed of a second FinFET; Each of the first FinFET and the second FinFET is formed by using a FinFET with multiple fins. The first FinFET has multiple first source regions formed in the plurality of fins, and the plurality of first source regions are connected together by a first source line contact. The second FinFET has multiple second source regions formed in the plurality of fins, and the multiple second source regions are connected together by a second source line contact. The first FinFET and the second FinFET have multiple common drain regions formed in the plurality of fins, and the multiple common drain regions are connected together by bit line contacts. The semiconductor device further includes an isolation region formed between the plurality of fins. The isolation area has a first portion and a second portion. In a plan view, the first portion is arranged between the plurality of fins, and the second portion is arranged outside the plurality of fins. The upper surface of the first portion is lower than the upper surface of the second portion in the thickness direction of the semiconductor substrate.

5. The semiconductor device according to claim 4, The plurality of common drain regions are arranged between the memory gates of each of the first and second FinFETs.

6. A semiconductor device, comprising: Semiconductor substrate, having a main surface; as well as The memory cell, formed on the main surface of the semiconductor substrate, has a split-gate MONOS structure and is composed of FinFETs. The FinFET mentioned above is formed by using a FinFET with multiple fins. The FinFET has multiple source regions formed in the plurality of fins, and the plurality of source regions are connected together by source line contacts. The FinFET has multiple drain regions formed in the plurality of fins, and the plurality of drain regions are connected together by bit line contacts. The FinFETs therein constitute a 1-bit memory cell. The semiconductor device further includes an isolation region formed between the plurality of fins. The isolation area has a first portion and a second portion. In a plan view, the first portion is arranged between the plurality of fins, and the second portion is arranged outside the plurality of fins. The upper surface of the first portion is lower than the upper surface of the second portion in the thickness direction of the semiconductor substrate.

7. The semiconductor device according to claim 6, The number of the plurality of fins is 2.

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