Drive Circuit for Voltage-Controlled Power Semiconductor Device

Abstract

The present invention provides a drive circuit for a voltage-controlled semiconductor element for electric power, so as to suppress the generation of a high surge voltage even when a turn-off signal is input during the period from the detection of an overcurrent to the start of protective cut-off. When the IGBT (10) is turned on upon receiving an L-level control signal Vin, if the overcurrent detection circuit (34) detects an overcurrent and, during the period before the delay time of the soft cut-off delay circuit (35) has elapsed in this overcurrent detection state, an H-level control signal Vin for turning off the IGBT (10) is received, the slow cut-off detection circuit (39) outputs an H-level slow cut-off detection signal. Thereby, by using the normally cut-off NMOS transistor (30) and the slow cut-off NMOS transistor (40) to extract the charge of the gate capacitance when turning off the IGBT (10) more slowly than normal cut-off, the generation of a high surge voltage is suppressed.

Description

Technical Field

[0001] The present invention relates to a drive circuit for a voltage-controlled power semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), and more particularly to a drive circuit having a function of protecting and cutting off if an overcurrent flows through the voltage-controlled power semiconductor device due to a load short circuit or the like. Background Art

[0002] As a device for switching and controlling a load such as a motor, an IPS (Intelligent Power Switch) in which a power semiconductor device for driving the load and its control circuit are integrated is known. In an IPS using an IGBT as a power semiconductor device, the chips of the IGBT and the FWD (Free Wheeling Diode) and a control IC (Integrated Circuit) having drive and protection functions are integrated in one package.

[0003] The control IC conducts control of the IGBT by charging the gate capacitance of the IGBT, and conducts turn-off control of the IGBT by extracting the charge accumulated in the gate capacitance. In the case of conducting turn-off control of the IGBT, if the current flowing suddenly stops, the current has nowhere to go, and sometimes a surge voltage is generated at the collector terminal of the IGBT. Therefore, usually, the extraction of the charge accumulated in the gate capacitance is performed in two stages (for example, refer to Patent Document 1).

[0004] In this Patent Document 1, in the normal operation in which no abnormality occurs in the IGBT, when a turn-off signal for conducting turn-off control of the IGBT is input, two switching elements are made to conduct at different times. Here, the magnitude of the sink current that can flow when extracting charge from the gate capacitance of the IGBT when the two switching elements are conducting (hereinafter, the ability to conduct current according to the on-resistance of the switching element is referred to as "extraction ability") is set to different values. By using switching elements having different extraction abilities and extracting charge at different times, the IGBT is cut off in stages, and thus the generation of a surge voltage is suppressed.

[0005] In Patent Document 1, the collector current flowing through the IGBT is also indirectly monitored, and when the overcurrent state in which the collector current abnormally increases continues for a predetermined time or more, the IGBT is protected and cut off (soft cut-off). In this soft cut-off, the IGBT is gradually cut off by conducting control of a switching element having an extraction ability smaller than that at the time of normal cut-off.

[0006] Prior Art Documents

[0007] Patent document

[0008] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-23899 Summary of the invention

[0009] Technical problem

[0010] In the control IC (gate drive circuit) of Patent Document 1, when an overcurrent state continues for a predetermined time or more, soft cut-off is performed to protect the IGBT. However, depending on the switching cycle of the IGBT, it is possible that a turn-off signal for turning off the IGBT is input during the period when the overcurrent state continues for a predetermined time. In this case, since the IGBT is turned off while an overcurrent is flowing, soft cut-off is not performed and hard cut-off occurs, resulting in a higher surge voltage.

[0011] The present invention has been made in view of this point, and an object thereof is to provide a drive circuit for a voltage-controlled power semiconductor device that does not generate a high surge voltage even when a turn-off signal is input during a period in which an overcurrent detection state continues for a predetermined time.

[0012] Technical solution

[0013] In the present invention, in order to solve the above problems, in one aspect, a driving circuit for a voltage-controlled semiconductor device for power use is provided, which includes: a first switching element that conducts according to the input of a turn-off signal for controlling the turn-off of the voltage-controlled semiconductor device for power use, and extracts the charge accumulated in the gate capacitance from the gate terminal of the voltage-controlled semiconductor device for power use; a first delay circuit that outputs a first delay signal after a first predetermined time has elapsed since the input of the turn-off signal; a second switching element that conducts according to the input of the first delay signal, extracts charge from the gate terminal of the voltage-controlled semiconductor device for power use, and the extraction ability of the second switching element is greater than that of the first switching element; an overcurrent detection circuit that outputs an overcurrent detection signal if an overcurrent of the voltage-controlled semiconductor device for power use is detected; a second delay circuit that outputs a second delay signal after a second predetermined time has elapsed since receiving the overcurrent detection signal; a flip-flop that holds the second delay signal; and a third switching element that conducts according to the input of the second delay signal held by the flip-flop, extracts charge from the gate terminal of the voltage-controlled semiconductor device for power use, and the extraction ability of the third switching element is smaller than that of the first switching element. The driving circuit for the voltage-controlled semiconductor device for power use further includes: a slow turn-off detection circuit that outputs a slow turn-off detection signal if a turn-off signal is received during the period from receiving the overcurrent detection signal to the output of the second delay signal; and a fourth switching element that conducts according to the input of the slow turn-off detection signal, extracts charge from the gate terminal of the voltage-controlled semiconductor device for power use, and has an extraction ability between the extraction ability of the second switching element and the extraction ability of the third switching element.

[0014] Technical effects

[0015] The driving circuit for the voltage-controlled semiconductor device for power use configured as described above has the following advantages, that is, when a turn-off signal for controlling the turn-off of the voltage-controlled semiconductor device for power use is received before soft turn-off is performed after an overcurrent is detected, slow turn-off is performed instead of hard turn-off in normal cut-off, so that surge voltage can be suppressed. Description of the drawings

[0016] Figure 1 is a circuit diagram showing the driving circuit of the IGBT of the first embodiment.

[0017] Figure 2 is a timing diagram showing the operation of the driving circuit during soft turn-off.

[0018] Figure 3 is a timing diagram showing the operation of the driving circuit during slow turn-off.

[0019] Figure 4 is a waveform diagram of the operation of the IGBT during slow turn-off.

[0020] Figure 5 This is a circuit diagram showing the drive circuit of the IGBT in the second embodiment.

[0021] Figure 6 This is a diagram showing a configuration example of the dead time circuit of the input circuit.

[0022] Figure 7 This is a waveform diagram of the operation of the IGBT during slow turn-off.

[0023] Symbol Explanation

[0024] 10: IGBT

[0025] 20, 20a: Drive circuit

[0026] 21: Input circuit

[0027] 21a: Dead time circuit

[0028] 21b: OR circuit

[0029] 21c: First dead time circuit

[0030] 21d: Second dead time circuit

[0031] 21e: Switching circuit

[0032] 22: Reference voltage source

[0033] 23: Operational amplifier

[0034] 24: NMOS transistor

[0035] 25: Resistor

[0036] 26, 27: PMOS transistors

[0037] 28, 29, 30: NMOS transistors

[0038] 31: Delay circuit

[0039] 32: AND circuit

[0040] 33: Current detection resistor

[0041] 34: Overcurrent detection circuit

[0042] 34a: Comparator

[0043] 34b: Reference voltage source

[0044] 35: Delay circuit

[0045] 36: RS flip-flop

[0046] 37: Delay circuit

[0047] 38: NMOS transistor

[0048] 39: Slow turn-off detection circuit

[0049] 39a, 39b, 39c: AND circuit

[0050] 40: NMOS transistor Detailed implementation mode

[0051] Hereinafter, taking the case of an IPS that uses an IGBT as a voltage-controlled power semiconductor element as an example, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same components are denoted by the same reference numerals.

[0052] [First Embodiment]

[0053] Figure 1 is a circuit diagram showing a drive circuit of an IGBT according to the first embodiment, Figure 2 is a timing diagram showing the operation of the drive circuit during soft turn-off, Figure 3 is a timing diagram showing the operation of the drive circuit during slow turn-off, Figure 4 is an operation waveform diagram of the IGBT during slow turn-off.

[0054] Figure 1 shows the IGBT 10 and the drive circuit 20 that drives the IGBT 10. In order to indirectly detect the collector current, a sense IGBT is integrally formed in the IGBT 10. Further, although not shown, an FWD is connected in anti-parallel. The drive circuit 20 is ICized. These IGBT 10, FWD, and drive circuit 20 are housed in one package to form an IPS.

[0055] The drive circuit 20 has an input circuit 21 to which a control signal Vin for turning on or off the IGBT 10 is input. The input circuit 21 has a dead-time circuit 21a that delays the turn-off time by, for example, 300 nanoseconds (ns) when a control signal Vin indicating turn-off is input, and an OR circuit 21b. The OR circuit 21b outputs a signal that prohibits the generation of the gate voltage Vg of the IGBT 10 when it receives a signal for turning off the IGBT 10 from the dead-time circuit 21a at one input terminal, and when soft turn-off is performed while the IGBT 10 is on.

[0056] The drive circuit 20 has a turn-on control circuit for turning on the IGBT 10. The turn-on control circuit includes a transconductance amplifier that generates a constant current, a current mirror circuit that supplies the generated constant current to the gate terminal of the IGBT 10, and a switching element that prohibits the generation of current. The transconductance amplifier has a reference voltage source 22, an operational amplifier 23, an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter referred to as an NMOS transistor) 24, and a resistor 25. The current mirror circuit has P-channel MOSFETs (hereinafter referred to as PMOS transistors) 26, 27. The switching element is constituted by an NMOS transistor 28.

[0057] In the turn-on control circuit, the positive terminal of the reference voltage source 22 that outputs the reference voltage Vref1 is connected to the non-inverting input terminal of the operational amplifier 23, and the negative terminal of the reference voltage source 22 is connected to the ground. The output terminal of the operational amplifier 23 is connected to the gate terminal of the NMOS transistor 24, the source terminal of the NMOS transistor 24 is connected to the inverting input terminal of the operational amplifier 23 and one terminal of the resistor 25, and the other terminal of the resistor 25 is connected to the ground. The drain terminal of the NMOS transistor 24 is connected to the drain terminal and the gate terminal of the PMOS transistor 26 of the current mirror circuit, and the source terminal of the PMOS transistor 26 is connected to the power supply Vcc line. The gate terminal of the PMOS transistor 26 is also connected to the gate terminal of the PMOS transistor 27, and the source terminal of the PMOS transistor 27 is connected to the power supply Vcc line. The drain terminal of the PMOS transistor 27 is connected to the gate terminal of the IGBT 10. The output terminal of the operational amplifier 23 is also connected to the drain terminal of the NMOS transistor 28, the source terminal of the NMOS transistor 28 is connected to the ground, and the gate terminal of the NMOS transistor 28 is connected to the output terminal of the OR circuit 21b of the input circuit 21.

[0058] In this turn-on control circuit, when the NMOS transistor 28 is turned off, a constant current proportional to the reference voltage Vref1 is generated and supplied to the gate terminal of the IGBT 10. That is, the operational amplifier 23 controls the NMOS transistor 24 such that the terminal voltage generated by passing a current through the resistor 25 is equal to the reference voltage Vref1. As a result, a drain current having a value determined by the voltage value of the reference voltage Vref1 and the resistance value of the resistor 25 flows through the NMOS transistor 24. The drain current of the NMOS transistor 24 supplies a current proportional to the drain current of the NMOS transistor 24 as a charging current (source current) to the gate terminal of the IGBT 10 via the current mirror circuit composed of the PMOS transistors 26 and 27. The current supplied to the gate terminal of the IGBT 10 charges the gate capacitance of the IGBT 10, and when the gate voltage Vg at the gate terminal of the IGBT 10 exceeds the turn-on threshold of the IGBT 10, the IGBT 10 turns on.

[0059] The NMOS transistor 28 connected to the output terminal of the operational amplifier 23 receives a signal for prohibiting the generation of the gate voltage Vg of the IGBT 10 from the OR circuit 21b of the input circuit 21 and is turned on. As a result, the NMOS transistor 24 is turned off, and the drain current of the NMOS transistor 24 becomes zero.

[0060] The turn-off control circuit for turning off the IGBT 10 includes NMOS transistors 29 and 30 that function as switching elements, a delay circuit 31 that outputs a delayed signal obtained by delaying an input signal by, for example, 350 ns, and an AND circuit 32. The gate terminal of the NMOS transistor 29 is connected to the output terminal of the dead time circuit 21a of the input circuit 21, the drain terminal of the NMOS transistor 29 is connected to the gate terminal of the IGBT 10, and the source terminal of the NMOS transistor 29 is connected to the ground. The output terminal of the dead time circuit 21a of the input circuit 21 is also connected to the input terminal of the delay circuit 31, the output terminal of the delay circuit 31 is connected to the positive logic input terminal of the AND circuit 32, and the output terminal of the AND circuit 32 is connected to the gate terminal of the NMOS transistor 30. The drain terminal of the NMOS transistor 30 is connected to the gate terminal of the IGBT 10, and the source terminal of the NMOS transistor 30 is connected to the ground.

[0061] In this turn-off control circuit, the charge accumulated in the gate capacitance of the IGBT 10 is extracted through the normally-off NMOS transistors 29 and 30, thereby forcibly reducing the gate voltage to turn off the IGBT 10. Here, as the charge extraction ability of the turn-off control circuit, when the extraction ability when both of the NMOS transistors 29 and 30 are turned on is set to 100%, the extraction ability of the NMOS transistor 29 is set to 10%, and the extraction ability of the NMOS transistor 30 is set to 90%. Therefore, if the turn-off control circuit receives a signal to turn off the IGBT 10 from the input circuit 21, first the NMOS transistor 29 starts to extract charge with an extraction ability of 10%. Then, after a time of 350 ns has elapsed, the NMOS transistor 30 extracts charge with an extraction ability of 90%. It should be noted that the extraction ability is adjusted according to the sizes of the NMOS transistors 29 and 30.

[0062] The drive circuit 20 also has a soft cut-off circuit that detects an overcurrent of the IGBT 10 to protect the IGBT 10. This soft cut-off circuit has a current detection resistor 33, an overcurrent detection circuit 34, a delay circuit 35, an RS flip-flop 36, a delay circuit 37, and an NMOS transistor 38 that functions as a switching element. One terminal of the current detection resistor 33 is connected to the sense emitter terminal of the IGBT that senses the IGBT 10, and the other terminal of the current detection resistor 33 is connected to ground. The overcurrent detection circuit 34 has a comparator 34a and a reference voltage source 34b. The non-inverting input terminal of the comparator 34a is connected to one terminal of the current detection resistor 33, the inverting input terminal of the comparator 34a is connected to the positive terminal of the reference voltage source 34b, and the negative terminal of the reference voltage source 34b is connected to ground. Here, the reference voltage Vref2 of the reference voltage source 34b is set to a voltage equivalent to the voltage detected by the current detection resistor 33 when a current that is 2 to 3 times the rated current flows through the IGBT 10, for example. The output terminal of the comparator 34a is connected to the input terminal of the delay circuit 35, the output terminal of the delay circuit 35 is connected to the set input terminal of the RS flip-flop 36, the output terminal of the RS flip-flop 36 is connected to the gate terminal of the NMOS transistor 38, the input terminal of the delay circuit 37, and the other input terminal of the OR circuit 21b of the input circuit 21. The output terminal of the delay circuit 37 is connected to the reset input terminal of the RS flip-flop 36. The delay time of the delay circuit 35 is set to 3.5 microseconds (μs), for example, and the delay time of the delay circuit 37 is set to 2 milliseconds (ms), for example. The drain terminal of the NMOS transistor 38 is connected to the gate terminal of the IGBT 10, and the source terminal of the NMOS transistor 38 is connected to ground. The extraction ability of this NMOS transistor 38 is set to 5%, which is smaller than the extraction ability of the NMOS transistor 29, which is 10%, for example.

[0063] In this soft cut-off circuit, when the overcurrent detection circuit 34 detects an overcurrent of the IGBT 10 and the overcurrent detection state continues for more than 3.5 μs from the detection time point, the delay circuit 35 sets the RS flip-flop 36, and the RS flip-flop 36 maintains the set state. The set RS flip-flop 36 outputs a signal for turning on the NMOS transistor 38. Through this signal, the delay circuit 37 starts a delay operation and controls the conduction of the NMOS transistor 28 via the OR circuit 21b of the input circuit 21, thereby stopping the generation of the constant current supplied to the gate terminal of the IGBT 10. The soft cut-off NMOS transistor 38 is controlled to conduct, thereby extracting the charge accumulated in the gate capacitance of the IGBT 10 with a 5% extraction ability, and softly cutting off the IGBT 10. After the IGBT 10 is softly cut off, the RS flip-flop 36 is reset after a delay time of 2 ms achieved by the delay circuit 37 has elapsed since the soft cut-off of the IGBT 10 started.

[0064] The drive circuit 20 also has a slow cut-off circuit that slowly cuts off the IGBT 10 when a control signal Vin for turning off the IGBT 10 is input before detecting an overcurrent of the IGBT 10 and softly cutting off the IGBT 10. This slow cut-off circuit has a slow cut-off detection circuit 39 and an NMOS transistor 40 that functions as a switching element. The slow cut-off detection circuit 39 has an AND circuit 39a. The first positive logic input terminal of the AND circuit 39a is connected to the output terminal of the overcurrent detection circuit 34, and the second positive logic input terminal of the AND circuit 39a is connected to the output terminal of the dead time circuit 21a of the input circuit 21. The negative logic input terminal of the AND circuit 39a is connected to the output terminal of the RS flip-flop 36, and the output terminal of the AND circuit 39a is connected to the negative logic input terminal of the AND circuit 32 and the gate terminal of the NMOS transistor 40. The drain terminal of the NMOS transistor 40 is connected to the gate terminal of the IGBT 10, and the source terminal of the NMOS transistor 40 is connected to the ground. The extraction ability of this NMOS transistor 40 is set to, for example, 12.5% which is smaller than the extraction ability of the NMOS transistor 30 (90%) and larger than the extraction ability of the NMOS transistor 38 (5%).

[0065] In this slow turn-off circuit, when the IGBT 10 is conducting, regardless of whether the overcurrent detection circuit 34 detects an overcurrent, the NMOS transistor 40 is turned off, and the AND circuit 32 allows the transmission of the delay signal output by the delay circuit 31. However, if the IGBT 10 is turned off within the period when the overcurrent detection state detected by the overcurrent detection circuit 34 has not continued for 3.5 μs of the delay circuit 35, the conduction control of the NMOS transistor 30 with a large extraction ability is prohibited, and the conduction control of the slow turn-off NMOS transistor 40 is performed. Thus, the charge accumulated in the gate capacitance of the IGBT 10 is extracted by the NMOS transistor 29 and the NMOS transistor 40 with an extraction ability of 22.5% (10% + 12.5%). At this time, after a time of 350 ns has elapsed since the NMOS transistor 29 was turned on, a delay signal is output from the delay circuit 31, but since this delay signal is blocked by the AND circuit 32, the NMOS transistor 30 is not turned on.

[0066] Next, the operation of the drive circuit 20 during normal conduction operation will be described. When the overcurrent detection circuit 34 does not detect an overcurrent, the overcurrent detection circuit 34 outputs a signal of low (L) level. Therefore, since the delay circuit 35 does not operate, soft turn-off does not occur either. In addition, since the slow turn-off detection circuit 39 also has an L-level signal input to the first positive logic input terminal of the AND circuit 39a from the overcurrent detection circuit 34, it outputs an L-level signal, and slow turn-off does not occur either.

[0067] Next, with reference to Figure 2 and Figure 3 the timing diagrams, the soft turn-off when the load of the IGBT 10 is short-circuited, for example, and this short circuit continues for more than 3.5 μs and the slow turn-off when this short circuit does not exceed 3.5 μs and the IGBT 10 is turned off will be described. In these Figure 2 and Figure 3 from the top, the control signal Vin, the gate voltages Vg(A), Vg(B) of the NMOS transistors 29, 30, the output of the overcurrent detection circuit 34, the gate voltages Vg(C), Vg(D) of the NMOS transistors 38, 40, the gate voltage Vg of the IGBT 10, and the collector current Ic are shown.

[0068] First, in Figure 2When the soft cut-off as shown is performed, if a control signal Vin of L level is input to the input circuit 21 to turn on the IGBT 10, the overcurrent detection circuit 34 detects an overcurrent and outputs an overcurrent detection signal of high (H) level. During the conduction control of the IGBT 10, since the output signal of the input circuit 21 is at L level, the gate voltages Vg(A) and Vg(B) of the NMOS transistors 29 and 30 that are normally cut off are at L level and are turned off. During the initial period of the conduction control of the IGBT 10, since the output signal of the delay circuit 35 is at L level and the RS flip-flop 36 is in the reset state, the gate voltage Vg(C) of the soft cut-off NMOS transistor 38 is at L level and is turned off. After a delay time of 3.5 μs has elapsed since the overcurrent was detected, the output signal of the delay circuit 35 becomes H level, setting the RS flip-flop 36 to the set state, so that the gate voltage Vg(C) becomes H level and the NMOS transistor 38 is turned on. At this time, the H level of the gate voltage Vg(C) is continuously held by the RS flip-flop 36 until a delay time of 2 ms achieved by the delay circuit 37 has elapsed. The slow cut-off NMOS transistor 40 is turned off because its gate voltage Vg(D) is at L level. This is because during the conduction control of the IGBT 10 in the AND circuit 39a, an output signal of L level of the input circuit 21 is input to the second positive logic input terminal and an L-level signal is output at the output terminal, and this L-level signal becomes the gate voltage Vg(D).

[0069] Since the NMOS transistors 29, 30, 38, and 40 are turned off during the initial period of the conduction control of the IGBT 10, the gate voltage Vg of the IGBT 10 has a value of H level. Since the detected current exceeds the value of the current corresponding to the reference voltage Vref2, the collector current Ic of the IGBT 10 is in an overcurrent state. It should be noted that even if the gate voltage Vg of the IGBT 10 is constant, the collector current Ic of the IGBT 10 will continue to rise until saturation while being limited by the external inductance component.

[0070] Here, if the soft cut-off NMOS transistor 38 is turned on after a delay time of 3.5 μs achieved by the delay circuit 35 has elapsed, the NMOS transistor 28 of the conduction control circuit is turned on, and the generation of the constant current by the conduction control circuit is stopped. As a result, since the conduction control circuit is stopped and soft cut-off starts, the gate voltage Vg and the collector current Ic of the IGBT 10 will gradually decrease.

[0071] If the detected current of the collector current Ic is lower than the current corresponding to the reference voltage Vref2, the overcurrent detection circuit 34 outputs a signal of L level, but the gate voltage Vg(C) is held at H level by the RS flip-flop 36.

[0072] Thereafter, if it is desired to turn off the IGBT 10 and a control signal Vin of H level is input to the input circuit 21, after passing through a dead time of 300 ns implemented by the dead time circuit 21a, the output signal of the input circuit 21 becomes H level. Thus, the turn-off control circuit attempts to perform a turn-off control of normal cut-off, but since soft cut-off has already started at this time, the reduction of the gate voltage Vg and the collector current Ic of the IGBT 10 continues.

[0073] If the soft cut-off continues and the gate voltage Vg of the IGBT 10 decreases and becomes lower than the conduction threshold voltage of the IGBT 10, the collector current Ic becomes 0. It should be noted that since the RS flip-flop 36 is set to the reset state after a delay time of 2 ms implemented by the delay circuit 37 from being set, the gate voltage Vg(C) of the NMOS transistor 38 for soft cut-off becomes a signal of L level. During the period until the gate voltage Vg(C) becomes L level, the conduction control of the NMOS transistor 28 of the conduction control circuit and the NMOS transistor 38 for soft cut-off continues. Therefore, even if a control signal Vin for turning on or off the IGBT 10 is input to the input circuit 21, the IGBT 10 remains off.

[0074] Next, refer to Figure 3 Describe the operation of slow cut-off. Slow cut-off is the operation when the IGBT 10 is turned on while the load of the IGBT 10 is in a short-circuit state, for example, and the IGBT 10 is turned off before the soft cut-off operation. This slow cut-off has the characteristic of reducing the gate voltage Vg of the IGBT 10 more slowly than normal cut-off without performing cut-off through normal cut-off when turning off the IGBT 10.

[0075] First, if the control signal Vin of L level is input to turn on the IGBT 10 and the overcurrent detection circuit 34 detects an overcurrent, the overcurrent detection circuit 34 outputs an overcurrent detection signal of H level. During the period when the IGBT 10 is on, the output signal of the input circuit 21 is of L level. Therefore, the gate voltages Vg(A) and Vg(B) of the NMOS transistors 29 and 30 that are normally cut off are of L level and are turned off. The NMOS transistor 38 for soft cut-off does not have its gate voltage Vg(C) turn to H level during the slow cut-off operation, so it remains under turn-off control. In addition, the AND circuit 39a of the slow cut-off detection circuit 39 receives the output signal of L level of the input circuit 21 at the second positive logic input terminal and outputs an output signal of L level. Therefore, the NMOS transistor 40 for slow cut-off is also under turn-off control.

[0076] Here, if within the 3.5 μs delay time achieved by the delay circuit 35, the control signal Vin turns to H level to switch to the turn-off control of the IGBT 10, then after a dead time of 300 ns, the output signal of the input circuit 21 turns to H level. Thereby, the gate voltage Vg(A) of the normally cut-off NMOS transistor 29 turns to H level and is under turn-on control. At the same time, the AND circuit 39a of the slow cut-off detection circuit 39 receives the output signal of H level of the input circuit 21 at the second positive logic input terminal. At this time, the overcurrent detection circuit 34 outputs an overcurrent detection signal of H level, and the RS flip-flop 36 outputs a signal of L level. Therefore, the AND circuit 39a outputs a slow cut-off detection signal of H level. Therefore, the NMOS transistor 40 for slow cut-off is under turn-on control because its gate voltage Vg(D) turns to H level. At this time, since a signal of H level is received at the negative logic input terminal of the AND circuit 32, the delay signal of the delay circuit 31 is prohibited from being transmitted to the gate terminal of the normally cut-off NMOS transistor 30, and the NMOS transistor 30 is not under turn-on control.

[0077] If the NMOS transistor 28 of the turn-on control circuit is under turn-on control due to the H level of the output signal of the input circuit 21 to stop the operation of the turn-on control circuit, and the normally cut-off NMOS transistor 29 and the slow cut-off NMOS transistor 40 are under turn-on control, then the gate voltage Vg and the collector current Ic of the IGBT 10 start to decrease.

[0078] Thereafter, if the overcurrent detection circuit 34 becomes unable to detect an overcurrent, the overcurrent detection circuit 34 outputs an L level. Since the output signal of the overcurrent detection circuit 34 becomes the L level, the slow turn-off detection circuit 39 outputs a slow turn-off detection signal of the L level. As a result, the slow turn-off NMOS transistor 40 is turned off, and the circuit 32 allows the transmission of the delay signal of the delay circuit 31. Therefore, the normally turn-off NMOS transistor 30 is turned on. At this time, since the normally turn-off NMOS transistors 29 and 30 extract the charge of the gate capacitance with the maximum extraction ability, the gate voltage Vg and the collector current Ic of the IGBT 10 rapidly decrease.

[0079] Next, the operation of the IGBT 10 during slow turn-off will be described in detail with reference to Figure 4 the operation waveform diagram. In this Figure 4 figure, the control signal Vin, the gate voltage Vg of the IGBT 10, the collector current Ic of the IGBT 10, and the collector-emitter voltage Vce of the IGBT 10 are shown from the top. In addition, in the operation waveforms of the gate voltage Vg, the collector current Ic, and the collector-emitter voltage Vce of the IGBT 10, the dotted line indicates the turn-off operation without the slow turn-off function, and the solid line indicates the turn-off operation during slow turn-off.

[0080] When the control signal Vin changes from the L level that turns on the IGBT 10 to the H level that turns off the IGBT 10, first, if the voltage of the control signal Vin exceeds the turn-off threshold voltage Vinth(off) of the input circuit 21, the dead time circuit 21a is started. After the time of the dead time tdoff (= 300 ns) set by the dead time circuit 21a has elapsed, the normally turn-off NMOS transistor 29 and the slow turn-off NMOS transistor 40 are turned on. As a result, the gate voltage Vg of the IGBT 10 decreases.

[0081] Since a charging current flows from the collector to the gate capacitance via the parasitic Miller capacitance during the decrease of the gate voltage Vg, it enters the Miller region where the voltage value does not change temporarily. At the same time, the collector current Ic decreases, and the collector-emitter voltage Vce increases. If the gate voltage Vg passes through the Miller region, it decreases again.

[0082] According to the drive circuit 20, if the control signal Vin is switched from the conduction signal for turning on the IGBT 10 to the turn-off signal for turning off the IGBT 10 within 3.5 μs from the detection of an overcurrent by the overcurrent detection circuit 34, the turn-off time of the IGBT 10 becomes longer. The turn-off time refers to the time from when the voltage of the control signal Vin exceeds the turn-off threshold voltage Vinth(off) until the collector current Ic decreases to 10%. Here, in the case without the slow turn-off function, if the IGBT 10 is turned off in a state where an overcurrent is flowing, the gate capacitance is discharged with a 100% extraction ability. In contrast, in the case with the slow turn-off function, the gate capacitance is discharged with a 22.5% extraction ability. Therefore, since the slope when the gate voltage Vg decreases becomes gentler compared to the case without the slow turn-off function, correspondingly, in terms of the turn-off time, the turn-off time toff2 in the case with the slow turn-off function becomes longer than the turn-off time toff1 in the case without the slow turn-off function. If the slope of the decrease in the gate voltage Vg becomes gentler, in the illustrated example, the surge voltage of the collector-emitter voltage Vce decreases from 680 volts (V) to 650 V. In addition, since the surge voltage decreases by 30 V, the IGBT 10 is not only less likely to be damaged by the surge voltage, but also a protection circuit for surge countermeasures can be eliminated or reduced.

[0083] [Second Embodiment]

[0084] Figure 5 is a circuit diagram showing the drive circuit of the IGBT of the second embodiment, Figure 6 is a diagram showing a configuration example of the dead time circuit of the input circuit, Figure 7 is an operation waveform diagram of the IGBT during slow turn-off. It should be noted that in Figure 5 , for components that are the same as or equivalent to the components Figure 1 shown, the same reference numerals are used and their detailed descriptions are omitted. In addition, in the operation waveforms of Figure 7 , the one-dot chain line indicates the case where slow turn-off is performed in a state where the dead time is not switched, and the solid line indicates the case where slow turn-off is performed in a state where the dead time is switched.

[0085] The drive circuit 20a of the IGBT 10 in the second embodiment changes the configurations of the input circuit 21 and the slow turn-off detection circuit 39 compared to the drive circuit 20 of the IGBT 10 in the first embodiment.

[0086] As shown in Figure 6As shown, the dead time circuit 21a of the input circuit 21 includes a first dead time circuit 21c, a second dead time circuit 21d, and a switching circuit 21e. The input terminals of the first dead time circuit 21c and the second dead time circuit 21d are connected to the input terminal of the input circuit 21 that receives the control signal Vin. The output terminal of the first dead time circuit 21c is connected to the normally closed terminal of the switching circuit 21e, and the output terminal of the second dead time circuit 21d is connected to the normally open terminal of the switching circuit 21e. The common terminal of the switching circuit 21e is connected to the output terminal of the input circuit 21 and the first input terminal of the OR circuit 21b, and the control terminal of the switching circuit 21e is connected to the output terminal of the AND circuit 39b of the slow turn-off detection circuit 39.

[0087] The first dead time circuit 21c sets the same dead time tdoff (= 300 ns) as the dead time circuit 21a of the first embodiment, and the second dead time circuit 21d sets a dead time tdoff1 shorter than that of the first dead time circuit 21c. The dead time tdoff1 of the second dead time circuit 21d is preferably set to a value obtained by subtracting the time difference between the turn-off time toff1 and the turn-off time toff2 in Figure 4 from the dead time tdoff. In this embodiment, the dead time tdoff1 is set to 200 ns.

[0088] When the slow turn-off NMOS transistor 40 is under turn-off control and the overcurrent detection circuit 34 does not detect an overcurrent, the switching circuit 21e selects the output of the first dead time circuit 21c. In addition, when the slow turn-off NMOS transistor 40 is under turn-off control and the overcurrent detection circuit 34 detects an overcurrent, the switching circuit 21e selects the output of the second dead time circuit 21d.

[0089] The slow turn-off detection circuit 39 has AND circuits 39b and 39c. The positive logic input terminal of the AND circuit 39b is connected to the output terminal of the overcurrent detection circuit 34, and the negative logic input terminal of the AND circuit 39b is connected to the output terminal of the RS flip-flop 36. The output terminal of the AND circuit 39b is connected to one input terminal of the AND circuit 39c and the control terminal of the dead time circuit 21a of the input circuit 21. The other input terminal of the AND circuit 39c is connected to the output terminal of the input circuit 21. The output terminal of the AND circuit 39c is connected to the negative logic input terminal of the AND circuit 32, the other input terminal of the OR circuit 21b of the input circuit 21, and the gate terminal of the slow turn-off NMOS transistor 40.

[0090] When the period during which an overcurrent is detected by the overcurrent detection circuit 34 is less than 3.5 μs, the slow turn-off detection circuit 39 instructs the dead time circuit 21a to select the second dead time circuit 21d. Further, when the period during which an overcurrent is detected by the overcurrent detection circuit 34 is less than 3.5 μs, if a control signal Vin of H level for turning off the IGBT 10 is input, the slow turn-off detection circuit 39 outputs a slow turn-off detection signal. Thereby, the generation of a constant current by the conduction control circuit is prohibited, and slow turn-off by the NMOS transistor 40 is started. At this time, the AND circuit 32 prohibits the transmission of the delay signal of the delay circuit 31 so that the NMOS transistor 30 with the highest extraction ability is not subjected to conduction control.

[0091] According to the drive circuit 20a of the second embodiment, the time from the turn-off time toff1 to the turn-off time toff2 in the slow turn-off in the first embodiment can be restored to the turn-off time toff1, and the characteristics can be the same as those without the slow turn-off function.

[0092] In the drive circuit 20a, if an L-level control signal Vin for turning on the IGBT 10 is received and the overcurrent detection circuit 34 detects an overcurrent, the switching circuit 21e selects the second dead time circuit 21d. In this state, if the control signal Vin changes to an H-level signal for turning off the IGBT 10, then as Figure 7 shown, slow turn-off starts after a dead time of 200 ns. The subsequent slow turn-off operation is the same as the slow turn-off operation of the first embodiment indicated by the one-dot chain line in Figure 7 , but the turn-off time is shortened from the turn-off time toff2 to the turn-off time toff1.

[0093] As described above, in the drive circuit 20a, if the slow turn-off detection circuit 39 operates during the turn-off of the IGBT 10, the decrease in the gate voltage Vg of the IGBT 10 becomes slower than in normal turn-off, but correspondingly, the dead time is shortened from 300 ns to 200 ns. Thereby, the turn-off time can be made to coincide with the turn-off time toff1 (for example, 1.2 μs) of a drive circuit without a slow turn-off function. Since the turn-off time does not change during normal turn-off and when slow turn-off is detected, the switching loss of the IGBT 10 when slow turn-off is detected can be made to be the same level as during normal turn-off.

[0094] In the above embodiments, the case where an IGBT is used as the voltage-controlled power semiconductor element of the IPS has been described, but it is not limited to an IGBT, and a MOSFET can also be applied in the same manner.

Claims

1. A driving circuit for a voltage-controlled semiconductor element for power applications, characterized in that, Comprising: A first switching element that conducts in response to the input of a turn-off signal for turn-off control of a voltage-controlled power semiconductor element, and extracts the charge accumulated in the gate capacitance from the gate terminal of the voltage-controlled power semiconductor element; A first delay circuit that outputs a first delay signal after a first predetermined time has elapsed since the input of the turn-off signal; A second switching element that conducts in response to the input of the first delay signal, extracts the charge from the gate terminal of the voltage-controlled power semiconductor element, and has a greater charge extraction ability than the first switching element; An overcurrent detection circuit that outputs an overcurrent detection signal if an overcurrent in the voltage-controlled power semiconductor element is detected; A second delay circuit that outputs a second delay signal after a second predetermined time has elapsed since the receipt of the overcurrent detection signal; A flip-flop that holds the second delay signal; A third switching element that conducts in response to the input of the second delay signal held by the flip-flop, extracts the charge from the gate terminal of the voltage-controlled power semiconductor element, and has a smaller charge extraction ability than the first switching element; A slow turn-off detection circuit that outputs a slow turn-off detection signal if the turn-off signal is received during the period from the receipt of the overcurrent detection signal to the output of the second delay signal; And A fourth switching element that conducts in response to the input of the slow turn-off detection signal, extracts the charge from the gate terminal of the voltage-controlled power semiconductor element, and has a charge extraction ability between that of the second switching element and that of the third switching element.

2. The driving circuit for a voltage-controlled semiconductor element for power applications according to claim 1, characterized in that, When the slow turn-off detection circuit outputs the slow turn-off detection signal, the first delay signal is not transmitted to the second switching element.

3. The driving circuit for a voltage-controlled semiconductor element for power applications according to claim 1, characterized in that, Receives the second delay signal and stops generating a turn-on signal for turn-on control of the voltage-controlled power semiconductor element.

4. The driving circuit for a voltage-controlled semiconductor element for power applications according to claim 1, characterized in that, The drive circuit for the voltage-controlled power semiconductor element comprises: A first dead time circuit and a second dead time circuit that delay the turn-off signal; and A switching circuit that selects the output of the first dead time circuit when the overcurrent detection signal is not received, and selects the output of the second dead time circuit during the period from the receipt of the overcurrent detection signal to the output of the second delay signal by the second delay circuit, and the second dead time circuit is set with a shorter dead time than the first dead time circuit.

5. The driving circuit for a voltage-controlled semiconductor element for power applications according to claim 4, characterized in that, The time difference between the dead times set by the first dead time circuit and the second dead time circuit is the same as the time difference between the turn-off time when the first switching element and the second switching element perform charge extraction during turn-off control of the voltage-controlled power semiconductor element and the turn-off time when the first switching element and the fourth switching element perform charge extraction based on the slow turn-off detection signal.

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