In-package sequencer for performing error correction and memory test operations

Abstract

A processing device of a sequencer component may receive data from a controller external to the sequencer component. The processing device of the sequencer component may perform an error correction operation on the data received from the controller external to the sequencer component to generate a codeword associated with the data. The codeword may be stored at a memory component coupled to the sequencer component.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to memory subsystems including an in-package sequencer for performing error correction and memory testing operations. Background Art

[0002] The memory subsystem may be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] One aspect of the present disclosure relates to a method of performing error correction, the method comprising: receiving, by a processing device of a sequencer component, data from a controller external to the sequencer component, wherein the sequencer component and a memory component reside in a package separate from the controller; performing, by the processing device of the sequencer component, an error correction operation on the data received from the controller external to the sequencer component to generate a codeword associated with the data; and storing the codeword at the memory component coupled to the sequencer component.

[0004] Another aspect of the present disclosure relates to a memory system, comprising: a memory component; and a processing device of a sequencer component, the processing device of the sequencer component being operably coupled to the memory component to: receive data from a controller external to the sequencer component, wherein the sequencer component and the memory component reside in a package separate from the controller; perform an error correction operation on the data received from the controller external to the sequencer component to generate a codeword associated with the data; and store the codeword at the memory component to which the processing device of the sequencer component is operably coupled.

[0005] Another aspect of the present disclosure relates to a method for performing error correction, the method comprising: generating, by a processing device of a sequencer component, a test pattern to perform a test of a memory component, wherein the test pattern corresponds to a plurality of operations of writing data to the memory component, and wherein the sequencer component resides in a package separate from a controller; executing the test pattern to write the data to the memory component; retrieving the data from the memory component; comparing the retrieved data with the data of the test pattern written to the memory component; and determining whether the test of the memory component is successfully completed based on the comparison of the retrieved data with the data of the test pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be more fully understood through the detailed description given below and through the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An exemplary computing environment including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 is a flowchart of an exemplary method for performing encoding error correction operations on data according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of an exemplary method for performing a decoding error correction operation on data according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an exemplary method for performing testing of a memory component according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an exemplary computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to a memory subsystem including an in-package sequencer component for performing error correction and memory test operations. The memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), etc. In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Typically, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem, and can request to retrieve data from the memory subsystem.

[0013] The memory subsystem may include a plurality of memory components capable of storing data from a host system. Each memory component may include different types of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory and flash-based memory, such as single-level cell (SLC) memory, triple-level cell (TLC) memory, and quad-level cell (QLC) memory. Characteristics of different types of media may vary depending on the type of media. An example of a characteristic associated with a memory component is data density. Data density corresponds to the amount of data (e.g., data bits) that can be stored in each memory cell of a memory component. Another example of a characteristic of a memory component is access speed, which corresponds to the amount of time a memory component can access data stored at the memory component.

[0014] The memory subsystem may also include a controller operably coupled to the memory component. The controller may serve as a "bridge" between the host system and the memory component of the memory subsystem for data transmission and / or management. In some cases, the controller and the associated memory component may be manufactured by different suppliers, and each of the controller and / or the memory component may have a corresponding package. In order to increase the capacity of the memory subsystem, a memory component may be added to the memory subsystem, and the controller may interface with multiple memory components. In conventional systems, when a parallel interface is used between the controller and the memory component, the controller may include a large number of pins to interface with the memory component. Including a large number of pins may increase the package size of the controller, which in turn may increase the form factor of the conventional system.

[0015] In some conventional systems, the controller uses a serializer / deserializer (SerDes) connection (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Universal Flash Memory (UFS), etc.) to interface with the host system to minimize the number of pins. Conventional controllers may include a sequencer component that interfaces with and instructs the memory component using protocols and timing requirements (e.g., read / write latency, etc.) specific to the memory type of the memory component. The controller may interface with the memory component via a parallel interface, utilizing a double data rate (DDR) to obtain a certain bandwidth and capacity. Increasing the number of memory components that interface directly with the controller takes up more space and creates difficulties in routing parallel interfaces. As a result, the routing path (e.g., trace) between the controller and the memory component may be long, thereby compromising signal integrity. Further, using a longer routing path to the memory component via a parallel interface results in a greater load, thereby consuming an undesirable amount of power.

[0016] Additionally, to improve the reliability of data stored in the memory subsystem, some conventional controllers may perform error correction operations. Error correction operations may refer to any suitable technique for correcting one or more errors in data, such as error correction codes, redundancy operations, and the like.

[0017] The error correction operation uses parameters specific to the memory type of the memory component coupled to the traditional controller. For example, the parameters can be used to configure the size of the codeword based on the type of memory component. When a new generation of memory components is added to the memory subsystem to expand the capacity of the memory subsystem, the firmware of the controller is typically updated with new parameters for the memory type of the new generation of memory components. The controller may be shut down for the update, resulting in a processing downtime. When the controller is updated, the memory system may experience throughput issues because the controller is not performing error correction operations. In addition, when attempting to decode the codeword, the controller may read and reread data from the memory component storing the codeword. The data may be sent over a parallel interface between the controller and the memory component, which may use an undesirable amount of power and / or affect data integrity due to the length of the trace.

[0018] Further, conventionally, when testing a memory component, the memory component may be coupled to a test board that performs one or more tests on the memory component. The memory components of each memory type may have different test requirements. Therefore, there may be different test boards dedicated to testing a specific type of memory component. The cost of using a dedicated test board to test the memory component may be very high. Further, for some newer memory components, there may not be a test board developed to test the newer memory components.

[0019] Aspects of the present disclosure address the above and other deficiencies by separating a sequencer component from a controller and including a sequencer component with one or more memory components in a single package. The sequencer component can perform error correction operations and / or memory test operations. The sequencer component can be manufactured in independent silicon, the memory component can be manufactured in an independent die, and the independent silicon and the independent die can be included in the same package. The package can refer to a housing that supports electrical contacts, which connect the package to an application board and prevent physical damage and corrosion. The application board can refer to a printed circuit board where the controller, package and / or memory component are located. Each sequencer component operates with a memory component of a certain type (e.g., a crosspoint array, NAND flash memory, etc.) and can operate with multiple memory components having the type of memory. The sequencer component can interface with the memory component via a protocol specific to the memory type. Each package can include multiple sequencer components that interface with memory components of different types. Further, the memory subsystem can include multiple packages, each package including one or more sequencer components that interface with one or more memory components.

[0020] The sequencer component can interface with the controller via a SerDes connection, which provides higher bandwidth than a parallel interface. Further, a SerDes connection uses fewer pins than a parallel connection. Thus, using the disclosed techniques, the pin count in the controller can be reduced while still accommodating the same number or more memory components included in a package coupled to the controller. Reducing the pin count of the controller can result in a reduced form factor for a memory subsystem that includes the same capacity (e.g., the same number of memory components) as a previous conventional system that includes more pins.

[0021] Further, signal integrity can be improved because the distance between the sequencer component and the memory component within the separate package is shorter than the distance between the sequencer component and the memory component in a conventional system where the sequencer component is located within the controller. That is, the package is smaller than the application board, and therefore, the traces between the sequencer component and the memory component within the package are shorter than in a conventional system where the traces extend over the application board. The shorter traces can improve signal integrity, as well as reduce package loading and consume less power than conventional systems with longer routing paths.

[0022] In some embodiments, the sequencer component can perform error correction operations. For example, the sequencer component may include a processing device that performs an error correction engine. The error correction engine may include an encoder and a decoder that perform encoding error correction operations and decoding error correction operations, respectively. The error correction engine may be programmed to perform error correction operations based on the memory type of the memory component to which the sequencer component is attached. Performing at least some error correction operations at the sequencer component can reduce the complexity at the controller because the controller does not have to manage all the different error correction code parameters associated with the memory components of different memory types in the memory subsystem. Further, by reducing the data flow on the connection between the controller and the sequencer component, power consumption can be reduced and the integrity of the data signal can be improved because the sequencer component can perform error correction operations locally in the package and send the decoded data to the controller. That is, in some embodiments, the sequencer component that performs at least some error correction operations can reduce the data flow sent by the connection between the controller and the sequencer component.

[0023] In some embodiments, the sequencer component may iteratively perform an error correction operation until an error in the data read from one or more memory components is corrected. For example, a first error correction operation may be performed to correct at least one error in the data, and another error correction operation may be performed on the modified data to correct another error. Such embodiments may enhance the performance of the memory subsystem, because the shorter traces in the package are used during error correction compared to the longer traces between the memory component and the controller in the conventional memory system, and multiple data transmissions between the memory component and the sequencer component are faster. In addition, in some embodiments, the sequencer component may perform one or more error correction operations of the first level, which corrects one or more errors included in the data read from the one or more memory components, and the controller may perform one or more error correction operations of the second level to correct additional (e.g., remaining) errors included in the data. Such embodiments may also enhance performance by correcting most errors at the sequencer component, thereby reducing the number of times sent back and forth between the controller and the memory component in the conventional memory system.

[0024] In some embodiments, the sequencer component can send a notification to the controller, and the notification indicates that the sequencer component includes an error correction function. This notification can cause the controller to send the original data received from the host to the sequencer component without performing an encoding error correction operation on the original data. In such cases, the sequencer component can receive the original data and encode the original data to generate a code word based on the memory type of the memory component in the package. In addition, if the sequencer component indicates that the sequencer component does not have an error correction function or does not provide a notification indicating that the sequencer component includes an error correction function, the controller can perform an error correction operation on any data associated with the memory component coupled to the sequencer component. In another example, the controller can query the sequencer component to determine whether the sequencer has an error correction function. If not, the controller can perform an error correction operation on any data associated with the memory component coupled to the sequencer component.

[0025] In addition, in some embodiments, the sequencer component may also include a memory test engine to perform one or more tests on the memory component coupled to the sequencer component. Including a memory test engine and performing memory tests in the sequencer component can reduce the cost associated with testing the memory component. Further, the memory test engine can be updated to perform tests specific to the type of memory component coupled to the sequencer component, so that new memory component types that lack test boards can be tested. The memory test engine may include a test pattern generator and a comparator. The test pattern generator may generate a test pattern corresponding to an operation of reading and / or writing data to one or more memory components. The test pattern generator may generate data to be written to one or more memory components. The test pattern may simulate certain operating conditions, such as performing multiple writes to determine whether the memory component can work properly at a certain temperature. Further, the test pattern may emphasize the test timing requirements for sending signals from the sequencer component to the memory component through the interface between the sequencer component and the memory component. Tests may be performed using different voltages to determine whether the memory component correctly writes and / or reads data at different voltages. Further, the memory test engine can program memory parameters, such as read voltage levels, to improve the quality of read data during testing.

[0026] The test pattern may be based on the memory type of one or more memory components. For example, there may be known interface problems on different memory types, so the test pattern may include certain read and / or write patterns to screen out defects in a specific memory type. The test pattern generator may be programmed by a test engineer. In some embodiments, the test pattern may already be stored in a memory accessible to the memory test engine and / or may be received from another component and / or device.

[0027] After executing the test mode to read and / or write data, the comparator can be used to determine whether the data read from the one or more memory components is as expected by the specific test by comparing the data retrieved from the one or more memory components with the data written to the one or more memory components. If the test is successful, the retrieved data and the written data should match, and a notification indicating success can be sent. If the test is unsuccessful, the retrieved data and the written data should not match, and a notification indicating failure can be sent.

[0028] Some advantages of the present disclosure include enhancing the performance of the memory subsystem by performing error correction operations at the sequencer and reducing the number of transmissions between the memory controller and the memory components. Further, power consumption can be reduced by performing error correction operations at the sequencer because the data read by the sequencer during the error correction operation is transmitted between the sequencer and the memory components via short traces. This can improve signal integrity by performing error correction operations using short traces between the sequencer and the memory components, which can improve the quality of correcting any errors if no errors are introduced in the data during transmission. Additional advantages can include reducing the cost of testing memory components by including a memory test engine in the sequencer.

[0029] Figure 1 An exemplary computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is shown. The memory subsystem 110 may include media, such as a memory component 112. The memory component 112 may be a volatile memory component, a non-volatile memory component, or a combination thereof. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem.

[0030] In some embodiments, the memory component 112 may be included in the package 130. There may be multiple packages (indicated by ellipsis 131), each package including one or more corresponding memory components. As shown, the memory components 112A to 112N are coupled to the sequencer component 140 in the package 130. It should be understood that multiple sequencer components may be included in the package 130, and each sequencer component may be coupled to one or more corresponding memory components. Each sequencer component 140 may be manufactured in independent silicon, and each memory component 112 may be manufactured in an independent die. The memory subsystem 110 may include a memory system controller 115 (hereinafter referred to as "controller"). The sequencer component 140 and the memory component 112 may be included in a single package 130, and coupled via a short trace 162 to improve the performance of issuing commands from the sequencer component 140 to the memory component 112. Compared with the conventional arrangement, by using a shorter trace between the sequencer component 140 and the memory component, power load consumption can be reduced, and data signal integrity can be improved. Furthermore, as discussed herein, moving the sequencer component 140 to a package 130 separate from the controller 115 may provide numerous other benefits, such as reducing the form factor of the memory subsystem 110 , increasing bandwidth between the controller 115 and the memory component 112 , and the like.

[0031] For example, compared to a parallel interface, the sequencer component 140 and the memory component 112 in the package 130 can be coupled to the controller 115 via a SerDes interface 160. The SerDes interface 160 provides a higher bandwidth than a parallel interface and also uses fewer output pins, thereby reducing the number of pins required for the controller 115 to provide the same capacity (e.g., the number of memory components 112) to the memory subsystem 110. For example, a SerDes interface can use six pins (e.g., two for clock, two for transmission, and two for reception), while a parallel interface can operate using more than twenty pins. By reducing the size of the controller 115, reducing the number of output pins of the controller 115 can improve the form factor of the entire memory subsystem 110. Further, removing the sequencer component 140 from the controller 115 can also reduce the size of the controller 115.

[0032] The sequencer component 140 can perform one or more operations and can be configured based on the type of memory component 112 to which the corresponding sequencer component is coupled. For example, the sequencer component 140 may include an error correction engine 141, a memory test engine 145, and a protocol engine 150. The error correction engine 141 may perform one or more error correction operations to encode data received from the controller 115 and / or decode data read from the memory component 112A. Therefore, the error correction engine 141 may include an encoder 142 and a decoder 143. The decoding error correction operation may use any suitable error correction technology, such as error correction codes, redundant operations (e.g., XOR), etc. Error correction codes may be used to improve the reliability of data stored in the memory subsystem 110. Error correction codes may refer to a technique for representing a sequence of data so that errors introduced into the data can be detected and corrected based on other remaining data. The data sequence may be referred to as a codeword. The type of error correction code may include a block code (e.g., Hamming code, Reed-Solomon code, etc.). Redundant operation may refer to using a logical operation (eg, XOR) to reconstruct data. Redundant reconstruction operation uses information of exact error locations, and the number of known error locations does not exceed a threshold.

[0033] Using shorter traces in package 130 can improve the performance of the error correction process, thereby enhancing the overall performance of the memory subsystem. Further, in some embodiments, the controller does not need to manage the various error correction parameters of the memory types of the memory components 112, because the corresponding sequencer component of each package can manage the parameters of its respective memory component 112.

[0034] In addition, the sequencer component 140 may include a memory test engine 145 to perform one or more tests on the memory component 112. The tests may be customized to ensure that the memory component 112 is compatible with the controller 115. The memory test engine 145 includes a test pattern generator 146 and a comparator 147. The test pattern generator 146 may generate a test pattern to test the memory component 112. The test pattern may correspond to an operation (e.g., read and / or write) associated with the generated data to be performed on the memory component 112. The test may emphasize testing the memory component 112 by using the test pattern to test the operation of the memory component 112 at various temperatures. In addition, the test pattern may test the timing window when sending and / or receiving data signals associated with the memory component 112. The test may ensure that the memory component 112 meets the timing requirements for sending signals via the interface between the memory component 112 and the sequencer component 140. The test pattern generator 146 may apply different voltages throughout the test to determine whether the memory component 112 operates normally (e.g., stores correct data) when different voltages are applied. Furthermore, because different memory types (e.g., cross point arrays, flash memory, etc.) can be associated with different read voltage levels, the test pattern generator 146 can program memory parameters such as read voltage levels to enhance the quality of data read from memory components 112 of a particular memory type.

[0035] After the test is completed, the comparator 147 can compare the data read from the memory component 112 with the data associated with the test pattern written to the memory component 112 during the test. If the data is as expected (e.g., the read data matches the written data), the comparator 147 can determine that the test was successfully completed and a notification indicating success can be provided. If the data is not as expected (e.g., the read data does not match the written data), the comparator 147 can determine that the test was not successfully completed and a notification indicating failure can be provided.

[0036] The sequencer component 140 may also use the protocol engine 150 to perform other operations. For example, the protocol engine 150 may attempt to maximize the interface bandwidth between the memory component 112 and the sequencer component 140 by implementing timing requirements for the memory type of the memory component 112. The timing requirements may be related to the latency of performing read / write operations on the memory type. The protocol engine 150 may determine when to issue a read / write command based on the latency of the type of the memory component 112. Further, the protocol engine 150 may reorder commands based on certain rules related to the commands and the addresses involved in the commands. That is, the protocol engine 150 may reorder read / write requests by considering rules that ensure data consistency. For example, if there are write requests and read requests for the same address, the rules may specify that the read request cannot be moved before the write request because the read request will return old data. Therefore, the protocol engine 150 may reorder operations based on the bandwidth of the memory component 112 and apply the timing of when the operation is sent to the memory component 112.

[0037] Typically, the computing environment 100 may include a host system 120 that uses a memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110. The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 may read data from or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component) (whether wired or wireless), including connections such as electrical, optical, magnetic, etc. Examples of the physical host interface include, but are not limited to, a serial / deserialized (SerDes) interface, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), etc. The physical host interface can be used to send data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through the PCIe interface, the host system 120 can further utilize the NVM express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0038] The memory components 112 may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include "NAND" (NAND) type flash memory. Each memory component 112 may include an array of one or more memory cells, such as a single-level cell (SLC) or a multi-level cell (MLC) (e.g., a triple-level cell (TLC) or a quad-level cell (QLC)). In some embodiments, a specific memory component may include an SLC portion and an MLC portion of a memory cell. Each memory cell may store one or more bits of data (e.g., a data block) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, the memory component 112 may be based on any other type of memory such as a volatile memory. In some embodiments, the memory component 112 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a cross-point array of non-volatile memory cells, such as non-NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and non-volatile memory cells. The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, the cross-point non-volatile memory may perform write-in-place operations, in which non-volatile memory cells may be programmed without having to erase the non-volatile memory cells in advance. Furthermore, the memory cells of the memory component 112 may be grouped into memory pages or data blocks, which may refer to cells of a memory component used to store data.

[0039] The controller 115 may communicate with the memory component 112 via the sequencer component 140 to perform operations such as reading data, writing data, or erasing data at the memory component 112, as well as other such operations. In one example, the controller 115 may include an error component 116 having an encoder 118 and a decoder 121. In some embodiments, for a package including a sequencer lacking error correction capabilities, the error component 116 may be used to perform any suitable encoding and / or decoding error correction operations using the encoder 118 and the decoder 121, respectively. In some embodiments, the error component 116 may be used as a second level of error correction to provide additional error correction capabilities to data partially corrected by the first level of error correction performed by the error correction engine 141 of the sequencer component 140. In some embodiments, the error component 116 may encode a portion of the data received from the host system 120, and send the partially encoded data to the sequencer component 140 so that the data can be encoded by the error correction engine 141. In some embodiments, the controller 115 may receive a notification that the sequencer component 140 includes an error correction capability. In such cases, the controller 115 may forward raw data received from the host system 120 to the sequencer component 140. Raw data may refer to data to which no error correction operations (eg, encoding) are applied.

[0040] If used, the error unit 116 can perform an encoding error correction operation of encoding the original data received by the host system 120 with additional data bits (e.g., parity bits) to form a codeword to be written to the memory unit 112 via the sequencer unit 140. The error unit 116 can also perform a decoding error correction operation of decoding the codeword by removing the additional data bits. The encoding / decoding operation can use certain configuration parameters based on the type of memory unit 112 in which the data is to be stored. The controller 115 can send one or more codewords to the sequencer unit 140. The sequencer unit 140 can determine which parts of which codewords are to be stored on the memory units 112A to 112N by considering the bandwidth and availability of the memory units 112A to 112N, the timing requirements of the memory units 112A to 112N (e.g., read / write latency), and the rules for sequencing read / write operations.

[0041] The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routes for controlling the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers for storing memory pointers, extracted data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although Figure 1 The exemplary memory subsystem 110 in has been shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0042] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory component 112. In some embodiments, the controller 115 may also perform address translation between logical block addresses and physical block addresses associated with the memory component 112. The controller 115 may also perform memory management operations, such as determining a wear leveling scheme customized for the memory type of the memory component and issuing operations to the sequencer component 140 indicating the wear leveling scheme.

[0043] The controller 115 may be responsible for other operations, such as garbage collection operations, encryption operations, and / or cache operations. The controller 115 may further include a host interface circuit to communicate with the host system 120 via a physical host interface. The host interface circuit may convert commands received from the host system into command instructions to access the memory component 112 via the sequencer component 140, and convert responses associated with the memory component 112 into information for the host system 120.

[0044] The memory subsystem 110 may also include additional circuit systems or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory component 112.

[0045] Figure 2 is a flow chart of an exemplary method 200 for performing a coding error correction operation on data according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The processing device (e.g., error correction engine 141) of the sequencer component 140 is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0046] At block 210, a processing device of the sequencer component 140 receives data from a controller 115 external to the sequencer component 140. The sequencer component 140 is included in a package 130 that includes the memory component 112A, and the controller 115 is external to the package 130. The data received from the controller 115 may be sent to the controller 115 by the host system 120 as raw data (e.g., data from the host system 120 that is not encoded), and the host system 120 may specify that the data is to be written to the memory component 112. In some embodiments, before receiving the data, the processing device of the sequencer component 140 may send a notification to the controller 115 indicating that the sequencer component 140 includes functionality to perform an error correction operation. The notification may cause the controller 115 to send the raw data to the sequencer component 140 external to the memory controller 115 without performing an encoding operation on the raw data at the controller 115. In some embodiments, where the controller 115 and the sequencer 140 coordinate to perform error correction operations, the controller 115 may partially encode data and the processing device of the sequencer component 140 may fully encode the partially encoded data received from the controller 115 .

[0047] At block 220, a processing device of the sequencer component 140 performs an error correction operation on the data received from the controller 115. The error correction operation may be a coding error correction operation that encodes the original data or partially encoded data received from the controller 115 with additional data bits (e.g., parity bits) to generate a codeword. The processing device may receive an indication of the memory type of the memory component 112A. The memory type may correspond to the structure of the memory component 112A (e.g., crosspoint, flash memory, etc.). The coding error correction operation may use certain configuration parameters based on the memory type of the memory component 112A in which the codeword is to be stored. For example, the size of the codeword, the rate of the codeword, and / or the type of the codeword may be selected based on the memory type of the memory component 112A.

[0048] In some embodiments, a maximum distance separable code, such as a Reed-Solomon code, can be used for encoding error correction operations. Reed-Solomon codes encode data blocks by adding additional redundant bits to the data. For example, each s-bit k data symbol can be encoded into n symbol codewords, where parity symbols are added to the k data symbols. Mathematical operations (e.g., polynomials) can be generated based on the data block, and mathematical operations can be used to obtain parity bits. Parity bits can be added to the data block.

[0049] Various reasons (e.g., noisy communications, memory component failures, asynchronous power loss, etc.) may cause the data of a codeword to include errors (e.g., flipped bits, missing bits, etc.) If errors exist in a codeword stored at memory component 112A or memory components 112A-112N, parity bits or other bits of the codeword may be used in a raw mathematical operation to obtain the original data block and / or parity bits and correct the errors in the codeword.

[0050] At block 230, a processing device of the sequencer component 140 stores the codeword at a memory component 112A coupled to the sequencer component 140. In some embodiments, there may be multiple memory components 112A-112N coupled to the sequencer component 140. The processing device may determine one or more of the memory components 112A-112N to store the codeword based on the bandwidth of the memory components 112A-112N, the available storage of the memory components 112A-112N, wear leveling, etc. For example, the processing device may stripe the codeword across more than one memory component 112A-112N to distribute the codeword, which may implement certain techniques such as redundant array of independent disks.

[0051] Figure 3is a flow chart of an exemplary method 300 for performing a decoding error correction operation on data according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The processing device (e.g., error correction engine 141) of the sequencer component 140 is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0052] At block 310 , a processing device of sequencer component 140 receives an operation to read data (eg, a codeword) stored at memory component 112A. The operation may be sent by host system 120 to controller 115 , and controller 115 may send the operation to the processing device of sequencer component 140 .

[0053] At block 320 , in response to the receive operation, the processing device of the sequencer component 140 retrieves the codeword from the memory component 112A or the memory components 112A- 112N.

[0054] At block 330, a processing device of sequencer component 140 performs a decoding operation associated with the codeword to generate data. In some embodiments, the decoding operation may include applying an error correction code to the codeword in an attempt to decode the codeword (e.g., remove a parity bit) and / or repair one or more bit errors. For example, applying an error correction code to data stored in memory component 112A or memory components 112A-112N may result in obtaining updated data including at least one corrected bit. If a Reed-Solomon code is used, a mathematical operation (e.g., a polynomial) for encoding the codeword may be used with one or more original bits and / or parity bits of the codeword to obtain the correct bit to which the bit including the error is changed.

[0055] In some embodiments, a processing device of the sequencer component 140 may identify that a portion of the data includes a first error that cannot be decoded by a decoding operation performed by the sequencer component 140. The decoding operation may have corrected one or more other errors, but the portion of the data may still include at least one other error. Therefore, the processing device may perform another error correction operation (e.g., error correction code, redundant operation, etc.) on the data including the portion. Performing multiple reads of the data may enable the processing device to obtain information indicating whether the value of the data is authentic (e.g., each read returns the same value), undergoes a flip (e.g., a shift in the read voltage level shows a change in value), or is erroneous (e.g., an erroneous value). As previously described, because the sequencer component 140 is close to the memory component 112A in the package 130, the trace between the sequencer component 140 and the memory component 112A is shorter, thereby reducing power consumption and improving read latency during decoding. Therefore, including a sequencer component 140 that performs error correction operations in the package 130 with the memory component 112A can improve the performance of the memory subsystem 110.

[0056] In some embodiments, when the processing device of the sequencer component 140 identifies that a portion of the data includes an error that cannot be decoded by the decoding operation performed by the sequencer component 140, the processing device may send the data to the controller 115 so that the controller 115 decodes at least the portion of the data to correct the error that cannot be decoded by the decoding operation performed by the sequencer component 140. As a result of the decoding operation performed by the sequencer component 140, the data may include at least one corrected bit. In this embodiment, the decoding operation performed by the sequencer component 140 may represent a first level of error correction, while the decoding operation performed by the controller 115 may represent a second level of error correction. The error correction operation may or may not use any information related to the position of the error bit. In some embodiments, the first level of error correction performed by the sequencer component 140 may be stronger than the second level of error correction performed by the controller 115. That is, the first level of error correction can generally correct more errors than the second level of error correction. For example, the first level of error correction may correct a first number of bits (e.g., 20) in a 128-byte codeword, while the second level of error correction may correct a second number of bits (e.g., 1 symbol) that is less than the first number of bits. In any embodiment, when the codeword is decoded and the raw data is obtained, the raw data may be sent to the host system 120 .

[0057] Figure 44 is a flow chart of an exemplary method 400 for performing a test of the memory component 112A according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The processing device (e.g., memory test engine 145) of the sequencer component 140 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0058] At block 410, a processing device of the sequencer component 140 generates a test pattern to perform a test of the memory component. The sequencer component 140 resides in a package 130 separate from the controller 115. The test pattern may correspond to a read, write, and / or erase operation of data at the memory component 112A. The processing device may generate an operation pattern to be performed, and data to be written and / or read from the memory component 112A. Certain memory types of the memory component 112A may be associated with certain problems (e.g., bridging problems). The processing device may receive an indication of the memory type of the memory component 112A, and customize the test pattern based on the memory type to test known problems.

[0059] The test mode can be designed to test whether the memory component 112A is functioning properly (e.g., storing data correctly and providing data correctly) at a certain temperature. The temperature can be selected based on the design specifications of the memory component 112A, taking into account the memory type of the memory component 112A. The test mode can use a specific number or sequence of operations to be performed so that the memory component 112A reaches various temperatures during operation. Further, a variety of different voltages can be used during the test to evaluate whether the memory component is functioning properly when different voltages are applied. Such temperature and / or voltage stress tests can provide an indication of the durability of the memory component 112A.

[0060] In some embodiments, the test pattern may emphasize test timing requirements (e.g., timing windows) associated with the memory component 112A via an interface between the sequencer component 140 and the memory component 112A. The timing requirements may specify an amount of time that the memory component 112A must send a signal and / or perform an operation. The test timing requirements may ensure that the memory component 112A meets certain responsiveness standards associated with the memory type of the memory component 112A, and may ensure that the memory component 112A is compatible with the controller 115 with which the memory component 112A is to operate. In some embodiments, the test pattern may be generated to emphasize the test timing requirements at different temperatures and / or different voltages.

[0061] At block 420, the processing device of the sequencer component 140 executes a test mode to write data to the memory component 112A. As described above, in some embodiments, the test mode may include any suitable operating mode (e.g., write, read, erase, etc.) and data determined to be useful for testing one or more aspects of the memory component 112A.

[0062] At block 430, the processing device of the sequencer component 140 retrieves data from the memory component 112A. The processing device can retrieve data by reading data from the memory component 112A. In some cases, the data may include one or more errors (e.g., flip bits, erased bits, etc.). The processing device of the sequencer component 140 executing the memory test engine 145 can program memory parameters, such as read level voltages to attempt to re-read data using modified read level voltages. In some embodiments, data can be returned without errors using different read level voltages. If the data still contains one or more errors, the processing device can attempt to correct the errors using the error correction engine 141 of the sequencer component 140. The error correction engine 141 can perform one or more error correction operations on the data of the test mode written into the memory component 112A, and return the corrected data to the memory test engine 145.

[0063] At block 440, the processing device of the sequencer component 140 compares the retrieved data with the data of the test pattern written to the memory component 112A. The processing device of the sequencer component 140 executing the comparator 147 may compare the retrieved data with the data of the test pattern written to the memory component 112A.

[0064] At block 450, the processing device of the sequencer component 140 determines whether the test of the memory component 112A was successfully completed based on the comparison of the retrieved data with the data of the test pattern. For example, if the retrieved data matches the written data of the test pattern written to the memory component 112A, the processing device can determine that the test was successfully completed (e.g., the memory component 112A is working as expected). In response to determining that the test of the memory component 112A was successfully completed, the processing device can send a notification indicating that the test was successfully completed. If the retrieved data does not match the data of the test pattern written to the memory component 112A, the processing device can determine that the test was not successfully completed. In response to determining that the test of the memory component 112A was not successfully completed, the processing device can send a notification indicating that the test was not successfully completed.

[0065] Embedding the memory test engine 145 into the sequencer component 140 in a single package 130 including the memory components 112A-112N can reduce the complexity and cost associated with testing the memory components 112A-112N. For example, a separate board dedicated to the memory type of the memory component may not be needed because the memory test engine 145 generates test patterns specifically for the memory type of the memory component 112A-112N coupled to the sequencer component 140. Therefore, the package 130 can be connected to a memory type agnostic board to test the memory component using the memory test engine 145 of the sequencer component 140. Multiple different packages 130 including memory components of different memory types can use the same memory type agnostic board to run their respective tests.

[0066] Figure 5 An exemplary machine of a computer system 500 is shown, in which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 The host system 120 may be used to execute the operation of the controller or to execute the operation of the sequencer component 140 (e.g., to execute the operation corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0067] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (in sequence or otherwise) that specify actions to be taken by the machine. In addition, while a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0068] The exemplary computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0069] Processing device 502 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or multiple processors that implement a combination of instruction sets. Processing device 502 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 can further include a network interface device 508 to communicate through a network 520.

[0070] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution of the instructions by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0071] In one embodiment, instructions 526 include implementing a Figure 1The machine-readable storage medium 524 is a memory storage medium that is used to store or encode instructions for functions of the error correction engine 141 and / or memory test engine 145 of the sequencer component 140. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions executed by a machine and cause the machine to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0072] Some parts of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of the operations of the data bits in a computer memory. These algorithmic descriptions and representations are the means by which the technical personnel in the field of data processing use to most effectively communicate the essence of their work to other technical personnel in the art. Algorithms are here and are generally considered to be self-consistent sequences of operations that lead to desired results. These operations are those operations that require physical manipulation of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that sometimes, in principle, it is convenient to refer to these signals as bits, values, elements, symbols, characters, items, quantities, etc. for general reasons.

[0073] It should be borne in mind, however, that all of these or similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0074] The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specifically constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems can be used together with programs according to the teachings herein, or it may be convenient to construct more specialized equipment to perform the method. As described below, structures for various of these systems will occur. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0076] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. Machine-readable media include any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, machine-readable (e.g., computer-readable) media include machine (e.g., computer) readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0077] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Therefore, the present description and the accompanying drawings should be understood in an illustrative rather than a restrictive sense.

Claims

1. A method for performing error correction, the method comprising: sending, by a sequencer component, a notification to a controller, the notification indicating that the sequencer component includes functionality to perform an error correction operation, so that the controller sends data including raw data to the sequencer component external to the controller without performing an encoding operation on the raw data at the controller; receiving, by a processing device of the sequencer component, the data from the controller external to the sequencer component, wherein the sequencer component and memory component reside in a package separate from the controller; performing, by the processing device of the sequencer component, the error correction operation on the data received from the controller external to the sequencer component to generate a codeword associated with the data; as well as The codeword is stored at the memory component coupled to the sequencer component.

2. The method according to claim 1, further comprising: An indication of a memory type of the memory component is received, the memory type corresponding to a structure of the memory component, wherein the error correction operation is performed based on the memory type of the memory component to generate the codeword.

3. The method according to claim 1, further comprising: Receiving an operation of reading the data; in response to receiving the operation, retrieving the codeword from the memory component; and A decoding operation associated with the codeword is performed by the processing device of the sequencer component to generate the data.

4. The method according to claim 3, further comprising: identifying that a portion of the data includes a first error that cannot be decoded by the decoding operation performed by the sequencer component, wherein decoding the data corrects at least a second error in the data; and A second error correction operation is performed by the processing device of the sequencer component to decode the portion of the data to correct the first error.

5. The method according to claim 3, further comprising: identifying that a portion of the data includes a first error that cannot be decoded by the decoding operation performed by the sequencer component, wherein the decoding operation corrects at least a second error in the data; and The data is sent to the controller to cause the controller to decode at least the portion of the data to correct the first error, which could not be decoded by the decoding operation performed by the sequencer component.

6. A memory system comprising: Memory components; as well as a processing device of a sequencer component, the processing device of the sequencer component being operatively coupled to the memory component to: sending a notification to a controller, the notification indicating that the sequencer component includes functionality to perform an error correction operation, so that the controller sends data including raw data to the sequencer component external to the controller without performing an encoding operation on the raw data at the controller; receiving the data from the controller external to the sequencer component, wherein the sequencer component and the memory component reside in a package separate from the controller; performing the error correction operation on the data received from the controller external to the sequencer component to generate a codeword associated with the data; as well as The codeword is stored at the memory component operatively coupled to the processing device of the sequencer component.

7. The memory system of claim 6, wherein the processing device of the sequencer component is further configured to: An indication of a memory type of the memory component is received, the memory type corresponding to a structure of the memory component, wherein the error correction operation is performed based on the memory type of the memory component to generate the codeword.

8. The memory system of claim 6, wherein the processing device of the sequencer component is further configured to: Receiving an operation of reading the data; in response to receiving the operation, retrieving the codeword from the memory component; and A decoding operation associated with the codeword is performed to generate the data.

9. The memory system of claim 8, wherein the processing device of the sequencer component is further configured to: identifying that a portion of the data includes a first error that cannot be decoded by the decoding operation performed by the sequencer component, wherein decoding the data corrects at least a second error in the data; and A second error correction operation is performed to decode the portion of the data to correct the first error.

10. The memory system of claim 8, wherein the processing device of the sequencer component is further configured to: identifying that a portion of the data includes a first error that cannot be decoded by the decoding operation performed by the sequencer component, wherein the decoding operation corrects at least a second error in the data; and The data is sent to the controller to cause the controller to decode at least the portion of the data to correct the first error, which could not be decoded by the decoding operation performed by the sequencer component.

11. A method for performing error correction, the method comprising: generating, by a processing device of a sequencer component, a test pattern to perform a test of a memory component, wherein the test pattern corresponds to a plurality of operations of writing data to the memory component, wherein the sequencer component resides in a package separate from a controller, the sequencer component being configured to send a notification to the controller, the notification indicating that the sequencer component includes a function of performing an error correction operation to cause the controller to send data including raw data to the sequencer component external to the controller without performing an encoding operation on the raw data at the controller; executing the test mode to write the data into the memory component; retrieving said data from said memory component; comparing said retrieved data with said data of said test pattern written to said memory component; as well as Based on a comparison of the retrieved data with the data of the test pattern, it is determined whether the test of the memory component was successfully completed.

12. The method of claim 11, wherein executing the test mode causes the memory component to operate at a plurality of different temperatures.

13. The method of claim 11, wherein the test mode is performed using a plurality of different voltages.

14. The method of claim 11, wherein the test mode emphasizes test timing requirements for sending signals from the sequencer component to the memory component via an interface between the sequencer component and the memory component.

15. The method of claim 11, wherein the processing device is further for modifying a read voltage level to be applied when reading the data from the memory component.

16. The method of claim 11, wherein the processing device is further configured to: In response to determining that the test of the memory component completed successfully, sending a notification indicating that the test completed successfully; or In response to determining that the test of the memory component did not complete successfully, a notification is sent indicating that the test did not complete successfully.

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