Semiconductor device having a metal oxide semiconductor structure

Abstract

A semiconductor device includes a semiconductor substrate. A drift region is provided in the semiconductor substrate. The drift region has a first conductivity type. A body region is provided in the semiconductor substrate, adjacent to the drift region. The body region has a second conductivity type. A drain region is provided in the drift region, opposite to the body region. A drain isolation insulating film is provided in a part of the drift region adjacent to the drain region. A gate insulating film is provided on the semiconductor substrate and extends over a part of the body region and a part of the drift region. A gate electrode is provided on the gate insulating film, and the gate electrode has at least one closed-type opening.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10 - 2019 - 0150271, filed with the Korean Intellectual Property Office on November 21, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a metal - oxide - semiconductor (MOS) structure. Background art

[0004] Electronic devices are becoming increasingly compact, lighter, and more versatile. Accordingly, metal - oxide - semiconductor (MOS) transistors are often used in various types of semiconductor devices. An example of such a power MOS transistor is a laterally - diffused metal - oxide - semiconductor (LDMOS) transistor. In an LDMOS transistor, a channel region and a drain electrode are separated by a drift region and / or a well region, and thus its operation can be controlled by a gate electrode. Summary of the invention

[0005] A semiconductor device includes a semiconductor substrate. A drift region having a first conductivity type is provided in the semiconductor substrate. A body region is provided in the semiconductor substrate, adjacent to the drift region. The body region has a second conductivity type. A drain region is disposed opposite to the body region in the drift region. A drain isolation insulating film is provided in a part of the drift region adjacent to the drain region. A gate insulating film is provided on the semiconductor substrate and extends over a part of the body region and a part of the drift region. A gate electrode is provided on the gate insulating film. The gate electrode has at least one closed - type opening.

[0006] A semiconductor device includes a semiconductor substrate. A drift region having a first conductivity type is provided in the semiconductor substrate and extends to the upper surface of the semiconductor substrate. A body region having a second conductivity type is provided in the semiconductor substrate and shares a boundary with the drift region. The body region extends to the upper surface of the semiconductor substrate. A gate insulating film is provided on the boundary between the body region and the drift region and extends over a part of the body region and a part of the drift region. A gate electrode is provided on the gate insulating film and has a plurality of closed - type openings. Each of the plurality of closed - type openings has a region overlapping with the drift region.

[0007] A semiconductor device includes a semiconductor substrate. A drift region having a first conductivity type is provided in the semiconductor substrate. A body region having a second conductivity type is provided in the semiconductor substrate and is adjacent to the drift region. A drain region having the first conductivity type is disposed in the drift region opposite to the body region. A source region having the first conductivity type is provided in the body region. A body contact region having the second conductivity type is provided in the body region adjacent to the source region. A drain isolation insulating film is provided in a part of the drift region adjacent to the drain region. A gate electrode is provided on the semiconductor substrate and extends over a part of the body region and a part of the drift region. The gate electrode has at least one closed-type opening. A gate insulating film is provided between the gate electrode and the semiconductor substrate. An impurity region of the first conductivity type is provided in the drift region, at least partially overlapping with the at least one closed-type opening, and having an impurity concentration greater than that of the drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the present disclosure and many of its attendant aspects and features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan view showing a semiconductor device (e.g., a power MOS transistor) according to an exemplary embodiment of the present disclosure;

[0010] Figure 2A and Figure 2B is a cross-sectional view showing the semiconductor device taken along lines I1-I1' and I2-I2'; Figure 1 of;

[0011] Figure 3 is a plan view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] Figure 4A and Figure 4B is a cross-sectional view showing the semiconductor device taken along lines II1-II1' and II2-II2'; Figure 3 of;

[0013] Figure 5A and Figure 5B is a graph showing and comparing the parasitic capacitances (Cgg and Cgd) of power MOS transistors according to exemplary and comparative examples of the present disclosure;

[0014] Figure 6A and Figure 6B is a graph showing and comparing the BV characteristics and resistance characteristics (Rsp) of power MOS transistors according to exemplary and comparative examples of the present disclosure;

[0015] Figure 7A graph showing and comparing the hot carrier injection reliability of a power MOS transistor according to an example and a comparative example of the present disclosure;

[0016] Figure 8 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] Figures 9A to 9C is a plan view showing a semiconductor device according to various exemplary embodiments of the present disclosure;

[0018] Figure 10 and Figures 11A to 13A is a cross-sectional view (II1-II1') showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0019] Figures 11B to 13B is a cross-sectional view (II2-II2') showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; and

[0020] Figure 14 is a cross-sectional view showing a semiconductor device (power MOS transistor + memory device) according to an exemplary embodiment of the present disclosure. Detailed Description

[0021] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0022] Figure 1 is a plan view showing a semiconductor device (e.g., a power MOS transistor) according to an exemplary embodiment of the present disclosure, and Figure 2A and Figure 2B are cross-sectional views showing the semiconductor device taken along lines I1-I1' and I2-I2'. Figure 1 of the semiconductor device.

[0023] Referring to Figure 1 、 Figure 2A and Figure 2B According to an exemplary embodiment, a semiconductor device 10A having a MOS structure includes a semiconductor substrate 100, a drift region 120 provided in the semiconductor substrate 100 and having a first conductivity type, and a body region 130 provided in the semiconductor substrate 100 and having a second conductivity type. The second conductivity type may be different from or opposite to the first conductivity type.

[0024] In the exemplary embodiment, the semiconductor substrate 100 employed may have a well 110 of the second conductivity type (e.g., a well having the second conductivity type). The drift region 120 and the body region 130 may each be formed in the well 110 of the second conductivity type. The drift region 120 and the body region 130 may be arranged in a direction parallel to the upper surface of the semiconductor substrate 100 (e.g., laterally).

[0025] For example, the semiconductor substrate 100 may include a semiconductor substrate of a second conductivity type (e.g., a semiconductor substrate having a second conductivity type), such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. In some embodiments, the semiconductor substrate 100 may be provided as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0026] The drift region 120 and the body region 130 may extend to the upper surface of the semiconductor substrate 100 (e.g., the upper surface of the well 110 of the second conductivity type). In an exemplary embodiment, the body region 130 may be adjacent to the drift region 120 to share a boundary therewith. However, the present invention is not necessarily limited to this particular arrangement, and the body region 130 and the drift region 120 may be spaced apart from each other and disposed in the well 110 of the second conductivity type.

[0027] A barrier region 102 may also be provided between the lower region of the semiconductor substrate 100 and the well 110 of the second conductivity type. The impurity concentration of the barrier region 102 may be higher than the impurity concentration of the lower region of the semiconductor substrate 100 and / or the well 110 of the second conductivity type. For example, the barrier region 102 may have impurities of a first conductivity type.

[0028] A source region 135 of the first conductivity type may be formed in the body region 130 (e.g., a region starting from the upper surface of the body region 130). In addition, a body contact region 132 of the second conductivity type may be formed in the body region 130 (e.g., a region starting from the upper surface of the body region 130). The body contact region 132 and the source region 135 may be in contact with each other. The source region 135 and the body contact region 132 are in contact with each other in one direction, and the source region 135 may be closer to the drift region 120 or the channel region within the body region 130 than the body contact region 132.

[0029] In the drift region 120, a drain region 145 of the first conductivity type may be in contact with the opposite side of the body region 130. The drain region 145 may be formed in a region starting from the upper surface of the drift region 120. For example, the drain region 145 may be disposed opposite to the body region 130 in the said one direction. The drain region 145 may be formed in the drift region 120, as Figure 2A and Figure 2B shown. Alternatively, the drain region may be in contact with the drift region 120 other than on the opposite side of the drift region 120.

[0030] As in the exemplary embodiment, a drain well 140 of the first conductivity type may be formed opposite to the drift region 120. The drain region 145 may be formed in the drain well 140.

[0031] The drain isolation insulating film 160 may be disposed on the drift region 120. The drain isolation insulating film 160 may be formed in the drift region 120 between the gate electrode 155 and the drain region 145. The drain isolation insulating film 160 employed in the exemplary embodiment may be local oxidation of silicon (LOCOS). In the exemplary embodiment, the drain isolation insulating film 160 may be shallow trench isolation (STI) (see Figure 8 ).

[0032] The drain isolation insulating film 160 may reduce current concentration between the gate electrode 155 and the drain region 145, thereby ensuring a stable breakdown voltage and improving high-voltage resistance. In addition, the drain isolation insulating film 160 may remove the increase in resistance (e.g., on-resistance (Ron)) caused by current bypass between the gate electrode 155 and the drain region 145. Therefore, a semiconductor device 10A in which a predetermined breakdown voltage is ensured can be implemented, while the resistance is reduced to have an increased operating speed.

[0033] The gate electrode 155 may be formed on the semiconductor substrate 100 and may extend over both a part of the body region 130 and a part of the drift region 120. The gate electrode 155 may extend from the body region 130 to the drift region 120. A part of the gate electrode 155 may be formed on the drain isolation insulating film 160. The gate electrode 155 may selectively extend over a part of the source region 135. For example, the gate electrode 155 may include polysilicon. In some exemplary embodiments, the gate electrode 155 may include a conductive material such as metal, metal nitride, metal silicide, and the like.

[0034] The gate electrode 155 may have at least one closed-type opening. As used herein, the phrase "closed-type opening" is intended to mean that although the opening may penetrate the entire thickness of the gate electrode 155, they do not divide the gate electrode into discrete parts. Instead, since the diameter of the closed-type opening is smaller than the planar length and width of the gate electrode 155, the gate electrode 155 remains undivided, and in this case, the gate electrode 155 remains "closed" around the closed-type opening, so that the closed-type opening is like a hole in the gate electrode 155.

[0035] The at least one closed-type opening OG may have a region overlapping with the drift region 120 and may expose a part of the gate insulating film 151. In the exemplary embodiment, the at least one closed-type opening OG may include a plurality of closed-type openings (e.g., two openings). The plurality of closed-type openings OG may be arranged in another direction (e.g., the second direction) crossing the one direction (e.g., the first direction) (e.g., the direction in which the body region 130, the drift region 120, and the drain region 145 are arranged) between the body region 130 and the drain region 145.

[0036] When there are a plurality of opening OGs of the closed type, the opening OGs of the closed type are separated from each other by the gate electrode 155, and the gate electrode 155 remains as a single undivided structure.

[0037] The opening OG employed in the exemplary embodiment has a closed type structure that does not open at the edge of the gate electrode (e.g., the opening OG does not extend to the planar edge of the gate electrode in a plan view). Thus, the integrated electrode structure of the gate electrode 155 can be maintained while the gate electrode is not divided into a plurality of electrode regions, as Figure 1 shown. As described above, although the integrated electrode structure of the gate electrode 155 is maintained, the area of the gate electrode 155 can be reduced due to the opening OG of the closed type.

[0038] As the area of the gate electrode 155 is reduced, parasitic capacitances such as the gate input capacitance Cgg and the gate-drain capacitance Cgd can be reduced. Specifically, the parasitic capacitance of the semiconductor device 10A (e.g., a power MOS transistor) can be proportional to the product of the overlap length between the gate electrode and the gate insulating film (or the effective length of the gate electrode) and the width of the transistor. According to the prior art, the width of the transistor is a value determined based on the on-resistance (Ron) value of the power MOS transistor for a switch-mode power supply (SMPS). In this regard, in order to reduce the parasitic capacitance (e.g., Cgg), the effective length of the gate electrode 155 is reduced. However, the reduction in the effective length can allow the hot carrier characteristics to degrade. While maintaining the width of the transistor and the effective length of the gate electrode 155, the opening OG of the closed type is introduced to reduce the parasitic capacitance, thereby reducing the switching loss. Therefore, the function of the opening OG of the closed type is to reduce the area of the gate electrode 155 without reducing the length or width of the gate electrode 155.

[0039] In a plan view, the total area of the opening OGs of the closed type can be formed to be in the range of 20% to 80% of the external reference area of the gate electrode 155, and more preferably in the range of 30% to 60%. For example, the ratio of the total area of the opening OGs of the closed type to the actual area of the gate electrode 155 can be in the range of 2:8 to 8:2.

[0040] The opening OG of the closed type employed in the exemplary embodiment can be processed to allow its inner corner to be an obtuse angle. For example, the opening of the closed type is processed to allow the angle of its inner corner to be greater than 90° (e.g., 120°), so that the electric field can be dispersed. In the exemplary embodiment, the inner corner of the opening OG of the closed type can have a circular portion to allow the electric field to be effectively dispersed. Thus, the opening OG of the closed type can have a cylindrical shape, a prismatic shape, or some other related shape.

[0041] The gate insulating film 151 may be disposed under the gate electrode 155. The gate insulating film 151 and the gate electrode 155 may be stacked in sequence on the semiconductor substrate 100. The gate insulating film 151 may have a portion 151E extending to the body region 130 and the drain region 145, but the present invention is not necessarily limited thereto, and the gate insulating film 151 may be patterned to correspond to the gate electrode 155.

[0042] For example, the gate insulating film 151 may be formed by a deposition process or a thermal oxidation process. When the gate insulating film 151 is formed by a deposition process, the gate insulating film 151 may be formed on the drain isolation insulating film 160. In an example, when the gate insulating film 151 is formed by a thermal oxidation process, the gate insulating film 151 may not be formed on the drain isolation insulating film 160. Further, even if the gate insulating film 151 is formed on the drain isolation insulating film 160, if the gate insulating film and the drain isolation insulating film are formed of the same material or similar materials, it can also be seen that the gate insulating film 151 and the drain isolation insulating film 160 are integrally formed without distinction. For example, the gate insulating film 151 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0043] The gate spacer 156 may be formed on the side surface of the gate electrode 155. For example, the gate spacer 156 may include silicon oxide or metal oxide.

[0044] The interlayer insulating film 170 is formed on the semiconductor substrate 100 and may cover the gate insulating film 151 and the gate electrode 155. For example, the interlayer insulating film 170 may include a silicon oxide-based material, such as a plasma enhanced oxide (PEOX)-based material, a tetraethyl orthosilicate (TEOS)-based material, or a flowable oxide (FOX)-based material.

[0045] The source contact plug 180S and the drain contact plug 180D each pass through both the interlayer insulating film 170 and the gate insulating film 151, and the source contact plug 180S and the drain contact plug 180D may be electrically connected to the source region 135 and the drain region 145, respectively (see Figure 2B ). In an exemplary embodiment, the source contact plug 180S may also be electrically connected to the body contact region 132 and the source region 135. In a similar manner, the gate contact plug 180G may pass through the interlayer insulating film 170 to be electrically connected to a portion of the gate electrode 155 (see Figure 2A ). At least one of the source contact plug 180S, the drain contact plug 180D, and the gate contact plug 180G may include a conductive material, for example, a metal (such as tungsten, copper, and / or aluminum), a metal nitride, and / or doped polysilicon.

[0046] In an exemplary embodiment, a common bias voltage may be applied to the source region 135, which is electrically connected to the source contact plug 180S in the source region 135 and the body contact region 132. In some embodiments, additional contact plugs are formed in the source region 135 and the body contact region 132, so that additional bias voltages can be applied.

[0047] A metal silicide layer 185 is disposed between both the source contact plug 180S and the source region 135 / body contact region 132, and between the drain contact plug 180D and the drain region 145 to reduce the contact resistance (see Figure 2B ). The metal silicide layer 185 may be formed from the exposed semiconductor regions of the source region 135 / body contact region 132 and the drain region 145.

[0048] The gate electrode 155 may include undoped polysilicon or doped polysilicon. The doped polysilicon may be doped with n-type (n+ or n-) or p-type (p+ or p-) impurities. When the gate electrode 155 is polysilicon, a metal silicide layer 185 may be formed between the gate contact plug 180G and the gate electrode 155 (see Figure 2A ).

[0049] The source region 135, the body region 130, the drain region 145, the gate electrode 155, and the drift region 120 may together constitute a power MOS transistor. The semiconductor device 10A according to the exemplary embodiment may have a laterally diffused metal oxide semiconductor (LDMOS) structure. The semiconductor device 10A may include a device isolation portion 161 having STI. The power MOS transistor region may be defined by the device isolation portion 161.

[0050] The first conductivity type may be n-type or p-type, and the second conductivity type may be p-type or n-type. When the first conductivity type is n-type and the second conductivity type is p-type, the power MOS transistor formed in the semiconductor device 10A may be an n-type power MOS transistor. When the first conductivity type is p-type and the second conductivity type is n-type, the power MOS transistor formed in the semiconductor device 10A may be a p-type power MOS transistor.

[0051] For example, when the power MOS transistor formed in the semiconductor device 10A is an n-type power MOS transistor, the semiconductor substrate 100 is p-type and may have an impurity concentration of about 1×10 14 / cm 3 to 1×10 16 / cm 3 , and the barrier region 102 is p-type or n-type and may have an impurity concentration of about 1×10 19 / cm 3Or a greater impurity concentration. The well region of the second conductivity type is p-type and may have about 1×10 15 / cm 3 to 1×10 17 / cm 3 of impurity concentration. The drift region 120 is n-type and may have about 1×10 15 / cm 3 to 1×10 17 / cm 3 of impurity concentration, and the body region 130 is p-type and may have about 1×10 16 / cm 3 to 1×10 18 / cm 3 of impurity concentration. The drain well 140 is n-type and its impurity concentration may be higher than that of the drift region 120, for example, about 2×10 15 / cm 3 to 1×10 18 / cm 3 of impurity concentration. The body contact region 132, the source region 135, and the drain region 145 are p-type, n-type, and n-type, respectively, and may have about 10 19 / cm 3 or a greater impurity concentration.

[0052] When a negative bias voltage is applied to the gate electrode 155, depletion occurs in the drift region 120, and thus the drain region 145 can be extended. Therefore, in the power MOS transistor formed in the semiconductor device 10A, a current flow path can be formed in which current flows through the lower side of the drift region 120 in the lower part of the drain isolation insulating film 160.

[0053] For example, when the power MOS transistor formed in the semiconductor device 10A is a p-type power MOS transistor, the conductivity of the corresponding components can be selected and formed in a manner opposite to that of the n-type power MOS transistor case.

[0054] Figure 3 is a plan view showing a semiconductor device according to an exemplary embodiment of the present disclosure, and Figure 4A and Figure 4B are cross-sectional views of the semiconductor device taken along lines II1-II1' and line II2-II2'. Figure 3 of the semiconductor device.

[0055] Referring to Figure 3 、 Figure 4A and Figure 4B, except that an impurity region 195 of the first conductivity type is additionally formed in the drift region 120 overlapping with the opening OG of the closed type, the inner corner of the opening OG of the closed type has a rounded portion, and no drain trap is employed, the semiconductor device 10B according to the exemplary embodiment can be understood as having a structure similar to that of the semiconductor device 10A of the exemplary embodiment shown in Figure 1 , Figure 2A and Figure 2B . Therefore, unless otherwise specified, Figure 1 , Figure 2A and Figure 2B . The description of the exemplary embodiment shown can be combined with the description provided below.

[0056] In a manner similar to the foregoing exemplary embodiment, the semiconductor device 10B may include a power MOS transistor. However, in the semiconductor device 10B, according to the exemplary embodiment, although no drain trap ( Figure 2A 140) is employed, the drain region 145 can be directly formed with an impurity concentration higher than that of the drift region 120 (for example, about 10 19 / cm 3 or greater).

[0057] Meanwhile, the semiconductor device 10B according to the exemplary embodiment may further include an impurity region 195 of the first conductivity type provided in a region overlapping with the opening OG of the closed type. The impurity concentration of the impurity region 195 of the first conductivity type may be higher than that of the drift region 120. For example, the drift region 120 is n-type and may have an impurity concentration of about 1×10 15 / cm 3 to 1×10 17 / cm 3 , while the impurity region 195 of the first conductivity type is n-type and may have an impurity concentration of about 2×10 15 / cm 3 to 1×10 18 / cm 3 .

[0058] As described above, in order to reduce the effective length (or area) of the gate electrode 155, the opening OG of the closed type is formed. Therefore, the hot carrier SOA characteristics are reduced. To compensate for this reduction, the impurity region 195 of the first conductivity type can be additionally introduced.

[0059] The effective length of the gate electrode 155 can be determined based on the sum of the channel length and the drain overlap length (Ldov). Here, the channel length determines the threshold voltage Vth and the leakage characteristics of the power MOS transistor, and in addition to the parasitic capacitance Cgd, the drain overlap length also determines the hot carrier reliability. Therefore, since the closed-type opening OG is introduced, the parasitic capacitance can be reduced, but the hot carrier characteristics, which are the main reliability factors of the power MOS transistor, may be adversely affected.

[0060] As in the exemplary embodiment, in order to improve the hot carrier characteristics, the impurity region 195 of the first conductivity type can be formed through the closed-type opening OG to increase the impurity concentration in the drift region 120 under the gate electrode 155. In the impurity region 195 of the first conductivity type, after ion implantation, through a diffusion process, a part of the impurity region 195 of the first conductivity type can be located under the gate electrode 155.

[0061] Although the impurity region 195 of the first conductivity type expands through the diffusion process, the impurity region of the first conductivity type can be spaced apart from the body region 130. The distance "d" between the impurity region 195 of the first conductivity type and the body region 130 can be in the range of 0.1 μm to 0.3 μm, or can be greater than 0.3 μm.

[0062] The closed-type opening OG employed in the exemplary embodiment can be processed to allow its inner corner to have a rounded portion. Since the corner of the inner corner of the closed-type opening OG is replaced by a rounded portion, the electric field can be effectively dispersed.

[0063] Measure, compare, and evaluate the characteristics of the power MOS transistor according to the exemplary embodiment of the present disclosure and the power MOS transistor having a structure according to the prior art. The power MOS transistor (example) according to the exemplary embodiment of the present disclosure and the power MOS transistor having a structure according to the prior art (comparative example) are fabricated to have the same structure. Here, as Figure 3 、 Figure 4A and Figure 4B shown, the difference is that the gate electrode includes a closed-type opening, and the impurity region of the first conductivity type is formed through the closed-type opening, and each of the parasitic capacitance, breakdown voltage, and resistance characteristics of the power MOS transistor is measured.

[0064] Figure 5A and Figure 5B are graphs showing and comparing the parasitic capacitances (Cgg and Cgd) of the power MOS transistors according to the example and comparative example of the present disclosure.

[0065] Referring to Figure 5A and Figure 5B, since an opening of the closed type of the power MOS transistor according to the example is introduced, it can be seen that the gate-drain capacitance Cgd and the gate input capacitance Cgg are reduced by about 10% to 20% compared with the power MOS transistor according to the comparative example. As described above, it can be understood that the gate electrode length for forming the channel is reduced to reduce the gate input capacitance Cgg, and the drift overlap length is reduced to reduce the gate-drain capacitance Cgd.

[0066] Figure 6A and Figure 6B are graphs showing and comparing the BV characteristics and the resistance characteristic Rsp of the power MOS transistors according to the example and the comparative example of the present disclosure, and Figure 7 include graphs showing and comparing the hot carrier injection reliability of the power MOS transistors according to the example and the comparative example of the present disclosure.

[0067] Referring to Figure 6A and Figure 6B , in the power MOS transistor according to the example, although an opening of the closed type is introduced, it can be determined that, considering the breakdown voltage side and the resistance characteristic (Rsp), the characteristic level of the power MOS transistor according to the comparative example is maintained without significant change.

[0068] Referring to Figure 7 , in a manner similar to the breakdown voltage characteristic and the like, it can be confirmed that the reliability of hot carrier injection does not change significantly.

[0069] As described above, in the example embodiment, it can be understood that the hot carrier characteristics are maintained by the following method: forming an impurity region of the first conductivity type via the opening of the closed type to increase the impurity concentration under the gate electrode so as to facilitate maintaining the hot carrier characteristics, while reducing the parasitic capacitance due to the introduction of the opening of the closed type.

[0070] Figure 8 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure.

[0071] Referring to Figure 8 , except that a drain isolation insulating film 165 is adopted to have an STI structure, a first-conductivity-type impurity region 195 is additionally formed in the drift region 120 overlapping with the opening OG of the closed type, the inner corner of the opening OG of the closed type has a circular portion, and a drain well is not adopted, the semiconductor device 10C according to the example embodiment can be understood to have a structure similar to the structure of the semiconductor device 10A of the example embodiment shown in Figure 1 , Figure 2A and Figure 2B . Therefore, unless otherwise stated, Figure 1 , Figure 2A and Figure 2BThe description of the illustrated exemplary embodiment may be combined with the following description.

[0072] The semiconductor device 10C may include a power MOS transistor having a structure similar to that of the Figure 4B illustrated semiconductor device 10B. In the semiconductor device 10C, a drain trap ( Figure 2A 140) is not employed, and the drain region 145 may be formed directly in the drift region 120.

[0073] The drain isolation insulating film 165 employed in the exemplary embodiment may have an STI structure. For example, a trench (not shown) is formed in the upper portion of the drift region 120, the trench is filled with an insulating material such as silicon oxide, and then, the upper portion of the insulating film is flattened by a chemical mechanical polishing (CMP) process to form the STI structure for the drain isolation insulating film 165. The drain isolation insulating film 165 may be formed together with the device isolation portion 161 having the same / similar STI structure.

[0074] In a manner similar to that of the Figure 4B illustrated semiconductor device 10B, the semiconductor device 10C according to the exemplary embodiment may further include an impurity region 195 of a first conductivity type provided in a region overlapping with the closed-type opening OG. The impurity concentration of the impurity region 195 of the first conductivity type may be greater than the impurity concentration of the drift region 120. Although the effective length (or area) of the gate electrode 155 is reduced by introducing the closed-type opening OG, the hot carrier characteristics may be maintained due to the impurity region 195 of the first conductivity type.

[0075] As described above, below the gate electrode 155, in order to increase the impurity concentration of the drift region 120, the impurity region 195 of the first conductivity type may be formed through the closed-type opening OG. In the impurity region 195 of the first conductivity type, after ion implantation, a part of the impurity region 195 of the first conductivity type may be located below the gate electrode 155 through a diffusion process.

[0076] The closed-type opening OG according to the exemplary embodiment may have various shapes and sizes and may provide various arrangements. Figures 9A to 9C is a plan view of a semiconductor device showing closed-type openings having various arrangements.

[0077] Except for the arrangement of the closed-type opening OG, Figures 9A to 9C each of the layouts shown in may be understood as a layout the same as or similar to the layout according to the Figure 1 illustrated exemplary embodiment. Thus, unless otherwise specified, Figure 1 , Figure 2A and Figure 2B the description of the illustrated exemplary embodiment may be combined with the description provided below.

[0078] Refer to Figure 9A According to an exemplary embodiment, a semiconductor device may include a single closed-type opening OG1 formed in a gate electrode 155.

[0079] The closed-type opening OG1 employed in the exemplary embodiment has a relatively wide area and may have a quadrilateral shape extending in the width direction of the device. The inner corners of the closed-type opening OG1 may have rounded portions to assist in electric field diffusion. An impurity region 195 of a first conductivity type may be formed in a drift region ( Figure 2B 120) overlapping with the closed-type opening OG1 by using an ion implantation / diffusion process.

[0080] Refer to Figure 9B According to an exemplary embodiment, a semiconductor device may include three closed-type openings OG2 formed in a gate electrode 155.

[0081] The closed-type opening OG2 employed in the exemplary embodiment may have a quadrilateral shape extending in a direction (hereinafter, the first direction) along which a body region 130, a drift region ( Figure 2B 120), and a drain region 145 are arranged. The three closed-type openings OG3 may be arranged in a second direction intersecting the first direction between the body region 130 and the drain region 145.

[0082] In a manner similar to the above-described exemplary embodiment, the inner corners of the closed-type opening OG2 may have rounded portions to assist in electric field diffusion. In addition, an impurity region 195 of a first conductivity type may be formed in a drift region ( Figure 2B 120) overlapping with the closed-type opening OG2 by using an ion implantation / diffusion process. In the exemplary embodiment, since a part of the closed-type opening OG2 is located on a drain isolation insulating film 160, the impurity region 195 of the first conductivity type may not be formed in a part where the drain isolation insulating film 160 is provided, except for a diffused part.

[0083] Refer to Figure 9C According to an exemplary embodiment, a semiconductor device may include a plurality of closed-type openings OG3 formed in a gate electrode 155.

[0084] Each of the closed-type openings OG3 employed in the exemplary embodiment may be arranged in two rows in a second direction intersecting the first direction between the body region 130 and the drain region 145. In a manner similar to the above-described exemplary embodiment, the inner corners of the closed-type opening OG3 may have rounded portions to assist in electric field diffusion. In addition, an impurity region 195 of a first conductivity type may be formed in a drift region ( Figure 2BIn (120), an impurity region 195 of the first conductivity type is formed by using an ion implantation / diffusion process. In some embodiments, although the closed-type openings are divided into a plurality of closed-type openings, when the closed-type openings are arranged adjacent to each other, the impurity regions of the first conductivity type can be connected to each other in the diffusion process.

[0085] Figure 10 and Figures 11A to 13A is a cross-sectional view (II1-II1') of the main process for describing a method of manufacturing a semiconductor device 10B according to an exemplary embodiment of the present disclosure, and Figures 11B to 13B is a cross-sectional view (II2-II2') of the main process for describing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0086] Referring to Figure 10 , a gate electrode material layer is formed on a semiconductor substrate in which a body region and a drift region are formed.

[0087] The semiconductor substrate 100 may be set as a silicon substrate, a germanium substrate, a silicon germanium substrate, a SOI substrate, a GOI substrate, etc. In some embodiments, for example, an epitaxial layer formed from a silicon substrate or a germanium substrate by using an epitaxial growth process may be used as the semiconductor substrate 100. The transistor region is defined by the device isolation portion 161, and a well 110 of the second conductivity type, a drift region 120 of the first conductivity type, and a body region 130 of the second conductivity type may be formed on the upper portion of the semiconductor substrate 100 by using an ion implantation process. For example, the impurities of the first conductivity type include N-type impurities such as phosphorus or arsenic, while the impurities of the second conductivity type include P-type impurities such as boron.

[0088] A drain isolation insulating film 160 is formed on the semiconductor substrate 100, and then, a gate insulating film 151 and a gate electrode layer 155' may be formed in sequence. In the exemplary embodiment, the drain isolation insulating film may have a LOCOS structure. The gate insulating film may be formed conformally. The gate insulating film 151 includes silicon oxide and is formed by using a CVD process (as an example), but may also be formed by using a thermal oxidation process, as in the exemplary embodiment. The gate electrode layer 155' includes undoped or doped polysilicon, but the present invention is not limited thereto. The gate electrode layer may include a metal or a metal nitride. For example, the gate electrode layer 155' may be formed by using a sputtering process or an atomic layer deposition (ALD) process.

[0089] Referring to Figure 11A and Figure 11B , the gate electrode layer 155' is partially etched by using a first photoresist pattern PR1 to form a gate electrode 155.

[0090] In this process, a gate electrode 155 is formed over a part of a drift region 120 of a first conductivity type and a part of a body region 130 of a second conductivity type, and a part thereof may be patterned to be located on a drain isolation insulating film 160. As Figure 1 shown, the gate electrode 155 may extend in a second direction (e.g., the width direction). Specifically, as Figure 11B shown, the gate electrode 155 may be formed to have a closed-type opening OG, and a part of the gate insulating film 151 may be exposed through the closed-type opening OG.

[0091] In an exemplary embodiment, when the gate electrode 155 includes polysilicon, the gate electrode 155 may be formed by a gas-phase etching process using chlorine gas (as an example).

[0092] In addition, a first-conductivity-type impurity region 195 may be formed in the drift region overlapping the closed-type opening OG by an ion implantation / diffusion process. As described above, its hot carrier characteristics may be improved due to the first-conductivity-type impurity region 195.

[0093] Referring to Figure 12A and Figure 12B , a source region 135 and a drain region 145, a body contact region 132, and a first-conductivity-type impurity region 195 are formed, and a spacer 156 for the gate electrode 155 may be formed.

[0094] By an ion implantation process, impurities of a first conductivity type are implanted into the upper part of the semiconductor substrate 100 to form a source region 135 and a drain region 145. The source region 135 and the drain region 145 may be set as N+ regions. Alternatively, when manufacturing the semiconductor device as a P-type laterally diffused metal oxide semiconductor (P-LDMOS), the source region 135 and the drain region 145 may be set as P+ regions. Impurities of a second conductivity type are implanted into the inside of the second-conductivity-type body region 130 to form a second-conductivity-type body contact region 132 in contact with the source region 135. The second-conductivity-type body contact region 132 may be set as a P+ region. Alternatively, when the semiconductor device is set as a P-LDMOS, the second-conductivity-type body contact region 132 may be set as an N+ region.

[0095] An insulating layer is deposited on the semiconductor substrate 100, and then, an anisotropic etching or etch-back process is applied to form a spacer 156 on the sidewalls of the gate electrode 155. The spacer 156 may also be formed on the inner sidewalls surrounding the closed-type opening OG.

[0096] Referring to Figure 13A and Figure 13B, a second photoresist pattern PR2 is used to form a metal silicide layer 185 in the contact regions of the source region 135 and the drain region 145.

[0097] The second photoresist pattern PR2 has a first opening O1 and a second opening O2 that expose the contact regions of the source region 135 and the drain region 145, and a metal silicide layer 185 is formed in the contact regions of the source region 135 and the drain region 145 exposed through the first opening O1 and the second opening O2. In this process, when the gate electrode 155 includes polysilicon, the second photoresist pattern PR2 forms a third opening O3 that exposes the contact region of the gate electrode 155 to form the metal silicide layer 185. In this silicide formation process, the closed-type opening OG of the gate electrode 155 can be covered by the second photoresist pattern PR2 so as not to be exposed outward.

[0098] Then, an interlayer insulating film 170 covering the gate electrode 155 is formed on the gate insulating film 151, contact holes are formed in the interlayer insulating film 170, and a source contact plug 180S, a drain contact plug 180D, and a gate contact plug 180G that respectively fill the contact holes can be provided. For example, a conductive material filling the contact holes can be formed using a sputtering process or an ALD process to include, for example, a metal, a metal nitride, or doped polysilicon on the interlayer insulating film 170. The source contact plug 180S, the drain contact plug 180D, and the gate contact plug 180G can be connected to the source region 135, the drain region 145, and the gate electrode 155 respectively with low contact resistance through the metal silicide layer 185.

[0099] Figure 14 is a cross-sectional view showing a semiconductor device (power MOS transistor + memory device) according to an exemplary embodiment of the present disclosure. References to Figure 3 , Figure 4A and Figure 4B detailed descriptions of the configurations and / or structures described are omitted, and it can be assumed that they are at least similar to the corresponding elements described elsewhere, and the same reference numerals can be used to denote similar or identical elements described elsewhere.

[0100] Referring to Figure 14 , according to an exemplary embodiment, a semiconductor device can have a structure in which an LDMOS device and a memory device are integrated. The LDMOS device can have a structure and / or configuration similar to that described with reference to Figure 3 , Figure 4A and Figure 4B (specifically, Figure 4B ). For example, the memory device can include a flash memory device having non-volatile characteristics.

[0101] As Figure 14As shown, the semiconductor substrate 100 can be divided into a first region A and a second region B. The LDMOS device according to the above exemplary embodiment can be provided on the first region A of the semiconductor substrate 100. As described above, the drift region 120, the body region 130 of the second conductivity type, and the drain region 145 that are spaced apart from each other in the first direction can be provided in the upper portion of the substrate 100 in the first region A. The gate electrode 155 can extend in the first direction from one region of the body region 130 of the second conductivity type to one region of the drift region 120 on the gate insulating film 151. A part of the gate electrode 155 can be provided on the drain isolation insulating film 160. In some embodiments, the LDMOS device can be provided as a transistor, a converter, a booster for power control, so as to constitute a switched mode power supply (SMPS).

[0102] The second region B of the semiconductor substrate 100 can be provided as a memory region. For example, a plurality of memory cells 260 can be arranged in the first direction on the second region B of the semiconductor substrate 100. Each memory cell 260 can extend in the second direction.

[0103] The memory cell 260 can include a tunnel insulating film pattern 210, a charge storage pattern 220, a dielectric pattern 230, and a gate line 240 that are stacked in sequence on the upper surface of the semiconductor substrate 100. For example, the gate line 240 can be provided as a coupling gate or a control gate. A gate mask 250 can also be formed on the gate line 240. In some embodiments, the memory cell 260 can be formed using the film materials, deposition processes, and / or etching processes for manufacturing the LDMOS device.

[0104] In some embodiments, the gate insulating film 151 and the dielectric pattern 230 can have a structure in which a plurality of insulating films are stacked. The gate electrode 155 and the gate line 240 can include a metal, a metal silicide, and / or a metal nitride. For example, the gate mask 250 can include silicon nitride or silicon oxynitride. A spacer 265 including silicon nitride or silicon oxynitride can be formed on the sidewalls of the memory cell 260.

[0105] The interlayer insulating film 170 can cover the gate electrode 155 on the first region A and the memory cell 260 on the second region B. The impurity region 205 can be formed in the upper portion of the semiconductor substrate 100 between adjacent pairs of memory cells 260. A part of the impurity region 205 can be provided as a common source line (CSL).

[0106] The plug 270 can pass through the interlayer insulating film 170 to be electrically connected to the impurity region 205. For example, the plug 270 can be provided as a CSL contact or a bit line contact. The wire 280 electrically connected to the plug 270 can be provided on the interlayer insulating film 170. For example, the wire 280 can be provided as a bit line.

[0107] As described above, in the first region A and the second region B, materials and / or processes for forming an LDMOS device and a memory device can be combined. Accordingly, process integration and process efficiency can be improved.

[0108] As described above, according to an exemplary embodiment of the inventive concept, in a semiconductor device having a MOS structure, a closed-type opening is formed in a gate electrode, thereby reducing parasitic capacitances (Cgg and / or Cgd) to improve switching characteristics. At the same time, impurities are additionally implanted into a drift region through the closed-type opening, thereby improving hot carrier safe operating area (SOA) characteristics without reducing breakdown voltage.

[0109] Although the exemplary embodiments have been shown and described above, it will be apparent to those of ordinary skill in the art that modifications and changes can be made thereto without departing from the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor substrate; A drift region provided in the semiconductor substrate, the drift region having a first conductivity type; A body region provided in the semiconductor substrate, adjacent to the drift region, the body region having a second conductivity type different from the first conductivity type; A drain region provided in the drift region, opposite to the body region; A drain isolation insulating film provided in a part of the drift region adjacent to the drain region; A gate insulating film provided on the semiconductor substrate and extending over a part of the body region and a part of the drift region; And A gate electrode provided on the gate insulating film and having at least one opening completely surrounded by the gate electrode in a plan view, Wherein, the ratio of the area of the at least one opening to the area of the gate electrode is in the range of 2:8 to 8:

2.

2. The semiconductor device according to claim 1, wherein, The at least one opening has a region overlapping with the drift region.

3. The semiconductor device according to claim 2, further comprising: An impurity region of the first conductivity type provided in the region overlapping with the at least one opening.

4. The semiconductor device according to claim 3, wherein, The impurity concentration of the impurity region of the first conductivity type is greater than the impurity concentration of the drift region.

5. The semiconductor device according to claim 3, wherein, The impurity region of the first conductivity type is spaced apart from the body region.

6. The semiconductor device according to claim 5, wherein, The distance between the impurity region of the first conductivity type and the body region is at least 0.1 μm.

7. The semiconductor device according to claim 1, wherein, The at least one opening includes a plurality of closed-type openings.

8. The semiconductor device according to claim 7, wherein, The body region, the drift region and the drain region are arranged in a first direction, and the plurality of openings are arranged in a second direction intersecting the first direction between the body region and the drain region.

9. The semiconductor device according to claim 8, wherein, The plurality of openings are arranged in multiple rows.

10. The semiconductor device according to claim 1, wherein, The planar shape of the at least one opening has a circular part or its inner corner is an obtuse angle.

11. The semiconductor device according to claim 1, further comprising: A source region provided in the body region and having the first conductivity type, and A body contact region provided adjacent to the source region in the body region and having the second conductivity type.

12. The semiconductor device according to claim 1, wherein, The drain isolation insulating film includes a local oxidation of silicon provided on a region of the upper surface of the semiconductor substrate between the gate electrode and the drain region.

13. The semiconductor device according to claim 1, wherein, The drain isolation insulating film includes a shallow trench insulating member provided in a region of the semiconductor substrate between the gate electrode and the drain region.

14. A semiconductor device, comprising: A semiconductor substrate; A drift region provided in the semiconductor substrate, the drift region extending to the upper surface of the semiconductor substrate and having a first conductivity type; A body region provided in the semiconductor substrate and sharing a boundary with the drift region, the body region extending to the upper surface of the semiconductor substrate and having a second conductivity type different from the first conductivity type; A gate insulating film provided on the boundary between the body region and the drift region, the gate insulating film extending over a part of the body region and a part of the drift region; And A gate electrode is disposed on the gate insulating film and has a plurality of openings, each of which is completely surrounded by the gate electrode in a plan view. Wherein, each of the plurality of openings has a region overlapping with the drift region. Wherein, the semiconductor device further includes a plurality of impurity regions of a first conductivity type, the plurality of impurity regions of the first conductivity type respectively overlap with the plurality of openings and have an impurity concentration greater than that of the drift region.

15. The semiconductor device according to claim 14, further comprising: A drain region disposed opposite to the body region in the drift region and having the first conductivity type. A source region disposed in the body region and having the first conductivity type, and A body contact region disposed adjacent to the source region in the body region and having the second conductivity type.

16. The semiconductor device according to claim 15, further comprising: A drain isolation insulating film disposed between the drift region and the drain region.

17. A semiconductor device, comprising: A semiconductor substrate; A drift region disposed in the semiconductor substrate and having a first conductivity type; A body region disposed in the semiconductor substrate, adjacent to the drift region, and having a second conductivity type different from the first conductivity type; A drain region disposed in the drift region, opposite to the body region, and having the first conductivity type; A source region disposed in the body region and having the first conductivity type; A body contact region disposed in the body region, adjacent to the source region, and having the second conductivity type; A drain isolation insulating film disposed in a part of the drift region adjacent to the drain region; A gate electrode disposed on the semiconductor substrate and extending over a part of the body region and a part of the drift region, and having at least one opening completely surrounded by the gate electrode in a plan view; A gate insulating film disposed between the gate electrode and the semiconductor substrate; And An impurity region of a first conductivity type disposed in the drift region, overlapping with the at least one opening, and having an impurity concentration greater than that of the drift region, Wherein, the planar shape of the at least one opening has a circular part or its inner corner is an obtuse angle.

18. The semiconductor device according to claim 17, further comprising: A first contact plug and a second contact plug, the first contact plug being connected to both the body contact region and the source region, and the second contact plug being connected to the drain region.

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