Grayscale data display drive module and grayscale data transmission method

Abstract

The present application relates to a grayscale data display driving module and a grayscale data transmission method, which divides grayscale data into common integer data and remainder data, wherein the remainder data is divided into a plurality of remainder coefficient data, and then the common integer data and the remainder coefficient data are mixed and sent, so that the displayed PWM has the remainder coefficient data from the beginning, which reduces the space for data storage, reduces the chip cost, and makes the remainder coefficient data more evenly distributed in each frame, thereby improving the display effect.

Description

Technical Field

[0001] The present application relates to the field of grayscale display, and in particular to a grayscale data display driving module and a grayscale data transmission method. Background Art

[0002] Grayscale data is the data of grayscale display intensity of the display. In medium and high-level display screens, constant current source driver chips that can output high refresh PWM are usually used. Such chips usually receive and store all grayscale data, and then use PWM generation devices to generate PWM drive signals. Full storage of grayscale data requires a large memory, especially chips using ping-pong storage structure, which require two memories, which increases the cost of the chip. Based on this premise, a method of sending grayscale data separately is proposed. For example, the Chinese patent with publication number CN105096821B discloses a grayscale display driving method and a grayscale display driving device. In this patent, the grayscale display driving device calculates the grayscale data including high-significant bits and remainder bits according to the display data in the video signal, and then distributes the weights of the high-significant bits and remainder bits to m subframes, obtains multiple subframe bit weight sequences and multiple subframe bit value sequences, and outputs grayscale drive signals subframe by subframe to drive the LED of the LED display screen.

[0003] The patent provides a method of dividing grayscale data into high-significant bits and remainder bits, and then displaying them separately, which solves the problem of requiring a large memory to transmit grayscale data at one time, and also improves the refresh rate of grayscale data. To a certain extent, it solves the problems of uneven display and low refresh rate during grayscale display. However, the patent does not solve the display problem during grayscale data transmission. Generally, grayscale data is transmitted using a data bus. At present, driver chips generally use a data bus, and when grayscale data is divided into high-significant bits and remainder bits for display, the high-significant bits and remainder bits of grayscale data are transmitted separately.

[0004] For devices that receive common integer data and remainder coefficient data separately, receiving the common integer requires a certain amount of bus time (bus bandwidth). Furthermore, in the case of receiving the common integer first and then the remainder coefficient, the grayscale is incomplete before the remainder coefficient is received, and the display effect is poor, especially for low-gray data, the picture display effect is even worse. Summary of the invention

[0005] The purpose of the present application is to overcome the shortcomings of the prior art and to provide a grayscale data display driving module and a grayscale data display transmission method, which not only reduces the chip cost but also makes the remainder coefficient data more evenly distributed in each frame by mixing the sending and receiving of integer data and remainder coefficient data, thereby improving the display effect.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] A grayscale data display driving module comprises a first storage unit, a remainder coefficient analysis unit and a PWM generation unit;

[0008] A first storage unit stores common integer data and remainder high-bit data of grayscale data, and the common integer data is output to the PWM generation unit;

[0009] A remainder coefficient analysis unit controls the first storage unit to selectively output the remainder high-bit data to the PWM generation unit;

[0010] When the first storage unit does not output the remainder high-order data, the remainder coefficient data is transmitted to the PWM generating unit via the data bus;

[0011] The PWM generating unit generates PWM for display according to the common integer data and the remainder high-order data or the remainder coefficient data.

[0012] In order to improve the uniformity of grayscale data display and reduce the memory capacity and thus reduce the chip cost, the present application divides the grayscale data into common integer data and remainder data, wherein the remainder data is divided into a number of remainder coefficient data, and only the common integer data and the remainder high-order data are stored when transmitting data, which greatly reduces the amount of data storage, reduces the requirements for the memory, and reduces the capacity and size of the memory, thereby reducing the cost. During the transmission process, the common integer data and the remainder coefficient data are mixed and sent, so that in the display PWM, there is remainder coefficient data + common integer data at the beginning, and there is no need to display multiple common integers additionally, thereby solving the problem of needing to display several groups of common integers or waiting for remainder coefficient data during the transmission of traditional common integer data and remainder coefficient data, making the PWM display more uniform.

[0013] Further, the remainder coefficient data is sent to the remainder coefficient parsing unit, parsed by the remainder coefficient parsing unit and transmitted to the PWM generating unit;

[0014] or,

[0015] The remainder coefficient data is sent to the first storage unit for storage, parsed by the remainder coefficient parsing unit and then transmitted to the PWM generating unit;

[0016] or,

[0017] The remainder coefficient data is sent directly to the PWM generation unit.

[0018] The public integer needs to be used repeatedly, so the complete public integer must be stored in the first storage unit. Here, the public integer data stored in the first storage unit refers to the public integer data corresponding to all channels of the driver module (driver chip). That is to say, after the public integer is sent, there is no need to send the public integer again, that is, only the remainder coefficient data is sent.

[0019] Furthermore, the first storage unit is composed of a memory 1-A and a memory 1-B, and the memory 1-A and the memory 1-B adopt a ping-pong structure to alternately send and receive data; or, the first storage unit includes only one memory.

[0020] The use of a ping-pong structure to alternately send and receive data can completely solve the problem of screen tearing. Its disadvantage is that the structure cost is higher than that of a single memory. However, compared with the traditional mode, the capacity of memory 1-A and memory 1-B in this solution are smaller, which means that it still has a lower cost technological advancement compared to the existing technology.

[0021] Furthermore, within a complete display frame, the common integer data and remainder high-order data of the current display frame are stored in the memory 1-A, and when the memory 1-A outputs the remainder high-order data, the data bus transmits the common integer data and remainder high-order data of the next display frame to the memory 1-B.

[0022] The present application also provides another grayscale data display driving module, including:

[0023] It includes a first storage unit, a second storage unit and a PWM generating unit;

[0024] A first storage unit stores common integer data of grayscale data and outputs the data to the PWM generation unit;

[0025] A second storage unit stores the remainder data of the grayscale data and outputs it to the PWM generating unit. After the remainder data is displayed, the remainder data of other bits is stored and continuously output to the PWM generating unit until all the remainder data are displayed.

[0026] A PWM generation unit generates PWM for display according to the common integer data and the remainder data;

[0027] or,

[0028] It also includes a remainder coefficient parsing unit, which controls the second storage unit to selectively output remainder data to the PWM generating unit, and the remainder data is remainder high-order data;

[0029] When the second storage unit does not output the remainder high-order data, the remainder coefficient data is transmitted to the PWM generation unit via the data bus;

[0030] The PWM generating unit generates PWM for display according to the common integer data and the remainder high-order data or the remainder coefficient data.

[0031] Compared with the grayscale data display driving module described above, the difference of the other grayscale data display driving module here is that a second storage unit is added to store remainder coefficient data, but the storage capacity of the first storage unit is reduced relatively, because the first storage unit can only store public integer data. Compared with traditional technology, the present application still has a lower cost technical progress.

[0032] Furthermore, the storage capacity of the second storage unit is smaller than that of the first storage unit.

[0033] Furthermore, the first storage unit is composed of a memory 1-A and a memory 1-B, and the memory 1-A and the memory 1-B use a ping-pong structure to alternately send and receive data; or, the first storage unit includes only one memory. Using a ping-pong structure to alternately send and receive data can completely solve the problem of screen tearing. Its disadvantage is that the cost is higher than that of a single memory structure, but compared with the traditional mode, the capacity of the memory 1-A and the memory 1-B in this solution are both smaller, that is, it still has a lower cost technology progress compared with the existing technology.

[0034] Furthermore, within a complete display frame, the common integer data and remainder data used by the current display frame are stored in the memory 1-A, and when the memory 1-A outputs the remainder data, the data bus transmits the common integer data and remainder data of the next display frame to the memory 1-B.

[0035] Furthermore, the common integer data and the remainder high-order data are mixed and sent, including:

[0036] The common integer data and the remainder high-order data are mixed to form data packet A for cyclic transmission;

[0037] or;

[0038] The public integer data is sent as data packet A, the remainder high-order data is sent as data packet B, and data packet A and data packet B are sent mixedly;

[0039] or;

[0040] The common integer data and the remainder high-order data are mixed to form data packet A, and the remainder coefficient data is used as data packet B. Data packet A and data packet B are mixed and sent.

[0041] Since it is necessary to selectively output the common integer data and the remainder high-order data, that is, both the common integer data and the remainder high-order data need to be stored, when sending data, if the common integer data is sent first, and then the remainder high-order data is sent after the common integer data is sent, it will cause the remainder coefficient data to be missing in the initial stage of the display. In this application, the common integer data and the remainder high-order data are mixed and sent and stored.

[0042] Further, the remainder coefficient analysis unit and the PWM generation unit are packaged together as a PWM generation device;

[0043] or;

[0044] The PWM generating unit is packaged as a PWM generating device, and the remainder coefficient analyzing unit is electrically connected to the PWM generating device.

[0045] Further, the PWM generating unit or the remainder coefficient parsing unit stores the remainder coefficient data and the weight W of the remainder data. R ;

[0046] The gray value actually displayed by the remainder coefficient data and the remainder high-order data = W R × remainder coefficient data / remaining high-order data, the W R =2 x , where x is an integer.

[0047] Furthermore, when x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes:

[0048] Display the remainder low-order data D[j] in the PWM whose remainder coefficient data is always 0, where j takes the value of [0, x-1];

[0049] or,

[0050] The remainder coefficient data is always 0 in the PWM and the additional PWM, and the remainder low-order data D[j] is displayed, where j takes the value of [0, x-1];

[0051] or,

[0052] The remainder low-order data D[j] is displayed in the PWM when the remainder coefficient data does not need to be transmitted, where j takes the value of [0, x-1].

[0053] Furthermore, when the remainder low-order data D[j] is displayed in the PWM when the remainder coefficient data does not need to be transmitted, the corresponding PWM display period is extended to ensure that the grayscale value corresponding to the display period is greater than or equal to the common integer data+remainder coefficient data+remainder low-order data D[j];

[0054] Or, the corresponding PWM display period is not extended. When the common integer data + remainder coefficient data + remainder low-order data D[x-1:0] is greater than the grayscale data corresponding to the PWM, the overflow part is ignored.

[0055] In a complete display frame, the first M groups of PWM or the first M odd-numbered groups of PWM use the common integer data and remainder high-order data stored in the first storage unit for display, and the remaining groups of PWM alternately use the remainder high-order data stored in the first storage unit and the remainder coefficient data transmitted by the data bus.

[0056] Further, the remainder high-order data is the i-th bit of the remainder data, or the [(ib),i]-th bit; the remainder data of other bits are used as remainder coefficient data, wherein 1≤b;

[0057] Alternatively, the remainder high-order data is obtained by calculating the remainder data.

[0058] That is, when the common integer data and the remainder coefficient data are mixed and sent as a data packet, each data packet A contains only 1 bit or i bit of remainder coefficient data. In order to reduce the storage space of the first storage unit, it is the best choice to contain only 1 bit of remainder coefficient data in the data packet A. According to the width of the data bus, 2-3 data packets A are sent each time, and generally the total does not exceed 16 bits (the transmission bandwidth of the data bus is generally 16 bits). When the grayscale data is not binary, the remainder high-bit data can also be confirmed by looking up a table.

[0059] Furthermore, within a display frame period, the display timing of PWM is:

[0060] Timing 1: The odd-numbered PWM includes common integer data and remainder high-order data, and the even-numbered PWM includes common integer data and remainder coefficient data; or the even-numbered PWM includes common integer data and remainder high-order data, and the odd-numbered PWM includes common integer data and remainder coefficient data;

[0061] or,

[0062] Timing 2: The first M groups of PWM include common integer data and remainder high-order data, and the remainder coefficient data and remainder high-order data are displayed alternately in the remaining PWM, and the common integer is sent completely within the M groups of PWM display period.

[0063] Furthermore, the remainder coefficient parsing unit controls the first storage unit to output the remainder high-bit data to the PWM generating unit according to timing 1 or timing 2.

[0064] Furthermore, between each display frame, a dynamic switching method is adopted to switch between the timing 1 and the timing 2.

[0065] Furthermore, the switching between timing 1 and timing 2 is completed through a controller / logic processing module, and the controller / logic processing module is connected to the remainder coefficient analysis unit. The controller / logic processing module has a built-in threshold K, and controls the remainder coefficient analysis unit according to the threshold K to analyze the remainder coefficient data stored in the first storage unit or the remainder coefficient data transmitted by the data bus.

[0066] Furthermore, the timing 1 and the timing 2 are dynamically switched according to the grayscale of the picture. When the grayscale of the picture is greater than or equal to the grayscale threshold K, the timing 2 is used, and when it is less than the grayscale threshold K, the timing 1 is used.

[0067] Furthermore, the grayscale threshold K represents:

[0068] The grayscale value of a complete display frame;

[0069] Or, the average gray value corresponding to each PWM in a complete display frame;

[0070] Or, determine whether the integer is less than a certain threshold value, and further, count the number of pixels meeting the condition in the display area to see whether it is less than a certain preset value.

[0071] Further, the remainder coefficient analysis unit and the PWM generation unit are packaged together as a PWM generation device;

[0072] or;

[0073] The PWM generating unit is packaged as a PWM generating device, and the remainder coefficient analyzing unit is electrically connected to the PWM generating device.

[0074] Furthermore, the PWM generating unit or the remainder coefficient parsing unit stores the remainder coefficient data and the weight W of the remainder high-order data. R ;

[0075] The PWM generation unit generates the PWM signal according to the common integer data, the remainder coefficient data and the weight W. R Generate PWM for display, the gray value actually displayed by the remainder coefficient data and the remainder high-order data = W R × remainder coefficient data / remaining high-order data, the W R =2 x , where x is an integer.

[0076] Furthermore, when x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes:

[0077] Display the remainder low-order data D[j] in the PWM whose remainder coefficient data is always 0, where j takes the value of [0, x-1];

[0078] or,

[0079] The remainder coefficient data is always 0 in the PWM and the additional PWM, and the remainder low-order data D[j] is displayed, where j takes the value of [0, x-1];

[0080] or,

[0081] The remainder low-order data D[j] is displayed in the PWM when the remainder coefficient data does not need to be transmitted, where j takes the value of [0, x-1].

[0082] Furthermore, when the remainder low-order data D[j] is displayed in the PWM when the remainder coefficient data does not need to be transmitted, the corresponding PWM display period is extended to ensure that the grayscale value corresponding to the display period is greater than or equal to the common integer data+remainder coefficient data+remainder low-order data D[j];

[0083] Or, the corresponding PWM display period is not extended. When the common integer data + remainder coefficient data + remainder low-order data D[x-1:0] is greater than the grayscale data corresponding to the PWM, the overflow part is ignored.

[0084] A grayscale data transmission method, the method comprising:

[0085] S100: Data grouping, dividing each frame of grayscale data into common integer data and remainder data, wherein the remainder data is divided into several groups of remainder coefficient data;

[0086] S200: Data transmission: firstly, the common integer data and part of the remainder coefficient data are mixed and transmitted, and then, after the common integer data is transmitted, the remaining remainder coefficient data is transmitted.

[0087] Further, the transmission timing of the common integer data and the partial remainder coefficient data includes:

[0088] Sequence A1: The common integer data and part of the remainder coefficient data are sent in the first M groups of sequences;

[0089] Timing A2: The common integer data and part of the remainder coefficient data are sent in the timing of the first M odd groups.

[0090] Furthermore, the timing A1 and timing A2 can be switched between each display frame according to the grayscale threshold K. When the grayscale of the picture is greater than or equal to the threshold K, the timing A2 is used, and when it is less than the threshold K, the timing A1 is used.

[0091] Further, the data sending in S200 includes:

[0092] S201: The common integer data and part of the remainder coefficient data are formed into a data packet A, and the remaining remainder coefficient data are formed into a data packet B;

[0093] S202: Data transmission, first cyclically sending data packet A, then sending data packet B; or first mixedly sending data packet A and data packet B, then sending data packet B;

[0094] or;

[0095] S201: The common integer data is formed into a data packet A, part of the remainder coefficient data is formed into a data packet B1, and the rest of the remainder data is formed into B2;

[0096] S202: Data transmission: firstly, mixedly transmit data packet A and data packet B1, and then transmit data packet B2.

[0097] Furthermore, the partial remainder coefficient data is the remainder high-order data t in the remainder data.

[0098] Further, the remainder high-order data is the i-th bit of the remainder data, or the [(ib),i]-th bit; the remainder data of other bits are used as remainder coefficient data, wherein 1≤b;

[0099] Alternatively, the remainder high-order data is obtained by calculating the remainder data.

[0100] Further, the common integer data and part of the remainder coefficient data are stored in a driver chip;

[0101] The remaining remainder coefficient data is not stored or is stored in the driver chip.

[0102] Furthermore, the weight W of the remainder coefficient data R =2 x , where x is an integer.

[0103] Furthermore, when x≥1, it is necessary to send the remainder low-order data D[x-1:0] in addition;

[0104] The remainder low-order data D[x-1:0] is sent in an idle timing group;

[0105] Or, add several groups of timing to send the remainder low-order data D[x-1:0].

[0106] Furthermore, the idle timing groups can be used to transmit the common integer data and part of the remainder coefficient data of the next display frame as well as the register data and the double-edge instructions.

[0107] The beneficial effects of this application are:

[0108] (1) Compared with the traditional grayscale data transmission, the grayscale data in the present application is divided into common integer data and remainder data, wherein the remainder data is divided into a number of remainder coefficient data, and only the common integer data is stored during storage. Compared with the traditional mode, the present application has lower requirements for the memory, which can reduce the memory capacity and size, and save chip costs;

[0109] (2) During the data transmission process, the present application sends the common integer data and the remainder coefficient data in a mixed manner, so that the remainder coefficient data is already available when the common integer is displayed, thereby making the screen display more uniform and avoiding gray jumping;

[0110] (3) The common integer data and the remainder coefficient data are sent together. When displayed, the remainder coefficient data is available from the beginning, so there is no need to display the common integer additionally, thus avoiding image distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] Figure 1 is the hardware schematic diagram of this application;

[0112] Figure 2 This is a principle block diagram of an embodiment of the present application;

[0113] Figure 3 It is another principle block diagram of an embodiment of the present application;

[0114] Figure 4 This is a schematic diagram of the cyclic sending of data packet A;

[0115] Figure 5 This is a schematic diagram of mixed transmission of data packet A and data packet B;

[0116] Figure 6 This is another schematic diagram of data packet A and data packet B being sent in a mixed manner;

[0117] Figure 7 It is a schematic diagram of the principle of storing the remainder coefficient data separately in this application;

[0118] Figure 8 This is the schematic diagram of the storage of all the remainder coefficients;

[0119] Fig. 9 It is a schematic diagram of data receiving and displaying in the prior art;

[0120] Fig.10 It is a prior art data packet sending and display relationship diagram;

[0121] Fig.11 This is the schematic diagram of data reception and display in this application;

[0122] Fig.12 This is the relationship diagram between sending and displaying the data packet;

[0123] Fig.13 is a schematic diagram of timing 1;

[0124] Fig.14 It is a schematic diagram of timing 2;

[0125] Fig.15 This is the structural principle diagram of the dynamic switching between timing 1 and timing 2;

[0126] Fig.16 is a schematic diagram of a data transmission system;

[0127] Fig.17 It is a schematic diagram of the composition of data packet A and data packet B;

[0128] Fig.18 It is a diagram showing the relationship between the first-issue remainder coefficient data and the display;

[0129] Fig.19 It is a principle block diagram of the first storage unit adopting a ping-pong structure;

[0130] Fig. 20 It is a schematic diagram of data transmission and display when multiple remainder coefficient data are not scattered;

[0131] Fig.21 It is another schematic diagram of data transmission and display when multiple remainder coefficient data are not scattered;

[0132] Fig. 22 It is another schematic diagram of data transmission and display when multiple remainder coefficient data are not scattered;

[0133] Fig.23 This is an example diagram of grayscale data being divided into 32 groups for transmission;

[0134] Fig.24 This is an example diagram of grayscale data being divided into 64 groups for transmission;

[0135] Fig.25 It is a waveform diagram of a single pulse display;

[0136] Fig.26 It is the optimized display waveform. DETAILED DESCRIPTION

[0137] The technical solution of the present application is further described in detail below in conjunction with specific embodiments, but the protection scope of the present application is not limited to the following.

[0138] It should be noted that, unless otherwise specified, the remainder data and common integer data in this embodiment and the foregoing description all refer to the grayscale data of the same display frame in the LED display screen.

[0139] In a complete display frame, grayscale data is divided into common integer data and remainder data. Take a 13-bit binary grayscale data as an example, and define the 13-bit data as D[12:0], that is, a data with a bit width of 13 bits. At present, the maximum grayscale data is generally 16 bits. No matter how large the grayscale data is, the principle of dividing the common integer data and remainder data is as follows:

[0140] Public integer data Find the whole function;

[0141] Remainder Data Remainder function;

[0142] Where N is the integer part weight, which can be understood as the number of groups of common integer data. For example, in this embodiment, let N = 64, that is, it includes 64 groups of common integer data, that is, Q = D[12:6], R = D[5:0]. In other words, the common integer data is the 7-bit high-order data of grayscale data, and the remainder data is the 6-bit low-order data of grayscale data, which is a total of 64 PWMs. Each 1 bit, 2 bits or more bits in the 6-bit low-order data are remainder coefficient data.

[0143] In addition to the above methods, the present embodiment also provides another division method in this field. For example, a 13-bit grayscale data is expressed as a 13-bit binary digital string in data form. The 13-bit binary digital string is split into common integer data and remainder data, that is, the division is performed according to the data bits. The high-order data is used as the common integer data and the low-order data is used as the remainder data, wherein the high-order data and the low-order data are relative. When the number of division bits is determined, the high-order data and the low-order data are automatically generated. For example, in a 13-bit grayscale data, when the lower 6 bits are defined as the remainder data, the upper 7 bits are automatically used as the common integer data, that is, the 1st to 6th bits of data are low-order data, and the 7th to 13th bits are high-order data, and vice versa. When the high-order data is determined, the low-order data is also naturally determined.

[0144] That is to say, the essence of dividing the grayscale data into common integer data and remainder data is to divide the grayscale data into high-order data and low-order data. This is also a commonly used decomposition method in this field. For example, in the patent with publication number CN105096821B, the grayscale display driving method and the grayscale display driving device divide the grayscale data into high-significant bits and low-significant bits.

[0145] Based on the decomposition, it can be seen that for any grayscale data, the common integer data is fixed. For example, when the grayscale value is 1110111111011, the common integer data is fixed to 1110111, and its weight is 64, which means that it needs to be displayed 64 times, which is equivalent to the common integer data needing to be displayed 64 times in a cycle. Therefore, the common integer data is stored in this application for repeated use. Compared with the traditional mode, the entire grayscale data is stored in 13 bits. This application only stores 7 bits of the common integer, which is equivalent to saving nearly half of the memory capacity. Therefore, this application has technical progress in lower chip cost and smaller memory size.

[0146] The remainder data can be further split as follows:

[0147] R[5]: Displayed in 32 groups.

[0148] R[4]: Displayed in 16 groups.

[0149] R[3]: Displayed in 8 of the groups.

[0150] R[2]: Displayed in 4 of the groups.

[0151] R[1]: Displayed in 2 of the groups.

[0152] R[0]: Displayed in one of the groups.

[0153] Among them, R[0]-R[5] is the order of the remainder coefficient data, that is, the remainder data is decomposed into 1-bit data (it can also be decomposed into multiple bits), and each bit of the remainder coefficient data may be different. Among them, R[5] can determine the remainder coefficients in 32 groups of PWM, that is, it represents the value of 32 remainder coefficient data, R[4] can determine the remainder coefficients in 16 groups of PWM, R[3] can determine the remainder coefficients in 8 groups of PWM, and so on. The total is 63 groups, that is, 63 remainder coefficient data R i , numbered in the order in which they are displayed, i.e. R 1 -R 63 That is, there is a group of PWM that does not contain a remainder coefficient, but only a common integer, or the remainder coefficient of the group can be considered to be fixed at 0, which is equivalent to each of the 64 PWMs containing a common integer data and remainder coefficient data. The PWM that contains both common integer data and remainder coefficient data is called a complete PWM in this application.

[0154] The above is N value 2 nAn example of this case, in which the common integer data and the remainder data can be divided exactly according to the number of binary bits, that is, the high bit of the grayscale data is used as the common integer data, and the low bit of the grayscale data is used as the remainder data. This is the most preferred and most common in the example application. At this time, the common integer data, remainder data, and remainder high bit data can be directly taken out from the grayscale data level. For example, R[5] above is the highest bit of the remainder data, R[4] is the second highest bit of the remainder data, and so on. The remainder high bit data mentioned in this application can be any one except R[0], but in general, R[1] and R[2] are not satisfied.

[0155] When the value of N is not 2 n , it cannot be limited by the high or low bits of the grayscale data. In this case, the public integer data and the remainder coefficient data are calculated, or determined by a lookup table (its essence is background calculation). Let's take 1110111111011 as a column to illustrate. Converting it to a decimal number is 7675. Let N = 40, then the public integer data After calculation, the public integer becomes 191, which is 10111111 in binary. The remainder data is 35, which is 100011 in binary. Obviously, neither 10111111 nor 100011 is directly taken from 1110111111011 by bit, but is confirmed by calculation. In this case, the public integer data can still be represented by 10111111, and 10111111 is also stored when it is stored. However, the remainder data cannot be taken from 100011. The remainder data 35 here means that among the 40 groups of PWM, the remainder coefficient of 35 groups is 1, and the remaining 5 groups are 0. If 100011 is represented by R[0]-R[5], it also represents 63 groups. That is, in this case, the remainder high-order data cannot be directly taken from 100011 by bit. Instead, it can only be taken by calculation. Assuming that the weight of the remainder coefficient is 1, the remainder data is less than 40. Assuming that the high bit of the remainder stores 1 bit, we can set the high bit of the remainder to 1 when the remainder data is greater than or equal to 20 (indicating that the remainder coefficient data is 1 in 20 groups), otherwise the high bit of the remainder is 0, and the remaining remainder coefficients are transmitted in real time through the data bus. Then the high bit of the remainder 1 stored in the memory can be used as the remainder coefficients of 20 groups, and the high bits of the remainder of these 20 groups do not need to be transmitted multiple times through the bus. In this example, the high bit of the remainder is not taken from a certain bit of the remainder data, but is calculated through the remainder data. The calculation principle is that the high bit of the remainder can determine the remainder coefficients of multiple groups, and the high bit of the remainder multiplied by the number of groups plus the remainder coefficients of the remaining groups, the sum is equal to the remainder data. The existence of the high bit of the remainder makes it unnecessary to send the remainder coefficients of several groups repeatedly through the bus, saving bus time for sending other data, such as integer data. It is not necessary to limit the remainder data to be greater than 20, as long as the remainder high-order data can represent multiple groups of remainder coefficient data. For example, even if the remainder data is 10, the remainder high-order data can be set to 1, indicating that the remainder coefficient is 1 in 10 groups. It only needs to meet the requirement that the public integer can be sent in the timing of displaying 10 groups of PWM. The calculation of the remainder coefficient data and the public integer data by the lookup table is also applicable to N value 2 n situation.

[0156] In addition to the above binary grayscale data, the principle of decimal and hexadecimal data processing is the same. In this embodiment, decimal numbers are introduced. For example, the decimal data 8191, assuming that N=64, the common integer data is 127, and 63 is the remainder data, then 8191 includes 64 groups of 127, and the remainder data 63 can be displayed as 1 in each group, and the remaining group does not contain remainder data, or it is considered that the remainder data of this group is always 0. The principle is exactly the same as that of binary. The final result expressed in this way is still 8191.

[0157] refer to Figure 1 As shown, a grayscale data display driving module is hereinafter referred to as a driving chip or chip, including a first storage unit 100, a remainder coefficient parsing unit 400 and a PWM generating unit 200. The first storage unit 100 stores common integer data and remainder high-order data of grayscale data, and the common integer data is output to the PWM generating unit 200. The remainder coefficient parsing unit 400 controls the first storage unit 100 to selectively output the remainder high-order data to the PWM generating unit 200. The selective output referred to here means that the first storage unit 100 can output the remainder high-order data to the PWM generating unit 200 for use in any group, and is not limited to certain fixed groups. When the first storage unit 100 does not output the remainder high-order data, the remainder coefficient data is transmitted to the PWM generating unit 200 by the data bus. Assuming that the remainder coefficient data displayed in the 1st, 2nd, 3rd, 5th, 7th, and 8th groups use the remainder high-order data stored in the first storage unit 100, the remainder coefficient data displayed in the 4th and 6th groups are transmitted through the data bus. The PWM generating unit 200 generates PWM for display according to the common integer data and the remainder high-bit data or the remainder coefficient data.

[0158] In a complete display frame, it is divided into N groups of PWM, where N is the integer part weight mentioned above, and each PWM includes a common integer data and remainder coefficient data (from the above analysis, it can be seen that there is actually one group of PWM that does not contain remainder coefficient data), and the remainder coefficient data here is either directly transmitted from the data bus, or obtained from the remainder high-order data stored in the first storage unit 100. Among them, the common integer data and the remainder coefficient data can be displayed as one PWM, or as two PWMs, whether one or two, are called a group of PWM. Usually, it is displayed as one PWM. The core of this application is to divide the original display frame into N groups of PWM for display. That is, the generated PWM includes two types of PWM, one PWM is composed of common integer data + remainder high-order data, and the other PWM is composed of common integer data + remainder coefficient data.

[0159] More specifically, the first storage unit 100 is connected to the data bus, receives data packets transmitted from the data bus for storage, and the data stored in the first storage unit 100 includes not only common integer data but also remainder high-order data. The first storage unit 100 provides the stored data for use by the remainder coefficient analysis unit 400 and the PWM generation unit 200.

[0160] The remainder coefficient analysis unit 400 includes two input interfaces, one of which is connected to the data bus to receive the data packet transmitted from the data bus to analyze and output the remainder coefficient data, and the other interface is connected to the first storage unit 100 to read the stored remainder high-order data to analyze and obtain the corresponding remainder coefficient data. When the remainder coefficient analysis unit 400 uses the remainder high-order data stored in the first storage unit 100 to generate the remainder coefficient data, the data bus is in an idle state and can be used to send register data or double rising edge instructions, etc. When the remainder coefficient analysis unit 400 does not use the remainder high-order data stored in the first storage unit 100 to generate the remainder coefficient data, the data bus directly sends the remainder coefficient data to the remainder coefficient analysis unit 400 or the PWM generation unit 200.

[0161] If the remainder coefficient data is not stored, the remainder coefficient data needs to be sent through the data bus, that is, it needs to be sent 63 times. In addition, the public integer data needs to be sent, and the public integer data generally needs to be sent multiple times. Under normal circumstances, the data bus transmission capacity is generally 16 bits. For a 16-channel chip, the amount of public integer data required is 16*7 bits, and the data bus can only send 2 7-bit public integer data at a time, so it takes 8 times to complete the transmission. When transmitting the public integer data, the remainder coefficient data is lacking, which makes the displayed PWM lack the remainder coefficient data, making the picture uneven and the performance poor. Therefore, the general practice at present is not to display when sending public integer data. The principle is as follows: Fig. 9 and Fig.10 As shown, this situation will cause black fields between frames. When the chip refresh rate is large enough, it is generally difficult to detect with the naked eye. In order to solve this problem, the art has adopted the method of additionally displaying public integer data when the remainder coefficient data is missing, but this will cause gray jumping phenomenon and the picture uniformity is not enough.

[0162] In order to solve this technical problem, the present application mixes the common integer and the remainder coefficient data (remainder high-order data) and sends them so that the remainder coefficient data is available at the beginning of the display, thereby ensuring the integrity of PWM and improving the display effect. The principle is as follows: Fig.11 and Fig.12 As shown, reference Fig.11 As shown, there is a certain delay between the reception and display of data. The length of this delay is limited by the transmission rate of the data bus. Generally, this delay cannot be observed by the naked eye. Therefore, in the subsequent schematic diagrams, the reception and display are generally regarded as synchronous. However, those skilled in the art should know that in fact, this delay still exists. For example, Fig.12 In the example above, the public integer data packet is aligned with the display, where Fig.12 The first public integer data packet on the left refers to the public integer data of the previous displayed frame rather than the current frame.

[0163] In one embodiment, the specific implementation scheme of mixed transmission of common integer and remainder coefficient data is as follows:

[0164] In the front section of the display frame, the common integer data and the remainder coefficient data are mixed and sent to the first storage unit 100 for storage. That is, when the common integer data is sent, the remainder coefficient data is also stored in the first storage unit 100, so that the PWM generating unit 200 can read not only the common integer data but also the remainder coefficient data, thereby generating a complete PWM for display.

[0165] Taking the 13-bit grayscale data as an example, the public integer data is 7 bits. If 2 public integer data are sent each time, it will occupy a data width of 14 bits, so an additional 2 bits of remainder coefficient data can be sent.

[0166] Since the public integer data needs 8 transmissions to complete, that is, 2bit*8=16bit of remainder coefficient data can be sent additionally, and the chip has 16 channels, that is, each channel corresponds to 1bit of remainder coefficient data. In other words, 2bit of remainder coefficient data can be sent each time, and the public integer data is 2, that is, 1 data packet includes data of 2 channels, that is, each channel corresponds to 7bit of public integer data and 1bit of remainder coefficient data. The schematic diagram can be referred to Fig.17 shown.

[0167] In addition to the above-described embodiments, when the public integer data is less than 7 bits, the remainder coefficient data that can be sent is greater than 1 bit, as long as the public integer data + remainder coefficient data ≤ 16 bits is satisfied. Those skilled in the art should know that any data combination that meets this formula should be included in the protection scope of this application.

[0168] Obviously, in order to reduce the capacity of the memory as much as possible, that is, to reduce the capacity of the first storage unit 100, the remainder coefficient data is naturally as small as possible, so it is the best choice to store only 1 bit of remainder coefficient data for each channel. For example, in the above 13-bit grayscale data, the remainder coefficient data is 6 bits, namely R[0]-R[5]. So which remainder coefficient data is best to store? Since the common integer data needs 8 times to be sent, and the time and display of sending data are basically equal, that is, when sending the common integer data, 8 PWMs are displayed. In order to ensure that there is remainder coefficient data in each PWM, it should be required that the stored remainder coefficient data can be displayed in at least 8 groups. Obviously, R[0]-R[2] do not meet this requirement, while R[3]-R[5] all meet this requirement. That is to say, the stored remainder coefficient data should be the remainder high-bit data. The principle can be referred to. Figure 3 shown.

[0169] Furthermore, which bit of the remainder coefficient data is best to store in R[3]-R[5]? Since the remainder coefficient data can only store one bit, the rest needs to be transmitted through the data bus. Based on the above analysis, it can be seen that R[5] needs to be displayed in 32 groups, that is, it needs to be transmitted 32 times. Obviously, when storing the highest bit of the remainder coefficient data, the time occupied by the data bus to transmit data can be minimized, that is, the high bit R[5] of the remainder data is sent to the first storage unit 100 for storage. That is, the common integer data and the high bit of the remainder data are mixed to form data packet A for cyclic transmission. Here, the high bit of the remainder data is preferably R[5]. The data reception and display diagram can be referred to Figure 4 As shown, Figure 4 The nth combination n+1 groups in the LED screen represent different display rows. Since the data packet A contains the remainder coefficient data, the PWM displayed at the beginning also contains the remainder coefficient data to ensure the integrity of the PWM.

[0170] As analyzed above, on the other hand, storing the high bits of the remainder data reduces the data transmission volume of the data bus. Originally, the data bus needs to send the remainder coefficient data 63 times. After the highest bits of the remainder coefficient data are stored, it only needs to be sent 31 times, which is equivalent to reducing the transmission volume of the data bus by half. That is to say, compared with the prior art, the present application has a technical advancement in lower data bus transmission load.

[0171] In addition to the above mixing methods of the common integer data and the remainder coefficient data, another mixing method is provided in this embodiment, and the specific method is as follows:

[0172] The public integer data is sent as data packet A, the remainder high-order data is sent as data packet B, and data packet A and data packet B are sent mixedly;

[0173] or;

[0174] The common integer data and the remainder high-order data are mixed to form data packet A, and the remainder coefficient data is used as data packet B. Data packet A and data packet B are mixed and sent.

[0175] The data receiving diagrams of the above two methods can be referred to Figure 5 and Figure 6As shown, data packet A and data packet B can be sent alternately, or several data packets A can be sent and then one data packet B. Based on the above analysis, it can be seen that at least 1 bit of grayscale data must be sent for each channel of the remainder coefficient data. For a 16-channel chip, at least 16 bits of remainder coefficient data need to be sent, and the maximum data bus transmission capacity is 16 bits, that is, only sending data packet B once can meet the demand for remainder coefficient data, but multiple transmissions are not excluded. For example, when 2-3 bits of remainder coefficient data are sent per channel, multiple transmissions are required to completely send the remainder coefficient data. The advantage of sending remainder coefficient data greater than 1 bit is that the data bus transmission capacity can be further reduced. The disadvantage is that the storage capacity of the first storage unit 100 will increase, which increases the chip cost.

[0176] refer to Figure 6 As shown, the sending order of data packet B can be set arbitrarily. In order to ensure that the common integer data is available in PWM as soon as possible, data packet B should be sent as early as possible, that is, the first data packet and the second data packet should include data packet A and data packet B, especially when data packet A does not contain remainder coefficient data.

[0177] Compared with mixing the common integer data and the remainder high-order data to form data packet A for cyclic transmission, when data packet A only includes the common integer data, the first PWM displayed does not contain the remainder coefficient data or the common integer data. For example, if the first one is data packet B, it does not contain the common integer, and if the first one is data packet A, it does not contain the remainder coefficient data. The impact on the display is that the grayscale data of the first PWM is incomplete, which is equivalent to the incompleteness of multiple PWM data in the traditional mode. This solution still has great progress and advantages. Taking the above 13-bit grayscale data as an example, there are 64 groups of common integer data, which means that 64 groups of PWM need to be displayed, and there are only 63 groups of remainder coefficient data, and there is exactly one group without remainder coefficient data. Therefore, sending data packet A first coincides with the actual situation, that is, sending data packet A first (when data packet A does not contain remainder coefficient data) is the best choice.

[0178] After the data of the front section of the display frame is sent, the data transmission of the rear section of the display frame begins. Since all the public integer data have been stored in the first storage unit 100, only the remainder coefficient data is sent in the rear section of the display frame.

[0179] The sending methods include the following:

[0180] (1) The remainder coefficient data is sent to the remainder coefficient analysis unit 400, the structure of which can be referred to Figure 1 or Figure 3 As shown, the remainder coefficient data is sent to the PWM generating unit 200 via the remainder coefficient analyzing unit 400 .

[0181] (2) The remainder coefficient data is sent to the first storage unit 100 for storage; its structure can be referred to Figure 8 As shown, in this case, the time for data bus to transmit data can be greatly saved. The difference is that the previously stored remainder coefficient data needs to be overwritten, which may cause a delay in data sending and receiving (as mentioned above, this delay can be ignored).

[0182] (3) The remainder coefficient data is directly sent to the PWM generation unit 200, and its structure can be referred to Figure 2 As shown, it is directly sent to the PWM generation unit 200 for display without passing through the remainder coefficient analysis unit 400. In this case, the timing of sending data can be controlled by a clock or by a controller (control card).

[0183] In summary, the remaining remainder coefficient data sent in the latter part of the display frame can be generally divided into two types: storage and non-storage. That is, the remaining remainder coefficient data are all transmitted through the data bus without storage, or the remaining remainder data continue to be stored, provided that all the remainder coefficient data stored previously have been displayed. For example, if the remainder coefficient data R[5] is stored, the remaining remainder coefficient data can only be sent after 32 groups of PWM are displayed.

[0184] It is worth emphasizing that the display frame front section and the display frame back section in this application are distinguished by the point where all the public integers are sent. That is, the sending of the public integer data is regarded as the display frame front section, and the point after the public integer data is sent is regarded as the display frame back section.

[0185] Optionally, in one embodiment, when the number of PWM groups is 2 n , the public integer data and the remainder coefficient data can be split exactly by bit level, the remainder high-order data is the i-th bit of the remainder data, or the [(ib),i]-th bit; the remainder data of other bits are used as remainder coefficient data; wherein, 2≤b<n, 2≤i≤n, and n is the bit width of the remainder data. The remainder high-order data can be a remainder coefficient other than R[0], that is, it can be any one or two of R[1]-R[5]. For example, when the remainder high-order data is 1 bit, it can be R[3]. Then R[0], R[1], R[2], R[4], and R[5] are respectively used as remainder coefficient data. When the remainder high-order data is 2 bits, that is, b=1 and i=4, R[3]-R[4] can be used as remainder high-order data. Then R[0], R[1], R[2], and R[5] are respectively used as remainder coefficient data. Generally speaking, R[5] is the best choice for the remainder high-order data.

[0186] For example, in the above 13-bit grayscale data, the remainder coefficient data is 6 bits, that is, n=6. The remainder high-order data here refers to the remainder coefficient data mixed with the public integer data as data packet A. When data packet A is sent cyclically, it can be understood that the public integer data and the remainder coefficient data are sent at the same time, where the remainder coefficient data can be 1 bit (here it refers to 1 bit of remainder coefficient data for each channel of the chip, rather than only 1 bit of remainder coefficient data in the entire data packet A). It can also be multi-bit remainder coefficient data. When ib=0, its essence is equivalent to sending the grayscale data as a whole. This scheme generally does not adopt this mode in actual operation, that is, the bit width of the remainder high-order data generally does not exceed 3 bits.

[0187] Optionally, in one embodiment, the maximum data volume of data packet B is mbit, where m is the number of channels of the driving chip, that is, each channel corresponds to 1bit or ibit of remainder coefficient data. Currently, the main chip channels are generally 16 channels. Since the bit width of the data bus is 16 bits, the maximum data packet is generally 16 bits. It can be understood here that, for a 16-channel chip, if each channel sends 1bit of remainder coefficient data, it can be sent through 1 data packet B. When each channel needs 2bit of remainder coefficient data, 2 data packets B are required to send it. In actual situations, data packet B contains remainder coefficient data, which is generally only 1bit, that is, only 1 data packet B is needed each time to send the remainder coefficient data required by all channels, so as to reduce the number of remainder coefficient data transmissions and save the occupancy time of the data bus. At the same time, since the first storage unit 100 also stores the remainder coefficient data, when the first storage unit 100 uses two memories to work in a ping-pong structure, the saved time can be used to send the common integer data of the next display frame (that is, the common integer data and remainder coefficient data of the next display frame are mixed).

[0188] It is known from the above description that when the common integer data and the remainder coefficient data are mixed and sent for storage, the stored remainder coefficient data is preferably the remainder high-order data, that is, the remainder high-order data is not the lowest and second lowest bits of the remainder data, that is, it is not meaningful to store the lowest and second lowest bits of the remainder data.

[0189] Optionally, in one embodiment, the high-order data of the remainder is the highest order or the second highest order of the remainder data, that is, the highest order + the second highest order. That is, when the remainder coefficient data is 2 bits, the high order and the second highest order of the remainder data can be stored. This can minimize the time taken by the data bus to transmit the remainder coefficient data. The saved time can be used to transmit integer data or registers, dual-edge instructions, etc.

[0190] In order to further improve the uniformity of grayscale data display, this embodiment makes further design on which groups of PWM the stored remainder coefficient data are displayed.

[0191] Through the above analysis, it can be known that when the first storage unit 100 stores the remainder high-bit data, it can determine the grayscale data in multiple groups of PWM. For the convenience of explanation, 13-bit grayscale data is used as an example, the common integer is 7 bits, and the remainder coefficient is 6 bits. From the above, it can be known that R[5] is displayed in 32 groups, and there are 64 groups of PWM in total, that is, which groups R[5] is displayed in can be controlled. For this, the following implementation methods are provided in this application.

[0192] Optionally, in one embodiment, among all PWMs in a complete display frame, several groups of remainder coefficient data are generated by the remainder high-order data stored in the first storage unit 100, and the remainder coefficient data of other groups are transmitted by the bus. That is to say, it is not limited in which groups of PWM the remainder high-order data stored in the first storage unit 100 is displayed, that is, it can be displayed randomly, that is, it is not emphasized that R[5] specifically controls which groups, which can be the first 32 groups, the middle 32 groups, or the last 32 groups, or 32 groups are displayed randomly. However, those skilled in the art should know that since the common integer data has the greatest impact on the PWM display, the common integer data should be sent as quickly as possible. If the stored remainder coefficient data controls the last 32 groups, this means that the first 32 groups need to send additional remainder coefficient data, and the data bus cannot send data packet A and data packet B at the same time, which greatly delays the transmission time of the common integer data.

[0193] Optionally, in one embodiment, within a display frame period, PWM is displayed according to timing 1, that is, the remainder coefficient data in the odd-numbered PWM array is generated by the remainder high-order data stored in the first storage unit 100, and the remainder coefficient data in the even-numbered PWM array is directly transmitted by the data bus. The principle is as follows: Fig.13 shown.

[0194] Depend on Fig.13It can be seen that in the displayed PWM, the integer (common integer data) + remainder high bit displayed in the odd array, the remainder high bit here is the remainder coefficient data stored in the first storage unit 100, and the even array PWM only has integers (common integer data) without remainder high bits, but the remainder coefficient data must be displayed in actual display, so in the even array PWM display, the remainder coefficient data must be sent through the data bus for filling. In this case, the mixed transmission of the common integer data and the remainder coefficient data is sent according to "the common integer data and the remainder high bit data are mixed to form data packet A, the remainder coefficient data is used as data packet B, and data packet A and data packet B are mixed and sent", wherein data packet A and data packet B are sent alternately. The advantage of this solution is that the remainder high bit is evenly distributed in each group of PWM, which can make the entire display more uniform and improve the picture effect. Its disadvantage is that it takes longer for the common integer to be sent. Assume that the grayscale value D has 13 bits; the weight is 64, and a total of 64 groups are displayed. In this way, the public integer data is D[12:6], and the remainder coefficient data is D[5:0] (here it is assumed that multiple data are not considered and are not scattered). A data packet A that sends integers can send 2 public integer data and 2 remainder high bits, that is, {D0[12:5], D1[12:5]}. The principle can be referred to Fig.17 As shown, data packet A includes the common integer data of points P1 and P2, as well as the remainder coefficient data of points P1 and P2. Here, points P1 and P2 correspond to D0 and D1. Data packet B is the same, including the remainder coefficient data of multiple points. Generally speaking, when only 1 bit of remainder coefficient data is sent, a data packet B can include the remainder coefficient data of up to 16 points. Assuming that there are 32 rows and each IC has 16 channels, there are 32*16=512 integer data to be stored; assuming that the bus transmission time of a joint data packet is close to the display time of a row, it takes 512 / 2=256 row display times to transmit all integer data (including the remainder high bit), that is, 256 / 32=8 group display times. Considering the uniformity of display grouping, it is assumed that the remainder high bit D[5] controls the remainder coefficients of the 32 odd groups 1 / 3 / 5 / 7…63. Based on the above analysis, it can be seen that the common integer originally only needs 8 times to be transmitted. However, in this embodiment, since the remainder coefficient data (data packet B) needs to be inserted at intervals, the common integer data can only be sent out in full at the 15th time, which is equivalent to delaying the length of the front segment of the display frame in disguise. The disadvantage is that it will cause screen tearing, but when the grayscale data is low, it has basically no effect.

[0195] In addition to the above display modes, the odd and even groups can also be interchanged, that is, the remainder coefficient data in the even group PWM is generated by the remainder high-bit data stored in the first storage unit 100, and the remainder coefficient data in the odd group PWM is directly transmitted by the data bus. The difference is that the first data packet sent in the display timing must be the remainder coefficient data packet, which makes the first PWM displayed have no common integer, but for the entire display frame, it will hardly cause any impact. The principle can be referred to Fig.18 shown.

[0196] When data packet A contains only public integer data and data packet B contains remainder coefficient data, it is obvious that when data packet A is sent first, the first group of PWM has no remainder coefficient data available. Based on the above, the number of groups of remainder coefficient data displayed is one group less than the number of public integer data. For example, in 13-bit grayscale data, if the weight of the public integer data is 64 (displaying 64 groups), there are only 63 groups of remainder coefficient data, which means that there must be no remainder coefficient data in one group of PWM. Therefore, when data packet A contains only public integer data and data packet B contains remainder coefficient data, the first group of PWM does not display remainder coefficient data.

[0197] In other words, the timing 1 defines that the stored remainder coefficient data and the remainder coefficient data transmitted by the data bus are used alternately and cyclically in the displayed PWM sequence, and does not define the source of a specific group of remainder coefficient data, that is, when the odd-numbered group uses the stored remainder coefficient data, the even-numbered group must use the remainder coefficient data transmitted by the data bus, and vice versa. The essence is that the remainder coefficient data displayed by the first M odd-numbered groups are generated by the remainder high-order data stored in the first storage unit 100.

[0198] Optionally, in one embodiment, within a display frame period, PWM is displayed according to timing 2, the remainder coefficient data in the first M groups of PWM are generated by the remainder high-order data stored in the first storage unit 100, and the remaining PWM uses a mixture of the stored remainder coefficient data and the remainder coefficient data transmitted by the data bus, and the common integers are all sent within the M groups of PWM display periods. The principle can be referred to Fig.14As shown. The first M groups of PWM display integer (common integer data) + remainder high bit, where the remainder high bit is the remainder coefficient data stored in the first storage unit, that is, in the first M groups, there is no need to occupy the data bus to transmit the remainder coefficient data, and the public integer data can be sent quickly. Taking the above 13-bit grayscale data as an example, the 7-bit public integer data, the 16-channel chip only needs 8 times to complete the transmission, that is, M=8. The advantage of this embodiment is that the public integer data can be sent as quickly as possible, which can reduce the tearing degree of the picture. The disadvantage is that the display of PWM is not as uniform as that of timing 1, but when the grayscale data is large, the influence of the remainder coefficient data on the picture is relatively small, and its uniformity is basically unaffected.

[0199] Optionally, in one embodiment, the remainder coefficient data required for timing 1 and timing 2 are provided by a remainder coefficient parsing unit, that is, the remainder coefficient parsing unit 400 parses the corresponding remainder coefficient data according to timing 1 or timing 2 and sends it to the PWM generating unit 200, that is, during the display process, the remainder coefficient parsing unit 400 either parses the remainder high-order data stored in the first storage unit 100 to obtain the remainder coefficient data, or directly sends the remainder coefficient data transmitted from the data bus to the PWM generating unit 200.

[0200] In addition to the above methods, since timing 1 and timing 2 each have their own advantages and disadvantages, the combination of the two is undoubtedly the best option. This embodiment also provides a solution for dynamic switching between timing 1 and timing 2, that is, in one embodiment, timing 1 and timing 2 can be dynamically switched. Based on the above analysis, it can be seen that when the grayscale data values ​​are different, the display effect is better when different timings are used. The grayscale value here refers to the overall grayscale of a certain display frame. In other words, in a continuous multi-frame picture, dynamic switching can be used to switch between timing 1 and timing 2. When the grayscale of the picture is greater than or equal to the grayscale threshold K, timing 2 is used, and when it is less than the grayscale threshold K, timing 1 is used.

[0201] Optionally, in some embodiments, within a complete display frame, a PWM displayed by a grayscale data display driving module includes 2 n Groups, of which 32 groups and 64 groups are preferred, please refer to Fig.23 and Fig.24 As shown, the low-order data in the figure is the lost remainder low-order data, the middle-order data is the remainder coefficient data sent through the data bus, and no data means that the reorganized remainder coefficient data is generated by the stored remainder high-order data.

[0202] In addition to the above switching methods, timing 1 and timing 2 can also be switched by manual configuration.

[0203] refer to Fig.15 As shown, a grayscale data display driving module (hereinafter referred to as the driving chip or chip) includes a first storage unit 100, and a PWM generating unit 200 and a remainder coefficient parsing unit 400 connected to the first storage unit 100, the remainder coefficient parsing unit 400 is connected to the PWM generating unit 200, the PWM generating unit 200 generates PWM for display according to the remainder coefficient data parsed by the remainder coefficient parsing unit 400 and the common integer data stored in the first storage unit 100, the switching between timing 1 and timing 2 is completed by the controller / logic processing module 500, the controller / logic processing module 500 is connected to the remainder coefficient parsing unit 400, the controller / logic processing module 500 has a built-in threshold value K, and controls the remainder coefficient parsing unit 400 according to the threshold value K to parse the remainder high-order data stored in the first storage unit 100 or parse the remainder coefficient data transmitted by the data bus.

[0204] Optionally, in one embodiment, the controller / logic processing module 500 may be implemented by using a controller in a grayscale transmission system. The principle of this may be referred to in Fig.16 As shown, the controller is connected to each level of the driving chips, and is used to control the remainder coefficient analysis unit 400 to receive data transmitted by the data bus or analyze the remainder high-bit data stored in the first storage unit 100 .

[0205] In addition, a logic processing module may be designed separately to implement the above control, wherein the logic processing module may be integrated with the driver chip.

[0206] Whether it is a controller or a logic processing module, its essence is to be realized by controlling the clock signal of the display timing. For example, the high-level remainder coefficient analysis unit 400 analyzes the remainder high-bit data stored in the first storage unit 100, and the low-level data bus directly transmits the remainder coefficient data to the remainder coefficient analysis unit 400 and outputs the remainder coefficient data to the PWM generation unit 200.

[0207] Optionally, in one embodiment, the grayscale threshold K represents the grayscale value of a complete display frame, or represents the average grayscale value corresponding to each PWM in a complete display frame; or determines whether the integer is less than the threshold K1, and further, counts the number of data that meet the conditions to see whether it is less than a preset number of pixels, or whether it is less than a preset value K2. Regardless of whether the average grayscale value is used as the basis for determining the grayscale threshold K or the overall grayscale value is used as the basis for determining the grayscale threshold K, it can ultimately measure the grayscale value of the picture, that is, the brightness of the picture.

[0208] Optionally, in one embodiment, the remainder coefficient analysis unit 400 and the PWM generation unit 200 are packaged together as a PWM generation device. That is, the remainder coefficient analysis unit 400 and the PWM generation unit 200 are different functional units in the same module in terms of hardware expression, which is equivalent to the PWM generation device in the prior art. This design method can make the driver chip simpler in structure and occupy a smaller area.

[0209] Optionally, in another embodiment, the PWM generating unit 200 is packaged as a PWM generating device, and the remainder coefficient parsing unit 400 is electrically connected to the PWM generating device. In this embodiment, the PWM generating unit 200 and the remainder coefficient parsing unit 400 are two independent modules in terms of expression, and the PWM generating unit 200 and the remainder coefficient parsing unit 400 are electrically connected to realize data transmission.

[0210] In other words, the remainder coefficient analysis unit 400 and the PWM generation unit 200 referred to in this application are limited by the functions of the modules, and are not specific limitations on the hardware structure. Any module known in the art and having these two functions can be used in this application as a substitute.

[0211] Among them, the remainder coefficient analysis unit 400 is essentially a logic module, and its main function is to select the corresponding remainder coefficient data to be input into the PWM generation unit 200. As in the above embodiment, the remainder coefficient analysis unit 400 can be controlled by a controller, or by a logic processing module, or it itself is a logic module. According to timing 1 or timing 2 combined with a clock module, the selection and output of the remainder coefficient data can be realized. All modules known in the art that can realize this function can be used as the remainder coefficient analysis unit 400, or the module should be considered to be the remainder coefficient analysis unit 400. If only the name of the functional module is changed and the function finally realized is the same, it should be treated the same as the remainder coefficient analysis unit 400 in this solution.

[0212] In addition to the solutions described in the above embodiments, this embodiment also provides another grayscale data display driving module. The difference from the above embodiments is that a small storage is added in this embodiment to store remainder coefficient data, and the first storage unit only stores common integer data.

[0213] refer to Figure 7As shown, it includes a first storage unit 100, a second storage unit 300 and a PWM generating unit 200; the first storage unit 100 stores the common integer data of the grayscale data and outputs it to the PWM generating unit 200; the second storage unit 300 stores the remainder data of the grayscale data and outputs it to the PWM generating unit 200, and after the remainder data is displayed, the remainder data of other bits is stored and continuously output to the PWM generating unit 200 until all the remainder data are displayed; the PWM generating unit 200 generates PWM for display according to the common integer data and the remainder data. The PWM referred to here can be 1 or 2. In terms of the form of expression, the common integer data and the remainder data can continuously form a PWM, or the common integer data and the remainder data can be displayed at both ends of the PWM respectively, thereby showing the form of 2 PWMs. Regardless of 1 PWM or 2 PWMs, they are collectively referred to as 1 group of PWMs, that is, each group of PWMs contains common integer data and remainder coefficient data.

[0214] In another embodiment, a grayscale data display driving module, in addition to the above differences, also includes a remainder coefficient parsing unit 400, which controls the second storage unit 300 to selectively output remainder data to the PWM generating unit 200, and the remainder data is the remainder high-order data; when the second storage unit 300 does not output the remainder high-order data, the remainder coefficient data is transmitted to the PWM generating unit 200 by the data bus; the PWM generating unit 200 generates PWM for display according to the common integer data and the remainder high-order data or the remainder coefficient data.

[0215] It includes a first storage unit 100 and a second storage unit 300, a PWM generating unit 200 connected to the first storage unit 100, a remainder coefficient parsing unit 400 connected to the second storage unit 300, and the remainder coefficient parsing unit 400 is connected to the PWM generating unit 200; within a complete display frame, the grayscale data is divided into common integer data and remainder data, wherein the remainder data is divided into a plurality of remainder coefficient data; in the front section of the display frame, the common integer data and the remainder coefficient data are mixedly sent, wherein the common integer data is sent to the first storage unit 100 for storage, and the remainder coefficient data is sent to the second storage unit 300 for storage; in the rear section of the display frame, only the remainder coefficient data is sent to the second storage unit 300 for storage; or it can be directly transmitted to the PWM generating unit 200 or the remainder coefficient parsing unit 400 through a data bus, and the PWM generating unit 200 generates PWM for display according to the remainder coefficient data parsed by the remainder coefficient parsing unit 400 and the common integer data stored in the first storage unit 100. In this embodiment, a second storage unit 300 is newly added to store the remainder coefficient data, and the first storage unit 100 is used to store the public integer data, that is, the public integer data and the remainder coefficient data are stored separately. Compared with the case of only the first storage unit 100, this embodiment can further reduce the storage space and size of the first storage unit 100, but it is also necessary to add an additional second storage unit 300, which slightly increases the cost, but still has a greater technical progress compared with the traditional technology. Since the public integer data and the remainder coefficient data are stored separately, when mixed transmission, only the method of separate mixed transmission of data packet A and data packet B can be adopted, that is, data packet A only has public integers, and data packet B only has remainder coefficient data, and the transmission method of data packet A and data packet B is the same as the previous embodiment. That is to say, in the front section of the display frame, data packet A (public integer data) is mainly sent, and 1 or 2 data packets B can be sent, and the order of sending can be data packet A first or data packet B first. The front section of the display frame and the back section of the display frame are distinguished by the completion of sending all public integers. Optionally, the remainder coefficient data sent in the front segment of the display frame is the high bit or the second high bit of the remainder data, or the highest bit + the second high bit. Optionally, the remainder coefficient parsing unit 400 and the PWM generating unit 200 are packaged together as a PWM generating device; or the PWM generating unit 200 is packaged as a PWM generating device, and the remainder coefficient parsing unit 400 is electrically connected to the PWM generating device.

[0216] Optionally, in a grayscale data display driving module, the second storage unit 300 is used to store remainder coefficients. According to the above embodiments, the remainder coefficient data can be sent as little as 1 bit. For a 16-channel chip, only 16 bits of storage space are required. Therefore, the storage capacity of the second storage unit 300 is smaller than that of the first storage unit 100, or even much smaller than that of the first storage unit 100.

[0217] Optional, reference Fig.19 As shown, in a grayscale data display driving module, the first storage unit 100 is composed of a memory 1-A and a memory 1-B, and the memory 1-A and the memory 1-B use a ping-pong structure to alternately send and receive data. The use of a ping-pong structure to alternately send and receive data can completely solve the problem of screen tearing. Its defect is that the cost is higher than that of a single memory structure, but compared with the traditional mode, the memory 1-A and the memory 1-B in this solution have smaller capacities, that is, compared with the prior art, it still has a lower cost technical progress. Under this structure, in addition to displaying the display frame in the manner of timing 1 and timing 2, another display mode is also provided in this embodiment to completely solve the problem of screen tearing. In all PWMs within a complete display frame, when the data bus does not transmit the remainder coefficient data, the public integer data of the next frame is sent for storage, that is, the sending and receiving states of the memory 1-A and the memory 1-B are switched, and the mixed sending of the public integer data and the remainder coefficient data to be stored in the next display frame is completed, that is, the saved data bus transmission time is used to send the grayscale data of the next display frame in advance to avoid occupying the display time of the next display frame. Among them, M can be determined according to timing 1 and timing 2. For example, in the above 13-bit embodiment, if the common integer data and the remainder coefficient data are sent in a mixed manner according to timing 1, 15 PWMs are required to completely send them, that is, M=15, that is, 15 PWMs are reserved in the previous frame for mixed sending of the common integer data and the remainder coefficient data of the next display frame; if the common integer data and the remainder coefficient data are sent in a mixed manner according to timing 2, then M=8.

[0218] That is, when the current display frame is displayed using the stored remainder coefficient data, the data bus transmits the common integer data and remainder coefficient data of the next display frame for storage. It can also be that when the stored remainder coefficient is used for display in timing 1 and timing 2, the common integer data or remainder coefficient data required to be stored for the next display frame is sent. The specific method is that the memory 1-A stores the common integer data and remainder coefficient data of the previous display frame, and when displaying, the data stored in the memory 1-A is used for display. When the stored remainder coefficient data is used, the data bus is in idle time, and it can be used to send the common integer data and remainder coefficient data required to be stored for the next display frame, and send it to the memory 1-B. Since the time for the data bus to transmit the remainder coefficient data can be reduced by more than half, there is enough time to send the common integer data and remainder coefficient data required to be stored for the next display frame, that is, the common integer data and remainder coefficient data mixed and sent in the front section of the display frame.

[0219] It is worth noting that in the two embodiments with or without the second storage unit 300, the manner of mixing and sending the common integer data and the remainder coefficient data is the same, the only difference being the storage location. In the embodiment without the second storage unit 300, the data is stored in the first storage unit 100, and in the embodiment with the second storage unit 300, the data is stored in the second storage unit 300.

[0220] Optionally, in one embodiment, a grayscale data display driving module, the PWM generating unit 200 or the remainder coefficient parsing unit 400 stores the weight W of the remainder coefficient data. R The purpose of setting the weight is to optimize the displayed waveform. When the remainder coefficient data is 1, the displayed width is only 1 unit pulse. Fig.25 As shown, the rising and falling edges at both ends of the waveform are severely deformed, affecting the display effect. For this reason, this application adds a weight to the remainder coefficient data so that its displayed width is greater than 1 unit pulse. Fig.26 As shown, when the proportion of the rising edge and the falling edge to the display width decreases, the optimization effect of the display is more obvious.

[0221] The PWM generating unit 200 generates a PWM signal according to the common integer data, the remainder coefficient data and the weight W. R Generate PWM for display, the gray value actually displayed by the remainder coefficient data and the remainder high-order data = W R × remainder coefficient data / remaining high-order data, W R =2 x , where x is an integer. Since the remainder coefficient data adds weight, for the common integer, in order to ensure that the number of groups displayed by PWM remains unchanged, a corresponding weight W must also be added. Q , generally speaking, the weight WQ =Weight W R After the increase, the original public integer data also changes accordingly, and satisfies the public integer data = W Q × Public integer data.

[0222] Let's take the case of 4 undispersed bits as an example (i.e. x=2). Assuming the original 6-bit remainder data is D[5:0] and the 7-bit public integer is D[12:6], after the 4 bits are undispersed, the remainder low bit D[1:0] is lost, the 6-bit remainder data becomes D[7:2]*D[1:0], and the public integer becomes D[12:8]*D[1:0].

[0223] Furthermore, when x≥1, it is necessary to send the remainder low-order data D[x-1:0] for display. Taking the case of 4 unbroken bits as an example, for the lost D[1:0], we need to send the remainder coefficient corresponding to the 2 bits of the remainder low-order D[1:0]. Since there is always a group of remainder coefficients in the displayed PWM that are all 0, this remainder coefficient idle group can be used to transmit the remainder low-order D[1:0]. For a 16-channel IC, D[1:0] requires 2 16-bit data packets to be sent, so there are two situations:

[0224] A: If the bus transmission speed is fast enough to send these two data packets (or combined data packets) within one line display time, they can be transmitted and displayed in this remainder coefficient idle group.

[0225] B: If the bus transmission speed is not fast enough, the idle group of the remainder coefficient can only display 1 bit, and the other 1 bit needs to be displayed by adding another display group. For example, if there are 32 groups of PWM originally, it becomes 33 groups after adding a display group.

[0226] The situation where the bus transmission is fast enough is usually difficult to occur. We focus on the situation where the bus is not fast enough and an additional display group is needed.

[0227] In addition, for the case where the four are not scattered, the transmission does not necessarily require 1 to 2 data packets, and can be further expanded and sent using multiple data packets; in addition, it is also possible not to use the idle group of the remainder coefficient for transmission, but more display and transmission groups will be added. From the perspective of saving display time and transmission time, this is meaningless.

[0228] There are four common numbers that are not scattered: 2, 4, 8, and 16, which correspond to the low-order 1 bit, 2 bits, 3 bits, and 4 bits of the remainder respectively. If the idle display groups are used, they require 0, 1, 2, and 3 additional display groups.

[0229] According to the above example of D[12:0] grayscale value, 64 groups and 4 unbroken (x=2), we can know that the display period of one row in each display group is 27=128 periods. There is no need to transmit the remainder coefficient in the group (the idle group with non-remainder coefficients always equal to 0), and its display data is D[12:8]*4+D[7]*4. At this time, we use this group to transmit the remainder coefficient. Assuming that D[0] is transmitted, the total display data is D[12:8]*4+D[7]*4+D[0]. For most cases, this value will not be greater than 128, but for the extreme case D[12:8]max=31, D[7]max=1, D[0]max=1, and the total display grayscale=129, which exceeds 128. When several un-dispersed data are used, the low-bit grayscale data is lost, so it is necessary to send the low-bit grayscale data additionally. The saved data bus time can be used for transmission, that is, the low-bit grayscale data is sent when the stored remainder coefficient data is used for display, which will not cause data bus delay.

[0230] Here, W is added to the remainder coefficient data R The purpose is to improve the waveform of a single pulse displayed by PWM, so as to reduce the single pulse PWM in each PWM as much as possible to optimize the display effect.

[0231] Summarize:

[0232] (1) If the bus transmission speed is fast enough to transmit all the remainder low bits within a group time, the remainder low bits can be displayed in the idle group (or extra group) where the remainder coefficient is always 0, and the remainder low bits data D[j] can be displayed in the PWM where the remainder coefficient data is always 0, where j is [0, x-1]. The principle can be referred to Fig. 20 As shown, assuming that the remainder coefficient data in the 64th group PWM is 0, the remainder low-order data D[x-1:0] is displayed in the 64th group PWM. This situation is generally only applicable to the case where X=1. Because it is difficult to be "fast enough" in practice, there are only 2 cases where it is not scattered, and the remainder low-order data is only 1 bit, so this method can be used.

[0233] (2) Display the remainder low-order data D[j] in the PWM whose remainder coefficient data is always 0 and the additional PWM, where j is [0, x-1], refer to Fig.21 As shown, the total number of PWMs displayed becomes 65 groups, that is, an additional group of PWM is added to display the 1-bit remainder low-order data D[0], and the 1-bit remainder low-order data D[1] is also displayed in the 64th group of PWM.

[0234] (3) Display the remainder low-order data D[j] in PWM when the remainder coefficient data does not need to be transmitted, where j is [0, x-1], and its display reference Fig. 22As shown, the data bus is used to send the remainder low-order data D[x-1:0] and display it by utilizing the gap when the remainder coefficient data is not transmitted. At this time, the grayscale data included in a PWM = public integer data + stored remainder coefficient data + 1 bit remainder low-order data. This may cause the width of the PWM to overflow. In view of this situation, the corresponding PWM display period is extended to ensure that the grayscale value corresponding to the display period is greater than or equal to the public integer data + remainder coefficient data + remainder low-order data D[j];

[0235] In general, the remainder low-order data D[x-1:0] is sent in the idle time when the remainder coefficient data is not sent, that is, in the group using the remainder high-order data stored in the first storage unit 100 for display, refer to Fig.23 and Fig.24 As shown in the figure, in a 32-group PWM and a 64-group PWM, the remainder low-order data is displayed in the last few idle PWM groups. Generally speaking, several bits of remainder low-order data are displayed in several groups of PWM, that is, only 1 bit of remainder low-order data is displayed in one group of PWM as much as possible.

[0236] Or, the corresponding PWM display period is not extended. When the common integer data + remainder coefficient data + remainder low-order data D[x-1:0] is greater than the grayscale data corresponding to the PWM, the overflow part is ignored.

[0237] In another aspect, the present embodiment further provides a grayscale data transmission method, the method comprising:

[0238] S100: Data grouping, dividing each frame of grayscale data into common integer data and remainder data, wherein the remainder data is divided into several groups of remainder coefficient data;

[0239] S200: Data transmission: firstly, the common integer data and part of the remainder coefficient data are mixed and transmitted, and then, after the common integer data is transmitted, the remaining remainder coefficient data is transmitted.

[0240] refer to Fig.16 As shown, it is a schematic diagram of a chip data transmission system, where multiple chips are connected in series (the chip here is a grayscale data display driver module in this solution), and the data transmission is controlled by the controller. The controller and the chip are connected through a data bus to complete the data transmission. The overall system framework is completely consistent with the traditional chip data transmission system. The difference lies in the controller's data processing flow, that is, the grayscale data transmission method provided in this embodiment.

[0241] The controller divides the grayscale data into common integer data and remainder data, wherein the remainder data is divided into a number of remainder coefficient data, and the decomposition method is the same as that of the above embodiment, that is, the grayscale data is divided into high-order data and low-order data, for example, 13-bit grayscale data is divided into 7-bit common integers and 6-bit remainder coefficient data, and in addition, it can also be decomposed into 8-bit common integer data and 5-bit remainder coefficient data. Generally speaking, it is advisable that the remainder coefficient data does not exceed 7 bits. For another example, in a 16-bit grayscale data, it can be decomposed into 10-bit common integer data and 6-bit remainder coefficient data. This decomposition method is also a commonly used decomposition method in the art, which will not be repeated here, but those skilled in the art should know that all common integer data and remainder coefficient data decomposition methods known in the art can be used in this solution.

[0242] After the grayscale data is decomposed, the controller controls the sending order of data packet A and data packet B. Inevitably, data packet A and data packet B also include a compression and decompression process at the sending end and the receiving end.

[0243] In some embodiments, the step of sending data includes:

[0244] S201: The common integer data and part of the remainder coefficient data are formed into a data packet A, and the remaining remainder coefficient data are formed into a data packet B;

[0245] S202: Data transmission, first cyclically sending data packet A, then sending data packet B; or first mixedly sending data packet A and data packet B, then sending data packet B;

[0246] In some other embodiments, the step of sending data includes:

[0247] S201: The common integer data is formed into a data packet A, part of the remainder coefficient data is formed into a data packet B1, and the rest of the remainder data is formed into B2;

[0248] S202: Data transmission: firstly, mixedly transmit data packet A and data packet B1, and then transmit data packet B2.

[0249] Optionally, a grayscale data transmission method comprises: public integer data and remainder high-order data forming data packet A, and remainder coefficient data as data packet B. The remainder coefficient data as data packet B in the present application does not mean that the remaining remainder coefficient data are compressed in one data packet B, but that one data packet B contains 1 bit or several bits of remainder coefficient data for each channel of the chip, that is, there are multiple data packets B. Among them, the remainder high-order data in data packet A generally refers to the highest or second highest bit of the remainder data, or the highest bit + the second highest bit. For example, a 16-bit grayscale data is assumed to be 1111111001110111, and the public integer data is defined as 9 bits and the remainder coefficient data is 7 bits. Then the public integer data is R[15,7]=111111100, and the remainder coefficient data is R[6,0]=1110111, that is, R[6]=1, R[5]=1, R[4]=1, R[3]=0, R[2]=1, R[1]=1, R[0]=1, where R[6] is displayed in 64 groups, R[5] is displayed in 32 groups, R[4] is displayed in 16 groups, R[3] is displayed in 8 groups, R[2] is displayed in 4 groups, R[1] is displayed in 2 groups, and R[0] is displayed in 1 group. The number of groups in which it is displayed means the number of times it needs to be sent through the data bus. In this application, the remainder high-order data is stored to reduce the time of occupying the data bus. That is to say, a total of 63 data packets B are needed, of which 32 data packets B contain data R[5], 16 data packets B contain data R[4], and so on.

[0250] Obviously, the higher the number of bits of the remainder coefficient data stored, the more the data bus occupancy time is reduced. In this embodiment, if R[6] is stored, the data bus time can be reduced by half, so when storing, half of the high or second high bits of the remainder data are stored. Or the highest bit + the second high bit are stored at the same time. Compared with storing only one bit (1 bit) of the remainder coefficient data, storing the highest bit + the second high bit obviously requires a larger storage space. Therefore, in actual application, storing 1 bit of remainder coefficient data is the best solution. The cumulative storage space required is equal to m*1bit1, where m is the number of channels of the chip. The principle is as follows: Fig.17 As shown, a data packet B contains the remainder high-order data of multiple points (that is, channels). Similarly, a data packet A also contains the common integer data of 1-3 points. However, it does not rule out the situation of storing 2-bit or 3-bit remainder coefficient data. In other words, when only R[6] is stored, R[5]-R[0] needs to be sent 63 times in total, which means that there are 63 data packets B and data packet B needs to be sent 63 times. Furthermore, when data packets A and B are sent, the front part of the frame is displayed and data packet A is sent cyclically. The principle can be referred to Figure 4As shown. Data packet B is sent in the latter part of the display frame; since the remainder coefficient data needs to be included in the displayed PWM, the remainder coefficient data in the M PWMs in the first part of the display frame is the stored remainder coefficient data. This situation is defined as timing 2. The principle can be referred to Fig.14 shown.

[0251] In addition to the above, the high-order data of the remainder is not necessarily determined by the number of bits of the remainder data, that is, the high-order data of the remainder can be determined by the lookup table method described above. For example, among the 63 remainder coefficient data, the remainder coefficient data accumulates to 13 grayscale values, that is, it contains 13 1s and 50 0s. Then in the mixed transmission stage, for example, 8 groups of PWM are still required to send all the common integer data. Then, at least 8 remainder coefficient data are determined to be stored by means of a lookup table. Here, it can be 8 1s or 8 0s. In this case, the high-order data of the remainder does not only represent the number of bits of the remainder data, but indicates that it can represent multiple remainder coefficients.

[0252] In another embodiment, data packet A and data packet B are mixed and sent in the front section of the display frame, and data packet B is sent in the rear section of the display frame. Since data packet B is not stored, it must be displayed after it is sent. This situation also includes two situations. Data packet A and data packet B are sent alternately, that is, a data packet A is sent and a data packet B is sent. The stored remainder coefficient data is also used at intervals in the displayed PWM. This situation is defined as timing 1. The principle can be referred to Fig.13 In addition to the alternating transmission of data packets A and B, data packet B can also be sent randomly or out of order. This situation can be defined as timing 3. In this case, which groups of PWM use the stored remainder coefficient data is random. In practice, this situation is rarely used. The principle can be referred to Figure 6 Optionally, in the front section of the display frame, data packet A or data packet B is sent to the first storage unit 100 for storage; in the rear section of the display frame, data packet B is not stored and is directly sent through the data bus, or data packet B is sent to the first storage unit 100 for storage.

[0253] Optionally, a grayscale data transmission method, the first storage unit 100 is connected to the PWM generating unit 200, and also includes a remainder coefficient parsing unit 400 connected to the first storage unit 100, and the output end of the remainder coefficient parsing unit 400 is connected to the PWM generating unit 200; the PWM generating unit 200 generates a group of PWM according to the common integer data stored in the first storage unit 100 and the remainder coefficient data parsed by the remainder coefficient parsing unit 400; in a complete display frame, a total of N groups of PWM are generated, and N is the weight of the common integer data.

[0254] Optionally, the transmission timing of the common integer data and the partial remainder coefficient data includes:

[0255] Sequence A1: The common integer data and part of the remainder coefficient data are sent in the first M groups of sequences;

[0256] Timing A2: The common integer data and part of the remainder coefficient data are sent in the first M odd-numbered timings. Timing A1 and timing A2 correspond to timing 1 and timing 2 in the display, respectively.

[0257] In a complete display frame, the PWM display timing is:

[0258] Timing 1: The remainder coefficient data in the odd-numbered PWM is determined by the stored remainder coefficient data, and the remainder coefficient data in the even-numbered PWM is transmitted by the data bus; or the remainder coefficient data in the even-numbered PWM is determined by the stored remainder coefficient data, and the remainder coefficient data in the odd-numbered PWM is transmitted by the data bus. The principle can be referred to Fig.13 shown.

[0259] Timing 2: The remainder coefficient data in the first M groups of PWM in the display frame is determined by the stored remainder coefficient data, and the remainder coefficient data in the remaining PWM is transmitted by the data bus, and the common integer is sent within the M groups of PWM timing. The principle can be referred to Fig.14 shown.

[0260] Optionally, a grayscale data transmission method is provided, wherein each display frame is switched between timing 1 and timing 2 according to a grayscale threshold value K, timing 2 is used when the grayscale of the picture is greater than or equal to the threshold value K, and timing 1 is used when the grayscale of the picture is less than the threshold value K. The switching between timing 1 and timing 2 is determined by a controller / logic processing module 500, and the controller / logic processing module 500 is connected to the remainder coefficient parsing unit 400, and is used to control whether the remainder coefficient parsing unit 400 parses the stored remainder coefficient data or receives the remainder coefficient data transmitted by the data bus.

[0261] Optionally, a grayscale data transmission method is different from the above embodiment. In this embodiment, the public integer data is composed of data packet A, the remainder coefficient data is used as data packet B, the front part of the display frame is mixed with data packet A and data packet B, and the rear part of the display frame is sent. In the front part of the display frame, data packet B can be sent only once or multiple times. The principle can be referred to Figure 6As shown. Optionally, the data packet A of the front section of the display frame is sent to the first storage unit 100 for storage, and the data packet B is sent to the second storage unit 300 for storage; in the rear section of the display frame, the data packet B is not stored, but is directly sent through the data bus, or the data packet B is sent to the second storage unit 300 for storage. The first storage unit 100 is connected to the PWM generation unit 200, and the second storage unit 300 is connected to the remainder coefficient parsing unit 400, and the remainder coefficient parsing unit 400 is connected to the PWM generation unit 200; the remainder coefficient parsing unit 400 is used to parse the remainder coefficient data received by the second storage unit 300, and the PWM generation unit 200 generates a group of PWM according to the common integer data stored in the first storage unit 100 and the remainder coefficient data parsed by the remainder coefficient parsing unit 400; in a complete display frame period, a total of N groups of PWM are generated, and N is the weight of the common integer data.

[0262] During data transmission, the weight of the remainder coefficient data W R =2 x , where x is an integer, and the weight W is usually R Stored in the driver chip or controller to reduce the transmission bandwidth of the data bus. When x≥1, it is necessary to send the remainder low-order data D[x-1:0]; the remainder low-order data D[x-1:0] is sent in the idle timing group; or, add several timing groups to send the remainder low-order data D[x-1:0]. Reference Figure 23-24 , that is, sending the remainder low-order data D[x-1:0] in the idle timing group.

[0263] Optionally, a grayscale data transmission method can be used to transmit common integer data and part of remainder coefficient data of the next display frame as well as register data and dual-edge instructions in an idle timing group.

[0264] The above is only a preferred embodiment of the present application. It should be understood that the present application is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present application, and shall be within the scope of protection of the claims attached to the present application.

Claims

1. A grayscale data display driving module, It is characterized in that It comprises a first storage unit (100), a remainder coefficient analysis unit (400) and a PWM generation unit (200); A first storage unit (100) stores common integer data of grayscale data and remainder high-bit data in remainder data, wherein the common integer data is output to a PWM generating unit (200); the remainder high-bit data is the i-th bit, or the [(ib),i]-th bit, of the remainder data; the remainder data of other bits are used as remainder coefficient data, wherein 1≤b; or the remainder high-bit data is calculated by the remainder data; the remainder high-bit data can be displayed in multiple groups of PWM; A remainder coefficient analysis unit (400) controls the first storage unit (100) to selectively output remainder high-order data to the PWM generation unit (200); When the first storage unit (100) does not output the remainder high-order data, the remainder coefficient data is transmitted to the PWM generation unit (200) via the data bus; A PWM generating unit (200) generates PWM for display according to common integer data and remainder high-bit data, or generates PWM for display according to common integer data and remainder coefficient data; The PWM generating unit (200) or the remainder coefficient analyzing unit (400) stores the remainder coefficient data and the weight W of the remainder high-order data. R ; The actually displayed gray value of the remainder coefficient data = W R × the remainder coefficient data; the actually displayed gray value of the high-order remainder data = W R × the high-order remainder data, where the W R = 2 x , where x is an integer.

2. A grayscale data display driving module according to claim 1, It is characterized in that The remainder coefficient data is sent to a remainder coefficient parsing unit (400), parsed by the remainder coefficient parsing unit (400), and then transmitted to a PWM generating unit (200).

3. A grayscale data display driving module according to claim 1, It is characterized in that The remainder coefficient data is sent to the first storage unit (100) for storage, parsed by the remainder coefficient parsing unit (400), and then transmitted to the PWM generating unit (200).

4. The grayscale data display driving module according to claim 1, It is characterized in that The remainder coefficient data is directly sent to the PWM generation unit (200).

5. The grayscale data display driving module according to claim 1, It is characterized in that The first storage unit (100) is composed of a memory 1-A and a memory 1-B, and the memory 1-A and the memory 1-B use a ping-pong structure to alternately send and receive data; In a complete display frame, the common integer data and remainder high-order data of the current display frame are stored in the memory 1-A. When the memory 1-A outputs the remainder high-order data, the data bus transmits the common integer data and remainder high-order data of the next display frame to the memory 1-B.

6. The grayscale data display driving module according to claim 1, It is characterized in that The first storage unit (100) comprises only one memory.

7. The grayscale data display driving module according to claim 1, It is characterized in that The common integer data and the remainder high-order data are mixed and sent, including: The common integer data and the remainder high-order data are mixed to form data packet A for cyclic transmission.

8. The grayscale data display driving module according to claim 1, It is characterized in that The common integer data and the remainder high-order data are sent in a mixed manner, including: the common integer data is used as data packet A, the remainder high-order data is used as data packet B, and data packet A and data packet B are sent in a mixed manner.

9. The grayscale data display driving module according to claim 1, It is characterized in that The common integer data and the remainder high-order data are mixed and sent, including: the common integer data and the remainder high-order data are mixed to form a data packet A, the remainder coefficient data is used as a data packet B, and the data packet A and the data packet B are mixed and sent.

10. The grayscale data display driving module according to claim 1, It is characterized in that The remainder coefficient analysis unit (400) and the PWM generation unit (200) are packaged together as a PWM generation device.

11. The grayscale data display driving module according to claim 1, It is characterized in that The PWM generating unit (200) is packaged as a PWM generating device, and the remainder coefficient analyzing unit (400) is electrically connected to the PWM generating device.

12. The grayscale data display driving module according to claim 1, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM where the remainder coefficient data is always 0, where j takes the value of [0, x-1].

13. The grayscale data display driving module according to claim 1, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM whose remainder coefficient data is always 0 and the additional PWM, where j takes the value of [0, x-1].

14. The grayscale data display driving module according to claim 1, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM when there is no need to transmit the remainder coefficient data, where j is [0, x-1]; the corresponding PWM display period is extended to ensure that the grayscale value corresponding to the display period is greater than or equal to the common integer data + remainder coefficient data + remainder low-order data D[j].

15. The grayscale data display driving module according to claim 1, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM when the remainder coefficient data does not need to be transmitted, where j takes the value of [0, x-1]; the corresponding PWM display period is not extended, and when the common integer data + remainder coefficient data + remainder low-order data D[x-1:0] is greater than the grayscale data corresponding to the PWM, the overflow part is ignored.

16. The grayscale data display driving module according to claim 1, It is characterized in that In a complete display frame, the first M groups of PWM or the first M odd-numbered groups of PWM are displayed using the common integer data and the remainder high-order data stored in the first storage unit (100), and the remaining groups of PWM alternately use the remainder high-order data stored in the first storage unit (100) and the remainder coefficient data transmitted by the data bus; In one display frame period, the PWM display timing is: Timing 1: The odd-numbered PWM includes common integer data and remainder high-order data, and the even-numbered PWM includes common integer data and remainder coefficient data; or the even-numbered PWM includes common integer data and remainder high-order data, and the odd-numbered PWM includes common integer data and remainder coefficient data; or, Timing 2: The first M groups of PWM include common integer data and remainder high-order data, and the remainder coefficient data and remainder high-order data are displayed alternately in the remaining PWM, and the common integer is sent completely within the M groups of PWM display period.

17. A grayscale data display driving module according to claim 16, It is characterized in that The remainder coefficient analysis unit (400) controls the remainder high-order data to be output to the PWM generation unit (200) according to the timing 1 or the timing 2; Between each display frame, a dynamic switching method is used to switch between timing 1 and timing 2.

18. A grayscale data display driving module according to claim 17, It is characterized in that The switching between the timing 1 and the timing 2 is completed by a controller / logic processing module (500), the controller / logic processing module (500) is connected to the remainder coefficient analysis unit (400), the controller / logic processing module (500) has a built-in threshold value K, and controls the remainder coefficient analysis unit (400) according to the threshold value K to analyze the stored remainder coefficient data or analyze the remainder coefficient data transmitted by the data bus.

19. A grayscale data display driving module according to claim 18, It is characterized in that The timing 1 and the timing 2 are dynamically switched according to the grayscale of the picture. When the grayscale of the picture is greater than or equal to the grayscale threshold K, the timing 2 is used, and when it is less than the grayscale threshold K, the timing 1 is used. The grayscale threshold K represents: The grayscale value of a complete display frame; Or, the average gray value corresponding to each PWM in a complete display frame; Or, determine whether the common integer is less than a certain threshold value, and further, count the number of pixels meeting the condition in the display area to see whether it is less than a certain preset value.

20. A grayscale data display driving module, It is characterized in that It comprises a first storage unit (100), a second storage unit (300) and a PWM generating unit (200); A first storage unit (100) stores common integer data of grayscale data and outputs the data to a PWM generation unit (200); A second storage unit (300) stores the remainder data of the grayscale data and outputs it to the PWM generating unit (200), and after the remainder data is displayed, stores the remainder data of other bits and continuously outputs it to the PWM generating unit (200) until all the remainder data are displayed; The PWM generating unit (200) generates PWM for display according to the common integer data and the remainder data; the gray value actually displayed by the remainder coefficient data = W R × remainder coefficient data; the gray value actually displayed by the remainder high-order data = W R × remainder high-order data, the W R =2 x , where x is an integer, W R is the weight; The storage capacity of the second storage unit (300) is smaller than that of the first storage unit (100); The first storage unit (100) is composed of a memory 1-A and a memory 1-B, and the memory 1-A and the memory 1-B use a ping-pong structure to alternately send and receive data; within a complete display frame, the common integer data used by the current display frame is stored in the memory 1-A, and when the second storage unit (300) outputs remainder data, the common integer data of the next display frame transmitted by the data bus is stored in the memory 1-B; or, The first storage unit (100) comprises only one memory.

21. A grayscale data display driving module, It is characterized in that It comprises a first storage unit (100), a second storage unit (300) and a PWM generating unit (200); A first storage unit (100) stores common integer data of grayscale data and outputs the data to a PWM generation unit (200); A second storage unit (300) storing remainder data of grayscale data; It also includes a remainder coefficient analysis unit (400) for controlling the second storage unit (300) to selectively output remainder data to the PWM generation unit (200), wherein the remainder data is remainder high-order data; When the second storage unit (300) does not output the remainder high-order data, the remainder coefficient data is transmitted to the PWM generation unit (200) via the data bus; A PWM generating unit (200) generates PWM for display according to the common integer data and the remainder high-order data or the remainder coefficient data; The remainder high-order data is the i-th bit of the remainder data, or the [(ib),i]-th bit; the remainder data of other bits are used as remainder coefficient data, wherein 1≤b; or, the remainder high-order data is obtained by calculating the remainder data; the remainder high-order data can be displayed in multiple groups of PWM; the PWM generation unit (200) or the remainder coefficient analysis unit (400) stores the remainder coefficient data and the weight W of the remainder high-order data. R ; The gray value actually displayed by the remainder coefficient data = W R × remainder coefficient data; the gray value actually displayed by the remainder high-order data = W R × remainder high-order data, the W R =2 x , where x is an integer; The storage capacity of the second storage unit (300) is smaller than that of the first storage unit (100); The first storage unit (100) is composed of a memory 1-A and a memory 1-B, and the memory 1-A and the memory 1-B use a ping-pong structure to alternately send and receive data; within a complete display frame, the common integer data used by the current display frame is stored in the memory 1-A, and when the second storage unit (300) outputs remainder data, the common integer data of the next display frame transmitted by the data bus is stored in the memory 1-B; or, The first storage unit (100) comprises only one memory.

22. A grayscale data display driving module according to claim 21, It is characterized in that The common integer data and the remainder high-order data are mixed and sent, including: The common integer data and the remainder high-order data are mixed to form data packet A for cyclic transmission.

23. The grayscale data display driving module according to claim 21, It is characterized in that The common integer data and the remainder high-order data are mixed and sent, including: The public integer data is sent as data packet A, the remainder high-order data is sent as data packet B, and data packet A and data packet B are sent mixedly.

24. The grayscale data display driving module according to claim 21, It is characterized in that The common integer data and the remainder high-order data are mixed and sent, including: The common integer data and the remainder high-order data are mixed to form data packet A, and the remainder coefficient data is used as data packet B. Data packet A and data packet B are mixed and sent.

25. The grayscale data display driving module according to claim 21, It is characterized in that The remainder coefficient analysis unit (400) and the PWM generation unit (200) are packaged together as a PWM generation device.

26. The grayscale data display driving module according to claim 21, It is characterized in that The PWM generating unit (200) is packaged as a PWM generating device, and the remainder coefficient analyzing unit (400) is electrically connected to the PWM generating device.

27. The grayscale data display driving module according to claim 21, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM where the remainder coefficient data is always 0, where j takes the value of [0, x-1].

28. The grayscale data display driving module according to claim 21, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM whose remainder coefficient data is always 0 and the additional PWM, where j takes the value of [0, x-1].

29. The grayscale data display driving module according to claim 21, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM when there is no need to transmit the remainder coefficient data, where j is [0, x-1]; the corresponding PWM display period is extended to ensure that the grayscale value corresponding to the display period is greater than or equal to the common integer data + remainder coefficient data + remainder low-order data D[j].

30. The grayscale data display driving module according to claim 21, It is characterized in that When x≥1, it is necessary to send additional remainder low-order data D[x-1:0] for display, and the display method includes: The remainder low-order data D[j] is displayed in the PWM when the remainder coefficient data does not need to be transmitted, where j takes the value of [0, x-1]; the corresponding PWM display period is not extended, and when the common integer data + remainder coefficient data + remainder low-order data D[x-1:0] is greater than the grayscale data corresponding to the PWM, the overflow part is ignored.

31. A grayscale data display driving module according to claim 21, It is characterized in that In a complete display frame, the first M groups of PWM or the first M odd-numbered groups of PWM are displayed using the common integer data and the remainder high-order data stored in the first storage unit (100), and the remaining groups of PWM alternately use the remainder high-order data stored in the first storage unit (100) and the remainder coefficient data transmitted by the data bus; In one display frame period, the PWM display timing is: Timing 1: The odd-numbered PWM includes common integer data and remainder high-order data, and the even-numbered PWM includes common integer data and remainder coefficient data; or the even-numbered PWM includes common integer data and remainder high-order data, and the odd-numbered PWM includes common integer data and remainder coefficient data; or, Timing 2: The first M groups of PWM include common integer data and remainder high-order data, and the remainder coefficient data and remainder high-order data are displayed alternately in the remaining PWM, and the common integer is sent completely within the M groups of PWM display period.

32. A grayscale data display driving module according to claim 30, It is characterized in that The remainder coefficient analysis unit (400) controls the remainder high-order data to be output to the PWM generation unit (200) according to the timing 1 or the timing 2; Between each display frame, a dynamic switching method is used to switch between timing 1 and timing 2.

33. A grayscale data display driving module according to claim 32, It is characterized in that The switching between the timing 1 and the timing 2 is completed by a controller / logic processing module (500), the controller / logic processing module (500) is connected to the remainder coefficient analysis unit (400), the controller / logic processing module (500) has a built-in threshold value K, and controls the remainder coefficient analysis unit (400) according to the threshold value K to analyze the stored remainder coefficient data or analyze the remainder coefficient data transmitted by the data bus.

34. A grayscale data display driving module according to claim 32, It is characterized in that The timing 1 and the timing 2 are dynamically switched according to the grayscale of the picture. When the grayscale of the picture is greater than or equal to the grayscale threshold K, the timing 2 is used, and when it is less than the grayscale threshold K, the timing 1 is used. The grayscale threshold K represents: The grayscale value of a complete display frame; Or, the average gray value corresponding to each PWM in a complete display frame; Or, determine whether the common integer is less than a certain threshold value, and further, count the number of pixels meeting the condition in the display area to see whether it is less than a certain preset value.

35. A grayscale data transmission method, It is characterized in that The method includes: S100: Data grouping, dividing each frame of grayscale data into common integer data and remainder data, wherein the remainder data is divided into several groups of remainder coefficient data; S200: Data transmission: firstly, the common integer data and part of the remainder coefficient data are mixed and transmitted, and then, after the common integer data is transmitted, the remaining remainder coefficient data is transmitted.

36. A grayscale data transmission method according to claim 35, It is characterized in that The transmission timing of the common integer data and the partial remainder coefficient data includes: Sequence A1: The common integer data and part of the remainder coefficient data are sent in the first M groups of sequences; Timing A2: The common integer data and part of the remainder coefficient data are sent in the timing of the first M odd groups; The timing A1 and timing A2 can be switched between each display frame according to the grayscale threshold K. When the grayscale of the picture is greater than or equal to the threshold K, the timing A2 is used, and when the grayscale is less than the threshold K, the timing A1 is used.

37. A grayscale data transmission method according to claim 35, It is characterized in that The data sending in S200 includes: S201: The common integer data and part of the remainder coefficient data are formed into a data packet A, and the remaining remainder coefficient data are formed into a data packet B; S202: Data transmission, first cyclically sending data packet A, then sending data packet B; or first mixedly sending data packet A and data packet B, then sending data packet B; or; S201: The common integer data is formed into a data packet A, part of the remainder coefficient data is formed into a data packet B1, and the rest of the remainder data is formed into B2; S202: Data transmission: firstly, mixedly transmit data packet A and data packet B1, and then transmit data packet B2.

38. A grayscale data transmission method according to claim 35, It is characterized in that The part of the remainder coefficient data is the remainder high-order data in the remainder data, and the remainder high-order data refers to the remainder coefficient data that can be displayed in multiple groups of PWM; The remainder high-order data is the i-th bit, or the [(ib)-i]-th bit of the remainder data; The remainder data of other bits are used as remainder coefficient data, where 1≤b; Alternatively, the remainder high-order data is obtained by calculating the remainder data.

39. A grayscale data transmission method according to claim 35, It is characterized in that The common integer data and part of the remainder coefficient data are stored in the driver chip; The remaining remainder coefficient data is not stored or is stored in the driver chip.

40. A grayscale data transmission method according to claim 35, It is characterized in that The weight W of the remainder coefficient data R =2 x , where x is an integer; When x≥1, it is necessary to send the remainder low-order data D[x-1:0]; The remainder low-order data D[x-1:0] is sent in an idle timing group; Or, add several groups of timing to send the remainder low-order data D[x-1:0].

41. A grayscale data transmission method according to claim 35, It is characterized in that The idle timing groups can be used to transmit common integer data and partial remainder coefficient data of the next display frame as well as register data and double-edge instructions.

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