Memory array and method of manufacturing the same

Abstract

The present disclosure provides a storage array and a manufacturing method thereof. The storage array comprises: mn / 2 single crystal silicon pillars arranged in m rows and n columns, the single crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or located in odd rows and odd columns and even rows and even columns; n / 2 bit lines arranged in parallel, each bit line is connected to the lower part of two adjacent columns of single crystal silicon pillars; m word lines arranged in parallel, each word line wraps the middle part of a row of single crystal silicon pillars; and mn / 2 capacitors, the lower plates of the capacitors are respectively electrically connected to the upper parts of the mn / 2 single crystal silicon pillars. The embodiments of the present disclosure can increase the density of storage units in the storage array, or increase the capacitance of the storage units.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a memory array with higher memory cell density and a method for manufacturing the same. Background Technology

[0002] To address the difficulty in expanding storage capacity, a new method for increasing storage cell density—4F—has been proposed. 2 Structure. 4F 2 The structure includes multiple vertical transistors and multiple capacitors connected to the top of the vertical transistors. Figure 1 It's 4F 2 Top view of the structure. (Reference) Figure 1 4F 2 The structure can be fabricated using a GAA (Gate All-Around) 3D transistor. The transistor is positioned perpendicular to the substrate surface, and the capacitor is electrically connected to the top surface of the transistor. From bottom to top, the bit line (BL), dielectric layer, word line (WL), and capacitor are arranged in this order. (Reference) Figure 1 From a top-down view, in related technologies, multiple transistors (and capacitors located on top of the transistors) are arranged at the intersections of bit lines and word lines in a checkerboard pattern, i.e., in a checkerboard arrangement.

[0003] In the above three-dimensional structure, since the word lines connecting the gate need to wrap around the single-crystal silicon pillar, the spacing between two adjacent word lines is small, which often causes large coupling noise.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a storage array and a method for manufacturing the same, which at least partially overcomes the problem of large storage capacitor coupling noise caused by limitations and defects in related technologies.

[0006] According to one aspect of this disclosure, a memory array is provided, comprising: mn / 2 single-crystal silicon pillars arranged in m rows and n columns, the single-crystal silicon pillars being located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns; n / 2 parallel bit lines, each bit line connecting the lower part of two adjacent columns of single-crystal silicon pillars, each bit line connecting to different single-crystal silicon pillars; m parallel word lines, each word line wrapping around the middle part of one row of single-crystal silicon pillars; and mn / 2 capacitors, the lower plates of the capacitors being electrically connected to the upper parts of the mn / 2 single-crystal silicon pillars respectively.

[0007] In one exemplary embodiment of this disclosure, the cross-section of the single-crystal silicon pillar is circular.

[0008] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal, and the spacing between the word lines is equal.

[0009] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines.

[0010] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines. times.

[0011] In one exemplary embodiment of this disclosure, a dielectric layer is disposed between the bit line and the word line, and the dielectric layer is made of silicon nitride and / or silicon oxide.

[0012] In one exemplary embodiment of this disclosure, both the bit line and the word line are straight lines.

[0013] In one exemplary embodiment of this disclosure, the capacitor is aligned with the axis of the monocrystalline silicon pillar.

[0014] According to one aspect of this disclosure, a method for fabricating a memory array is provided, comprising: providing an SOI wafer; etching the device layer silicon of the SOI wafer to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, the single-crystal silicon pillars being located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns; fabricating n / 2 columns of parallel bit lines on the device layer silicon, each bit line connecting the lower part of two adjacent columns of single-crystal silicon pillars, and each bit line connecting to different single-crystal silicon pillars; depositing a dielectric on the bit lines to create a dielectric layer enclosing the bit lines and the lower part of the single-crystal silicon pillars; after surface oxidation of the single-crystal silicon pillars, fabricating m rows of parallel word lines on the dielectric layer, each word line enclosing the middle part of a row of single-crystal silicon pillars, the upper surface of the word line not exceeding the upper surface of the single-crystal silicon pillars; and fabricating capacitors above the upper part of the single-crystal silicon pillars.

[0015] In one exemplary embodiment of this disclosure, the fabrication of n / 2 parallel rows of bit lines on the device layer silicon includes: etching n / 2 parallel rows of bit lines downwards onto the device layer silicon.

[0016] In one exemplary embodiment of this disclosure, the fabrication of n / 2 parallel rows of bit lines on the device layer silicon includes: fabricating the n / 2 parallel rows of bit lines on the device layer silicon by a deposition process.

[0017] In one exemplary embodiment of this disclosure, the cross-section of the monocrystalline silicon pillar is circular, and the capacitor is aligned with the axis of the monocrystalline silicon pillar.

[0018] In one exemplary embodiment of this disclosure, the word line is a straight line and the bit line is a straight line.

[0019] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal, and the spacing between the word lines is equal.

[0020] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines.

[0021] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines. times.

[0022] In one exemplary embodiment of this disclosure, the dielectric layer is made of silicon nitride and / or silicon oxide.

[0023] In one exemplary embodiment of this disclosure, the method further includes implanting first ions into the device layer silicon before etching the single-crystal silicon pillar.

[0024] In one exemplary embodiment of this disclosure, the method further includes: implanting a second ion into the region corresponding to the bit line before or after the bit line is fabricated.

[0025] The embodiments disclosed herein, by setting the storage cells in a honeycomb pattern, have a higher storage cell density than the storage cells arranged in a checkerboard pattern in related technologies, which can effectively increase the number of storage cells in the storage array and increase the storage capacity per unit area of ​​the chip; in addition, by staggering the vertical transistors, the minimum spacing between word lines can be increased, reducing coupling noise.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 It's 4F 2 A top view of the structure.

[0029] Figure 2This is a schematic diagram of the structure of the storage array in an exemplary embodiment of this disclosure.

[0030] Figure 3 This is a flowchart of the manufacturing process of the storage array in this embodiment of the present disclosure.

[0031] Figure 4 yes Figure 3 A schematic diagram of step S31.

[0032] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of step S32.

[0033] Figures 6A to 6D yes Figure 3 A schematic diagram of step S33.

[0034] Figure 7 yes Figure 3 A schematic diagram of step S34.

[0035] Figure 8A and Figure 8B yes Figure 3 A schematic diagram of step S35.

[0036] Figure 9A and Figure 9B yes Figure 3 A schematic diagram of step S36.

[0037] Figure 10 This is a schematic diagram of the storage array layout in another embodiment of this disclosure. Detailed Implementation

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0039] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted.

[0040] Detailed description of example embodiments of the present disclosure is provided below with reference to the accompanying drawings.

[0041] Figure 2 is a schematic structural diagram of a memory array in an exemplary embodiment of the present disclosure.

[0042] With reference to Figure 2 , the memory array 200 may include:

[0043] mn / 2 monocrystalline silicon columns 21 arranged in m rows and n columns, wherein the monocrystalline silicon columns are located in odd rows and even columns and even rows and odd columns, or located in odd rows and odd columns and even rows and even columns;

[0044] n / 2 parallel bit lines 22, wherein each bit line is connected to lower parts of two adjacent columns of monocrystalline silicon columns, and the monocrystalline silicon columns connected by each bit line are all different;

[0045] m parallel word lines 23, wherein each word line wraps a middle part of one row of monocrystalline silicon columns;

[0046] mn / 2 capacitors 24, wherein lower plates of the capacitors are electrically connected to upper parts of the mn / 2 monocrystalline silicon columns respectively.

[0047] In Figure 2 the illustrated embodiment, both the bit lines 22 and the word lines 23 are straight lines. In an embodiment of the present disclosure, a straight line means that the axis of symmetry is a straight line. Since the word line 23 is fully connected to the gate of a vertical transistor and completely wraps the monocrystalline silicon column, the width of the word line near the monocrystalline silicon column is larger than the width at other positions. The axis of symmetry (length direction) of the word line 23 is a straight line, but its edges have radian near the monocrystalline silicon column (as in Figure 2 the protrusion of the word line in).

[0048] In Figure 2 the illustrated embodiment, the cross-section of the monocrystalline silicon column is circular, the cross-section of the capacitor is circular, and the capacitor is axially aligned with the monocrystalline silicon column. It can be seen from the figure that compared with the memory cells arranged in a checkerboard pattern in Figure 1 , the word lines according to an embodiment of the present disclosure have a wider minimum spacing (the distance between two protrusions), thereby reducing coupling noise.

[0049] In other embodiments of the present disclosure, since the minimum spacing between word lines is increased, the cross-section of the capacitor can also be arranged as an ellipse, such that the axial length of the ellipse parallel to the word line is greater than the axial length parallel to the bit line, which increases the area of the capacitor without increasing the area occupied by the memory array, increases the capacitance, and further reduces coupling noise.

[0050] In addition, in Figure 2In the illustrated embodiment, the spacing between bit lines 22 is equal, and the spacing between word lines 23 is equal (the spacing here refers to the spacing between adjacent straight sections of two word lines); in other embodiments of this disclosure, the spacing between bit lines 22 may also have two or more sizes, and the spacing between word lines 23 may also have two or more sizes, and this disclosure does not impose any special restrictions on this.

[0051] When the spacing between bit lines 22 and word lines 23 are equal, the spacing between word lines 23 can be set to be equal to the spacing between bit lines 22. This means that the spacing between single-crystal silicon pillars in different rows is greater than the spacing between adjacent single-crystal silicon pillars in the same row. In some embodiments, the spacing between single-crystal silicon pillars in different rows can also be set to be equal to the spacing between adjacent single-crystal silicon pillars in the same row, that is, the spacing between word lines 23 is set to be the spacing between bit lines 22. times.

[0052] Figure 3 This is a flowchart of the manufacturing process of the storage array in this embodiment of the present disclosure.

[0053] refer to Figure 3 The storage array manufacturing method 300 may include:

[0054] Step S31: Provide an SOI wafer;

[0055] Step S32: Etch mn / 2 single-crystal silicon pillars arranged in m rows and n columns on the device layer silicon of the SOI wafer. The single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.

[0056] Step S33: Fabricate n / 2 columns of parallel bit lines on the device layer silicon, with each bit line connecting the lower part of two adjacent columns of single-crystal silicon pillars, and each bit line connecting to a different single-crystal silicon pillar.

[0057] Step S34: Deposit dielectric on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar;

[0058] Step S35: After surface oxidation of the single-crystal silicon pillar, m rows of parallel word lines are manufactured on the dielectric layer. Each word line wraps around the middle of a row of single-crystal silicon pillars, and the upper surface of the word line is not higher than the upper surface of the single-crystal silicon pillar.

[0059] Step S36: Fabricate a capacitor above the upper part of the single-crystal silicon pillar.

[0060] Figure 4 Figure 9 is Figure 3 The process flow diagram shown is a schematic diagram of the technological process.

[0061] Figure 4 yes Figure 3A schematic diagram of step S31.

[0062] In this embodiment of the disclosure, the memory array is fabricated on an SOI wafer. SOI (Silicon-On-Insulator) refers to the presence of a buried oxide layer 42 (SiO2) between a substrate silicon layer 41 and a device layer silicon layer 43.

[0063] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of step S32.

[0064] refer to Figure 5A The silicon 43 layer of the device can be etched in m rows and n columns (e.g., through processes such as masking and exposure of the pillar holes) Figure 5A The single-crystal silicon pillars 21 are arranged in a pattern of mn / 2 (m=4, n=10), such that the single-crystal silicon pillars 21 are located in odd-numbered rows and even-numbered columns, or in odd-numbered rows and even-numbered columns. In one embodiment of this disclosure, the pillar holes (i.e., the cross-sections of the single-crystal silicon pillars) are circular to provide a larger conductive area with a smaller perimeter. In other embodiments, the pillar holes (i.e., the cross-sections of the single-crystal silicon pillars) may also be of other shapes, which can be determined by those skilled in the art.

[0065] In one embodiment, if subsequent Figure 6A In the etching process shown to manufacture bit lines, in step S32, it is not necessary to control the etching of the single-crystal silicon pillar down to the oxide layer 42; a certain thickness of single-crystal silicon is sufficient for etching the bit lines. In another embodiment, if subsequent... Figure 6C The deposition process shown creates bit lines. In order to ensure the insulation between the single-crystal silicon pillars, the etching depth of the oxide layer 42 can be controlled when forming the single-crystal silicon pillars.

[0066] Figure 5B yes Figure 5A The diagram shows a top-down view of the manufacturing process.

[0067] Figures 6A to 6D yes Figure 3 A schematic diagram of step S33.

[0068] refer to Figure 6A In one embodiment, the method for fabricating n / 2 columns of parallel bit lines on the device layer silicon can be achieved, for example, by etching the device layer silicon, i.e., etching the device layer silicon downwards to fabricate n / 2 columns of parallel bit lines 22. Figures 6A-6D In the given n=10, n / 2=5.

[0069] Because the doping types of the silicon in the device layer are different, and the doping type of the bit line region needs to be different from that of the silicon in the device layer, ion implantation is required in the bit line region before or after etching the bit lines to change the doping type of the bit line region (e.g., ...). Figure 6B As shown), it finally forms as follows Figure 6C The effect shown.

[0070] In another embodiment, the method of fabricating n / 2 parallel rows of bit lines 22 on the device layer silicon can be achieved, for example, by performing a deposition process on the device layer silicon (the implementation effect is as follows). Figure 6C (As shown). The deposition process can be applied to the fabrication of bit lines in both semiconductor and metal materials.

[0071] Figure 6D yes Figure 6C The diagram shows a top-down view of the effect. In this embodiment, each bit line connects two adjacent columns of single-crystal silicon pillars 21, and each bit line connects to different single-crystal silicon pillars. Those skilled in the art can set the width of the bit line 22 to connect as many adjacent single-crystal silicon pillars as possible and evenly, and the bit lines are not connected to each other.

[0072] Figure 7 yes Figure 3 A schematic diagram of step S34 is shown. In step S34, the material of the deposited dielectric layer 44 is, for example, silicon dioxide (SiO2) or silicon nitride (Si3N4), and this disclosure does not impose any special limitations on it. The dielectric layer 44 can not only effectively isolate bit lines, but also isolate bit lines and word lines, and the area of ​​the single-crystal silicon pillar it encloses corresponds to the source of the transistor.

[0073] Figure 8A and Figure 8B yes Figure 3 A schematic diagram of step S35.

[0074] refer to Figure 8A In step S35, word lines connecting the gate are fabricated. First, the surface of the single-crystal silicon pillar corresponding to the word line region is oxidized to create a gate oxide layer. Then, m rows of parallel metal word lines 23 are fabricated through metal deposition and etching (including dry etching or wet etching) processes.

[0075] Figure 8B yes Figure 8A A top view diagram illustrating the steps shown. From Figure 8B As can be seen, by setting up staggered single-crystal silicon pillars and having the control bit line 22 connect two columns of single-crystal silicon pillars 21 simultaneously, the distance between the widest part of the word line (the part that wraps the single-crystal silicon pillar) and other word lines can be increased, thereby reducing crosstalk and coupling noise.

[0076] Figure 9A and Figure 9B yes Figure 3 A schematic diagram of step S36.

[0077] refer to Figure 9A Storage capacitors 24 can be fabricated at the top of the single-crystal silicon pillar 21, forming a structure like... Figure 2 or Figure 9B The storage array structure is shown. Because adjacent columns of single-crystal silicon pillars are located in different rows in this embodiment, after manufacturing the storage capacitors, from... Figure 9A From a side viewpoint, the storage capacitors block each other. The structure of storage capacitor 24 is, for example, cup-shaped.

[0078] from Figure 9B It can be seen that, due to the increased minimum distance between word lines 23, the area of ​​storage capacitor 24 is smaller. Figure 1 The results show a significant improvement, which can effectively solve the problem of large crosstalk and coupling noise caused by excessively small word line spacing.

[0079] Figure 10 This is a schematic diagram of the storage array layout in another embodiment of this disclosure.

[0080] refer to Figure 10 When it is not necessary to increase the area of ​​the storage capacitor 24, the spacing between adjacent word lines can be reduced based on the above process. Since the single-crystal silicon pillars are arranged in an interlaced manner, the same number of single-crystal silicon pillars can be used even with a smaller word spacing. Correspondingly, the storage capacitors 24 can achieve a higher density arrangement without changing their diameter, thereby manufacturing more storage cells per unit area and effectively increasing the storage capacity of the storage array per unit area. With the same number of storage cells... Figure 10 The structure shown is relatively Figure 1 The structure shown occupies 13% less area, which can effectively reduce the size of the memory chip without reducing the storage capacity.

[0081] In summary, the memory array manufacturing method provided in this disclosure can effectively solve the problems of large crosstalk and coupling noise caused by excessively small word line spacing by setting staggered single-crystal silicon pillars, or effectively increase the density of memory cells and reduce manufacturing costs.

[0082] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A storage array, characterized in that, include: mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns; n / 2 columns of parallel bit lines, each bit line connecting the lower part of two adjacent columns of single-crystal silicon pillars, and each bit line connecting to a different single-crystal silicon pillar; m rows of parallel word lines, each word line enclosing the middle of a row of single-crystal silicon pillars; mn / 2 capacitors, the lower plates of which are electrically connected to the upper parts of mn / 2 single-crystal silicon pillars.

2. The storage array as described in claim 1, characterized in that, The cross-section of the single-crystal silicon pillar is circular.

3. The storage array as described in claim 1, characterized in that, The spacing between the bit lines is equal, and the spacing between the word lines is equal.

4. The storage array as described in claim 3, characterized in that, The spacing between the word lines is equal to the spacing between the bit lines.

5. The storage array as described in claim 3, characterized in that, The spacing between the word lines is the same as the spacing between the bit lines. times.

6. The storage array as claimed in claim 1, characterized in that, A dielectric layer is disposed between the bit line and the word line, and the dielectric layer is made of silicon nitride and / or silicon oxide.

7. The storage array as claimed in claim 1, characterized in that, Both the bit line and the word line are straight lines.

8. The storage array as claimed in claim 1, characterized in that, The capacitor is aligned with the axis of the monocrystalline silicon pillar.

9. A method for manufacturing a storage array, characterized in that, include: Provide SOI wafers; The device layer silicon of the SOI wafer is etched to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns. n / 2 columns of parallel bit lines are fabricated on the silicon of the device layer. Each bit line connects to the lower part of two adjacent columns of single-crystal silicon pillars, and each bit line connects to a different single-crystal silicon pillar. A dielectric is deposited on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar; After surface oxidation of the single-crystal silicon pillar, m rows of parallel word lines are manufactured on the dielectric layer. Each word line wraps around the middle of a row of single-crystal silicon pillars, and the upper surface of the word line is not higher than the upper surface of the single-crystal silicon pillar. A capacitor is fabricated above the upper part of the single-crystal silicon pillar.

10. The manufacturing method as described in claim 9, characterized in that, The fabrication of n / 2 parallel rows of bit lines on the silicon device layer includes: The device layer silicon is etched downwards into n / 2 columns of parallel bit lines.

11. The manufacturing method as described in claim 9, characterized in that, The fabrication of n / 2 parallel rows of bit lines on the silicon device layer includes: The bit lines are fabricated on the silicon device layer by a deposition process, with n / 2 columns arranged in parallel.

12. The manufacturing method as described in claim 9, characterized in that, The cross-section of the single-crystal silicon pillar is circular, and the capacitor is aligned with the axis of the single-crystal silicon pillar.

13. The manufacturing method as described in claim 9, characterized in that, The word line is a straight line, and the bit line is a straight line.

14. The manufacturing method as described in claim 9, characterized in that, The spacing between the bit lines is equal, and the spacing between the word lines is equal.

15. The manufacturing method as described in claim 14, characterized in that, The spacing between the word lines is equal to the spacing between the bit lines.

16. The manufacturing method as described in claim 14, characterized in that, The spacing between the word lines is the same as the spacing between the bit lines. times.

17. The manufacturing method as described in claim 9, characterized in that, The dielectric layer is made of silicon nitride and / or silicon oxide.

18. The manufacturing method as described in claim 9, characterized in that, Also includes: Before etching the single-crystal silicon pillar, a first ion is implanted into the silicon layer of the device.

19. The manufacturing method as described in claim 18, characterized in that, Also includes: Before or after the bit line is fabricated, a second ion is injected into the region corresponding to the bit line.

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