Display device

Abstract

A display device is provided. The display device includes: a first data line extending along a first direction, arranged in a display area, and connected to a first display element; a second data line extending along the first direction, arranged in the display area, and connected to a second display element; an auxiliary line arranged in a first non-display area and connecting the first data line to the second data line; and a plurality of patterns arranged around the auxiliary line in the first non-display area to be separated from the auxiliary line.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0152598 filed on November 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device including a transmission area. Background Art

[0003] Recently, display devices have been used in various fields. In consumer electronic products, display devices are expected to be thin and lightweight.

[0004] Display devices have been developed to have larger display areas with more functions that can be combined or associated with the display devices. In order to add various functions while increasing the display area, research on display devices including areas in the display area for adding various functions instead of displaying images is ongoing. Summary of the invention

[0005] One or more embodiments include a display device including a transmissive region within a display region, the transmissive region being a region for adding various functions and for transmitting light. However, it should be understood that the embodiments described herein should be considered only in a descriptive sense and not for limiting the disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0007] According to an exemplary embodiment, a display device includes: a substrate including a transmission area, a display area, and a first non-display area, the display area surrounds the transmission area, and the first non-display area is located between the transmission area and the display area; a first display element and a second display element are arranged to be separated from each other in the display area, and the transmission area is located between the first display element and the second display element; a first data line extends along a first direction, is arranged in the display area, and is connected to the first display element; a second data line extends along the first direction, is arranged in the display area, and is connected to the second display element; an auxiliary line is arranged in the first non-display area and connects the first data line to the second data line; and a pattern is arranged around the auxiliary line in the first non-display area to be separated from the auxiliary line.

[0008] According to an exemplary embodiment, a display device includes: a substrate including a transmission area, a display area and a first non-display area, the display area surrounds the transmission area, and the first non-display area is located between the transmission area and the display area; a first display element and a second display element are arranged to be separated from each other in the display area, and the transmission area is located between the first display element and the second display element; a first data line extends along a first direction, is arranged in the display area, and is connected to the first display element; a second data line extends along the first direction, is arranged in the display area, and is connected to the second display element; and an auxiliary line is arranged in the first non-display area and connects the first data line to the second data line, wherein the auxiliary line includes a first portion, a second portion, a third portion, and a branch, the first portion and the second portion are parallel to the first direction, the third portion connects the first portion to the second portion and extends along an edge of the transmission area, and the branch protrudes and extends from the third portion toward a direction facing the third portion.

[0009] According to an exemplary embodiment, a display device including a display area and a transmission area includes a display layer disposed on a substrate and disposed in the display area, and a transmission hole penetrating the display layer and disposed in the transmission area. The display layer includes a non-pixel area and a first area having a plurality of pixels. The non-pixel area surrounds the transmission hole and is disposed between the first area and the transmission hole. The first pixel and the second pixel are spaced apart from each other in the first area, and the transmission hole is located between the first pixel and the second pixel. The display layer also includes a first data line and a pattern, the first data line having a first auxiliary line disposed in the non-pixel area and a first sub-data line and a second sub-data line located in the first area, the first sub-data line and the second sub-data line extending in a first direction and connected to the first pixel and the second pixel, respectively, the first auxiliary line connecting the first sub-data line to the second sub-data line, and the pattern arranged in the non-pixel area and spaced apart from the first auxiliary line.

[0010] According to an exemplary embodiment of the present invention, a display device including a display area and a transmission area includes a display layer located on a substrate and in the display area, and a transmission hole that penetrates the display layer and is arranged in the transmission area. The display layer includes a non-pixel area and a first area having a plurality of pixels. The non-pixel area surrounds the transmission hole and is placed between the first area and the transmission hole. The first pixel and the second pixel are spaced apart from each other in the first area, and the transmission hole is located between the first pixel and the second pixel. The display layer also includes a first data line, the first data line having a first auxiliary line arranged in the non-pixel area and a first sub-data line and a second sub-data line arranged in the first area, the first sub-data line and the second sub-data line extending along a first direction and connected to the first pixel and the second pixel respectively, and the first auxiliary line connecting the first sub-data line to the second sub-data line. The first auxiliary line includes a first portion, a second portion, a third portion and a first branch, the first portion and the second portion are parallel to the first direction, the third portion connects the first portion to the second portion and extends along the edge of the transmission area, and the first branch extends from the portion where the first portion is connected to the third portion along the first extension direction of the third portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain disclosed embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a perspective view of a display device according to an exemplary embodiment;

[0013] FIG. 2A to FIG. 2D is a cross-sectional view of a display device according to an exemplary embodiment;

[0014] FIG. 3A to FIG. 3C is a cross-sectional view of a display device according to an exemplary embodiment;

[0015] Figure 4 is a plan view of a display panel according to an exemplary embodiment;

[0016] Figure 5A and Figure 5B is an equivalent circuit diagram of a pixel arranged on a display panel according to an exemplary embodiment;

[0017] Figure 6 is a plan view of a portion of a display panel according to an exemplary embodiment;

[0018] Figure 7 is taken along line III-III' according to an exemplary embodiment Figure 6 a cross-sectional view of a display panel;

[0019] Figure 8 is a plan view of wiring around a component area according to an exemplary embodiment;

[0020] 9A to 9D is taken along the auxiliary line according to an exemplary embodiment Figure 8 a cross-sectional view of a display panel;

[0021] Fig.10 is a plan view of an auxiliary line arranged in a first non-display area according to an exemplary embodiment;

[0022] Fig.11 According to an exemplary embodiment Fig.10 An enlarged plan view of area A;

[0023] Fig.12 is a plan view of an auxiliary line arranged in a first non-display area according to an exemplary embodiment;

[0024] Fig.13 According to an exemplary embodiment Fig.12 an enlarged plan view of area B;

[0025] Fig.14 is taken along line IV-IV' according to an exemplary embodiment Fig.13 A cross-sectional view of region B;

[0026] Fig.15 According to an exemplary embodiment Fig.12 An enlarged plan view of the area corresponding to area B;

[0027] Fig.16A and Fig. 16B According to an exemplary embodiment Fig.15 A magnified image of any auxiliary line;

[0028] Fig.17 According to an exemplary embodiment Fig.15 An enlarged plan view of the auxiliary line (2-2); and

[0029] Fig.18 According to an exemplary embodiment Fig.12 Region B is an enlarged plan view of the region corresponding to the region. DETAILED DESCRIPTION

[0030] Now will make detailed reference to embodiment, the example of embodiment is shown in the accompanying drawings, wherein the same reference numerals refer to the same elements from time to time. In this regard, the present embodiment can have different forms, and should not be construed as being limited to the description set forth herein. Therefore, the following only describes the embodiment by reference to the drawings to illustrate the aspects of this description. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. Throughout disclosure, the statement "at least one (kind / person) of a, b and c" represents only a, only b, only c, both a and b, both a and c, both b and c, all a, b and c or its variants.

[0031] Hereinafter, the present embodiment is described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are given to the same or corresponding elements, and their repeated description is omitted.

[0032] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these components should not be limited by these terms. These terms are only used to distinguish one element from another.

[0033] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0034] It will be further understood that the terms “comprises” and / or “comprising” as used herein indicate the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0035] It will be understood that when a layer, region or element is referred to as being “formed on” another layer, region or element, the layer, region or element may be directly or indirectly formed on the other layer, region or element. For example, intervening layers, regions or elements may be present.

[0036] For the convenience of explanation, the size of the elements in the drawings may be enlarged or reduced. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0037] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0038] In the present specification, "A and / or B" means A or B or A and B. In the present specification, "at least one of A and B" means A or B or A and B.

[0039] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, the layer, region, or element may be "directly connected" to the other layer, region, or element and / or may be "indirectly connected" to the other layer, region, or element with other layers, regions, or elements interposed therebetween. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element may be "directly electrically connected" to the other layer, region, or element and / or may be "indirectly electrically connected" to the other layer, region, or element with other layers, regions, or elements interposed therebetween.

[0040] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0041] It will be understood that when a wiring is referred to as extending in a first direction or in a second direction, it may extend in the first direction or in the second direction not only in a straight line shape but also in a zigzag or curve shape.

[0042] It will be understood that when referred to as a "plane", it means when the object is viewed from above, and when referred to as a "section", it means when the object is viewed from one side of the section cut vertically of the object. It will be understood that when a first element is referred to as overlapping a second element, it means that the first element is positioned above or below the second element.

[0043] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0044] Reference Figure 1 The display device 1 may include a display area DA that emits light and a non-display area (i.e., a non-pixel area) NDA that does not emit light. The display device 1 may provide a predetermined image by using light emitted from a plurality of pixels arranged in the display area DA.

[0045] The display device 1 may include an assembly area OA. The assembly area OA may be at least partially surrounded by the display area DA. Figure 1 As shown in , the assembly area OA may be completely surrounded by the display area DA.

[0046] The non-display area NDA may include a first non-display area NDA1 surrounding the assembly area OA and a second non-display area NDA2 surrounding the display area DA. For example, the first non-display area NDA1 may completely surround the assembly area OA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0047] The component area OA may be where the following references are arranged Figure 2A The component area OA may be a transmission area through which light and / or sound output from the component to the outside or propagated from the outside toward the component may pass. In an embodiment, in the case where light passes through the component area OA, the transmittance of the component area OA may be 50% or more. In example embodiments, the transmittance may be 70% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0048] Hereinafter, the display device 1 according to the embodiment is described as an organic light-emitting display device. The display device 1 according to the embodiment is not limited thereto. In an exemplary embodiment, the display device 1 may be a display device of various types such as an inorganic light-emitting display and a quantum dot light-emitting display. For example, the emission layer of the display element (i.e., pixel) provided to the display device 1 may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0049] exist Figure 1 In the embodiment, the component area OA is arranged closer to one side (e.g., the upper right side) of the display area DA having a quadrilateral shape. The present invention is not limited thereto. In an exemplary embodiment, the shape of the display area DA may be circular, elliptical, or polygonal (such as a triangle or a pentagon). In an exemplary embodiment, the position of the component area OA may be variously changed. For example, the component area OA may be arranged closer to the central top side of the plane (e.g., the xy plane) of the display area DA.

[0050] FIG. 2A to FIG. 2D is a cross-sectional view of a display device 1 according to an embodiment. For example, FIG. 2A to FIG. 2D Can be along Figure 1 It corresponds to a cross section of the display device 1 taken along line II'.

[0051] Reference Figure 2A , the display device 1 may include a display panel 10 and an assembly 20. The display panel 10 may include a display element. The assembly 20 is positioned in the assembly area OA.

[0052] The display panel 10 may include a substrate 100, an encapsulation substrate 300a, and a display layer 200. The encapsulation substrate 300a may be an encapsulation member spaced apart from the substrate 100, and the display layer 200 may be disposed between the substrate 100 and the encapsulation substrate 300a. A sealing material 350 (sealant) may be disposed between the substrate 100 and the encapsulation substrate 300a, and the sealing material 350 covers the side surface of the display layer 200. Figure 2A In the embodiment of the present invention, the sealing material 350 is disposed on two opposite sides of the assembly area OA. When viewed from a direction perpendicular to the main surface of the substrate 100, the assembly area OA may be completely surrounded by the sealing material 350.

[0053] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate, polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) or cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer (not shown). The encapsulation substrate 300a may include glass or a polymer resin.

[0054] The display layer 200 may include a circuit layer, an organic light emitting diode OLED, and an insulating layer IL between the circuit layer and the organic light emitting diode OLED, the circuit layer including a thin film transistor TFT, and the organic light emitting diode OLED is a display element connected to the thin film transistor TFT. The thin film transistor TFT and the organic light emitting diode OLED connected thereto may be arranged in the display area DA. Some wirings WL of the display layer 200 may be positioned in the first non-display area NDA1. The wirings WL may provide predetermined signals or voltages to pixels spaced apart from each other with the assembly area OA therebetween. Figure 2A In the embodiment, the wiring WL does not overlap with the sealing material 350 in the first non-display area NDA1. The present invention is not limited thereto. In an exemplary embodiment, a portion of the sealing material 350 may overlap with the wiring WL. The insulating layer IL may include at least one inorganic insulating layer and / or at least one organic insulating layer.

[0055] The display panel 10 may include a through hole 10H corresponding to the assembly area OA. For example, the substrate 100 and the encapsulation substrate 300a may include sub-through holes 100H and 300H, respectively, each corresponding to the assembly area OA. The display layer 200 may include a sub-through hole corresponding to the assembly area OA. In an exemplary embodiment, the display panel 10 may include a through hole 10H having a first sub-through hole 100H penetrating the substrate 100, a second sub-through hole 200H penetrating the display layer 200, and a third sub-through hole 300H penetrating the encapsulation substrate 300a in the assembly area OA. The second sub-through hole 200H may be defined by a sealing material 350. The first sub-through hole 100H, the second sub-through hole 200H, and the third sub-through hole 300H overlap each other in the assembly area OA. The first sub-through hole 100H may be connected to the second sub-through hole 200H. The second sub-through hole 200H may be connected to the third sub-through hole 300H.

[0056] Elements such as an input sensing member that senses a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may be further disposed on the display panel 10 .

[0057] The component 20 may be positioned in the component area OA. The component 20 may be an electronic component that receives light or sound as input or generates light or sound as output. For example, the electronic component may be a sensor such as an infrared sensor that receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. The component 20 may use light of various wavelengths, such as visible light, infrared light, and ultraviolet light. In the case where the display panel 10 includes a through hole 10H in the component area OA, light or sound output or received from the component 20 may be more effectively utilized.

[0058] With Figure 2A Unlike the display panel 10 shown in FIG. 1 including the through hole 10H in the component area OA, some elements of the display panel 10 may not include a sub-through hole. Figure 2B As shown in FIG. 1 , the package substrate 300a includes a third sub-via hole 300H corresponding to the assembly area OA, and the substrate 100 may not include a sub-via hole. In an exemplary embodiment, the through hole 10H may include a second sub-via hole 200H penetrating the display layer 200 and a third sub-via hole 300H penetrating the package substrate 300a.

[0059] Alternatively, if Figure 2C and Figure 2D As shown in FIG, both the substrate 100 and the package substrate 300a may not include a sub-via in the assembly area OA. Figure 2CIn the embodiment, the sealing material 350 may be arranged in the first non-display area NDA1 and may surround the assembly area OA. In an exemplary embodiment, the second sub-via hole 200H may penetrate the display layer 200. The substrate 100 may cover the bottom of the second sub-via hole 200H, and the encapsulation substrate 300a may cover the top of the second sub-via hole 200H.

[0060] Figure 2D Shown along Figure 1 The cross section of the display device 1 is taken along the line IIa-IIa' and the line IIb-IIb'. Figure 2C Different, in Figure 2D In the embodiment, the sealing material 350 may not be disposed around the assembly area OA. Alternatively, the outer sealing material 360 may be positioned in the second non-display area NDA2, and the display layer 200 may be sealed from the outside air by bonding the substrate 100 to the encapsulation substrate 300a. In an exemplary embodiment, FIG. 2A to FIG. 2C The display device 1 may also include Figure 2D The outer sealing material 360 is shown in FIG. 1 to surround the display area DA.

[0061] Figure 2D The insulating layer IL may include an opening IL-OP corresponding to the assembly area OA. For example, the opening IL-OP may be formed in the assembly area OA, the opening IL-OP penetrating the insulating layer IL to expose a portion of the substrate 100. In an embodiment, any element corresponding to the assembly area OA may not be arranged between the substrate 100 and the package substrate 300a. In an exemplary embodiment, a portion of some inorganic insulating layers such as a buffer layer may remain in the assembly area OA of the substrate 100.

[0062] exist FIG. 2A to FIG. 2D In the embodiment, the component 20 is positioned below the display panel 10, that is, on one side of the substrate 100. The present invention is not limited thereto. In an exemplary embodiment, the component 20 may be at least partially inserted into the through hole 10H and positioned inside the through hole 10H so that the component 20 is confined to the display panel 10. Figure 2A The side surfaces of the through holes 10H in the embodiment are overlapped.

[0063] The component 20 may include another member other than the electronic element. In an exemplary embodiment, in the case where the display panel 10 is used as a smart watch or as an instrument panel for a car, the component 20 may be a member such as a clock hand or a needle indicating predetermined information (e.g., the speed of the vehicle, etc.). Alternatively, the component 20 may include an element such as an accessory that increases the aesthetics of the display panel 10.

[0064] FIG. 3A to FIG. 3C According to other embodiments, Figure 1A cross-sectional view of the display device 1 taken along line II'.

[0065] Reference Figure 3A , and the above reference Figure 2A Like the display device 1 described above, the display device 1 may include a display panel 10 and a component 20. In addition, the display device 1 may further include an input sensing member, an anti-reflection member, and a window disposed on the display panel 10, the input sensing member sensing a touch input.

[0066] With reference to above Figure 2A Unlike the display panel 10 described above including the encapsulation substrate 300a and the sealing material 350 as the encapsulation member, the display panel 10 according to the embodiment may include the thin film encapsulation layer 300b as the encapsulation member. In the case where the display panel 10 includes the thin film encapsulation layer 300b as the encapsulation member, the flexibility of the display panel 10 may be increased more. Hereinafter, for the convenience of description, the differences are mainly described.

[0067] The thin film encapsulation layer 300b may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3A As shown in , the thin film encapsulation layer 300 b may include a first inorganic encapsulation layer 310 , a second inorganic encapsulation layer 330 , and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 .

[0068] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide or polyethylene.

[0069] The display panel 10 may include a through hole 10H corresponding to the component area OA. For example, the substrate 100, the display layer 200, and the thin film encapsulation layer 300b may include sub-through holes 100H, 200H, and 300H, respectively, each corresponding to the component area OA. The thin film encapsulation layer 300b (for example, the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330, and the organic encapsulation layer 320) may include a hole corresponding to the component area OA. The size of the hole of the organic encapsulation layer 320 may be larger than the size of the hole of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 in the periphery of the component area OA. In an exemplary embodiment, the display panel 10 may include a through hole 10H having a first sub-through hole 100H penetrating the substrate 100, a second sub-through hole 200H penetrating the display layer 200, and a third sub-through hole 300H penetrating the thin film encapsulation layer 300b in the component area OA. The second sub-through hole 200H may penetrate the insulating layer IL. The first sub-via 100H, the second sub-via 200H, and the third sub-via 300H overlap each other in the assembly area OA. The first sub-via 100H may be connected to the second sub-via 200H. The second sub-via 200H may be connected to the third sub-via 300H.

[0070] and Figure 3A Differently, a portion of the display panel 10 may not include a sub-through hole. Figure 3B As shown in , the display layer 200 and the thin film encapsulation layer 300b may include sub through holes 200H and 300H in the assembly area OA, respectively, but the substrate 100 may not include the sub through holes.

[0071] In another example, if Figure 3C As shown in FIG. 1 , all of the substrate 100 , the display layer 200 , and the thin film encapsulation layer 300 b may not include a sub-via hole in the assembly area OA.

[0072] exist Figure 3B and Figure 3C In the invention, the substrate 100 does not include Figure 3A Since the portion of the display layer 200 in the assembly area OA is at least partially removed, light transmittance for the electronic component as the assembly 20 can be ensured.

[0073] In the case where the thin film encapsulation layer 300b does not include a through hole, each of the at least one inorganic encapsulation layer and the at least one organic encapsulation layer may cover the substrate 100 in the assembly area OA. A portion of the display layer 200 disposed between the substrate 100 and the thin film encapsulation layer 300b may not cover a portion of the substrate 100 located in the assembly area OA. A portion of the substrate 100 located in the assembly area OA may be covered by the thin film encapsulation layer 300b.

[0074] exist FIG. 3A to FIG. 3C In the embodiment, all the insulating layers IL in the assembly area OA are removed. The present invention is not limited thereto. In an exemplary embodiment, only a portion of the insulating layer IL having the multi-layer structure in the assembly area OA may be removed.

[0075] exist FIG. 3A to FIG. 3C In the embodiment, the component 20 is positioned below the display panel 10, that is, on one side of the substrate 100. The present invention is not limited thereto. In an exemplary embodiment, the component 20 may be at least partially inserted into the through hole 10H and positioned inside the through hole 10H so that the component 20 is confined to the display panel 10. Figure 3A The side surfaces of the through holes 10H in the embodiment are overlapped.

[0076] Figure 4 is a plan view of a display panel 10 according to an embodiment.

[0077] The display panel 10 may include a plurality of pixels P arranged in a display area DA. Figure 4 , the display panel 10 may include an assembly area OA, a display area DA, a first non-display area NDA1, and a second non-display area NDA2. Figure 4 A substrate 100 of the display panel 10 is shown, and for example, the substrate 100 may include an assembly area OA, a display area DA, a first non-display area NDA1, and a second non-display area NDA2.

[0078] In a top-down view, the first non-display area NDA1 may surround the component area OA. The first non-display area NDA1 is an area in which no light-emitting display element (such as an organic light-emitting diode) is arranged. A signal line may cross the first non-display area NDA1, and the signal line provides a signal to the pixels P arranged around the component area OA. The first scan driver 1100, the second scan driver 1200, the data driver 1300, and the main power line (not shown) may be arranged in the second non-display area NDA2, the first scan driver 1100 and the second scan driver 1200 provide a scan signal to each pixel P, the data driver 1300 provides a data signal to each pixel P, and the main power line provides a first power supply voltage and a second power supply voltage. The first scan driver 1100 and the second scan driver 1200 may both be arranged in the second non-display area NDA2, and arranged on two opposite sides of the display area DA, and the display area DA is located between the first scan driver 1100 and the second scan driver 1200. The first scan driver 1100, the second scan driver 1200, and the data driver 1300 may be disposed on the outer sealing material 360 (see FIG. 1 ) disposed in the second non-display area NDA2. Figure 2D ) on the outside.

[0079] exist Figure 4 In the embodiment, the data driver 1300 is adjacent to one side of the substrate 100. The present invention is not limited thereto. In an exemplary embodiment, the data driver 1300 may be arranged on a flexible printed circuit board (FPCB) electrically connected to a pad (also referred to as a "pad" or "solder pad") arranged on one side of the display panel 10.

[0080] Figure 5A and Figure 5B ⊥ is an equivalent circuit of a pixel P arranged on the display panel 10 according to the embodiment.

[0081] Reference Figure 5A , the pixel P includes a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel P may emit, for example, red light, green light, blue light, or white light from the organic light emitting diode OLED. Each of the first transistor T1 and the second transistor T2 may be implemented as a thin film transistor.

[0082] The second transistor T2 is a switching transistor, connected to the scan line SL and the data line DL, and is configured to transmit a data signal input from the data line DL to the first transistor T1 according to a switching voltage input from the scan line SL. The capacitor Cst is connected to the second transistor T2 and the power voltage line PL, and can store a voltage corresponding to a voltage difference between a voltage of the data signal transmitted from the second transistor T2 and a first power voltage ELVDD supplied to the power voltage line PL.

[0083] The first transistor T1 is a driving transistor connected to the power voltage line PL and the capacitor Cst, and can control a driving current I flowing from the power voltage line PL through the organic light emitting diode OLED in response to a voltage stored in the capacitor Cst. oled The organic light emitting diode OLED can be driven by using a driving current I oled To emit light with a predetermined brightness. The common electrode (eg, cathode) of the organic light emitting diode OLED may receive a second power voltage ELVSS.

[0084] exist Figure 5A In the embodiment, the pixel circuit PC includes two transistors and one capacitor. The present invention is not limited thereto. The number of transistors and the number of capacitors may be variously modified according to the design of the pixel circuit PC.

[0085] Reference Figure 5B, the pixel circuit PC of the pixel P may include first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 and a capacitor Cst. The first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 may be implemented as thin film transistors.

[0086] The pixel P may be connected to a first scan line SL1, a second scan line SL2, a third scan line SL3, an emission control line EL, and a data line DL, the first scan line SL1 being configured to transmit a first scan signal GW, the second scan line SL2 being configured to transmit a second scan signal GI, the third scan line SL3 being configured to transmit a third scan signal GB, the emission control line EL being configured to transmit an emission control signal EM, and the data line DL being configured to transmit a data signal DATA. In an embodiment, the third scan line SL3 may be the second scan line SL2 on the next row, and the third scan signal GB may be the second scan signal GI on the next row. For example, the third scan line of a pixel may be shared by another pixel adjacent to the pixel.

[0087] The power voltage line PL is configured to transmit a first power voltage ELVDD to the first transistor T1 , and the initialization voltage line VL is configured to transmit an initialization voltage VINT to the pixel P, which initializes the first transistor T1 and the organic light emitting diode OLED.

[0088] In the layout of the pixel circuit PC, the first scan line SL1, the second scan line SL2, the third scan line SL3, the emission control line EL, and the initialization voltage line VL may extend in the x-direction and be spaced apart from each other in the y-direction different from the x-direction. The data line DL and the power supply voltage line PL may extend in the y-direction and be spaced apart from each other in the x-direction.

[0089] The first transistor T1 is connected to the power supply voltage line PL through the fifth transistor T5 and is electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 is a driving transistor and is configured to receive the data signal DATA and supply a driving current I to the organic light emitting diode OLED according to a switching operation of the second transistor T2. oled .

[0090] The second transistor T2 is connected to the first scan line SL1 and the data line DL, is turned on in response to the first scan signal GW received through the first scan line SL1 , and performs a switching operation of transmitting the data signal DATA transmitted to the data line DL to the node N.

[0091] The third transistor T3 is connected to the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 is turned on in response to the first scan signal GW transmitted through the first scan line SL1, and is configured to diode-connect the first transistor T1.

[0092] The fourth transistor T4 is turned on in response to the second scan signal GI transmitted through the second scan line SL2 , and is configured to initialize the gate voltage of the first transistor T1 by transmitting the initialization voltage VINT from the initialization voltage line VL to the gate electrode of the first transistor T1 .

[0093] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM transmitted through the emission control line EL to form a current path so that the driving current I oled Flows in a direction from the power supply voltage line PL to the organic light emitting diode OLED.

[0094] The seventh transistor T7 is turned on in response to the third scan signal GB transmitted through the third scan line SL3 and initializes the organic light emitting diode OLED by transmitting the initialization voltage VINT from the initialization voltage line VL to the organic light emitting diode OLED. The seventh transistor T7 may be omitted.

[0095] Figure 5B A case where the fourth transistor T4 is connected to the second scan line SL2 and the seventh transistor T7 is separately connected to the third scan line SL3 is shown. In an exemplary embodiment, the seventh transistor T7 and the fourth transistor T4 may be simultaneously connected to the second scan line SL2.

[0096] Since the capacitor Cst is connected to the power voltage line PL and the gate electrode of the first transistor T1 and stores and maintains a voltage corresponding to a voltage difference between the first power voltage ELVDD and the gate voltage of the first transistor T1 , the capacitor Cst may maintain a voltage applied to the gate electrode of the first transistor T1 .

[0097] The organic light emitting diode OLED may include a pixel electrode and an opposite electrode. The opposite electrode may receive a second power supply voltage ELVSS. The organic light emitting diode OLED receives a driving current I from the first transistor T1. oled and emits light to display images.

[0098] Figure 6 is a plan view of a portion of the display panel 10 according to the embodiment.

[0099] Reference Figure 6 , some of the pixels P arranged in the display area DA may be spaced apart from each other around the component area OA. For example, the component area OA may be positioned along Figure 6Similarly, the component area OA can be located between two pixels P arranged in the ±x direction. Figure 6 Between two pixels P arranged in the ±y direction.

[0100] Two pixels P on the same column arranged along the ±y direction with the component area OA therebetween (i.e., two display elements on the same column) may be electrically connected to the same data line DL. That is, two display elements on the same column arranged along the ±y direction with the component area OA therebetween may be electrically connected to the same data line DL. The data line DL may include a first data line (or a first sub-data line) DL-L1, a second data line (or a second sub-data line) DL-L2, and an auxiliary line DL-C, the first data line DL-L1 and the second data line DL-L2 extending along the ±y direction in the display area DA, and the auxiliary line DL-C extending along the arc direction of the component area OA in the first non-display area NDA1 and connecting the first data line DL-L1 to the second data line DL-L2. For example, the auxiliary line DL-C may extend along the outer edge (i.e., edge) of the component area OA in the first non-display area NDA1 and connect the first data line DL-L1 to the second data line DL-L2. In an embodiment, the first data line DL-L1, the second data line DL-L2 and the auxiliary line DL-C may be an integrated wiring on the same layer. In an exemplary embodiment, the auxiliary line DL-C may be arranged on a layer different from the layer on which the first data line DL-L1 and the second data line DL-L2 are arranged and may be electrically connected to the first data line DL-L1 and the second data line DL-L2 through a contact hole of an insulating layer between two different layers. The auxiliary line DL-C may be arranged on a layer above the first data line DL-L1 and the second data line DL-L2 or may be arranged on a layer below the first data line DL-L1 and the second data line DL-L2.

[0101] The auxiliary line DL-C may be bent in the first non-display area NDA1. The auxiliary line DL-C may include a first portion CLa, a second portion CLb, and a third portion CLc, the third portion CLc connecting the first portion CLa to the second portion CLb. The first portion CLa and the second portion CLb may extend in the ±y direction in the first non-display area NDA1. The third portion CLc may be connected to an end of the first portion CLa, may extend around an edge of the assembly area OA (e.g., extend in an arc direction of the assembly area OA), and may be connected to an end of the second portion CLb. At the connection between the first portion CLa and the third portion CLc, the extension direction of the auxiliary line DL-C may be changed, for example, from the ±y direction (the extension direction of the first portion CLa) to the arc direction of the assembly area OA. At the connection between the second portion CLb and the third portion CLc, the extension direction of the auxiliary line DL-C may be changed, for example, from the arc direction of the assembly area OA to the ±y direction (the extension direction of the second portion CLb).

[0102] Two pixels P on the same row arranged along the ±x direction with the component area OA therebetween (i.e., two display elements on the same row) may be respectively connected and electrically connected to different scan lines SL. The scan line SL located on the left side of the component area OA may be electrically connected to the first scan driver 1100 (see Figure 4 ), and the scan line SL located on the right side of the device area OA may be electrically connected to the second scan driver 1200 (see Figure 4 ).like Figure 4 As shown in , in the case where the display panel 10 includes the two scan drivers, the pixels P arranged on two opposite sides of the component area OA may be respectively connected and electrically connected to the scan lines SL spaced apart from each other.

[0103] Figure 7 It is along Figure 6 1 is a cross-sectional view of the display panel 10 taken along line III-III'. For ease of description, some circuit elements and some wirings are omitted.

[0104] exist Figure 7 In the embodiment, the display element 130 may include Figure 5B The organic light emitting diode OLED. The thin film transistor TFT may include Figure 5A and Figure 5B For example, Figure 7 The thin film transistor TFT shown in FIG. 1 may include Figure 5A and Figure 5B The first transistor T1.

[0105] As mentioned above Figures 2A to 3CAs described, the substrate 100 may include glass or a polymer resin. The substrate 100 may include a single layer or multiple layers.

[0106] The buffer layer 110 may be positioned on the substrate 100. The buffer layer 110 may planarize the surface of the substrate 100 or prevent impurities from penetrating into the semiconductor layer on the buffer layer 110. The buffer layer 110 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and include a single layer or a multilayer including the inorganic insulating material. The buffer layer 110 may be omitted.

[0107] The thin film transistor TFT may be disposed on the buffer layer 110. The thin film transistor TFT may include a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0108] The semiconductor layer ACT may include amorphous silicon, polycrystalline silicon or an organic semiconductor material. The semiconductor layer ACT may include a source region, a drain region and a channel region, wherein the channel region is located between the source region and the drain region.

[0109] The gate electrode GE may include a single layer or a multilayer, and the single layer or the multilayer includes at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu).

[0110] The first insulating layer 111 may be disposed between the semiconductor layer ACT and the gate electrode GE. The second insulating layer 112 and the third insulating layer 113 may be disposed between the gate electrode GE and the source electrode SE and / or the drain electrode DE. Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. Figure 5A and Figure 5B The scan lines SL, SL1, SL2, and SL3 and the emission control line EL may be arranged on the same layer. Figure 5A and Figure 5B The scan lines SL, SL1, SL2, and SL3 and the emission control line EL may be disposed on the first insulating layer 111 on which the gate electrode GE is disposed.

[0111] The source electrode SE and the drain electrode DE may be respectively connected and electrically connected to the source region and the drain region of the semiconductor layer ACT through contact holes formed in the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 .

[0112] The source electrode SE and the drain electrode DE may include a single layer or a multilayer, and the single layer or the multilayer includes at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu).

[0113] The capacitor Cst may include a bottom electrode CE1 and a top electrode CE2 overlapped with each other, and a second insulating layer 112 is located between the bottom electrode CE1 and the top electrode CE2. The capacitor Cst may overlap the thin film transistor TFT. Figure 7 1 shows that the gate electrode GE of the thin film transistor TFT is used as the bottom electrode CE1 of the capacitor Cst. In an exemplary embodiment, the capacitor Cst may not overlap with the thin film transistor TFT, and the bottom electrode CE1 of the capacitor Cst may be an independent element separated from the gate electrode GE of the thin film transistor TFT. The capacitor Cst may be covered by the third insulating layer 113. The top electrode CE2 and Figure 5B The initialization voltage lines VL can be arranged on the same layer. Figure 5B The initialization voltage line VL may be disposed on the second insulating layer 112 on which the top electrode CE2 of the capacitor Cst is disposed.

[0114] The pixel circuit including the thin film transistor TFT and the capacitor Cst may be covered by the fourth insulating layer 114 and the fifth insulating layer 115. Each of the fourth insulating layer 114 and the fifth insulating layer 115 is a planarized insulating layer and may include an organic insulating layer. The fourth insulating layer 114 and the fifth insulating layer 115 may include a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a blend thereof. In an embodiment, the fourth insulating layer 114 and the fifth insulating layer 115 may include polyimide.

[0115] Various conductive layers may be further disposed on the third insulating layer 113. For example, the data line DL and the power supply voltage line PL may be disposed on the third insulating layer 113. The source electrode SE and the drain electrode DE may also be disposed on the third insulating layer 113. The data line DL and the power supply voltage line PL may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti) and include a single layer or multiple layers. In an embodiment, the data line DL and the power supply voltage line PL may include a multilayer structure of Ti / Al / Ti.

[0116] The fourth insulating layer 114 may be arranged on the data line DL and the power supply voltage line PL. For example, the fourth insulating layer 114 may cover the data line DL and the power supply voltage line PL. The connection electrode CM may be arranged on the fourth insulating layer 114. The connection electrode CM may electrically connect the pixel electrode 131 to the source electrode SE or the drain electrode DE of the thin film transistor TFT. The connection electrode CM may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti) and include a single layer or multiple layers. In an embodiment, the connection electrode CM may include a multilayer structure of Ti / Al / Ti.

[0117] An organic light emitting diode 130 as a display element may be disposed on the fifth insulating layer 115. The organic light emitting diode 130 may include a pixel electrode 131, an opposing electrode 135, and an intermediate layer 133 between the pixel electrode 131 and the opposing electrode 135.

[0118] The pixel electrode 131 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode 131 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture thereof. In an exemplary embodiment, the pixel electrode 131 may also include a reflective layer including ITO, IZO, ZnO or In on / under the reflective layer. 2 O 3 layer.

[0119] The sixth insulating layer 116 may be arranged on the fifth insulating layer 115, and the sixth insulating layer 116 covers the edge of the pixel electrode 131. The sixth insulating layer 116 may include an opening OP that exposes a portion of the pixel electrode 131. The opening OP of the sixth insulating layer 116 (the bottom surface of the opening OP) may define the emission area EA. For example, the display area DA may include the emission area EA and a non-emission area NEA located between the emission areas EA, and the non-emission area NEA surrounds the emission area EA. The sixth insulating layer 116 may correspond to the non-emission area NEA and include an organic material such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Alternatively, the sixth insulating layer 116 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0120] The intermediate layer 133 may be formed on a portion of the pixel electrode 131 exposed by the opening OP of the sixth insulating layer 116. The intermediate layer 133 includes an emission layer. The emission layer may include a polymer organic material or a low molecular weight organic material that emits light of a predetermined color. The emission layer may include a red emission layer, a green emission layer, or a blue emission layer. Optionally, the emission layer may have a multilayer structure in which a red emission layer, a green emission layer, and a blue emission layer are stacked to emit white light, or have a single-layer structure including a red emission material, a green emission material, or a blue emission material. In an embodiment, the intermediate layer 133 may include a first functional layer and / or a second functional layer, the first functional layer being arranged under the emission layer, and the second functional layer being arranged on the emission layer. The first functional layer and / or the second functional layer may include a layer that is integrated throughout a plurality of pixel electrodes 131, or may include a layer that is patterned to correspond to a plurality of pixel electrodes 131, respectively.

[0121] The counter electrode 135 may be spaced apart from the pixel electrode 131, and the intermediate layer 133 is located between the counter electrode 135 and the pixel electrode 131. The counter electrode 135 may include a conductive material with a low work function. For example, the counter electrode 135 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. Optionally, the counter electrode 135 may also include a (semi) transparent layer containing ITO, IZO, ZnO or In above / below the (semi) transparent layer containing the materials listed above. 2 O 3 layer.

[0122] exist Figure 7 In the embodiment, the data line DL and the power supply voltage line PL are arranged on the third insulating layer 113. The present invention is not limited thereto. In an exemplary embodiment, the data line DL and / or the power supply voltage line PL may be arranged on the same layer as, for example, the fourth insulating layer 114 on which the connection electrode CM is arranged.

[0123] Figure 8 is a plan view of the wirings WL around the component area OA according to the embodiment. 9A to 9D Each of the Figure 8 A cross-sectional view of the display panel 10 taken along the auxiliary line DL-C. For ease of description, Figure 8 Eight auxiliary lines DL-C arranged in the first non-display area NDA1 around the assembly area OA are shown.

[0124] The scan lines SL continuously extending in the ±x directions in the display area DA may be disconnected in the first non-display area NDA1 around the assembly area OA. Figure 8In the embodiment, the scan line SL is disconnected near the boundary between the display area DA and the first non-display area NDA1. The scan line SL may be disconnected near the boundary between the display area DA and the first non-display area NDA1 inside the first non-display area NDA1.

[0125] The data lines DL continuously extending in the ±y directions in the display area DA may bypass the assembly area OA in the first non-display area NDA1. In an exemplary embodiment, the data lines DL continuously extending in the ±y directions in the display area DA may be disconnected near a boundary between the display area DA and the first non-display area NDA1.

[0126] The auxiliary line DL-C may be arranged in the first non-display area NDA1 as part of the data line DL. The auxiliary line DL-C may include a first auxiliary line DL-C1 and a second auxiliary line DL-C2. The first auxiliary line DL-C1 and the second auxiliary line DL-C2 may be alternately arranged along the ±x direction. Each of the first auxiliary line DL-C1 and the second auxiliary line DL-C2 may include a first portion CLa, a second portion CLb, and a third portion CLc connecting the first portion CLa to the second portion CLb.

[0127] Each of the first auxiliary line DL-C1 and the second auxiliary line DL-C2 may be bent to connect the first data line DL-L1 located above the assembly area OA in the plan view to the second data line DL-L2 located below the assembly area OA in the plan view. Each of the first auxiliary line DL-C1 and the second auxiliary line DL-C2 may be a connection line connecting the first data line DL-L1 to the second data line DL-L2, the connection line being located between the first data line DL-L1 and the second data line DL-L2.

[0128] The first auxiliary line DL-C1 may be formed as one body with the first and second data lines DL-L1 and DL-L2. Fig.9A is a cross-sectional view of the first auxiliary line DL-C1. Fig.9AAs shown in , the first auxiliary line DL-C1 may include a first portion CLa connected to the end portion of the first data line DL-L1 of the display area DA and a second portion CLb connected to the end portion of the second data line DL-L2 of the display area DA. For ease of description, the dotted lines are marked as the boundary between the first data line DL-L1 and the first portion CLa, the boundary between the first portion CLa and the third portion CLc, the boundary between the third portion CLc and the second portion CLb, and the boundary between the second portion CLb and the second data line DL-L2. These boundaries do not exist in the integrated wiring of DL-L1, DL-C1, and DL-L2. For example, the first data line DL-L1, the second data line DL-L2, and the first auxiliary line DL-C1 may be arranged on the same layer of the third insulating layer 113. The first auxiliary line DL-C1 may include the same material as the first data line DL-L1 and the second data line DL-L2. In an embodiment, the first data line DL-L1, the second data line DL-L2, and the first auxiliary line DL-C1 may be arranged on the third insulating layer 113. In exemplary embodiments, the first data line DL-L1 , the second data line DL-L2 , and the first auxiliary line DL-C1 may be disposed on the fourth insulating layer 114 .

[0129] The second auxiliary line DL-C2 may include a wiring arranged on a layer different from the layer on which the first data line DL-L1 and the second data line DL-L2 are arranged, and the wiring is electrically connected to the first data line DL-L1 and the second data line DL-L2. The second auxiliary line DL-C2 may include (2-1) auxiliary lines DL-C2a, (2-2) auxiliary lines DL-C2b, and (2-3) auxiliary lines DL-C2c. The (2-1) auxiliary lines DL-C2a, (2-2) auxiliary lines DL-C2b, and (2-3) auxiliary lines DL-C2c may be arranged on different layers, respectively. The (2-1) auxiliary lines DL-C2a, (2-2) auxiliary lines DL-C2b, and (2-3) auxiliary lines DL-C2c may be arranged on a layer different from the layer on which the first auxiliary line DL-C1 is arranged. The (2-1) auxiliary line DL-C2a, the (2-2) auxiliary line DL-C2b, and the (2-3) auxiliary line DL-C2c may be spaced apart from each other and alternately arranged in the ±x directions.

[0130] Fig. 9B is a cross-sectional view of auxiliary line DL-C2a (2-1). Fig. 9BAs shown in , the first data line DL-L1 and the second data line DL-L2 may be arranged on the third insulating layer 113, and (2-1) the auxiliary line DL-C2a may be arranged on the first insulating layer 111. (2-1) The first portion CLa of the auxiliary line DL-C2a may be electrically connected to the first data line DL-L1 through a first via contact CNT1 formed in the second insulating layer 112 and the third insulating layer 113. (2-1) The second portion CLb of the auxiliary line DL-C2a may be electrically connected to the second data line DL-L2 through a second via contact CNT2 formed in the second insulating layer 112 and the third insulating layer 113. (2-1) The auxiliary line DL-C2a may include a gate electrode GE (see FIG. 1 ) connected to the gate electrode GE of the thin film transistor TFT. Figure 7 ) of the same material.

[0131] exist Fig. 9B , the (2-1) auxiliary line DL-C2a is electrically connected to the first data line DL-L1 and the second data line DL-L2 by directly contacting the first data line DL-L1 and the second data line DL-L2. In an exemplary embodiment, the connection electrodes are respectively disposed between the (2-1) auxiliary line DL-C2a and the first data line DL-L1 and between the (2-1) auxiliary line DL-C2a and the second data line DL-L2 (for example, disposed between the second insulating layer 112 and the third insulating layer 113). Since the (2-1) auxiliary line DL-C2a, the first data line DL-L1 and the second data line DL-L2 are electrically connected to the connection electrodes, the (2-1) auxiliary line DL-C2a can electrically connect the first data line DL-L1 to the second data line DL-L2.

[0132] Fig. 9C It is a cross-sectional view of auxiliary line DL-C2b (2-2). Fig. 9C As shown in FIG. 1 , the first data line DL-L1 and the second data line DL-L2 may be arranged on the third insulating layer 113, and (2-2) the auxiliary line DL-C2b may be arranged on the fourth insulating layer 114. (2-2) The first portion CLa of the auxiliary line DL-C2b may be electrically connected to the first data line DL-L1 through a first via contact CNT1 formed in the fourth insulating layer 114. (2-2) The second portion CLb of the auxiliary line DL-C2b may be electrically connected to the second data line DL-L2 through a second via contact CNT2 formed in the fourth insulating layer 114. (2-2) The auxiliary line DL-C2b may include a connection electrode CM (see FIG. 1 ). Figure 7 ) of the same material.

[0133] Fig.9D It is a cross-sectional view of the auxiliary line DL-C2c (2-3). Fig.9DAs shown in FIG. 1 , the first data line DL-L1 and the second data line DL-L2 may be arranged on the third insulating layer 113, and (2-3) the auxiliary line DL-C2c may be arranged on the second insulating layer 112. (2-3) The first portion CLa of the auxiliary line DL-C2c may be electrically connected to the first data line DL-L1 through a first via contact CNT1 formed in the third insulating layer 113. (2-3) The second portion CLb of the auxiliary line DL-C2c may be electrically connected to the second data line DL-L2 through a second via contact CNT2 formed in the third insulating layer 113. (2-3) The auxiliary line DL-C2c may include a top electrode CE2 (see FIG. 1 ) connected to the capacitor Cst. Figure 7 ) of the same material.

[0134] like FIG. 9B to FIG. 9D As shown in , the first data line DL-L1 and the second data line DL-L2 may be arranged on the third insulating layer 113, and the second auxiliary line DL-C2 may be arranged on the first insulating layer 111, the second insulating layer 112, or the fourth insulating layer 114 and directly connected to the first data line DL-L1 and the second data line DL-L2 through a via contact, or connected to the first data line DL-L1 and the second data line DL-L2 through a connecting electrode. In an exemplary embodiment, the first data line DL-L1 and the second data line DL-L2 may be arranged on the fourth insulating layer 114, and the second auxiliary line DL-C2 may be arranged on the first insulating layer 111, the second insulating layer 112, or the third insulating layer 113 and directly connected to the first data line DL-L1 and the second data line DL-L2 through a via contact, or connected to the first data line DL-L1 and the second data line DL-L2 through a connecting electrode.

[0135] Fig.10 is a plan view of an auxiliary line DL-C arranged in the first non-display area NDA1 according to an embodiment, Fig.11 yes Fig.10 An enlarged plan view of area A.

[0136] like Fig.10 As shown in , the auxiliary line DL-C may extend along the arc of the component area OA. The auxiliary lines DL-C adjacent to each other may be arranged on different layers and overlap each other. For example, the first portion CLa and the second portion CLb of the auxiliary line DL-C may be spaced apart from each other and opposite to each other, and the component area OA is located between the first portion CLa and the second portion CLb. The third portions CLc of the auxiliary lines DL-C adjacent to each other may be arranged on different layers and overlap each other.

[0137] like Fig.11As shown in , the first auxiliary line DL-C1 and the third portions CLc of the second auxiliary lines DL-C2a, DL-C2b, and DL-C2c may be arranged on different layers. Two adjacent third portions CLc of the third portions CLc may partially overlap each other. Therefore, in a high-resolution display device, the area of ​​the first non-display area NDA1 required for the arrangement of the first auxiliary line DL-C1 and the second auxiliary lines DL-C2a, DL-C2b, and DL-C2c may be minimized.

[0138] Fig.12 is a plan view of an auxiliary line DL-C arranged in the first non-display area NDA1 according to an exemplary embodiment. Fig.13 yes Fig.12 An enlarged plan view of area B. Fig.14 It is along Fig.13 A cross-sectional view of region B taken along line IV-IV'.

[0139] Reference Fig.12 The pattern DM may be arranged between the auxiliary lines DL-C in the first non-display area NDA1. The pattern DM may be arranged in an island type between first portions CLa of the auxiliary lines DL-C adjacent to each other and between second portions CLb of the auxiliary lines DL-C adjacent to each other.

[0140] Reference Fig.13 , the pattern DM may include a first pattern DM1, a second pattern DM2, a third pattern DM3, and a fourth pattern DM4 arranged on different layers. The first to fourth patterns DM1, DM2, DM3, and DM4 may be spaced apart from the auxiliary line DL-C between the first portion CLa of the auxiliary line DL-C. Similarly, the first to fourth patterns DM1, DM2, DM3, and DM4 may be spaced apart from the auxiliary line DL-C between the second portion CLb of the auxiliary line DL-C. Each of the first to fourth patterns DM1, DM2, DM3, and DM4 may have a rectangular shape having two pairs of sides opposite to each other. A pair of first sides of the first to fourth patterns DM1, DM2, DM3, and DM4 may be a circle having a curvature corresponding to the curvature of the auxiliary line DL-C. A pair of second sides may be spaced apart at a predetermined interval between two adjacent first portions CLa or two adjacent second portions CLb of the auxiliary line DL-C.

[0141] The pattern DM may include a conductive material. The pattern DM may include the same material as that of at least one of the auxiliary lines DL-C. Fig.14, the first pattern DM1 and the (2-1) auxiliary line DL-C2a may be arranged on the same layer (e.g., the first insulating layer 111) and may include the same material. The second pattern DM2 and the (2-3) auxiliary line DL-C2c may be arranged on the same layer (e.g., the second insulating layer 112) and may include the same material. The third pattern DM3 and the first auxiliary line DL-C1 may be arranged on the same layer (e.g., the third insulating layer 113) and may include the same material. The fourth pattern DM4 and the (2-2) auxiliary line DL-C2b may be arranged on the same layer (e.g., the fourth insulating layer 114) and may include the same material. The patterns DM located on the same layer may be spaced apart from each other, and the patterns DM located on different layers may partially overlap each other. For example, the pattern DM located on the upper layer may partially overlap at least one of the patterns DM located on the lower layer.

[0142] Reference Fig.14 , (2-1) The auxiliary line DL-C2a and the first pattern DM1 may be spaced apart from each other on the first insulating layer 111. (2-3) The auxiliary line DL-C2c and the second pattern DM2 may be spaced apart from each other on the second insulating layer 112. The second pattern DM2 may not overlap with the first pattern DM1. For example, in a top-down view, each of the second patterns DM2 may be arranged between two adjacent first patterns DM1. The first auxiliary line DL-C1 and the third pattern DM3 may be spaced apart from each other on the third insulating layer 113. Each of the third patterns DM3 may partially overlap with the first pattern DM1 and / or the second pattern DM2. (2-2) The auxiliary line DL-C2b and the fourth pattern DM4 may be spaced apart from each other on the fourth insulating layer 114. The fourth pattern DM4 may not overlap with the third pattern DM3. Each of the fourth patterns DM4 may partially overlap with the first pattern DM1 and / or the second pattern DM2.

[0143] like Fig.12As shown in , the wiring density of the auxiliary line DL-C in the ±x direction in the first non-display area NDA1 is greater than the wiring density of the auxiliary line DL-C in the ±y direction in the first non-display area NDA1. Since the third parts CLc of the auxiliary lines DL-C arranged on different layers overlap each other, a step difference may occur in the first non-display area NDA1. For example, the thickness of the top surface of the uppermost insulating layer (e.g., the fifth insulating layer 115) from the top surface of the substrate to the region in which the third part CLc of the auxiliary line DL-C is arranged may be greater than the thickness of the top surface of the uppermost insulating layer from the top surface of the substrate to the region in which the first part CLa and the second part CLb are arranged. Therefore, the part in which the first part CLa of the auxiliary line DL-C is connected to the third part CLc (the boundary between the first part CLa and the third part CLc) and the part in which the second part CLb of the auxiliary line DL-C is connected to the third part CLc (the boundary between the second part CLb and the third part CLc) may have a thin width. The auxiliary line DL-C is bent at the connection between the first part CLa and the third part CLc. The auxiliary line DL-C is also bent at a connection portion between the second portion CLb and the third portion CLc.

[0144] In the embodiment, since the first to fourth patterns DM1, DM2, DM3 and DM4 are arranged between the first portion CLa of the auxiliary line DL-C and between the second portion CLb of the auxiliary line DL-C, the wiring density of the first non-display area NDA1 along the ±y direction is similar to the wiring density along the ±x direction, and the step difference of the insulating layer in the first non-display area NDA1 can be minimized. Since the step difference of the insulating layer is minimized at the boundary between the first portion CLa and the third portion CLc of the auxiliary line DL-C and at the boundary between the second portion CLb and the third portion CLc of the auxiliary line DL-C, the width of the third portion CLc can be kept constant without a reduction in the width of the third portion CLc. Therefore, disconnection of the auxiliary line DL-C in the first non-display area NDA1 can be prevented.

[0145] Fig.13 and Fig.14 The arrangement of the patterns DM in is provided as an example, and the number of the patterns DM, whether the patterns DM overlap each other, and the degree of overlap may vary.

[0146] Fig.15 According to an exemplary embodiment Fig.12 Region B is an enlarged plan view of the region corresponding to the region. Fig.16A and Fig. 16B yes Fig.15 An enlarged view of any auxiliary line DL-C, and Fig.17 yes Fig.15An enlarged plan view of auxiliary line DL-C2b (2-2).

[0147] Reference Fig.15 , Fig.16A and Fig. 16B , each of the first auxiliary line DL-C1 and the second auxiliary line DL-C2 may further include a branch protruding from the first auxiliary line DL-C1 and a corresponding one of the second auxiliary lines DL-C2a, DL-C2b, and DL-C2c. The branch may include a first branch BR1 and a second branch BR2, the first branch BR1 extending from one end of the third portion CLc of each of the first auxiliary line DL-C1 and the second auxiliary line DL-C2, and the second branch BR2 extending from the other end of the third portion CLc. The first branch BR1 and the second branch BR2 may protrude from the third portion CLc along the extension direction of the third portion CLc. Each of the first auxiliary line DL-C1 and the second auxiliary lines DL-C2a, DL-C2b, and DL-C2c may include a first branch BR1 and / or a second branch BR2.

[0148] like Fig.16A As shown in , the first branch BR1 may include a portion extending in a direction (clockwise direction) opposite to the extending direction (counterclockwise direction) of the third portion CLc at a portion where the first portion CLa of the auxiliary line DL-C is connected to the third portion CLc. Fig. 16B As shown in , the second branch BR2 may include a portion extending in an extending direction (counterclockwise direction) of the third portion CLc at a portion where the third portion CLc of the auxiliary line DL-C is connected to the second portion CLb.

[0149] Since the branch extends between the first portion CLa or the second portion CLb of the other auxiliary line DL-C adjacent thereto, similar to Fig.12 The pattern DM shown in FIG. 1 , the branches may minimize the step difference of the insulating layer in the first non-display area NDA1 .

[0150] The branches of the auxiliary line DL-C may extend in an arc direction of the assembly area OA. The branches of the auxiliary line DL-C may cross the first portion CLa or the second portion CLb of other auxiliary lines DL-C disposed on different layers.

[0151] The first branch BR1 of the auxiliary line DL-C may extend from the third portion CLc without contacting or crossing the first portion CLa of another auxiliary line DL-C disposed on the same layer. Fig.15In the figure, the branch of the (2-3) auxiliary line DL-C2c, which is the second one from the left in the drawing, can cross the first parts CLa of the first auxiliary line DL-C1, (2-1) auxiliary line DL-C2a and (2-2) auxiliary line DL-C2b, which are spaced apart from each other in the +x direction, and extend in the clockwise direction, and can be spaced apart from the first part CLa of the (2-3) auxiliary line DL-C2c arranged on the rightmost side on the same layer without contacting the first part CLa of the (2-3) auxiliary line DL-C2c or crossing the first part CLa of the (2-3) auxiliary line DL-C2c. Similarly, the second branch BR2 of the auxiliary line DL-C can extend from the third part CLc in the counterclockwise direction without contacting the second part CLb of another auxiliary line DL-C arranged on the same layer or crossing the second part CLb of another auxiliary line DL-C arranged on the same layer.

[0152] The branch of the auxiliary line DL-C may have a length BL less than the interval between (n+1) data lines DL, where n is an integer equal to or greater than 2 and may be the number of connection lines arranged on different layers. Fig.15 As shown in , in the case where four connection lines arranged on different layers are repeatedly arranged in the first non-display area NDA1 , n may be 4.

[0153] The lengths BL of the branches of the auxiliary line DL-C may be the same or different from each other. Fig.15 As shown in the figure, the length BL of the first branch BR1 of the second (2-3) auxiliary line DL-C2c from the left side of the figure may be less than the interval between the five data lines DL. The length BL of the first branch BR1 of the first auxiliary line DL-C1 may be less than the interval between the four data lines DL. The length BL of the first branch BR1 of the (2-1) auxiliary line DL-C2a may be less than the interval between the three data lines DL. The length BL of the first branch BR1 of the (2-2) auxiliary line DL-C2b on the right may be less than the interval between the two data lines DL.

[0154] The lengths BL of the branches of the auxiliary line DL-C arranged on the same layer may be the same as or different from each other. Fig.17 As shown in FIG. 1 , the first length BL1 of the first branch BR1 of the left (2-2) auxiliary line DL-C2b1 is greater than the second length BL2 of the first branch BR1 of the right (2-2) auxiliary line DL-C2b2. The first length BL1 may be less than the interval between the five data lines DL. The second length BL2 may be less than the interval between the two data lines DL.

[0155] Some of the auxiliary lines DL-C may not include branches. Fig.15, the rightmost (2-3) auxiliary line DL-C2c does not include a branch. The auxiliary line DL-C not including a branch may be an auxiliary line DL-C whose first portion CLa (if extended along its longitudinal direction) extends toward the center of the component area OA or toward the vicinity of the center.

[0156] Fig.18 According to an exemplary embodiment Fig.12 Region B is an enlarged plan view of the region corresponding to the region.

[0157] Fig.18 The embodiment shown in FIG. Fig.13 The embodiments shown in Fig.15 For example, the branch and pattern DM may be arranged between the first portion CLa and the second portion CLb of the auxiliary line DL-C, the branch protruding from the auxiliary line DL-C.

[0158] Although the above embodiment describes four auxiliary lines DL-C arranged on different layers as an example, the embodiment is not limited thereto. For example, two or three auxiliary lines DL-C arranged on different layers may be arranged in the first non-display area NDA1 to connect the first data line DL-L1 to the second data line DL-L2 in the display area DA. In addition, in order to match the wiring density of the top, bottom, left and right in the first non-display area NDA1, a conductive pattern may be arranged between the first portion CLa and the second portion CLb of the auxiliary line DL-C arranged along the edge of the component area OA, and / or a branch protruding from the third portion CLc of the auxiliary line DL-C may be formed. In the case of using two auxiliary lines DL-C, two conductive patterns may be repeatedly arranged, and in the case of using three auxiliary lines DL-C, three conductive patterns may be repeatedly arranged.

[0159] The embodiment can provide a display device in which reliability is increased and a non-display area is reduced. This effect is provided as an example, and the scope of the present disclosure is not limited by this effect.

[0160] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A substrate, comprising a transmission area, a display area and a first non-display area, wherein the display area surrounds the transmission area, and the first non-display area is located between the transmission area and the display area; A first display element and a second display element are arranged in the display region to be separated from each other, and the transmission region is located between the first display element and the second display element; A first data line extending along a first direction, arranged in the display area, and connected to the first display element; a second data line extending along the first direction, arranged in the display area, and connected to the second display element; a first auxiliary line disposed in the first non-display area and connecting the first data line to the second data line; a second auxiliary line, arranged in the first non-display area and adjacent to the first auxiliary line; as well as a plurality of patterns arranged around the first auxiliary line and the second auxiliary line in the first non-display area and spaced apart from each of the first auxiliary line and the second auxiliary line, wherein each of the first auxiliary line and the second auxiliary line comprises a first portion, a second portion and a third portion, the first portion and the second portion are parallel to the first direction, and the third portion connects the first portion to the second portion and extends along an edge of the transmission area, wherein the first portion of the first auxiliary line is connected to the first data line, and the second portion of the first auxiliary line is connected to the second data line, wherein the plurality of patterns are arranged around the first portion and the second portion, and Wherein, in a plan view, the multiple patterns are arranged between the first portion of the first auxiliary line and the first portion of the second auxiliary line and between the second portion of the first auxiliary line and the second portion of the second auxiliary line, but are not arranged between the third portion of the first auxiliary line and the third portion of the second auxiliary line.

2. The display device according to claim 1, in, Each of the plurality of patterns includes a conductive material.

3. The display device according to claim 1, in, The first auxiliary line is arranged in a different layer from the second auxiliary line adjacent to the first auxiliary line, and Wherein, the third portion of the first auxiliary line partially overlaps the third portion of the second auxiliary line.

4. The display device according to claim 3, in, The first auxiliary line further includes a branch extending from a connection portion between the first portion and the third portion and along the edge of the transmission area.

5. The display device according to claim 4, in, The branch of the first auxiliary line overlaps the first portion of the second auxiliary line or the second portion of the second auxiliary line and extends along the edge of the transmission area.

6. The display device according to claim 1, in, The plurality of patterns include a first pattern arranged in the same layer as the first auxiliary line and a second pattern arranged in the same layer as the second auxiliary line, and The first pattern and the first auxiliary line include the same material, and the second pattern and the second auxiliary line include the same material.

7. The display device according to claim 1, in, The first auxiliary line, the first data line and the second data line are formed as one body.

8. The display device according to claim 1, in, The first auxiliary line is arranged on a layer different from a layer on which the first data line and the second data line are arranged.

9. The display device according to claim 8, in, The first auxiliary line is disposed under the first data line and the second data line, and an insulating layer is located between the first auxiliary line and the first data line and the second data line.

10. The display device according to claim 8, in, The first auxiliary line is disposed on the first data line and the second data line, and an insulating layer is located between the first auxiliary line and the first data line and the second data line.

11. The display device according to claim 1, in, Each of the first display element and the second display element includes a first electrode, a second electrode and an emission layer, wherein the second electrode is spaced apart from the first electrode, and Wherein, the emission layer is placed between the first electrode and the second electrode.

12. The display device according to claim 11, further comprising: a first thin film transistor connected to the first electrode of the first display element; as well as The second thin film transistor is connected to the first electrode of the second display element.

13. The display device according to claim 12, in, The first auxiliary line and the gate electrode of the first thin film transistor are arranged on the same layer and include the same material.

14. The display device according to claim 12, further comprising: an electrode layer overlapping the gate electrode of the first thin film transistor and arranged on the gate electrode, and The first auxiliary line and the electrode layer are arranged on the same layer and include the same material.

15. The display device according to claim 12, further comprising: a connecting electrode electrically connected to the semiconductor layer of the first thin film transistor and arranged below the first electrode of the first display element, wherein an insulating layer is disposed between the connecting electrode and the first electrode of the first display element, and The first auxiliary line and the connection electrode are arranged on the same layer and include the same material.

16. The display device according to claim 1, in, In a plan view, the plurality of patterns are arranged in an island shape between the first portion of the first auxiliary line and the first portion of the second auxiliary line and between the second portion of the first auxiliary line and the second portion of the second auxiliary line.

17. A display device, comprising: A substrate, comprising a transmission area, a display area and a first non-display area, wherein the display area surrounds the transmission area, and the first non-display area is located between the transmission area and the display area; A first display element and a second display element are arranged separately from each other in the display area, and the transmission area is located between the first display element and the second display element; A first data line extending along a first direction, arranged in the display area, and connected to the first display element; a second data line extending along the first direction, arranged in the display area, and connected to the second display element; as well as a first auxiliary line disposed in the first non-display area and connecting the first data line to the second data line, The first auxiliary line includes a first portion, a second portion, a third portion and a first branch, the first portion and the second portion are parallel to the first direction, the third portion connects the first portion to the second portion and extends along an edge of the transmission area, and the first branch extends from a first end portion of the third portion connected to the first portion along a first extension direction away from the third portion.

18. The display device according to claim 17, in, The first auxiliary line is arranged in a different layer from a second auxiliary line adjacent to the first auxiliary line, and Wherein, the third portion of the first auxiliary line partially overlaps a portion of the second auxiliary line.

19. The display device according to claim 18, in, The first branch of the first auxiliary line overlaps with the first portion of the second auxiliary line or the second portion of the second auxiliary line, wherein the first branch extends along the edge of the transmission area, and Wherein, the portion of the second auxiliary line connects the first portion of the second auxiliary line to the second portion of the second auxiliary line.

20. The display device according to claim 17, in, The first auxiliary line further includes a second branch extending from a second end portion of the third portion connected to the second portion along a second extending direction away from the third portion, the second extending direction being opposite to the first extending direction.

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