Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof, and a display device. The display substrate comprises: a base substrate, comprising a display area and a peripheral area; a gate scanning drive circuit, a light-emitting control scanning drive circuit and a first power line arranged in sequence; the gate scanning drive circuit comprises a first stable capacitor, the first plate of the first stable capacitor is electrically connected to the output end of the gate scanning drive circuit, and the second plate of the first stable capacitor is electrically connected to the first power line; the light-emitting control scanning drive circuit comprises a second stable capacitor, the first plate of the second stable capacitor is electrically connected to the output end of the light-emitting control scanning drive circuit, the second plate of the second stable capacitor is electrically connected to the first power line, and the second plate of the second stable capacitor comprises a first part and a second part, and an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the base substrate. The display substrate optimizes the layout of the circuit structure, which is conducive to realizing a narrow frame design of the display panel.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 28, 2020, application number 202010889271.2, and invention name “Display substrate, manufacturing method thereof, and display device”. Technical Field

[0002] Embodiments of the present disclosure relate to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0003] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The driving of the gate lines can be achieved by a bound integrated drive circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide a switching state voltage signal (scanning signal) for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to open in sequence, and at the same time, the data line provides a data signal to the pixel unit of the corresponding row in the pixel array, so as to form the grayscale voltage required for each grayscale of the display image in each pixel unit, thereby displaying a frame of image. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a display area and a peripheral area located at least on one side of the display area; a gate scanning driving circuit, a light emitting control scanning driving circuit and a first power line arranged in sequence in the peripheral area of ​​the base substrate and along a side away from the display area; the gate scanning driving circuit comprises a first stable capacitor, a first plate of the first stable capacitor is electrically connected to an output end of the gate scanning driving circuit, and a second plate of the first stable capacitor is electrically connected to the first power line; the light emitting control scanning driving circuit comprises a second stable capacitor, a first plate of the second stable capacitor is electrically connected to an output end of the light emitting control scanning driving circuit, a second plate of the second stable capacitor is electrically connected to the first power line, and the second plate of the second stable capacitor comprises a first part and a second part, an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the base substrate, a first part of the second plate of the second stable capacitor is located at a first shielding layer, a second part of the second plate of the second stable capacitor is located at a second shielding layer, and the first shielding layer and the second shielding layer are sequentially arranged on a side of the light emitting control scanning driving circuit away from the base substrate.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting control scanning drive circuit also includes: a third stabilizing capacitor and a first connecting part; the first electrode plate of the third stabilizing capacitor is electrically connected to the first connecting part, the second electrode plate of the third stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the third stabilizing capacitor includes a first part and a second part, and there is an organic insulating layer between the first part and the second part in a direction perpendicular to the base substrate.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light emitting control scanning driving circuit includes a plurality of cascaded light emitting control shift register units, the light emitting control shift register units include a plurality of transistors, a plurality of capacitors and a plurality of connection parts, the plurality of transistors include: a first transistor, the gate of the first transistor is connected to a first clock signal line to receive a first clock signal, the first electrode of the first transistor is connected to a first node, and the second electrode of the first transistor is connected to an input terminal; a second transistor, the gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to a second node, and the second electrode of the second transistor is connected to the first clock signal line to receive the first clock signal; a third transistor, the gate of the third transistor is connected to the first clock signal line to receive the first clock signal, the first electrode of the third transistor is connected to the second node, and the second electrode of the second control transistor is connected to the second power line to receive a second voltage; a fourth transistor, the gate of the fourth transistor is connected to the second clock signal line to receive a second clock signal, the first electrode of the fourth transistor is connected to the first node, and the second electrode of the fourth transistor is connected to the second electrode of the fifth transistor; the fifth transistor, the gate of the fifth transistor is connected to the second node, and the first electrode of the fifth transistor is connected to the third power line to receive a third voltage; a transistor, a first electrode of the sixth transistor being connected to the second clock signal line to receive the second clock signal, and a second electrode of the sixth transistor being connected to a third node; a seventh transistor, a gate of the seventh transistor being connected to the second clock signal line to receive the second clock signal, a first electrode of the seventh transistor being connected to the third node, and a second electrode of the seventh transistor being connected to a fourth node; an eighth transistor, a gate of the eighth transistor being connected to the first node, a first electrode of the eighth transistor being connected to the fourth node, and a second electrode of the eighth transistor being connected to the third power supply line to receive the third voltage; a ninth transistor, a gate of the ninth transistor being connected to the fourth node a third node connected to the ninth transistor, a first electrode connected to the third power line to receive the third voltage, and a second electrode connected to the output terminal of the ninth transistor; a tenth transistor, a first electrode connected to the second power line to receive the second voltage, and a second electrode connected to the output terminal of the tenth transistor; the plurality of capacitors include: a first capacitor, a second electrode connected to the third node; a second capacitor, a second electrode connected to the second clock signal line to receive the second clock signal; a third capacitor, a first electrode connected to the fourth node, and a second electrode connected to the third power line to receive the third voltage;The third stabilizing capacitor, the first plate of the third stabilizing capacitor is connected to the first node, and the second plate of the third stabilizing capacitor is electrically connected to the first power line; the second stabilizing capacitor, the first plate of the second stabilizing capacitor is connected to the output end of the light emitting control scanning driving circuit, and the second plate of the second stabilizing capacitor is electrically connected to the first power line; the multiple connecting parts include: the first connecting part and the third connecting part, the first connecting part includes the first node, and the third connecting part is connected to the output end of the light emitting control scanning driving circuit.;

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the gate scan driving circuit further includes a first scan capacitor, and the ratio of the first stable capacitor to the first scan capacitor satisfies the following relationship:

[0008] GH1 / EH1 <C24 / C21<GH1 / EH2

[0009] Among them, C21 represents the first scanning capacitor, C24 represents the first stabilizing capacitor, GH1 is the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit within one frame, EH1 is the duration of the effective level of the light-emitting control signal output by the light-emitting control scanning driving circuit within one frame, and EH2 is the duration of the invalid level of the light-emitting control scanning driving circuit within one frame.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the ratio of the second stabilizing capacitor to the second capacitor of the light emitting control scanning driving circuit satisfies the following relationship:

[0011] GH 1 / EH1 <C6 / C2<GH1 / EH2

[0012] Among them, C6 represents the second stable capacitor, C2 represents the second capacitor of the light-emitting control scanning driving circuit, GH1 is the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit within one frame, EH1 is the duration of the effective level of the light-emitting control signal output by the light-emitting control scanning driving circuit within one frame, and EH2 is the duration of the invalid level of the light-emitting control scanning driving circuit within one frame time.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the ratio of the first stable capacitor to the first scanning capacitor satisfies the following relationship at the same time:

[0014] GOL / GOW <C24 / C21<GH1 / EH2

[0015] Wherein, GOL / GOW is the aspect ratio of the output transistor of the gate scan driving circuit.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, when the light emitting control scanning driving circuit includes a second capacitor, the ratio of the second stabilizing capacitor to the second capacitor of the light emitting control scanning driving circuit satisfies the following relationship:

[0017] EOL / EOW <C6 / C2<GH1 / EH2

[0018] Wherein, EOL / EOW is the aspect ratio of the output transistor of the light emitting control scanning driving circuit.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the ratio of the first stable capacitor to the first scanning capacitor satisfies the following relationship at the same time:

[0020] (GSW / GSL) / (GOW / GOL) <C24 / C21<GH1 / EH2

[0021] Wherein, GOW / GOL is the width-to-length ratio of the output transistor of the gate scanning driving circuit, and GSW / GSL is the width-to-length ratio of any switch transistor of the gate scanning driving circuit.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the ratio of the second stabilizing capacitor to the second capacitor of the light emitting control scanning driving circuit satisfies the following relationship:

[0023] (ESW / ESL) / (EOW / EOL) <C6 / C2<GH1 / EH2

[0024] Wherein, EOW / EOL is the width-to-length ratio of the output transistor of the light emitting control scanning driving circuit, and ESW / ESL is the width-to-length ratio of any switch transistor of the light emitting control scanning driving circuit.

[0025] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting control scanning drive circuit also includes: a fourth stabilizing capacitor and a second connecting part; the first plate of the fourth stabilizing capacitor is electrically connected to the second connecting part, the second plate of the fourth stabilizing capacitor is electrically connected to the first power line, and the second plate of the fourth stabilizing capacitor includes a first part and a second part, and an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the base substrate.

[0026] For example, in the display substrate provided in at least one embodiment of the present disclosure, the multiple capacitors also include: a fourth stabilizing capacitor, a first plate of the fourth stabilizing capacitor is connected to the second node, and a second plate of the fourth stabilizing capacitor is electrically connected to the first power line; the multiple connecting parts also include: a second connecting part, and the second connecting part includes the second node.

[0027] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of transistors further include: an eleventh transistor, the gate of the sixth transistor is connected to the second electrode of the eleventh transistor, the first electrode of the first capacitor is connected to the second electrode of the eleventh transistor, the gate of the eleventh transistor is connected to the second power line to receive the second voltage, and the first electrode of the eleventh transistor is connected to the second node; a twelfth transistor, the gate of the tenth transistor is connected to the second electrode of the twelfth transistor, the first electrode of the second capacitor is connected to the second electrode of the twelfth transistor, the gate of the twelfth transistor is connected to the second power line to receive the second voltage, and the first electrode of the twelfth transistor is connected to the first node.

[0028] For example, in the display substrate provided in at least one embodiment of the present disclosure, the duration of the effective level of the light control signal output by the light control scan driving circuit within a frame is greater than the duration of the effective level of the gate scan signal output by the gate scan driving circuit within a frame.

[0029] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting control scanning driving circuit includes multiple transistors, the first shielding layer covers at least one transistor in the light-emitting control scanning driving circuit, and the second shielding layer covers at least one transistor among the multiple transistors in the light-emitting control scanning driving circuit except the at least one transistor; the second shielding layer is also arranged on the side of the gate scanning driving circuit away from the base substrate, and the second shielding layer covers at least one transistor in the gate scanning driving circuit.

[0030] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first part of the second plate of the third stable capacitor is located in the first blocking layer, and the second part of the second plate of the third stable capacitor is located in the second blocking layer, the light-emitting control scanning driving circuit also includes a fourth stable capacitor, the first part of the second plate of the fourth stable capacitor is located in the first blocking layer, and the second part of the second plate of the fourth stable capacitor is located in the second blocking layer, and the first blocking layer and the second blocking layer are sequentially arranged on the side of the light-emitting control scanning driving circuit away from the base substrate; the first blocking layer covers at least one transistor in the light-emitting control scanning driving circuit, and the second blocking layer covers at least one transistor among the multiple transistors in the light-emitting control scanning driving circuit except the at least one transistor; the second blocking layer is also arranged on the side of the gate scanning driving circuit away from the base substrate, and the second blocking layer covers at least one transistor in the gate scanning driving circuit.

[0031] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first shielding layer and the second shielding layer are connected to the first power line to receive a first voltage.

[0032] For example, in the display substrate provided in at least one embodiment of the present disclosure, for each of the light emitting control shift register units, the first blocking layer covers at least one transistor in the light emitting control shift register unit, and the second blocking layer covers at least one transistor among the multiple transistors in the light emitting control shift register unit except the at least one transistor.

[0033] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting control scan drive circuit also includes a second power line or a third scan line extending along a first direction, and the display substrate also includes a first power line extending along the first direction; the orthographic projection of the second power line or the third scan line on the base substrate is located between the orthographic projection of the transistor included in the light-emitting control scan drive circuit on the base substrate and the orthographic projection of the gate scan drive circuit on the base substrate; the orthographic projection of the first power line on the base substrate is located on the side of the orthographic projection of the light-emitting control scan drive circuit on the base substrate away from the display area.

[0034] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second power line, the third scan line and the first power line are located on a side of the first shielding layer away from the second shielding layer in a direction perpendicular to the base substrate.

[0035] For example, in the display substrate provided in at least one embodiment of the present disclosure, the boundary of the first shielding layer's orthographic projection on the light-emitting control scanning drive circuit close to the display area is located on the side of the orthographic projection of the second power line or the third scanning line on the base substrate away from the display area; the orthographic projection of the first shielding layer's boundary away from the display area on the base substrate overlaps with the orthographic projection of the first power line on the base substrate.

[0036] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting control scanning driving circuit includes a plurality of output transistors, which are configured to output the light-emitting control signal to the light-emitting control transistors of the display area row by row, and the orthographic projection of the boundary of the first shielding layer close to one side of the display area on the base substrate is located between the orthographic projection of the plurality of output transistors on the base substrate and the orthographic projection of the second power line or the third scanning line on the base substrate.

[0037] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the boundary of the second shielding layer close to the display area on the base substrate overlaps with the orthographic projection of the gate scanning drive circuit on the base substrate; the orthographic projection of the boundary of the second shielding layer away from the display area on the base substrate overlaps with the orthographic projection of the first power line on the base substrate.

[0038] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the boundary of the second shielding layer close to the display area on the base substrate overlaps with the orthographic projection of the output transistor of the gate scanning drive circuit that outputs the gate scanning signal on the base substrate; or the orthographic projection of the boundary of the second shielding layer close to the display area on the base substrate overlaps with the orthographic projection of the boundary of the second shielding layer close to the display area on the base substrate.

[0039] For example, in the display substrate provided by at least one embodiment of the present disclosure, the absolute value of the second voltage provided by the second power line is greater than the absolute value of the first voltage provided by the first power line.

[0040] For example, in the display substrate provided in at least one embodiment of the present disclosure, corresponding to each of the light emitting control shift register units, the first blocking layer includes a plurality of periodically arranged first openings, and the second blocking layer includes a plurality of periodically arranged second openings, so that the first blocking layer and the second blocking layer respectively cover at least part of the transistors of the light emitting control shift register unit.

[0041] For example, in the display substrate provided in at least one embodiment of the present disclosure, the density of the first openings ranges from 10% to 50%, and the density of the second openings ranges from 10% to 50%.

[0042] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first opening and the second opening are square in shape, and the size range of the first opening and the second opening is 10 μm*10 μm to 20 μm*20 μm.

[0043] For example, in the display substrate provided in at least one embodiment of the present disclosure, corresponding to each of the light emitting control shift register units, the first blocking layer includes a plurality of non-periodically arranged first openings, and the second blocking layer includes a plurality of non-periodically arranged second openings, so that the first blocking layer and the second blocking layer respectively cover at least part of the transistors of the light emitting control shift register unit.

[0044] For example, in the display substrate provided in at least one embodiment of the present disclosure, the density of the first openings ranges from 10% to 25%, and the density of the second openings ranges from 10% to 25%.

[0045] For example, in the display substrate provided in at least one embodiment of the present disclosure, the size of the first opening and the size of the second opening are positively correlated with the areas of the transistors respectively corresponding thereto.

[0046] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the edge of the first opening and the edge of the second opening on the base substrate do not overlap.

[0047] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the edges of the first openings on the base substrate and the orthographic projections of the edges of the second openings on the base substrate are alternately arranged.

[0048] For example, the display substrate provided by at least one embodiment of the present disclosure further includes: a first planarization layer and a second planarization layer, the first planarization layer is located on the side of the first blocking layer away from the second blocking layer in a direction perpendicular to the base substrate, and the second planarization layer is located between the first blocking layer and the second blocking layer in a direction perpendicular to the base substrate; the second planarization layer is the organic insulating layer.

[0049] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second blocking layer is connected to the first blocking layer through a plurality of via holes penetrating the second planarization layer; the light-emitting control scanning driving circuit includes a plurality of cascaded light-emitting control shift register units, and the light-emitting control shift register unit includes a plurality of transistors. For each of the light-emitting control shift register units, the first blocking layer covers at least one transistor in the light-emitting control shift register unit, and the second blocking layer covers at least one transistor among the plurality of transistors in the light-emitting control shift register unit except the at least one transistor; corresponding to each of the light-emitting control shift register units, the first blocking layer includes a plurality of periodically arranged first openings, and the second blocking layer includes a plurality of periodically arranged second openings, so that the first blocking layer and the second blocking layer respectively cover at least part of the transistors of the light-emitting control shift register unit; in a second direction perpendicular to the first direction, the plurality of via holes are located between the first opening and the second opening.

[0050] For example, in the display substrate provided in at least one embodiment of the present disclosure, the shape of the via hole is circular or square, and the aperture of the via hole ranges from 3 μm to 5 μm.

[0051] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a supporting layer, which is located on a side of the second blocking layer away from the first blocking layer, and the orthographic projection of the supporting layer on the base substrate overlaps with the orthographic projection of an edge of a column of vias among the multiple vias away from the display area on the base substrate.

[0052] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer and a fourth insulating layer arranged in sequence between the base substrate and the first blocking layer in a direction perpendicular to the base substrate; the semiconductor layer includes an active layer of the multiple transistors, the first conductive layer includes the gates of the multiple transistors and the first electrodes of the multiple capacitors, the second conductive layer includes the second electrodes of the multiple capacitors, and the third conductive layer includes the multiple connection parts, the first clock signal line, the second clock signal line, the second power line and the third power line.

[0053] For example, in the display substrate provided in at least one embodiment of the present disclosure, a plurality of stable capacitors are formed between the first blocking layer and the second blocking layer and the third conductive layer respectively; the first blocking layer and the second blocking layer respectively serve as the second plates of the plurality of stable capacitors, and the first plates of the plurality of stable capacitors are the third conductive layer.

[0054] For example, in the display substrate provided in at least one embodiment of the present disclosure, the portion of the first blocking layer away from the display area includes a first portion and a second portion located on a side of the first planarization layer away from the base substrate, and the portion of the second blocking layer away from the display area includes a first portion and a second portion located on a side of the second planarization layer away from the base substrate.

[0055] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first power line includes a portion of the third conductive layer away from the display area, a first portion of the first shielding layer, and a first portion of the second shielding layer, and the portion of the third conductive layer away from the display area, the first portion of the first shielding layer, and the first portion of the second shielding layer are in direct contact.

[0056] For example, in the display substrate provided in at least one embodiment of the present disclosure, the angle between the second portion of the first blocking layer and the third conductive layer ranges from 20° to 30°, and the angle between the second portion of the second blocking layer and the third conductive layer ranges from 25° to 40°.

[0057] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first planarization layer and the second planarization layer also include a groove arranged between the light-emitting control scanning driving circuit and the gate scanning driving circuit, the first planarization layer includes a first part located on a side of the groove away from the display area and covering the light-emitting control scanning driving circuit, and a second part covering the gate scanning driving circuit; the second planarization layer includes a first part located on a side of the groove away from the display area and covering the light-emitting control scanning driving circuit, and a second part covering the gate scanning driving circuit; the orthographic projection of the boundary of the first shielding layer on the side close to the display area on the base substrate falls within the orthographic projection of the first part of the second planarization layer on the base substrate; the orthographic projection of the first part of the second planarization layer on the base substrate falls within the orthographic projection of the first part of the first planarization layer on the base substrate; the second shielding layer extends from the area corresponding to the light-emitting control scanning driving circuit to the area corresponding to the gate scanning driving circuit, and covers the groove.

[0058] For example, in the display substrate provided in at least one embodiment of the present disclosure, the width B of the orthographic projection of the second shielding layer covering the groove on the base substrate along the second direction perpendicular to the first direction is expressed as follows:

[0059] B=A+k1*P1+k2*Q1+k3*P2+k4*Q2, P1=d1*tan(c1), P2=d2*tan(c2), wherein A represents the width of the orthographic projection of the groove on the substrate along the second direction, P1 represents the width of the orthographic projection of the first slope of the second blocking layer on the substrate, Q1 represents the width of the orthographic projection of the first platform of the second blocking layer on the substrate, P2 represents the width of the orthographic projection of the second slope of the second blocking layer on the substrate, Q2 represents the width of the orthographic projection of the second platform of the second blocking layer on the substrate, d1 represents the thickness of the first planarization layer, d2 represents the thickness of the second planarization layer, c1 represents the slope angle of the first planarization layer, c2 represents the slope angle of the second planarization layer, k1, k2, k3, k4 are coefficients, wherein 1<k1≤2, 1<k2≤2, 1<k3≤2, 1<k4≤2.

[0060] For example, in the display substrate provided in at least one embodiment of the present disclosure, at a position of the first shielding layer close to the groove, an angle between the first shielding layer and the second shielding layer ranges from 25° to 40°.

[0061] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a fifth insulating layer and a sixth insulating layer, the fifth insulating layer being located between the first blocking layer and the third conductive layer in a direction perpendicular to the base substrate, and the sixth insulating layer being located between the second blocking layer and the third conductive layer in a direction perpendicular to the base substrate.

[0062] For example, in the display substrate provided by at least one embodiment of the present disclosure, the fifth insulating layer includes the first planarization layer, and the sixth insulating layer includes the first planarization layer and the second planarization layer.

[0063] For example, in the display substrate provided in at least one embodiment of the present disclosure, the thickness of the first planarization layer and the second planarization layer are respectively in the range of 1.0 μm to 2.0 μm.

[0064] For example, the display substrate provided by at least one embodiment of the present disclosure further includes: a pixel defining layer, including a first portion located in the display area, and a second portion located on a side of the second shielding layer away from the base substrate, the orthographic projection of the first portion of the pixel defining layer close to the boundary of the peripheral area on the base substrate partially overlaps with the orthographic projection of the gate scanning drive circuit on the base substrate, and the orthographic projection of the second portion of the pixel defining layer on the base substrate partially overlaps with the orthographic projection of the second opening of the second shielding layer on the base substrate; a cathode layer, located on a side of the pixel defining layer away from the base substrate; a first encapsulation layer, located on a side of the cathode layer away from the base substrate; a second encapsulation layer, located on a side of the first encapsulation layer away from the base substrate; and a third encapsulation layer, located on a side of the second encapsulation layer away from the base substrate.

[0065] For example, in the display substrate provided in at least one embodiment of the present disclosure, the distance between the first shielding layer and the boundary of the display area and the distance between the third encapsulation layer and the boundary of the display area ranges from 95 μm to 105 μm.

[0066] For example, the display substrate provided by at least one embodiment of the present disclosure further includes: a touch control structure located on a side of the third packaging layer away from the base substrate.

[0067] For example, in the display substrate provided in at least one embodiment of the present disclosure, the touch structure includes a plurality of touch traces respectively connected to the touch drive electrodes and the touch sensing electrodes, the touch drive electrodes and the touch sensing electrodes are partially located in the display area, and the orthographic projections of the first shielding layer and the second shielding layer on the base substrate at least partially overlap with the orthographic projections of the touch traces on the base substrate.

[0068] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes: a first planarization layer and a second planarization layer; the first planarization layer and the second planarization layer further include a groove arranged between the light-emitting control scanning drive circuit and the gate scanning drive circuit; at least part of the touch control wiring has an orthographic projection on the base substrate falling into the groove.

[0069] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first blocking layer also includes a third part, and the orthographic projection of the third part on the base substrate overlaps and contacts with the orthographic projection of the signal line of the gate scanning drive circuit on the base substrate, and the signal line of the gate scanning drive circuit is configured to provide a clock signal to the gate scanning drive circuit.

[0070] For example, in the display substrate provided in at least one embodiment of the present disclosure, the output end of the gate scan drive circuit is electrically connected to at least one data write transistor in the display area, the gate scan drive circuit is configured to output a gate scan signal, the data write transistor is configured to control the writing of a data signal in response to the gate scan signal, the output end of the light emitting control scan drive circuit is electrically connected to at least one light emitting control transistor in the display area, the light emitting control scan drive circuit is configured to output a light emitting control signal, the light emitting control transistor is configured to control the light emitting element to emit light in response to the light emitting control signal, and the first power line is electrically connected to the cathode of at least one light emitting element in the display area.

[0071] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate provided by any embodiment of the present disclosure.

[0072] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, comprising: providing the base substrate; forming the gate scanning drive circuit, the light emitting control scanning drive circuit and a first power line on the base substrate, wherein the output end of the gate scanning drive circuit is electrically connected to at least one data writing transistor in the display area, the data writing transistor is configured to control the writing of a data signal in response to the gate scanning signal, the output end of the light emitting control scanning drive circuit is electrically connected to at least one light emitting control transistor in the display area, the light emitting control transistor is configured to control the light emitting element to emit light in response to the light emitting control signal, and the first power line is electrically connected to the cathode of at least one light emitting element in the display area; the gate scanning drive circuit includes a first stabilizing capacitor, the first plate of the first stabilizing capacitor is electrically connected to the output end of the gate scanning drive circuit, and the second plate of the first stabilizing capacitor is electrically connected to the first power line; the light emitting control scanning drive circuit includes a second stabilizing capacitor, the first plate of the second stabilizing capacitor is electrically connected to the output end of the light emitting control scanning drive circuit, the second plate of the second stabilizing capacitor is electrically connected to the first power line, and the second plate of the second stabilizing capacitor includes a first portion and a second portion, and an organic insulating layer is provided between the first portion and the second portion in a direction perpendicular to the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0074] Figure 1A A schematic diagram of an overall circuit structure of a display panel;

[0075] Figure 1B It is a circuit structure diagram of a 7T1C pixel circuit;

[0076] Figure 1C A circuit diagram of a light emitting control shift register unit;

[0077] Figure 1D for Figure 1C The signal timing diagram of the light emitting control shift register unit when it is working;

[0078] Figure 1E for Figure 1C A schematic diagram of the layout of the light emitting control shift register unit on the display substrate shown in ;

[0079] Figure 1F A schematic diagram of a gate scanning shift register unit provided in at least one embodiment of the present disclosure;

[0080] Figure 1G A schematic diagram of the layout of a gate scanning shift register unit on a display substrate provided by at least one embodiment of the present disclosure;

[0081] Figure 2A for Figure 1C A schematic diagram of a layout of the light emitting control shift register unit 105 on the display substrate shown in FIG.

[0082] Figure 2B A schematic diagram of a first shielding layer provided in at least one embodiment of the present disclosure;

[0083] Figure 2C A schematic diagram of a second shielding layer provided in at least one embodiment of the present disclosure;

[0084] Figure 2D for Figure 2A An oblique view of the light emitting control shift register unit 105 is shown;

[0085] Figure 2E for Figure 2D A schematic diagram of a second shielding layer of the light emitting control shift register unit 105 shown in FIG.

[0086] Figure 2F for Figure 2D A schematic diagram of a first shielding layer of the light emitting control shift register unit 105 shown in FIG.

[0087] Figure 3A for Figure 1C Another schematic diagram of the layout of the light emitting control shift register unit 105 on the display substrate is shown in FIG.

[0088] Figure 3B A schematic diagram of another first shielding layer provided for at least one embodiment of the present disclosure;

[0089] Figure 3C A schematic diagram of another second shielding layer provided for at least one embodiment of the present disclosure

[0090] Figure 4 A cross-sectional view of a display substrate provided in at least one embodiment of the present disclosure;

[0091] Figure 5A A schematic diagram of another display substrate provided for at least one embodiment of the present disclosure;

[0092] Figure 5B for Figure 5A A cross-sectional view of the display substrate along the AA' and BB' directions;

[0093] Figure 5C A schematic diagram of a light emitting control shift register unit provided by at least one embodiment of the present disclosure;

[0094] Figure 5D A schematic diagram of a gate scanning shift register unit provided in at least one embodiment of the present disclosure;

[0095] Figure 5E A connection diagram of a light emitting control shift register unit and a pixel circuit provided by at least one embodiment of the present disclosure;

[0096] Figure 6 A cross-sectional view of another display substrate provided for at least one embodiment of the present disclosure;

[0097] Figure 7 A schematic diagram of a light emitting control scanning driving circuit provided in at least one embodiment of the present disclosure;

[0098] Figure 8 A schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0099] Fig. 9 A flow chart of a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0100] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0101] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0102] The present disclosure is described below by several specific embodiments. In order to keep the following description of the embodiments of the present invention clear and concise, the detailed description of known functions and known components may be omitted. When any component of the embodiments of the present invention appears in more than one accompanying drawings, the component is represented by the same reference numeral in each of the accompanying drawings.

[0103] Figure 1A is a schematic diagram of an overall circuit architecture of a display panel. Figure 1A As shown, 101 represents the overall outer frame line of the display panel; the display panel includes a display area (i.e., a pixel array area) 102 and a peripheral area 106 located around the display area 102, the display area includes pixel units 103 arranged in an array; the peripheral area 106 includes a scan drive shift register unit 104, and a plurality of cascaded scan drive shift register units 104 constitute a gate scan drive circuit (Gate GOA), which is used to provide, for example, a gate scan signal that shifts row by row to the pixel units 103 arranged in an array in the display area 102 of the display panel 101; the peripheral area 106 also includes a light emitting control shift register unit 105, and a plurality of cascaded light emitting control shift register units 105 constitute a light emitting control scan drive circuit (EM GOA), which is used to provide, for example, a light emitting control signal that shifts row by row to the pixel units 103 arranged in an array in the display area 102 of the display panel 101, that is, a gate scan drive circuit for outputting a light emitting control signal.

[0104] like Figure 1AAs shown, the data lines DL1-DLN (N is an integer greater than 1) connected to the data driver chip IC vertically pass through the display area 102 to provide data signals for the pixel units 103 arranged in an array; the gate lines GL1-GLM (M is an integer greater than 1) connected to the scan drive shift register unit 104 and the light control shift register unit 105 cross the display area 102 to provide gate scanning signals and light control signals for the pixel units 103 arranged in an array. For example, each pixel unit 103 may include a pixel circuit and a light emitting element having a circuit structure of 7T1C, 7T2C, 8T2C or 4T1C in the art, and the pixel circuit operates under the control of the data signal transmitted through the data line and the gate scanning signal and light control signal transmitted through the gate line to drive the light emitting element to emit light to achieve display and other operations. The light emitting element may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0105] Figure 1B FIG. 1 is a circuit structure diagram of a 7T1C pixel circuit. Figure 1D As shown, the pixel circuit includes a driving transistor M1, a data writing transistor M2, a compensation transistor M3, a storage capacitor Cst, a light-emitting control transistor M4 / M5 and a reset transistor M6 / M7, and also includes a driving node S1, a data writing node S2, a compensation node S3 and a light-emitting control node S4. For example, the gate of the data writing transistor M2 is connected to the gate line GLm (m is an integer greater than 0 and less than or equal to M) to receive the gate scanning signal provided by the gate scanning driving circuit; the gate of the light-emitting control transistor M4 / M5 is respectively connected to the light-emitting control signal lines EM1 and EM2 (for example, the light-emitting control signal lines are gate lines) to receive the light-emitting control signal provided by the light-emitting control scanning driving circuit to drive the light-emitting element LE to emit light. The specific connection relationship and working principle of the pixel circuit can refer to the design in the art, and will not be repeated here.

[0106] Figure 1C The circuit structure diagram of a light emitting control shift register unit is shown in FIG. Figure 1D for Figure 1C The signal timing diagram of the light emitting control shift register unit when it is working is shown below. Figure 1C and Figure 1D The working process of the light emitting control shift register unit is briefly introduced.

[0107] like Figure 1CAs shown, the light emitting control shift register unit 105 includes 12 transistors (a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, an output transistor T9 (also called a ninth transistor), a tenth transistor T10 (also called an output transistor), an eleventh transistor T11 and a twelfth transistor T12) and three capacitors (a first capacitor C1, a second capacitor C2 and a third capacitor C3). For example, when a plurality of light emitting control shift register units 105 are cascaded, the first stage light emitting control shift register unit 105 is connected to the first stage light emitting control shift register unit 105. 05 is connected to the second electrode of the first transistor T1 and the input terminal EI, and the input terminal EI is configured to be connected to the trigger signal line ESTV to receive the trigger signal as the input signal, and the second electrode of the first transistor T1 in the other levels of light-emitting control shift register unit 105 is electrically connected to the output terminal of the previous level of light-emitting control shift register unit 105 to receive the output signal output by the output terminal EOUT of the previous level of light-emitting control shift register unit 105 as the input signal, thereby realizing the shift output to provide, for example, a row-by-row shifted light-emitting control signal to the array-arranged pixel units 103 in the display area 102 of the display panel 101.

[0108] In addition, if Figure 1C and Figure 1DAs shown, the light-emitting control shift register unit also includes a first clock signal terminal CK and a second clock signal terminal CB, ECK represents the first clock signal line, and ECB represents the second clock signal line. For example, the first clock signal terminal CK is connected to the first clock signal line ECK or the second clock signal line ECB to receive the first clock signal. For example, when the first clock signal terminal CK is connected to the first clock signal line ECK, the first clock signal line ECK provides the first clock signal, and when the first clock signal terminal CK and the second clock signal line ECB are connected, the second clock signal line ECB provides the first clock signal; it depends on the actual situation, and the embodiments of the present disclosure are not limited to this. Similarly, the second clock signal terminal CB is connected to the second clock signal line ECB or the first clock signal line ECK to receive the second clock signal. The following is an example of the first clock signal terminal CK and the first clock signal line ECK being connected to receive the first clock signal, and the second clock signal terminal CB and the second clock signal line ECB being connected to receive the second clock signal. The embodiments of the present disclosure are not limited to this. For example, the first clock signal and the second clock signal can adopt pulse signals with a duty cycle greater than 50%, and the two can differ by half a cycle, for example; VGL represents the second power line and the second voltage provided by the second power line, VGH represents the third power line and the third voltage provided by the third power line, and the third voltage is greater than the second voltage; for example, the third voltage is a DC high level, and the second voltage is a DC low level; N1, N2, N3 and N4 respectively represent the first node, the second node, the third node and the fourth node in the circuit schematic.

[0109] like Figure 1C and Figure 1D As shown, the gate of the first transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line ECK) to receive the first clock signal, the second electrode of the first transistor T1 is connected to the input terminal EI, and the first electrode of the first transistor T1 is connected to the first node N1. For example, when the light emitting control shift register unit is a first-stage light emitting control shift register unit, the input terminal EI is connected to the trigger signal line ESTV to receive the trigger signal, and when the light emitting control shift register unit is a light emitting control shift register unit of other stages except the first-stage light emitting control shift register unit, the input terminal EI is connected to the output terminal EOUT of the light emitting control shift register unit of the previous stage.

[0110] A gate of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal.

[0111] A gate of the third transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the second power line VGL to receive the second voltage.

[0112] The gate of the fourth transistor T4 is connected to the second clock signal terminal CB (for example, the second clock signal terminal CB is connected to the second clock signal line ECB) to receive the second clock signal, the first electrode of the fourth transistor T4 is connected to the first node N1, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.

[0113] A gate electrode of the fifth transistor T5 is connected to the second node N2 , and a first electrode of the fifth transistor T5 is connected to the third power line VGH to receive a third voltage.

[0114] A gate of the sixth transistor T6 is connected to the second electrode of the eleventh transistor T11 , a first electrode of the sixth transistor T6 is connected to the second clock signal terminal CB to receive the second clock signal, and a second electrode of the sixth transistor T6 is connected to the third node N3 .

[0115] A first electrode of the first capacitor C1 is connected to a second electrode of the eleventh transistor T11 , and a second electrode of the first capacitor C2 is connected to a third node N3 .

[0116] A gate of the seventh transistor T7 is connected to the second clock signal terminal CB to receive the second clock signal, a first electrode of the seventh transistor T7 is connected to the third node N3, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0117] A gate electrode of the eighth transistor T8 is connected to the first node N1 , a first electrode of the eighth transistor T8 is connected to the fourth node N4 , and a second electrode of the eighth transistor T8 is connected to the third power line VGH to receive a third voltage.

[0118] A gate of the output transistor T9 is connected to the fourth node N4 , a first electrode of the output transistor T9 is connected to the third power line VGH to receive the third voltage, and a second electrode of the output transistor T9 is connected to the output terminal EOUT.

[0119] A first electrode of the third capacitor C3 is connected to the fourth node N4 , and a second electrode of the third capacitor C3 is connected to the third power line VGH to receive a third voltage.

[0120] A gate of the tenth transistor T10 is connected to a second electrode of the twelfth transistor T12 , a first electrode of the tenth transistor T10 is connected to the second power line VGL to receive a second voltage, and a second electrode of the tenth transistor T10 is connected to the output terminal EOUT.

[0121] A first electrode of the second capacitor C2 is connected to a second electrode of the twelfth transistor T12 , and a second electrode of the second capacitor C2 is connected to the second clock signal terminal CB to receive the second clock signal.

[0122] A gate electrode of the eleventh transistor T11 is connected to the second power line VGL to receive the second voltage, and a first electrode of the eleventh transistor T11 is connected to the second node N2.

[0123] A gate electrode of the twelfth transistor T12 is connected to the second power line VGL to receive the second voltage, and a first electrode of the twelfth transistor T12 is connected to the first node N1.

[0124] Figure 1C The transistors in the light emitting control shift register unit 105 shown in the figure are all described by taking P-type transistors as examples, that is, each transistor is turned on when the gate is connected to a low level (on level), and is turned off when the gate is connected to a high level (off level). At this time, the first electrode of the transistor can be a source electrode, and the second electrode of the transistor can be a drain electrode.

[0125] The light emitting control shift register unit includes but is not limited to Figure 1C Configuration method, for example, the light emitting control shift register unit 105 may not include T11 and T12, and a transistor with similar function to T11 or T12 may be set at the N3 or N4 node position, and each transistor may also be an N-type transistor or a mixture of P-type transistors and N-type transistors, and it is only necessary to simultaneously connect the port polarities of the selected type of transistors according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0126] It should be noted that the transistors used in the light-emitting control shift register unit can be thin-film transistors or field-effect transistors or other switching devices with the same characteristics. Here, thin-film transistors are used as examples for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0127] Figure 1D for Figure 1C The signal timing diagram of the light emitting control shift register unit 105 when it is working is shown below. Figure 1C and Figure 1D The working process of the light emitting control shift register unit is described in detail. For example, the working principle of the first-stage light emitting control shift register unit 105 is described, and the working principles of the remaining stages of the light emitting control shift register unit 105 are similar to it and will not be described in detail. Figure 1D As shown, the working process of the light emitting control shift register unit 105 includes 6 stages, namely, the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6. Figure 1D The timing waveforms of each signal in each stage are shown.

[0128] In the first stage P1, if Figure 1D As shown, the first clock signal line ECK provides a low level, so the first clock signal terminal CK connected to the first clock signal line ECK receives the first clock signal of the low level, the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 transmits the high-level trigger signal ESTV to the first node N1, so that the level of the first node N1 becomes a high level, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. In addition, the turned-on third transistor T3 transmits the low-level second voltage to the second node N2, so that the level of the second node N2 becomes a low level, so the fifth transistor T5 and the sixth transistor T6 are turned on. Since the second clock signal line ECB provides a high level, the second clock signal received by the second clock signal terminal CB connected to the second clock signal line ECB is a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. In addition, due to the storage effect of the third capacitor C3, the level of the fourth node N4 can be kept at a high level, so that the output transistor T9 is turned off. In the first phase P1 , since the output transistor T9 and the tenth transistor T10 are both turned off, the output signal outputted from the output terminal EOUT_1 of the light emitting control shift register unit 105 maintains the previous low level.

[0129] In the second stage P2, if Figure 1DAs shown, the second clock signal line ECB provides a low-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned on. Since the first clock signal line ECK provides a high-level first clock signal to the first clock signal terminal, the first transistor T1 and the third transistor T3 are turned off. Due to the storage effect of the first capacitor C1, the second node N2 can continue to maintain the low level of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level third voltage VGH is transmitted to the first node N1 through the turned-on fifth transistor T5 and the fourth transistor T4, so that the level of the first node N1 continues to maintain the high level of the previous stage, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. In addition, the low-level second clock signal is transmitted to the fourth node N4 through the turned-on sixth transistor T6 and the seventh transistor T7, so that the level of the fourth node N4 becomes a low level, so the output transistor T9 is turned on, and the turned-on output transistor T9 outputs the high-level third voltage VGH, so the output signal outputted by the output terminal EOUT_1 of the light-emitting control shift register unit 105 in the second stage P2 is a high level.

[0130] In the third stage P3, if Figure 1D As shown, the first clock signal line ECK provides a low-level first clock signal to the first clock signal terminal CK, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal line ECB provides a high-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned off. Due to the storage function of the third capacitor C3, the level of the fourth node N4 can maintain the low level of the previous stage, so that the output transistor T9 remains in the on state, and the turned-on output transistor T9 outputs the high-level third voltage VGH, so the output signal output by the output terminal EOUT_1 of the light-emitting control shift register unit 105 in the third stage P3 is still high. At the same time, in this stage, the output terminal EOUT_2 of the second-stage light-emitting control shift register unit 105 outputs a high level (for a specific description, refer to the working process of the first-stage light-emitting control shift register unit 105 in the second stage P2 above).

[0131] In the fourth stage P4, if Figure 1DAs shown, the first clock signal line ECK provides a high-level first clock signal to the first clock signal terminal CK, so the first transistor T1 and the third transistor T3 are turned off. The second clock signal line ECB provides a low-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned on. Due to the storage function of the second capacitor C2, the level of the first node N1 remains at a high level in the previous stage, so that the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. Due to the storage function of the first capacitor C1, the second node N2 continues to maintain the low level of the previous stage, so that the fifth transistor T5 and the sixth transistor T6 are turned on. In addition, the low-level second clock signal is transmitted to the fourth node N4 through the turned-on sixth transistor T6 and the seventh transistor T7, so that the level of the fourth node N4 becomes a low level, so the output transistor T9 is turned on, and the turned-on output transistor T9 outputs the high-level third voltage VGH, so the output signal output by the output terminal EOUT_1 of the light-emitting control shift register unit 105 in the fourth stage P4 is still high. At the same time, in this stage, the output terminal EOUT_2 of the second-stage light emitting control shift register unit 105 outputs a high level (for a detailed description, please refer to the working process of the first-stage light emitting control shift register unit 105 in the third stage P3 above).

[0132] In the fifth stage P5, if Figure 1D As shown, the first clock signal line ECK provides a low-level first clock signal to the first clock signal terminal CK, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal line ECB provides a high-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned off. The turned-on first transistor T1 transmits the low-level trigger signal ESTV to the first node N1, thereby changing the level of the first node N1 to a low level.

[0133] For example, in the fifth stage P5, the low level voltage of the first clock signal is -6V, the low level voltage of the trigger signal ESTV is -6V, and the threshold voltage Vth of the first transistor T1 is -1.5V. Since the first transistor T1 is a P-type transistor, in order to turn on the first transistor T1, it is necessary to make the voltage Vgs of the gate and source of the first transistor T1 less than the threshold voltage Vth of the first transistor T1. Therefore, when the first node N1 is charged to -4.5V, the first transistor T1 is turned off, and the charging of the first node N1 is stopped at this time, that is, the low level voltage of the first node N1 is -4.5V at this stage, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on. The turned-on second transistor T2 transmits the low-level first clock signal to the second node N2, so that the level of the second node N2 can be further lowered, so the second node N2 continues to maintain the low level of the previous stage, so that the fifth transistor T5 and the sixth transistor T6 are turned on. In addition, the turned-on eighth transistor T8 transmits the high-level third voltage VGH to the fourth node N4, so that the level of the fourth node N4 becomes high, so the output transistor T9 is turned off. The turned-on tenth transistor T10 responds to the low level (e.g., -4.5V) of the first node N1 and outputs the low-level second voltage VGL (e.g., -6V). Similarly, the threshold voltage Vth of the tenth transistor T10 is -1.5V. In order to turn on the tenth transistor T10, it is necessary to make the voltage Vgs of the gate and source of the tenth transistor T10 less than the threshold voltage Vth of the tenth transistor T10. Therefore, when the voltage output by the output terminal EOUT_1 is -3V, the tenth transistor T10 is turned off, that is, the low-level voltage of the output terminal EOUT_1 is -3V at this stage, so the output signal output by the output terminal EOUT_1 of the first-stage light emitting control shift register unit 105 in the fifth stage P5 becomes the first low level (e.g., -3V). Meanwhile, in this stage, the output terminal EOUT_2 of the second-stage light emitting control shift register unit 105 outputs a high level (for a detailed description, please refer to the working process of the first-stage light emitting control shift register unit 105 in the fourth stage P4 above).

[0134] In the sixth stage P6, if Figure 1DAs shown, the first clock signal line ECK provides a high-level first clock signal to the first clock signal terminal CK, and the second clock signal line ECB provides a low-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned on. Since the second clock signal changes from a high level in the fifth stage P5 to a low level, for example, the change amount is Δt (for example, greater than 6V), according to the bootstrap effect of the second capacitor C2, the level of the first node N1 changes from a low level (for example, -4.5V) in the fifth stage P5 to a lower low level (for example, -4.5V-Δt), so that the second transistor T2 and the tenth transistor T10 are turned on under the control of the low level (for example, -4.5V-Δt) of the first node N1. According to the conduction characteristics of the tenth transistor T10 described above, the low-level second voltage VGL (for example, -6V) can be fully output to the output terminal EOUT_1. For example, in the sixth stage P6, the voltage output by the output terminal EOUT_1 is the second low level (for example, -6V). Meanwhile, at this stage, the output terminal EOUT_2 of the second-stage light emitting control shift register unit 105 outputs a low level (eg, -3V, for a detailed description, please refer to the working process of the first-stage light emitting control shift register unit 105 in the fifth stage P5 above).

[0135] It should be noted that in the above-mentioned stages, since the second power line VGL always provides a low level, the eleventh transistor T11 and the twelfth transistor T12 are always turned on, thereby avoiding the influence of the second clock signal provided by the second clock signal terminal CB connected to the sixth transistor T6 and the output signal of the output terminal EOUT connected to the tenth transistor on the levels of the second node N2 and the first node N1 respectively, thereby ensuring the stability of the circuit.

[0136] Figure 1F A schematic diagram of a gate scanning shift register unit provided by at least one embodiment of the present disclosure. Figure 1FAs shown, the gate scanning shift register unit 104 includes 8 transistors (input transistor T21, first control transistor T22, second control transistor T23, output control transistor T24, gate output transistor T25, first noise reduction transistor T26, second noise reduction transistor T27 and voltage stabilizing transistor T28) and 2 capacitors (first scanning capacitor C21 and second scanning capacitor C22). For example, when a plurality of gate scanning shift register units 104 are cascaded, the first electrode of the input transistor T1 in the first-stage gate scanning shift register unit 104 is connected to the input terminal IN, and the input terminal IN is configured to be connected to the trigger signal line GSTV to receive the trigger signal as the input signal, while the first electrode of the input transistor T1 in the other stages of the gate scanning shift register unit 104 is electrically connected to the output terminal of the previous stage of the gate scanning shift register unit 104 to receive the output signal outputted by the output terminal GOUT of the previous stage of the gate scanning shift register unit 104 as the input signal, thereby realizing the shift output, so as to perform, for example, row-by-row scanning on the array of pixel units in the active display area.

[0137] like Figure 1F As shown, the gate of the input transistor T21 is connected to the first sub-clock signal line GCK, the second electrode of the input transistor T1 is connected to the input terminal IN, and the first electrode of the input transistor T1 is connected to the first scanning node N21.

[0138] A gate of the first control transistor T22 is connected to the first scan node N21 , a second electrode of the first control transistor T22 is connected to the first sub-clock signal line GCK, and a first electrode of the first control transistor T22 is connected to the second scan node N22 .

[0139] A gate of the second control transistor T23 is connected to the first sub-clock signal line GCK, a second electrode of the second control transistor is connected to the second power line VGL, and a first electrode of the second control transistor T23 is connected to the second scan node N22.

[0140] A gate of the output control transistor T24 is connected to the second scan node N22 , a first electrode of the output control transistor T24 is connected to the third power line VGH, and a second electrode of the output control transistor T24 is connected to the output terminal GOUT.

[0141] A first electrode of the first scanning capacitor C21 is connected to the second scanning node N22, and a second electrode of the first scanning capacitor C21 is connected to the third power line VGH.

[0142] A gate of the gate output transistor T25 is connected to the third scanning node N23, a first electrode of the output transistor T5 is connected to the second clock sub-signal line GCB, and a second electrode of the gate output transistor T25 is connected to the output terminal GOUT.

[0143] A first electrode of the second scanning capacitor C22 is connected to the third scanning node N23, and a second electrode of the second scanning capacitor C2 is connected to the output terminal GOUT.

[0144] A gate of the first noise reduction transistor T26 is connected to the second scanning node N2 , a first electrode of the first noise reduction transistor T26 is connected to the third power line VGH, and a second electrode of the first noise reduction transistor T26 is connected to a second electrode of the second noise reduction transistor T7 .

[0145] A gate of the second noise reduction transistor T27 is connected to the second sub-clock signal line GCB of the second clock signal, and a first electrode of the second noise reduction transistor T27 is connected to the first scanning node N21.

[0146] A gate of the voltage stabilizing transistor T28 is connected to the second power line VGL, a second electrode of the voltage stabilizing transistor T28 is connected to the first scanning node N21, and a first electrode of the voltage stabilizing transistor T28 is connected to the third scanning node N3.

[0147] Figure 1F The transistors in the gate scanning shift register unit 104 shown in the figure are all described by taking P-type transistors as examples, that is, each transistor is turned on (on level) when the gate is connected to a low level, and is turned off (off level) when the gate is connected to a high level. At this time, the first electrode of the transistor can be a source electrode, and the second electrode of the transistor can be a drain electrode.

[0148] The gate scanning shift register unit includes but is not limited to Figure 1F Configuration method, for example, the capacitor C22 in the gate scan shift register unit 104 can be connected between the second scan node N2 and the second clock sub-signal line GCB, the N22 node can also be set with a transistor with similar functions such as a voltage regulator transistor T28, and each transistor can also use an N-type transistor or a mixture of P-type transistors and N-type transistors. It is only necessary to connect the port polarities of the selected type of transistors according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0149] It should be noted that the working principle of the gate scanning shift register unit can be referred to the introduction in the art and will not be elaborated here.

[0150] For example, the gate scan signal output by the gate scan drive circuit is maintained at an effective level (for example, a low level) only in a short period of time in a frame, so as to be output to the gate (for example, the signal terminal GLm) of the data write transistor M2 in the pixel circuit to control the writing of the data signal, that is, the gate scan drive circuit outputs a valid signal in the time period when the pixel should write the data signal in a frame, and the light-emitting control signal output by EM GOA is maintained at an effective level (for example, a low level) for a longer period of time in a frame, so as to be output to the light-emitting control signal terminal EM1 / EM2 of the light-emitting control transistor M4 / M5 in the pixel circuit, so as to control the pixel to emit light in a longer period of time in a frame.

[0151] The inventors have noticed that when the transistors in the circuit structure are affected by light, leakage current will be generated, and the adverse effect of leakage current on the circuit that needs to maintain the output of valid signals for a long time, such as EMGOA, is more serious. Therefore, how to design a new driving circuit structure to meet the different output signal requirements of the gate scanning driving circuit and EMGOA, that is, the different requirements for preventing TFT leakage, has become a problem that needs to be solved urgently.

[0152] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a display area and a peripheral area located at least on one side of the display area; a gate scanning drive circuit, a light emitting control scanning drive circuit and a first power line arranged in the peripheral area of ​​the base substrate and arranged in sequence along a side away from the display area; an output end of the gate scanning drive circuit is electrically connected to at least one data writing transistor in the display area, the data writing transistor is configured to control the writing of a data signal in response to a gate scanning signal, and an output end of the light emitting control scanning drive circuit is electrically connected to at least one light emitting control transistor in the display area, the light emitting control transistor is configured to control the light emitting element to emit light in response to the light emitting control signal. light, a first power line is electrically connected to a cathode of at least one light-emitting element in the display area; a gate scanning drive circuit includes a first stabilizing capacitor, a first plate of the first stabilizing capacitor is electrically connected to an output end of the gate scanning drive circuit, and a second plate of the first stabilizing capacitor is electrically connected to the first power line; a light-emitting control scanning drive circuit includes a second stabilizing capacitor, a first plate of the second stabilizing capacitor is electrically connected to an output end of the light-emitting control scanning drive circuit, a second plate of the second stabilizing capacitor is electrically connected to the first power line, and the second plate of the second stabilizing capacitor includes a first part and a second part, and an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the substrate.

[0153] At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned display substrate and a method for manufacturing the display substrate.

[0154] The display substrate provided by the above embodiment of the present disclosure can shield transistors at different positions in the light-emitting control scanning driving circuit to different degrees, thereby effectively preventing the generation of leakage current and improving the display quality of the display panel. At the same time, considering that the EM GOA needs to maintain the output of a valid signal for a long time, and the Gate GOA outputs a data writing transistor to drive the pixel circuit to open the valid signal time is short, the different structural designs of the first stabilizing capacitor and the second stabilizing capacitor of the above embodiment can effectively improve the driving capability of the EM GOA.

[0155] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0156] At least one embodiment of the present disclosure provides a display substrate. Figure 1E for Figure 1C A schematic diagram of the layout of the light emitting control shift register unit on the display substrate shown in ; Figure 2A for Figure 1C A schematic diagram of a layout of the light emitting control shift register unit 105 on the display substrate shown in FIG. Figure 2B A schematic diagram of a first shielding layer provided in at least one embodiment of the present disclosure; Figure 2C A schematic diagram of a second shielding layer provided in at least one embodiment of the present disclosure; Figure 3A for Figure 1C Another schematic diagram of the layout of the light emitting control shift register unit 105 on the display substrate is shown in FIG. Figure 3B A schematic diagram of another first shielding layer provided for at least one embodiment of the present disclosure; Figure 3C A schematic diagram of another second shielding layer provided in at least one embodiment of the present disclosure. Figures 1E to 3C A display substrate provided in at least one embodiment of the present disclosure is introduced in detail.

[0157] For example, Figure 1A and Figure 2A As shown, the display substrate 1 includes: a base substrate 10 and a gate scanning driving circuit 4 and a light emitting control scanning driving circuit 5 arranged on the base substrate 10 .

[0158] For example, Figure 1A As shown, the base substrate 10 includes a display area 102 (for example, the display area 102 can also be called a pixel array area) and a peripheral area 106 located at least on one side of the pixel array area. For example, the gate scanning drive circuit and the light emitting control scanning drive circuit are located in the peripheral area 106 of the base substrate 10 and are arranged in sequence along a side away from the display area 102. For example, the gate scanning drive circuit and the light emitting control scanning drive circuit are located on one side of the base substrate 10 (for example, Figure 1A As shown, it is located between the display area 102 and the side of the base substrate 10), for example, Figure 1AAs shown, it is located on the left side of the display area 102, and of course it can also be located on the right side or both sides of the display area 102, and the embodiments of the present disclosure are not limited to this. Figure 1A As shown, the gate scanning driving circuit 4 is located between the light emitting control scanning driving circuit 5 and the display area 102 .

[0159] For example, the duration of the effective level of the light emitting control signal output by the light emitting control scanning driving circuit 5 is greater than the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit 4. For example, the output terminal GOUT of the gate scanning driving circuit 4 is connected to at least one data writing transistor (such as Figure 1B The data writing transistor M2 is connected to the gate scanning signal GLm, and the data writing transistor M2 is configured to control the writing of the data signal Vdata in response to the gate scanning signal GLm. For example, the output terminal EOUT (e.g., the output terminal E021 and the output terminal E022) of the light emitting control scanning driving circuit 5 is connected to at least one light emitting control transistor (e.g., the output terminal E021 and the output terminal E022) of the display area 102. Figure 1B The light emitting control transistor M4 / M5 is configured to control the light emitting element LE to emit light in response to the light emitting control signal EM1 / EM2. Figure 1B The description will not be repeated here.

[0160] For example, Figure 2A As shown, the output terminal E021 and the output terminal E022 of the light emitting control shift register unit 105 of the light emitting control scanning driving circuit 5 are connected to the light emitting control transistor of the display area 102 through the wiring that crosses the gate scanning shift register unit 104 in the gate scanning driving circuit 4. Specifically, the output terminal E021 and the output terminal E022 include the second conductive layer pattern or the third conductive layer pattern in the light emitting control shift register unit 105 connected to the second electrode of the output transistor T9 or the second electrode of the output transistor T10.

[0161] For example, the light emission control scanning driving circuit 5 includes a plurality of cascaded light emission control shift register units 105. It should be noted that: Figure 1E and Figure 2A Only one light emitting control shift register unit 105 is shown. The structures of the remaining light emitting control shift register units 105 in the light emitting control scanning driving circuit 5 are similar to those in FIG. Figure 2A and Figure 1E Similar, no further elaboration.

[0162] For example, Figure 5DAs shown, the gate scanning driving circuit includes a first stable capacitor C24, a first plate C241 of the first stable capacitor C24 is electrically connected to the output terminal GOUT of the gate scanning driving circuit 4, and a second plate C242 of the first stable capacitor C24 is electrically connected to the first power line VSS. Specifically, the output terminal GOUT of the gate scanning driving circuit 4 includes a second conductive layer pattern or a third conductive layer pattern connected to the second electrode of the gate output transistor T25 or the second electrode of the output control transistor T24 in the gate scanning driving circuit. For example, the first plate refers to an independent and complete pattern located in the peripheral area, which can be electrically connected to the signal line of the display area by changing layers or vias / or it is limited that the two plates do not overlap with the anode of the light-emitting element (different from the small-sized peripheral cathode pattern).

[0163] like Figure 5C and Figure 5B As shown, the light emitting control scanning driving circuit 5 includes a second stabilizing capacitor C6, a first plate C61 of the second stabilizing capacitor C6 is electrically connected to the output terminal EOUT of the light emitting control scanning driving circuit 5, a second plate C62 of the second stabilizing capacitor C6 is electrically connected to the first power line VSS, and the second plate C62 of the second stabilizing capacitor C6 includes a first portion C621 and a second portion C622, and an organic insulating layer (for example, as shown in FIG. 1 ) is provided between the first portion C621 and the second portion C622 in a direction perpendicular to the base substrate 10. Figure 5B The second planarization layer PLN2 shown).

[0164] For example, Figure 5C As shown, the light emitting control scanning driving circuit 5 further includes: a third stabilizing capacitor C4, a fourth stabilizing capacitor C5, a first connecting portion E1 (such as Figure 1E and Figure 5B as shown) and the second connecting portion E2 (as shown Figure 1E and Figure 5B For example, the first connection portion E1 includes a first node N1, and the second connection portion E2 includes a second node N2.

[0165] For example, Figure 5B and Figure 5C As shown, the first electrode plate C41 of the third stabilizing capacitor C4 is connected to the first connecting portion E1 (i.e., the first node N1), the second electrode plate C42 of the third stabilizing capacitor C4 is electrically connected to the first power line VSS, and the second electrode plate C42 of the third stabilizing capacitor C4 includes a first portion C421 and a second portion C422, and an organic insulating layer (e.g., such as Figure 5B The second planarization layer PLN2 shown).

[0166] For example, the first plate C51 of the fourth stabilizing capacitor C5 is connected to the second connection portion E2 (i.e., the second node N2), the second plate C52 of the fourth stabilizing capacitor C5 is electrically connected to the first power line VSS, and the second plate C52 of the fourth stabilizing capacitor C5 includes a first portion C521 and a second portion C522, and an organic insulating layer (e.g., such as Figure 5B The second planarization layer PLN2 shown).

[0167] For example, the detailed structure of the shift register unit 105 of the light emission control scanning driving circuit 5 can be referred to. Figure 5C The introduction of , I will not go into details here.

[0168] For example, Figure 2A As shown, the display substrate 1 further includes a first shielding layer 21 and a second shielding layer 22 which are sequentially arranged on a side of the light emitting control scanning driving circuit 5 (i.e., the light emitting control shift register unit 105) away from the base substrate 10. For example, the first shielding layer 21 is composed of Figure 2A The solid line frame in FIG. 2 indicates that the second shielding layer 22 is composed of Figure 2A The dashed box shown in indicates that the following embodiments are the same as this and will not be described in detail. For example, the first shielding layer 21 and the second shielding layer 22 are connected to the first power line VSS to receive the first voltage.

[0169] Figure 2D for Figure 2A An oblique view of the light emitting control shift register unit 105 is shown; Figure 2E for Figure 2D A schematic diagram of a second shielding layer of the light emitting control shift register unit 105 shown in FIG. Figure 2F for Figure 2D Schematic diagram of the first shielding layer of the light emitting control shift register unit 105 shown in FIG. Figure 2D As shown, the first shielding layer 21 is located between the light emitting control shift register unit 105 and the second shielding layer 22 .

[0170] For example, Figure 5B and Figure 1EAs shown, the second stable capacitor C6 (whose second plate includes C621 and C622) is located (i.e., formed) between the first shielding layer 21 and the second shielding layer 22 and the third connection part E3. Specifically, the third connection part E3 includes a third conductive layer pattern connected to the output terminals E021 and E022 of the light emitting control shift register unit 105. The third stable capacitor C4 (whose second plate includes C421 and C422) is located between the first shielding layer 21 and the second shielding layer 22 and the first connection part E1. Specifically, the first connection part E1 includes a third conductive layer pattern connected to the first node N1 of the light emitting control shift register unit 105. The fourth stable capacitor C5 (whose second plate includes C651 and C652) is located between the first shielding layer 21 and the second shielding layer 52 and the second connection part E2. Specifically, the second connection part E2 includes a third conductive layer pattern connected to the second node N2 of the light emitting control shift register unit 105. For example, as Figure 5B As shown, the first part C621 of the second stable capacitor C6 is a part of the first shielding layer 21, and the second part C622 of the second stable capacitor C6 is a part of the second shielding layer 22. The first part C421 of the third stable capacitor C4 is a part of the first shielding layer 21, and the second part C422 of the third stable capacitor C4 is a part of the second shielding layer 22. The first part C521 of the fourth stable capacitor C5 is a part of the first shielding layer 21, and the second part C522 of the fourth stable capacitor C5 is a part of the second shielding layer 22. That is, the second stable capacitor C6 includes the capacitors formed by the third connecting portion E3 and the first shielding layer 21 and the second shielding layer 22, respectively, the third stable capacitor C4 includes the capacitors formed by the first connecting portion E1 and the first shielding layer 21 and the second shielding layer 22, respectively, and the fourth stable capacitor C5 includes the capacitors formed by the second connecting portion E2 and the first shielding layer 21 and the second shielding layer 22, respectively, and the embodiments of the present disclosure are not limited to this.

[0171] For example, the first shielding layer 21 covers at least one transistor in the light emission control scanning driving circuit 5 , and the second shielding layer 22 covers at least one transistor among the plurality of transistors in the light emission control scanning driving circuit 5 except the at least one transistor.

[0172] For example, "covering" means that the orthographic projections of the two on the substrate at least partially overlap, that is, the orthographic projections of the first shielding layer 21 and at least one transistor in the light-emitting control scanning driving circuit 5 on the substrate at least partially overlap, and the orthographic projections of the second shielding layer 22 and at least one transistor among the multiple transistors in the light-emitting control scanning driving circuit 5 except the at least one transistor on the substrate at least partially overlap.

[0173] For example, Figure 2AAs shown, the second shielding layer 22 is also located on the side of the gate scanning driving circuit 4 away from the base substrate 10, and the second shielding layer 22 covers at least one transistor in the gate scanning driving circuit 4, that is, the orthographic projections of the second shielding layer 22 and at least one transistor in the gate scanning driving circuit 4 on the base substrate at least partially overlap. Figure 2A As shown, the second shielding layer 22 covers all transistors except the first control transistor T21 in the gate scanning shift register unit 104. The embodiments of the present disclosure are not limited to this.

[0174] For example, the arrangement of the gate scanning shift register unit 104 in the gate scanning driving circuit 4 is as follows: Figure 1G As shown, other layouts may also be used, and the embodiments of the present disclosure are not limited thereto.

[0175] For example, Figure 2A As shown, taking a light-emitting control shift register unit 105 as an example, the first blocking layer 21 covers at least one transistor in the light-emitting control shift register unit 105 (for example, covering transistors T1, T3, T4, T11), and the second blocking layer 22 covers at least one transistor among multiple transistors in the light-emitting control shift register unit 105 except at least one transistor (for example, the above-mentioned transistors T1, T3, T4, T11) (for example, covering transistors T2, T3, T6, T11, T12).

[0176] Therefore, the display substrate provided in the above embodiment of the present disclosure can shield transistors at different positions in the light emitting control scanning driving circuit 5 to different degrees, thereby effectively preventing the generation of leakage current and improving the display quality of the display panel.

[0177] For example, Figure 1E As shown, the display substrate 1 further includes: a first power line VSS, for example, Figure 1B The cathode of the light emitting element LE in the pixel circuit of the display area 102 is connected as shown. For example, the light emitting control shift register unit 10 also includes a second power line VGL, a third power line VGH and a plurality of clock signal lines (for example, the first clock signal line ECK, the second clock signal line ECB and the trigger signal line ESTV shown in the figure). For the convenience and simplicity of description, the light emitting control shift register unit 105 is referred to as a shift register unit for introduction below.

[0178] For example, the second power line VGL, the first power line VSS, the third power line VGH and a plurality of clock signal lines (for example, the first clock signal line ECK, the second clock signal line ECB and the trigger signal line ESTV) extend along the first direction Y on the substrate 10, and are configured to provide the second voltage, the first voltage, the third voltage and a plurality of clock signals (for example, the first clock signal, the second clock signal or the trigger signal described above, etc.) to the shift register unit 105, respectively. For example, the second power line VGL is configured to provide the second voltage to the shift register unit 105, and the third power line VGH is configured to provide the third voltage to the shift register unit 105; the first clock signal line ECK and the second clock signal line ECB are configured to provide the first clock signal or the second clock signal to the shift register unit 105, respectively. For example, the second voltage is less than the third voltage, for example, the second voltage is a DC low level, and the third voltage is a DC high level. The specific connection relationship between the second power line VGL, the third power line VGH and the plurality of clock signal lines and the shift register unit 105 can be referred to the following description. For example, the absolute value of the second voltage provided by the second power line VGL is greater than the absolute value of the first voltage provided by the first power line VSS, for example, the second voltage is approximately -7 volts (V), and the first voltage is approximately -3 V. It should be noted that the values ​​of the second voltage and the first voltage may be determined according to specific circumstances, and the embodiments of the present disclosure are not limited thereto.

[0179] It should be noted that the second power line VGL, the first power line VSS, the third power line VGH and multiple clock signal lines can be arranged in parallel along the first direction Y, or they can cross at a certain angle (for example, less than or equal to 20°), and the embodiments of the present disclosure are not limited to this.

[0180] For example, the base substrate 10 may be made of glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0181] For example, the positive projection of the second power line VGL on the base substrate 10 is located on a side of the positive projection of the transistor (for example, the shift register unit 105) included in the light emission control scanning drive circuit 5 on the base substrate 10 close to the display area 102, for example, in the second direction X, located Figure 2A The right side of the shift register unit 105 shown is located between the positive projection of the shift register unit 105 on the substrate 10 and the positive projection of the shift register unit 104 included in the gate scanning drive circuit on the substrate 10; the positive projection of the first power line VSS on the substrate 10 is located on the side of the positive projection of the light emitting control scanning drive circuit 5 on the substrate 10 away from the display area 102.

[0182] For example, the positive projections of the third power line VGH and the plurality of clock signal lines on the substrate 10 are located on a side of the positive projection of the transistor included in the shift register unit 105 on the substrate 10 away from the display area 102, for example, in the second direction X, both are located Figure 2A The shift register unit 105 is shown on the left side. That is, the orthographic projection of the shift register unit 105 on the base substrate 10 is located between the orthographic projection of the second power line VGL on the base substrate 10 and the orthographic projection of the first power line VSS on the base substrate 10.

[0183] For example, Figure 2A As shown, the second power line VGL and the first power line VSS are located on the side of the first shielding layer 21 away from the second shielding layer 22 in a direction perpendicular to the base substrate 10, so that the first shielding layer 21 is away from the second shielding layer 22 and covers the light emitting control scanning driving circuit 5 and the second power line VSS to achieve shielding.

[0184] For example, Figure 2A As shown, the positive projection of the third power line VGH on the substrate substrate 10 is located between the positive projections of the first clock signal line ECK and the second clock signal line ECB on the substrate substrate 10 and the positive projection of the shift register unit 105 on the substrate substrate 10. For example, the trigger signal line (not shown in the figure), the second clock signal line ECB and the first clock signal line ECK are sequentially arranged from left to right along the second direction X on the substrate substrate 10.

[0185] It should be noted that the above wiring positions are merely exemplary, and as long as the wiring arrangement can facilitate connection with the shift register unit, the embodiments of the present disclosure do not impose any limitation on this.

[0186] For example, the positions of the second power line VGL and the third power line VGH are not limited to the above-mentioned routing positions. The positive projection of the second power line VGL on the substrate 10 can be located on the side of the positive projection of the transistor (for example, the shift register unit 105) included in the light emitting control scanning driving circuit 5 on the substrate 10 away from the display area 102, for example, in the second direction X, located Figure 2A On the left side of the shift register unit 105 shown in the figure, the positive projection of the third power line VGH on the substrate 10 can be located on the side of the positive projection of the transistor included in the shift register unit 105 on the substrate 10 close to the display area 102, for example, in the second direction X, located Figure 2A The right side of the shift register unit 105 is shown.

[0187] For example, the angle between the first direction Y and the second direction X is between 70° and 90°, including 70° and 90°. For example, the angle between the first direction Y and the second direction X is 70°, 75°, 85°, 90° or 80°, etc., which can be set according to actual conditions, and the embodiments of the present disclosure are not limited to this. The following is an example in which the first direction Y and the second direction X are perpendicular, and the embodiments of the present disclosure are not introduced to this.

[0188] For example, the display area 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel circuit, and may further include a light emitting element (not shown in the figure).

[0189] For example, a plurality of cascaded shift register units 105 form a light emission control scanning drive circuit (EM GOA). For example, the output terminals EOUT of the plurality of shift register units 105 are respectively connected to the pixel circuits of each row (such as Figure 1B The light emitting control signal terminals EM1 and EM2 of the light emitting control transistors M4 and M5 are connected to provide output signals (eg, light emitting control signals) to the pixel circuits of each row, thereby driving the light emitting elements to emit light. For example, the pixel circuit is not limited to Figure 1B The circuit structure of 7T1C shown may also be a pixel circuit of circuit structures such as 2T1C, 4T2C, 8T2C, etc. in the art, which will not be described in detail here.

[0190] Figure 1E Only the X-th shift register unit 105 in the light emitting control scanning driving circuit is shown. For example, the first clock signal terminal CK (eg, Figure 1C The first stage shift register unit 105 is connected to the first clock signal line ECK to receive the first clock signal, the second clock signal terminal CB of the first stage shift register unit 105 is connected to the second clock signal line ECB to receive the second clock signal, the first clock signal terminal CK of the second stage shift register unit (not shown in the figure) is connected to the second clock signal line ECB to receive the first clock signal, the second clock signal terminal CB of the second stage shift register unit is connected to the first clock signal line ECK to receive the second clock signal, and so on. Figure 1EAs shown, the first clock signal terminal CK of the Xth (X is an odd number greater than or equal to 1) shift register unit 105 is connected to the first clock signal ECK to receive the first clock signal, the second clock signal terminal CB of the Xth shift register unit 105 is connected to the second clock signal line ECB to receive the second clock signal, the first clock signal terminal CK of the X+1th shift register unit is connected to the second clock signal line ECB to receive the first clock signal, and the second clock signal terminal CB of the X+1th shift register unit is connected to the first clock signal line ECK to receive the second clock signal. It should be noted that the connection method of the shift register units at each level and the clock signal line can also adopt other connection methods in the art, which can be determined according to the actual situation, for example, according to the number of signal lines, etc., and the embodiments of the present disclosure are not limited to this. For example, the input terminal EI of the first-stage shift register unit is connected to the trigger signal line ESTV to receive the trigger signal as the input signal, the input terminal of the second-stage shift register unit 105 is connected to the output terminal EOUT of the previous-stage shift register unit (i.e., the first-stage shift register unit), and the connection mode of the remaining shift register units is similar. The structure of the X-th stage shift register unit 105 is used as an example for description, and the embodiments of the present disclosure are not limited to this.

[0191] For example, Figure 1E As shown, the first transistor T1, the third transistor T3 and the twelfth transistor T12 are arranged side by side in the second direction X, the positive projection of the second transistor T2 on the substrate is between the positive projection of the first transistor T1 on the substrate and the positive projection of the third transistor T3 on the substrate, the fourth transistor T4 and the fifth transistor T5 are formed in one piece and are located on the imaginary line of the first transistor T1 in the first direction Y, the sixth transistor T6 and the seventh transistor T7 are formed in one piece and are located on the imaginary line of the fifth transistor T5 in the first direction Y, and the eleventh transistor T11 is located between the third transistor T 3 is on an imaginary line in the first direction Y, and is arranged side by side with the fifth transistor T5 in the second direction X, the first capacitor C1 is located on an extension line of the eleventh transistor T11 in the first direction Y, the third capacitor C3 is located on a side of the second capacitor C2 away from the eleventh transistor T11, the second capacitor C2 is located on an extension line of the twelfth transistor T12 in the first direction Y, the eighth transistor T8 is located between the second capacitor C2 and the third capacitor C3, the ninth transistor T9 and the tenth transistor T10 are integrally arranged and extend along the first direction Y, and are located between the second capacitor C2 and the second power line VGL.

[0192] For example, Figure 2BAs shown, the orthographic projection of the boundary of the first shielding layer 21 close to the display area 102 on the substrate 10 is located on the side where the orthographic projection of the second power line VGL on the substrate 10 is away from the display area 102. For example, the orthographic projection of the boundary of the first shielding layer 21 away from the display area 102 on the substrate 10 overlaps with the orthographic projection of the first power line VSS on the substrate, so as to ensure that the transistors of the shift register unit 105 are completely covered to prevent the transistors from generating leakage current.

[0193] For example, Figure 2B As shown, the light emitting control scanning driving circuit 105 includes a plurality of output transistors T9, which are configured to output light emitting control signals to the light emitting control transistors M4 and M5 of the display area 102 row by row. Figure 1C and Figure 1E The introduction of , I will not go into details here.

[0194] For example, Figure 2B As shown, the orthographic projection of the boundary of the first shielding layer 21 close to the display area 102 on the substrate 10 is located between the orthographic projections of the plurality of output transistors T9 on the substrate 10 and the orthographic projection of the second power line VGL on the substrate 10, thereby covering the transistors included in the light-emitting control scanning drive circuit 105 to prevent the generation of leakage current.

[0195] For example, Figure 2C As shown, the orthographic projection of the boundary of the second shielding layer 22 close to the display area 102 on the base substrate 10 overlaps with the orthographic projection of the gate scanning driving circuit 4 on the base substrate 10. For example, the orthographic projection of the boundary of the second shielding layer 22 away from the display area 102 on the base substrate 10 overlaps with the orthographic projection of the first power line VSS on the base substrate 10, thereby covering the transistors included in the light emitting control scanning driving circuit 105 to prevent the generation of leakage current.

[0196] For example, the orthographic projection of the boundary of the second shielding layer 22 close to the display area 102 on the base substrate 10 overlaps with the orthographic projection of the output transistor T25 of the gate scanning driving circuit 4 outputting the gate scanning signal on the base substrate 10; or Figure 2A As shown, the orthographic projection of the boundary of the second shielding layer 22 close to the display area 102 on the base substrate 10 overlaps with the orthographic projection of the gate scanning driving circuit 4 close to the display area 4 on the base substrate 10, that is, the second shielding layer 22 covers the entire gate scanning driving circuit 5, and the embodiments of the present disclosure are not limited to this. For example, the circuit structure and layout of the gate scanning driving circuit 4 can adopt the settings in the art, which will not be repeated here.

[0197] It should be noted that for the sake of clarity and brevity, Figures 2B to 3CThe gate scanning shift register unit 104 is omitted in the figure. The specific coverage method can be found in the following figure. Figure 2A Description in .

[0198] It should be noted that the arrangement of the transistors in the gate scanning shift register unit 104 is not limited to Figure 2A The position arrangement relationship shown in FIG. 1 may also adopt other forms of stacked structures, which will not be described in detail herein. The embodiments of the present disclosure are not limited thereto.

[0199] Corresponding to each light emitting control shift register unit 105, for example, Figure 2B and Figure 2C The light emitting control shift register unit 105 is taken as an example for explanation, and the structures of the other light emitting control shift register units are similar to this, which will not be described in detail.

[0200] For example, Figure 2B and Figure 2C As shown, the first shielding layer 21 includes a plurality of periodically arranged first openings 210 (eg Figure 2B The size of the first opening C210 is q*r, where q is the size of the first opening along the first direction, and r is the size of the first opening along the second direction. The second shielding layer 22 includes a plurality of periodically arranged second openings 220 (such as Figure 2C As shown in the dotted rectangular box in the middle, the first shielding layer 21 and the second shielding layer 22 respectively cover at least part of the transistors of the light emitting control shift register unit 105. Figure 2B As shown, the first shielding layer 21 covers the transistors T1, T3, T4, and T11 in the light emitting control shift register unit 105. For example, Figure 2C As shown, the second shielding layer 22 covers the transistors T2, T3, T6, T11, and T12 of the light emitting control shift register unit 105. Since the first shielding layer 21 and the second shielding layer 22 are under the planarization layer, the planarization layer can also be degassed through the first opening and the second opening.

[0201] It should be noted that the number and position of transistors covered by the first blocking layer 21 and the second blocking layer 22 respectively may depend on specific circumstances, and the embodiments of the present disclosure are not limited to this.

[0202] It should be noted that, a plurality of periodically arranged first openings 210 represent that within each light-emitting control shift register unit 105, the sizes and spacings of the plurality of first openings 210 are the same; a plurality of periodically arranged second openings 220 represent that within each light-emitting control shift register unit 105, the sizes and spacings of the plurality of second openings 220 are the same.

[0203] For example, in some examples, the density of the plurality of first openings 210 ranges from 10% to 50%, and the density of the plurality of second openings 220 ranges from 10% to 50%. For example, the density of the plurality of first openings 210 and the density of the plurality of second openings 220 may be the same, and may be both 30%, for example, or may be 10% or 50%, or may be 15%, 35%, 45%, etc. Of course, the density of the plurality of first openings 210 and the density of the plurality of second openings 220 may also be different, depending on the actual situation, and the embodiments of the present disclosure are not limited thereto.

[0204] For example, the density refers to the ratio of the area of ​​each opening to the projected area of ​​one shift register unit 105 .

[0205] For example, in some examples, the shapes of the plurality of first openings 210 and the plurality of second openings 220 are rectangular, such as square, and may also be other regular or irregular shapes such as circular and diamond, which is not limited in the embodiments of the present disclosure.

[0206] For example, in some examples, the size range of the plurality of first openings 210 and the plurality of second openings 220 is 10μm*10μm to 20μm*20μm. For example, the size of the plurality of first openings 210 and the plurality of second openings 220 is the same, for example, both are 15μm*15μm, and of course can also be 10μm*10μm, 16μm*16μm or 20μm*20μm, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the sizes of the plurality of first openings 210 and the plurality of second openings 220 can also be different, depending on the actual situation, and the embodiments of the present disclosure are not limited to this.

[0207] For example, in some other examples, corresponding to each light emitting control shift register unit, for example, Figure 3B and 3C As shown, the first shielding layer 21 includes a plurality of first openings 210 arranged non-periodically (eg Figure 3B The second shielding layer 22 includes a plurality of second openings 220 arranged non-periodically (as shown in the rectangular frame of the solid line in the middle). Figure 3C The first shielding layer 21 and the second shielding layer 22 respectively cover at least part of the transistors of the light emitting control shift register unit 105.

[0208] For example, Figure 3B As shown, the first shielding layer 21 covers the transistors T1, T2, T3, T4, T6, T8, and T12 in the light emitting control shift register unit 105. For example, Figure 3C As shown, the second shielding layer 22 covers the transistors T5 , T7 , T9 , T10 , and T11 of the light emitting control shift register unit 105 .

[0209] It should be noted that the number and position of transistors covered by the first blocking layer 21 and the second blocking layer 22 respectively may depend on specific circumstances, and the embodiments of the present disclosure are not limited to this.

[0210] It should be noted that, multiple non-periodically arranged first openings 210 represent that within a light-emitting control shift register unit 105, the sizes and spacings of the multiple first openings 210 are variable; multiple non-periodically arranged second openings 220 represent that within a light-emitting control shift register unit 105, the sizes and spacings of the multiple second openings 220 are variable.

[0211] For example, in some examples, the density of the plurality of first openings 210 ranges from 10% to 25%, and the density of the plurality of second openings 220 ranges from 10% to 25%. For example, the density of the plurality of first openings 210 and the density of the plurality of second openings 220 may be the same, and may be both 20%, for example, and may also be 10% or 25%, or may also be 15%, etc. Of course, the density of the plurality of first openings 210 and the density of the plurality of second openings 220 may also be different, for example, the density of the plurality of first openings 210 is 10%, and the density of the plurality of second openings 220 is 20%, which may be determined according to actual conditions, and the embodiments of the present disclosure are not limited thereto.

[0212] For example, the density refers to the ratio of the area of ​​each opening to the projected area of ​​one shift register unit 105 .

[0213] For example, in some examples, the shapes of the plurality of first openings 210 and the plurality of second openings 220 are rectangular, such as square, and may also be other regular or irregular shapes such as circular and diamond, which is not limited in the embodiments of the present disclosure.

[0214] For example, in this example, the sizes of the plurality of first openings 210 and the plurality of second openings 220 are positively correlated with the areas of the transistors they respectively correspond to. For example, when one first opening 210 corresponds to the fifth transistor T5 and the eleventh transistor T11, and another first opening 210 corresponds to the seventh transistor T7, since the areas of the fifth transistor T5 and the eleventh transistor T11 are larger than the area of ​​the seventh transistor T7, the size of the first opening 210 corresponding to the fifth transistor T5 and the eleventh transistor T11 is larger than the size of the first opening 210 corresponding to the seventh transistor T7, and the determination of the size of the second opening 220 is similar to this, and will not be repeated.

[0215] For example, Figures 2A to 3CAs shown, the edges of the multiple first openings 210 and the edges of the multiple second openings 220 do not overlap in their orthographic projections on the base substrate 10, and the two are alternately arranged, so that different shielding layers shield different transistors to prevent leakage current of the transistors.

[0216] Figure 4 A cross-sectional view of a display substrate provided in at least one embodiment of the present disclosure.

[0217] For example, Figure 4 As shown, the display substrate 1 further includes a first planarization layer PLN1 and a second planarization layer PLN2. For example, the first planarization layer PLN1 is located on a side of the first shielding layer 21 away from the second shielding layer 22 in a direction perpendicular to the base substrate 10, that is, between the first shielding layer 21 and the light emitting control scanning drive circuit EMGOA; the second planarization layer PLN2 is located between the first shielding layer 21 and the second shielding layer 22 in a direction perpendicular to the base substrate 10.

[0218] For example, Figure 4 As shown, the portion 211 of the first shielding layer 21 away from the display area 102 includes a first portion 2111 and a second portion 2112 located on the side of the first planarization layer PLN1 away from the base substrate 10, and the portion 221 of the second shielding layer 22 away from the display area 102 includes a first portion 2211 and a second portion 2212 located on the side of the second planarization layer PLN2 away from the base substrate 10.

[0219] For example, Figure 4 As shown, the first portion 2111 and the second portion 2112 of the first shielding layer 21 are formed integrally, and the first portion 2211 and the second portion 2212 of the second shielding layer 22 are formed integrally.

[0220] For example, the first power line VSS is located in the third conductive layer, and the first power line VSS is integrally formed with the first portion 2111 of the first shielding layer 21 and the second portion 2211 of the second shielding layer 22, that is, the first power line VSS includes a portion 3401 of the third conductive layer away from the display area 102, the first portion 2111 of the first shielding layer 21 and the first portion 2211 of the second shielding layer 22, and the portion 3401 of the third conductive layer away from the display area 102, the first portion 2111 of the first shielding layer 21 and the first portion 2211 of the second shielding layer 22 are in direct contact, so that the first shielding layer 21, the second shielding layer 22 and the portion 3401 of the third conductive layer 102 are all used as the first power line VSS to transmit the first voltage, so as to increase the routing thickness of the first power line VSS, thereby reducing the routing resistance of the first power line VSS.

[0221] For example, the angle b between the second part 2112 of the first shielding layer 22 and the third conductive layer is in the range of 20° to 30°, for example, it can be 20°, 30° or 25°, and the angle a between the second part 2212 of the second shielding layer 22 and the third conductive layer is in the range of 25° to 40°, for example, it can be 25°, 30° or 40°, and the embodiments of the present disclosure are not limited to this.

[0222] For example, the second shielding layer 22 is connected to the first shielding layer 21 through the via hole HL penetrating the second planarization layer PLN2, and the first shielding layer 21 is connected to the first power line VSS (for example, Figure 4 As shown, the first power line VSS includes a portion 3401 of the third conductive layer away from the display area 102, a first portion 2111 of the first shielding layer 21, and a first portion 2211 of the second shielding layer 22, and the portion 3401 of the third conductive layer away from the display area 102, the first portion 2111 of the first shielding layer 21, and the first portion 2211 of the second shielding layer 22 are in direct contact), so that the first voltage provided by the first power line VSS can be evenly applied to the first shielding layer 21 and the second shielding layer 22, so that the portion 3401 of the third conductive layer, the first shielding layer 21, and the second shielding layer 22 all transmit the first voltage, and at the same time, the thickness of the first power line VSS is increased, and the wiring resistance on the first power line VSS is reduced, which is conducive to the accurate transmission of the first voltage on the first power line VSS to the cathode of the light-emitting element LE in the pixel circuit of the display area 102.

[0223] For example, Figure 4 and 5B As shown, the display substrate further includes a support layer PS. For example, the support layer is located on the side of the second shielding layer 22 away from the first shielding layer 21, and the orthographic projection of the support layer PS on the base substrate 10 overlaps with the orthographic projection of the edge of a row of vias away from the display area 102 among the plurality of vias on the base substrate 10. That is, the support layer PS only covers Figure 5A The leftmost column of via holes in the via holes HL shown in the figure along the second direction X plays a supporting role. For example, the support layer PS can be provided in the same layer as the pixel definition layer PDL described below, and the material of the support layer PS can be the same as that of the pixel definition layer PDL, which will be described in detail below and will not be repeated here.

[0224] For example, Figure 5B As shown, the orthographic projection of the pixel definition layer PDL on the base substrate 10 overlaps with the orthographic projection of the edges of the remaining via holes except the leftmost row of via holes on the base substrate.

[0225] Figure 5A A schematic diagram of another display substrate provided for at least one embodiment of the present disclosure; Figure 5B for Figure 5AA cross-sectional view of the display substrate along the AA' and BB' directions; Figure 5C A schematic diagram of a light emitting control shift register unit provided by at least one embodiment of the present disclosure; Figure 5E A connection diagram of a light emitting control shift register unit and a pixel circuit provided in at least one embodiment of the present disclosure.

[0226] For example, Figure 5A As shown, in the second direction X perpendicular to the first direction Y, the via hole HL is located between the plurality of first openings 210 and the plurality of second openings 220 .

[0227] For example, the via hole HL is a regular or irregular shape such as a circle, square or diamond, which is not limited in the embodiments of the present disclosure. For example, the aperture of the via hole HL ranges from 3 μm to 5 μm, which may be determined according to actual conditions, which is not limited in the embodiments of the present disclosure.

[0228] For example, Figure 1E As shown, the light emitting control shift register unit 105 further includes a plurality of connection parts, which include: a first connection part E1, a second connection part E2 and a third connection part E3. For example, the first connection part E1 includes (or serves as) Figure 1C The first node N1 shown in FIG. 1 , the second connection portion E2 includes (or serves as) Figure 1C The second node N2 shown in FIG. 1 , the third connection portion E3 includes (or serves as) Figure 1C The output terminal EOUT is shown in FIG.

[0229] For example, Figure 5C As shown, since fixed levels (for example, the second level on the first power line VSS as described above) are respectively applied to the first blocking layer 21 and the second blocking layer 22, the light emitting control shift register unit 105 also includes a third stabilizing capacitor C4, a fourth stabilizing capacitor C5 and a second stabilizing capacitor C6, thereby improving the ability of the light emitting control scanning drive circuit to maintain a valid level output.

[0230] For example, Figure 5C As shown, the first plate of the third stabilizing capacitor C4 is connected to the first node N1, and the second plate of the third stabilizing capacitor C4 is connected to the first power line VSS; the first plate of the fourth stabilizing capacitor C5 is connected to the second node N2, and the second plate of the fourth stabilizing capacitor C5 is connected to the first power line VSS; the first plate of the second stabilizing capacitor C6 is connected to the second node N2, and the second plate of the second stabilizing capacitor C6 is connected to the first power line VSS.

[0231] like Figure 5EAs shown, the first power line VSS in the light emitting control shift register unit 105 is connected to the cathode of the light emitting element LE of the pixel circuit in the display area 102. It should be noted that the first power line VSS in the light emitting control shift register unit 105 and the cathode of the light emitting element LE of the pixel circuit in the display area 102 are also connected to Figure 5D The second substrate C242 of the first stabilizing capacitor C24 in the gate scanning shift register unit 104 is connected.

[0232] For example, Figure 5B and 5C As shown, the third stabilizing capacitor C4 is located between the second shielding layer 22 and the first connecting portion E1, the fourth stabilizing capacitor C5 is located between the first shielding layer 21 and the second connecting portion E2, and the second stabilizing capacitor C6 is located between the first shielding layer 21 and the third connecting portion E3.

[0233] For example, Figure 5B As shown, in a direction perpendicular to the base substrate 10, a semiconductor layer, a first insulating layer 350, a first conductive layer, a second insulating layer 360, a second conductive layer, a third insulating layer 370, a third conductive layer and a fourth insulating layer 380 are arranged in sequence between the base substrate 10 and the first blocking layer 21.

[0234] For example, stable capacitors are formed between the first shielding layer 21 and the second shielding layer 22 and the first conductive layer, the second conductive layer and the third conductive layer, respectively. Figure 5B Only the capacitors formed between the first shielding layer 21 and the second shielding layer 22 and the first connection part E1, the second connection part E2 and the third connection part E3 in the third conductive layer (for example, the second stable capacitor C6, the third stable capacitor and the fourth stable capacitor) are shown, and the remaining capacitors are not shown, but it should be understood that they exist. The first shielding layer 21 and the multiple second shielding layers 22 together serve as the second plates of the multiple stable capacitors, and the first plates of the multiple stable capacitors are the first conductive layer, the second conductive layer or the third conductive layer, wherein the first plate refers to an independent and complete pattern in the first conductive layer, the second conductive layer or the third conductive layer located in the peripheral area, which can be electrically connected to the signal line located in the display area through a via.

[0235] For example, the semiconductor layer includes active layers of a plurality of transistors, e.g. Figure 5B Only the active layer A1 of the first transistor T1 , the active layer A2 of the second transistor T2 , the active layer A3 of the third transistor T3 , the active layer A5 of the fifth transistor T5 , and the active layer A9 of the ninth transistor T9 are shown.

[0236] For example, the first conductive layer includes gates of a plurality of transistors (eg, Figure 5BOnly the gate of the first transistor T1, the gate G2 of the second transistor T2, the gate G5 of the fifth transistor T5 and the first electrodes of the plurality of capacitors are shown, the second conductive layer includes the second electrodes of the plurality of capacitors, and the third conductive layer includes a plurality of connecting portions (for example, Figure 5B Only the first connection portion E1, the second connection portion E2 and the third connection portion E3, the first clock signal line GCK, the second clock signal line GCB, the second power line VGL and the third power line VGH are shown.

[0237] For example, in some examples, the display substrate 1 further includes a fifth insulating layer and a sixth insulating layer. For example, the fifth insulating layer is located between the first blocking layer 21 and the third conductive layer in a direction perpendicular to the base substrate 10, and the sixth insulating layer is located between the second blocking layer 22 and the third conductive layer in a direction perpendicular to the base substrate 10. For example, the fifth insulating layer includes a first planarization layer PLN1, and the sixth insulating layer includes a first planarization layer PLN1 and a second planarization layer PLN2. Since the distance between the first blocking layer 21 and the third conductive layer (for example, the connecting portion of the third conductive layer) is different from the distance between the second blocking layer 22 and the third conductive layer (for example, the connecting portion of the third conductive layer), the capacitance formed therefrom is also different.

[0238] For example, the thickness range of the first planarization layer PLN1 and the second planarization layer PLN2 is 1.0 μm to 2.0 μm, respectively. For example, the thickness of the first planarization layer PLN1 and the second planarization layer PLN2 is the same, for example, both are 1.5 μm, and can also be 1.0 μm or 2.0 μm, etc. Therefore, the thickness of the fifth insulating layer is about half of the thickness of the sixth insulating layer.

[0239] Of course, the thicknesses of the first planarization layer PLN1 and the second planarization layer PLN2 may also be different, and the embodiments of the present disclosure are not limited to this.

[0240] For example, the capacitance formed between the first shielding layer 21 and the third conductive layer (for example, the fourth stable capacitor C5 and the second stable capacitor C6) is one tenth of the first capacitor C1, the second capacitor C2, or the third capacitor C3. For example, the capacitance formed between the second shielding layer 22 and the third conductive layer (for example, the third stable capacitor C4) is a few tenths of the first capacitor C1, the second capacitor C2, or the third capacitor C3.

[0241] It should be noted that the first shielding layer 21 and the second shielding layer 22 and the first conductive layer and the second conductive layer will also form capacitors respectively, that is, each transistor and each electrode of the capacitor will form a capacitor with the first power line VSS (not shown in the figure), thereby improving the ability of the EM GOA to maintain a valid level output.

[0242] It should be noted that capacitance is also formed between each conductive layer of the gate scanning driving circuit and the second shielding layer 22 , and its principle is similar to that of EMGOA, which will not be described in detail here.

[0243] For example, in some embodiments, the gate scanning driving circuit further includes a first scanning capacitor, and the ratio of the first stabilizing capacitor C24 to the first scanning capacitor C21 satisfies the following relationship:

[0244] GH1 / EH1 <C24 / C21<GH1 / EH2

[0245] Among them, GH1 is the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit within one frame, EH1 is the duration of the effective level of the light emitting control signal output by the light emitting control scanning driving circuit within one frame, and EH2 is the duration of the invalid level of the light emitting control scanning driving circuit within one frame. Through the ratio of the effective level or invalid level of the gate scanning signal to the light emitting control signal, the size of the first stable capacitor C24 can be reasonably controlled to meet the different driving capabilities of the gate scanning driving circuit and the light emitting control scanning driving circuit, while not causing too much impact on the capacitance of the gate scanning driving circuit.

[0246] For example, the effective level of the gate scanning signal output by the gate scanning driving circuit in one frame refers to the control such as Figure 1B The effective level of the light emitting control signal output by the light emitting control scanning driving circuit in one frame refers to the level at which M2 is turned on as shown in FIG. Figure 1B The level at which M4 or M5 is turned on as shown in FIG. 1 , the effective level of the light control signal output by the light control scanning driving circuit in one frame refers to the control level of Figure 1B The level at which M4 or M5 is turned off is shown in FIG.

[0247] For example, C24 / C21≈1 / 10; GH1 / EH1=1 / (N-1), N is the number of scan lines, for example, N is 2560 or 1920; GH1 / EH2=1 / 2 or 1 / 3.

[0248] For example, in some embodiments, the ratio of the second stabilizing capacitor C6 to the second capacitor C2 of the light emitting control scanning driving circuit satisfies the following relationship:

[0249] GH 1 / EH1 <C6 / C2<GH1 / EH2

[0250] Among them, GH1 is the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit within one frame, EH1 is the duration of the effective level of the light emitting control signal output by the light emitting control scanning driving circuit within one frame, and EH2 is the duration of the invalid level of the light emitting control scanning driving circuit within one frame. Through the ratio of the effective level or invalid level of the gate scanning signal to the light emitting control signal, the size of the second stabilizing capacitor C6 can be reasonably controlled to meet the different driving capabilities of the gate scanning driving circuit and the light emitting control scanning driving circuit, while not causing too much impact on the capacitance of the light emitting control scanning driving circuit.

[0251] For example, C6 / C2≈1 / 5; GH1 / EH1=1 / (N-1), N is the number of scan lines, for example, N is 2560 or 1920; GH1 / EH2=1 / 2 or 1 / 3.

[0252] For example, in some embodiments, the ratio of the first stabilizing capacitor C24 to the first scanning capacitor C21 satisfies the following relationship:

[0253] GOL / GOW <C24 / C21<GH1 / EH2

[0254] Wherein, GOL / GOW is the aspect ratio of the output transistor of the gate scan driving circuit.

[0255] For example, GOL / GOW may also be the aspect ratio of the output control transistor of the gate scan driving circuit. Through the further relationship between the first stabilizing capacitor C24 and the first scanning capacitor, the size of the first stabilizing capacitor C24 can be further and more accurately designed according to the size of the output transistor or the output control transistor, so that the size of the first stabilizing capacitor C24 can meet the different driving capabilities of the gate scan driving circuit and the light emitting control scanning driving circuit, while not causing too much impact on the capacitance of the gate scan driving circuit.

[0256] For example, C24 / C21 is approximately equal to 1 / 10; GOL / GOW=1 / 50; GH1 / EH2=1 / 2 or 1 / 3.

[0257] For example, in some embodiments, the ratio of the second stabilizing capacitor C6 to the second capacitor C2 of the light emitting control scanning driving circuit satisfies the following relationship:

[0258] EOL / EOW <C6 / C2<GH1 / EH2

[0259] Wherein, EOL / EOW is the aspect ratio of the output transistor of the light emitting control scanning driving circuit. Through the further relationship between the second stabilizing capacitor C6 and the second capacitor, the size of the second stabilizing capacitor C6 can be further and more accurately designed according to the size of the output transistor, so that the size of the second stabilizing capacitor C6 meets the different driving capabilities of the gate scanning driving circuit and the light emitting control scanning driving circuit, and does not cause too much impact on the capacitance of the light emitting control scanning driving circuit.

[0260] For example, C6 / C2 is approximately equal to 1 / 5, EOW / EOL=3.5 / 75=1 / 21, and GH1 / EH2=1 / 2 or 1 / 3.

[0261] For example, in some embodiments, the ratio of the first stabilizing capacitor C24 to the first scanning capacitor C21 satisfies the following relationship:

[0262] (GSW / GSL) / (GOW / GOL) <C24 / C21<GH1 / EH2

[0263] Wherein, GOW / GOL is the width-to-length ratio of the output transistor of the gate scan drive circuit, for example Figure 1F The output transistor T25 in the gate scanning drive circuit; GSW / GSL is the width-to-length ratio of any switching transistor in the gate scanning drive circuit, for example Figure 1F The switching transistors T21, T22, T23, T26, T27, and T28 in the first stabilizing capacitor C24 are further defined by the relationship between the first stabilizing capacitor C24 and the first scanning capacitor, and the size of the first stabilizing capacitor C24 can be further and more accurately designed according to the size of the output transistor or the output control transistor and the other switching transistors, so that the size of the first stabilizing capacitor C24 can meet the different driving capabilities of the gate scanning driving circuit and the light emitting control scanning driving circuit, and at the same time does not cause too much impact on the capacitance of the gate scanning driving circuit.

[0264] For GateGOA, the width-to-length ratio of the output transistor is in the range of 170-235 / 3.5-4, and the width-to-length ratio of the switch transistor is in the range of 3-40 / 3.5-8. For example, the width-to-length ratio of the transistor T21 is 7.6 / 7 or 7.5 / 8, etc., and the transistor T22 is a dual-gate transistor, and the width-to-length ratio of T22 is 3 / 3.5, 3.5 / 3.5, etc., and the width-to-length ratio of the output transistor T25 is 175 / 3.5, for example, and the embodiments of the present disclosure are not limited thereto. Other transistors may adopt appropriate width-to-length ratios in the art, which will not be described in detail here.

[0265] For example, (GSW / GSL) / (GOW / GOL)=(7.5 / 3.5) / (175 / 3.5)=1 / 23. Taking the switching transistor with the largest aspect ratio as an example, C24 / C21 is approximately equal to 1 / 10; GH1 / EH2=1 / 2 or 1 / 3.

[0266] For example, in some embodiments, the ratio of the second stabilizing capacitor C6 to the second capacitor C2 of the light emitting control scanning driving circuit satisfies the following relationship:

[0267] (ESW / ESL) / (EOW / EOL) <C6 / C2<GH1 / EH2

[0268] Wherein, EOW / EOL is the width-to-length ratio of the output transistor of the light emitting control scanning driving circuit, for example, it can be Figure 1C Output transistor T9 or T10;

[0269] ESW / ESL is the width-to-length ratio of any switch transistor in the light-emitting control scanning drive circuit. For example, it can be Figure 1C The switching transistors T1, T2, T3, T4, T5, T6, T7, T8, T11, and T12 in the circuit are further defined by the relationship between the second stabilizing capacitor C6 and the second capacitor, and the size of the second stabilizing capacitor C6 can be further and more accurately designed according to the size of the output transistor and other switching transistors, so that the size of the second stabilizing capacitor C6 meets the different driving capabilities of the gate scanning driving circuit and the light-emitting control scanning driving circuit, and does not cause too much impact on the capacitance of the light-emitting control scanning driving circuit.

[0270] For example, (ESW / ESL) / (EOW / EOL)=(7.5 / 3.2) / (75 / 3.5)=1 / 9. Taking the switching transistor with the largest aspect ratio as an example, C6 / C2 is approximately equal to 1 / 5, and GH1 / EH2=1 / 2 or 1 / 3. For EMGOA, the width-to-length ratio of the output transistor is in the range of 75-80 / 3.5-4, and the width-to-length ratio of the switch transistor is in the range of 3.2-8 / 3.2-11; for example, the width-to-length ratio of transistor T1 is 7.5-7.8 / 4.6-5.5, such as 7.5 / 4.6 or 7.5 / 5.5, etc.; transistor T2 is a dual-gate transistor, and the width-to-length ratio of T2 is 3.6-4 / 8.2-11, such as 3.7 / 8.2 or 3.7 / 10, etc.; the width-to-length ratio of transistor T5 is 7-8 / 4.7-5, such as 7.5 / 4.7, and the width-to-length ratio of output transistor T9 is, for example, 75 / 3.5, which can be determined according to actual conditions, and the embodiments of the present disclosure are not limited thereto. Other transistors can adopt appropriate width-to-length ratios in the art, which will not be described in detail here.

[0271] For example, GOW / GOL may also be the aspect ratio of the output control transistor T24 of the gate scan driving circuit.

[0272] The second capacitor C2 in the above formula may also be replaced by the first capacitor C1 or the third capacitor C3, and the first scanning capacitor C21 may also be replaced by the second scanning capacitor C22, which is not limited in the embodiments of the present disclosure.

[0273] In the embodiment of the present disclosure, by controlling the sizes of the first stabilizing capacitor C24 and the second stabilizing capacitor C6, the first stabilizing capacitor C24 and the second stabilizing capacitor C6 are present to ensure the driving capability of the gate scanning driving circuit and the light emitting control scanning driving circuit, while at the same time the coupling capacitor does not cause too much influence on the original storage capacitor.

[0274] It should be noted that, since the first shielding layer 21 does not cover the shift register unit in the gate scanning drive circuit, almost no capacitance is formed between the first shielding layer 21 and the gate scanning drive circuit. Of course, the specific situation may depend on the actual situation, and the embodiments of the present disclosure are not limited to this.

[0275] For example, a pixel defining layer PDL is further included on a side of the second shielding layer 22 away from the first shielding layer 21 , for defining pixels of the display area 102 .

[0276] For example, in some examples, such as Figure 4 As shown, the first planarization layer PLN1 and the second planarization layer PLN2 further include a groove 30 arranged between the light emitting control scanning driving circuit 5 and the gate scanning driving circuit 4.

[0277] For example, the first planarization layer PLN1 includes a first portion located on a side of the groove 30 away from the display area 102 and covering the light-emitting control scanning driving circuit 5, and a second portion covering the gate scanning driving circuit 4; for example, the second planarization layer PLN2 includes a first portion located on a side of the groove 30 away from the display area 102 and covering the light-emitting control scanning driving circuit 5, and a second portion covering the gate scanning driving circuit 4.

[0278] For example, the orthographic projection of the boundary of the first blocking layer 21 on the side close to the display area 102 on the base substrate 10 falls within the orthographic projection of the first part of the second planarization layer PLN2 on the base substrate 10; the orthographic projection of the first part of the second planarization layer PLN2 on the base substrate 10 falls within the orthographic projection of the first part of the first planarization layer PLN1 on the base substrate, thereby ensuring that the second planarization layer PLN2 can cover the first blocking layer 21, and the boundary of the second planarization layer PLN2 maintains a certain distance from the boundary of the first planarization layer PLN1, so that the slope angle of the second planarization layer PLN2 and the first planarization layer PLN1 at the groove 30 is not too large, thereby ensuring that the second blocking layer 22 is not easily damaged at the groove 30.

[0279] For example, the second shielding layer 22 extends from the area corresponding to the light emitting control scanning driving circuit 5 to the area corresponding to the gate scanning driving circuit 4 and covers the groove 30 .

[0280] For example, the width B of the orthographic projection of the second shielding layer 22 covering the groove 30 on the base substrate 10 along the second direction X is expressed as follows:

[0281] B=A+k1*P1+k2*Q1+k3*P2+k4*Q2, P1=d1*tan(c1), P2=d2*tan(c2),

[0282] Wherein, A represents the width of the orthographic projection of the groove 30 on the base substrate 10 along the second direction X, P1 represents the width of the orthographic projection of the first slope 231 of the second blocking layer 22 on the base substrate 10, Q1 represents the width of the orthographic projection of the first platform 230 of the second blocking layer 22 on the base substrate 10, P2 represents the width of the orthographic projection of the second slope 229 of the second blocking layer 22 on the base substrate 10, Q2 represents the width of the orthographic projection of the second platform 228 of the second blocking layer 22 on the base substrate 10, d1 represents the thickness of the first planarization layer PLN1, d2 represents the thickness of the second planarization layer PLN2, c1 represents the slope angle of the first planarization layer PLN1, c2 represents the slope angle of the second planarization layer PLN2, k1, k2, k3, k4 are coefficients, wherein 1<k1≤2, 1<k2≤2, 1<k3≤2, 1<k4≤2, that is, by adjusting the thickness or slope angle of the first planarization layer PLN1, or by adjusting the thickness or slope angle of the second planarization layer PLN2, the width of the orthographic projection of the second shielding layer 22 covering the groove 30 on the base substrate 10 along the second direction X can be adjusted to ensure that the second shielding layer 22 covering the groove 30 has good continuity and is not prone to line breakage. Of course, k1, k2, k3 and k4 may not be equal, and their specific values ​​may be determined according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0283] For example, A is 11-12um, such as A=11.3um, 11.5um, etc.; d1 is 1.5-1.8um, d2 is 1.5-1.8um, for example, d1 and d2 are both 1.5um; the angle range of c1 is 20°-30°, the angle range of c2 is 20°-30°, for example, c1 is 25°, c2 is 28°; the range of Q1 is 3-5um, for example, Q1=4um; the range of Q2 is 1-4um, for example, Q2=2um.

[0284] For example, according to the above parameter range, it is obtained that the range of B is 30-50 um, for example, B=35.8 um.

[0285] For example, at a position of the first shielding layer 21 close to the slot 30, the angle between the first shielding layer 21 and the second shielding layer 22 is in the range of 25° to 40°. For example, the angle between the first shielding layer 21 and the second shielding layer 22 is 25°, 40°, 30°, etc., which is not limited in the embodiments of the present disclosure.

[0286] Figure 6 A cross-sectional view of another display substrate provided in at least one embodiment of the present disclosure. Figure 6 As shown, the display substrate 1 further includes: a pixel defining layer PDL, a cathode layer 23, a first encapsulation layer TFE-1, a second encapsulation layer TFE-2 and a third encapsulation layer TFE-3.

[0287] For example, the pixel defining layer PDL is located in the display area 102, includes a plurality of openings to define a plurality of pixel units, and is located on the side of the second shielding layer 22 away from the base substrate 10, and the orthographic projection of the boundary of the pixel defining layer PDL close to the peripheral area on the base substrate overlaps with the boundary of the gate scanning driving circuit 4 close to the display area 102. For example, the pixel defining layer PDL may extend from the display area 102 to the output transistor of the gate scanning driving circuit and be cut off. For example, the output transistor of the gate scanning driving circuit is configured to output a gate scanning signal.

[0288] The cathode layer 23 is located on a side of the pixel defining layer PDL away from the base substrate 10. For example, a portion of the cathode layer 23 away from the display area 102 contacts the first portion 2211 of the second blocking layer 22, and a portion of the cathode layer 23 away from the display area 102, except for a portion in contact with the first portion 2211 of the second blocking layer 22, contacts the second portion 2212 of the second blocking layer 22 except for a portion of the second opening, so that the first voltage on the first power line VSS can be transmitted to the cathode layer 23, so that the light-emitting element LE in the display area 102 can be driven to emit light.

[0289] For example, the anode layer of the light emitting element LE is disposed in the same layer as the second shielding layer 22 , wherein the anode layer of the light emitting element LE does not overlap with the first shielding layer 21 and the second shielding layer 22 .

[0290] For example, the first encapsulation layer TFE-1 is located on the side of the cathode layer 23 away from the base substrate 10; the second encapsulation layer TFE-2 is located on the side of the first encapsulation layer TFE-1 away from the base substrate 10; and the third encapsulation layer TFE-3 is located on the side of the second encapsulation layer TFE-2 away from the base substrate 10.

[0291] For example, the size of the gate scanning driving circuit 4 in the second direction X is approximately 250 μm, the size of the light emitting control scanning driving circuit 5 in the second direction X is approximately 100 μm, the third encapsulation layer TFE-3 completely covers the first shielding layer 21, and the distance between the first shielding layer 21 and the boundary of the display area 102 and the distance between the third encapsulation layer TFE-3 and the boundary of the display area 102 ranges from 95 μm to 105 μm, for example, approximately 95 μm, 100 μm or 105 μm, etc., and the embodiments of the present disclosure are not limited to this.

[0292] For example, the display substrate 1 also includes a touch structure 200, for example, the touch structure 200 is a flexible multi-layer On-Cell (FMLOC) structure, which is located on the side of the third encapsulation layer TFE-3 away from the base substrate 10 to realize the touch function of the display panel.

[0293] For example, the FMLOC includes a plurality of touch lines TL respectively connected to the touch driving electrodes Tx and the touch sensing electrodes Rx. For example, the touch driving electrodes Tx and the touch sensing electrodes Rx are located in the display area 102 to realize the touch function of the display panel. The specific structure and specific working principle thereof can refer to the design in the art and will not be described in detail here.

[0294] For example, Figure 6 As shown, the orthographic projections of the first shielding layer 21 and the second shielding layer 22 on the base substrate 10 at least partially overlap with the orthographic projections of the touch trace TL on the base substrate 10 .

[0295] For example, Figure 6 As shown, the orthographic projection of at least a portion of the touch line TL on the base substrate 10 falls into the grooves 30 of the first planarization layer PLN1 and the second planarization layer PLN2.

[0296] For example, in some examples, such as Figure 4 and Figure 6As shown, the first shielding layer 21 also includes a third portion 2213, the orthographic projection of the third portion 2113 on the base substrate 10 overlaps and contacts with the orthographic projection of the signal line (for example, the third signal line GCK and the fourth signal line GCB) of the gate scanning driving circuit 4 on the base substrate 10, so that the routing thickness of the signal can be increased to reduce the routing resistance on the signal line. For example, the signal line of the gate scanning driving circuit 4 is configured to provide a clock signal to the gate scanning driving circuit 4. For example, the third signal line GCK and the fourth signal line GCB are configured to provide a third clock signal and a fourth clock signal to the gate scanning driving circuit 4 to control the shift output of the gate scanning driving circuit 4. The specific working process can refer to the introduction of the art, which will not be repeated here.

[0297] It should be noted that, for example, the material of the semiconductor layer may include an oxide semiconductor, an organic semiconductor or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0298] For example, the material of the third conductive layer may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy or any other suitable composite material, which is not limited in the embodiments of the present disclosure. For example, the material of the first conductive layer and the second conductive layer may be the same as the material of the third conductive layer, which will not be repeated here.

[0299] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370 and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other suitable materials, which is not limited to the embodiments of the present disclosure.

[0300] For example, the anode layer of the light emitting element LE can be made of a material including a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has a high light transmittance. The material of the anode layer of the light emitting element LE is a metal, for example, the metal can be made of magnesium, magnesium alloy, aluminum or aluminum alloy.

[0301] For example, the material of the first shielding layer 21 and the second shielding layer 22 is metal, for example, the metal may be made of magnesium, magnesium alloy, aluminum or aluminum alloy, so as to shield the transistor, which is not limited in the embodiments of the present disclosure.

[0302] For example, the first planarization layer PLN1 and the second planarization layer PLN2 include organic materials, such as polymer resin materials, such as polyimide (PI), polymethyl methacrylate or polystyrene (PS), as well as aromatic, acrylic polymers, phthalimide-based polymers, aromatic ether-based polymers, amino polymers, fluorine-based polymers, paraxylene-based polymers, vinyl alcohol-based polymers, etc.

[0303] For example, the first encapsulation layer TFE-1 to the third encapsulation layer TFE-3 may include inorganic materials or organic materials. For example, the inorganic materials may include inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride. The inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. For example, the organic materials may be organic materials such as polymer materials containing desiccant or polymer materials that can block water vapor. These organic materials can planarize the surface of the display substrate and relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer. They can also include water-absorbing materials such as desiccant to absorb water, oxygen, and other substances that invade the interior.

[0304] At least one embodiment of the present disclosure further provides a light emitting control scan driving circuit. Figure 7 Schematic diagram of a light emitting control scanning driving circuit provided by at least one embodiment of the present disclosure. Figure 7 The circuit structure of the light emitting control shift register unit 105 shown in FIG. 1 includes a plurality of cascaded light emitting control shift register units 105. For example, the circuit structure of the light emitting control shift register unit 105 can be implemented as follows: Figure 5C The circuit structure shown.

[0305] For example, for each light emitting control shift register unit 105 , the light emitting control shift register unit 105 includes: a plurality of transistors, a plurality of capacitors, a plurality of connecting parts, a first shielding layer 21 and a second shielding layer 22 .

[0306] For example, the first shielding layer 21 is located between the plurality of connection portions and the second shielding layer 22 .

[0307] For example, the plurality of transistors include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 (also called an output transistor), a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The plurality of capacitors include a first capacitor C1, a second capacitor C2, a third capacitor C3, a third stabilizing capacitor C4, a fourth stabilizing capacitor C5, and a second stabilizing capacitor C6.

[0308] For example, Figure 5CAs shown, the gate of the first transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line ECK) to receive the first clock signal, the second electrode of the first transistor T1 is connected to the input terminal EI, and the first electrode of the first transistor T1 is connected to the first node N1.

[0309] A gate of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal.

[0310] A gate of the third transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the second power line VGL to receive the second voltage.

[0311] The gate of the fourth transistor T4 is connected to the second clock signal terminal CB (for example, the second clock signal terminal CB is connected to the second clock signal line ECB) to receive the second clock signal, the first electrode of the fourth transistor T4 is connected to the first node N1, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.

[0312] A gate electrode of the fifth transistor T5 is connected to the second node N2 , and a first electrode of the fifth transistor T5 is connected to the third power line VGH to receive a third voltage.

[0313] A gate of the sixth transistor T6 is connected to the second electrode of the eleventh transistor T11 , a first electrode of the sixth transistor T6 is connected to the second clock signal terminal CB to receive the second clock signal, and a second electrode of the sixth transistor T6 is connected to the third node N3 .

[0314] A first electrode of the first capacitor C1 is connected to a second electrode of the eleventh transistor T11 , and a second electrode of the first capacitor C2 is connected to a third node N3 .

[0315] A gate of the seventh transistor T7 is connected to the second clock signal terminal CB to receive the second clock signal, a first electrode of the seventh transistor T7 is connected to the third node N3, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0316] A gate electrode of the eighth transistor T8 is connected to the first node N1 , a first electrode of the eighth transistor T8 is connected to the fourth node N4 , and a second electrode of the eighth transistor T8 is connected to the third power line VGH to receive a third voltage.

[0317] A gate of the ninth transistor T9 is connected to the fourth node N4, a first electrode of the ninth transistor T9 is connected to the third power line VGH to receive the third voltage, and a second electrode of the ninth transistor T9 is connected to the output terminal EOUT.

[0318] A first electrode of the third capacitor C3 is connected to the fourth node N4 , and a second electrode of the third capacitor C3 is connected to the third power line VGH to receive a third voltage.

[0319] A gate of the tenth transistor T10 is connected to a second electrode of the twelfth transistor T12 , a first electrode of the tenth transistor T10 is connected to the second power line VGL to receive a second voltage, and a second electrode of the tenth transistor T10 is connected to the output terminal EOUT.

[0320] A first electrode of the second capacitor C2 is connected to a second electrode of the twelfth transistor T12 , and a second electrode of the second capacitor C2 is connected to the second clock signal terminal CB to receive the second clock signal.

[0321] A gate electrode of the eleventh transistor T11 is connected to the second power line VGL to receive the second voltage, and a first electrode of the eleventh transistor T11 is connected to the second node N2.

[0322] A gate electrode of the twelfth transistor T12 is connected to the second power line VGL to receive the second voltage, and a first electrode of the twelfth transistor T12 is connected to the first node N1.

[0323] For example, Figure 5C As shown, the first plate of the third stabilizing capacitor C4 is connected to the first node N1, and the second plate of the third stabilizing capacitor C4 is connected to the first power line VSS; the first plate of the fourth stabilizing capacitor C5 is connected to the second node N2, and the second plate of the fourth stabilizing capacitor C5 is connected to the first power line VSS; the first plate of the second stabilizing capacitor C6 is connected to the second node N2, and the second plate of the second stabilizing capacitor C6 is connected to the first power line VSS.

[0324] For example, the plurality of connection parts include: a first connection part E1, a second connection part E2 and a third connection part E3. For example, the first connection part E1 includes (or serves as) Figure 1C The first node N1 shown in FIG. 1 , the second connection portion E2 includes (or serves as) Figure 1C The second node N2 shown in FIG. 1 , the third connection portion E3 includes (or serves as) Figure 1C The output terminal EOUT is shown in FIG.

[0325] For example, in an embodiment of the present disclosure, the first blocking layer 21 covers at least one transistor in the light emitting control shift register unit 105 , and the second blocking layer 22 covers at least one transistor among multiple transistors in the light emitting control shift register unit 105 except the at least one transistor.

[0326] It should be noted that for a detailed description of the above-mentioned light emitting control scanning drive circuit, please refer to Figures 1A to 6The description in will not be repeated here.

[0327] The technical effects of the light emitting control scanning driving circuit provided in the above-mentioned embodiment may refer to the technical effects of the display substrate 1 provided in the embodiment of the present disclosure, which will not be described in detail here.

[0328] At least one embodiment of the present disclosure further provides a display device. Figure 8 Schematic diagram of a display device provided by at least one embodiment of the present disclosure. Figure 8 As shown, the display device 2 includes a display substrate 1 provided by any embodiment of the present disclosure, for example, Figure 2A The display substrate 1 shown in FIG.

[0329] It should be noted that the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 can also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0330] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device. To achieve the basic functions of the display device, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0331] The technical effects of the display device 2 provided in the above embodiment may refer to the technical effects of the display substrate 1 provided in the embodiment of the present disclosure, which will not be described in detail here.

[0332] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. Fig. 9 A flowchart of a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure. For example, the manufacturing method can be used to manufacture a display substrate provided in any embodiment of the present disclosure. For example, it can be used to manufacture Figure 2A The display substrate 1 shown in FIG.

[0333] like Fig. 9 As shown, the method for manufacturing the display substrate includes steps S110 to S120.

[0334] Step S110: providing a substrate.

[0335] Step S120: forming a gate scanning driving circuit, a light emitting control scanning driving circuit, a first shielding layer and a second shielding layer on the base substrate.

[0336] For example, the first shielding layer 21 covers at least one transistor in the light emission control scanning driving circuit 105 , and the second shielding layer 22 covers at least one transistor among the plurality of transistors except the at least one transistor in the light emission control scanning driving circuit 105 .

[0337] It should be noted that in multiple embodiments of the present disclosure, the process of the method for manufacturing the display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the process of the manufacturing method described above includes multiple operations that appear in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The manufacturing method described above can be performed once or multiple times according to predetermined conditions.

[0338] The technical effects of the method for manufacturing the display substrate provided in the above embodiment may refer to the technical effects of the display substrate provided in the embodiment of the present disclosure, which will not be described in detail here.

[0339] There are a few points to note:

[0340] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0341] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0342] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A base substrate, comprising a display area and a peripheral area located on at least one side of the display area; A gate scanning driving circuit, a light emitting control scanning driving circuit and a first power line are arranged in the peripheral area of ​​the base substrate and arranged in sequence along a side away from the display area; The gate scanning driving circuit comprises a first stabilizing capacitor, a first plate of the first stabilizing capacitor is electrically connected to an output end of the gate scanning driving circuit, and a second plate of the first stabilizing capacitor is electrically connected to the first power line; The light emitting control scanning driving circuit comprises a second stabilizing capacitor, a first plate of the second stabilizing capacitor is electrically connected to an output terminal of the light emitting control scanning driving circuit, a second plate of the second stabilizing capacitor is electrically connected to the first power line, and the second plate of the second stabilizing capacitor comprises a first portion and a second portion, an organic insulating layer is provided between the first portion and the second portion in a direction perpendicular to the substrate, The first part of the second plate of the second stabilizing capacitor is located in the first shielding layer, the second part of the second plate of the second stabilizing capacitor is located in the second shielding layer, and the first shielding layer and the second shielding layer are sequentially arranged on the side of the light emitting control scanning driving circuit away from the base substrate.

2. The display substrate according to claim 1, wherein: The light emitting control scanning driving circuit further includes: a third stabilizing capacitor and a first connecting portion; Among them, the first plate of the third stabilizing capacitor is electrically connected to the first connecting portion, the second plate of the third stabilizing capacitor is electrically connected to the first power line, and the second plate of the third stabilizing capacitor includes a first part and a second part, and an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the base substrate.

3. The display substrate according to claim 2, wherein: The light emission control scanning driving circuit includes a plurality of cascaded light emission control shift register units, wherein the light emission control shift register units include a plurality of transistors, a plurality of capacitors and a plurality of connecting parts. Wherein, the plurality of transistors include: A first transistor, wherein a gate of the first transistor is connected to a first clock signal line to receive a first clock signal, a first electrode of the first transistor is connected to a first node, and a second electrode of the first transistor is connected to an input terminal; a second transistor, wherein a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to the second node, and a second electrode of the second transistor is connected to the first clock signal line to receive the first clock signal; a third transistor, wherein a gate of the third transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to a second power supply line to receive a second voltage; a fourth transistor, wherein a gate of the fourth transistor is connected to the second clock signal line to receive a second clock signal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected to a second electrode of the fifth transistor; the fifth transistor, wherein a gate of the fifth transistor is connected to the second node, and a first electrode of the fifth transistor is connected to a third power line to receive a third voltage; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second clock signal line to receive the second clock signal, and a second electrode of the sixth transistor is connected to the third node; a seventh transistor, wherein a gate of the seventh transistor is connected to the second clock signal line to receive the second clock signal, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to the fourth node; an eighth transistor, wherein a gate of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the fourth node, and a second electrode of the eighth transistor is connected to the third power line to receive the third voltage; a ninth transistor, wherein a gate of the ninth transistor is connected to the fourth node, a first electrode of the ninth transistor is connected to the third power line to receive the third voltage, and a second electrode of the ninth transistor is connected to the output terminal; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the second power line to receive the second voltage, and a second electrode of the tenth transistor is connected to the output terminal; The plurality of capacitors include: A first capacitor, wherein a second electrode of the first capacitor is connected to the third node; a second capacitor, wherein a second electrode of the second capacitor is connected to the second clock signal line to receive the second clock signal; A third capacitor, wherein a first electrode of the third capacitor is connected to the fourth node, and a second electrode of the third capacitor is connected to the third power line to receive the third voltage; The third stabilizing capacitor, wherein a first plate of the third stabilizing capacitor is connected to the first node, and a second plate of the third stabilizing capacitor is electrically connected to the first power line; The second stabilizing capacitor, wherein a first plate of the second stabilizing capacitor is connected to an output end of the light emitting control scanning driving circuit, and a second plate of the second stabilizing capacitor is electrically connected to the first power line; The plurality of connection parts include: the first connection part and the third connection part, wherein: The first connection portion includes the first node, and the third connection portion is connected to an output end of the light emitting control scanning driving circuit.

4. The display substrate according to any one of claims 1 to 3, wherein: The gate scanning driving circuit further includes a first scanning capacitor, and a ratio of the first stabilizing capacitor to the first scanning capacitor satisfies the following relationship: GH1 / EH1 <C24 / C21<GH1 / EH2 Among them, C21 represents the first scanning capacitor, C24 represents the first stabilizing capacitor, GH1 is the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit within one frame, EH1 is the duration of the effective level of the light-emitting control signal output by the light-emitting control scanning driving circuit within one frame, and EH2 is the duration of the invalid level of the light-emitting control scanning driving circuit within one frame.

5. The display substrate according to any one of claims 1 to 3, wherein: When the light emitting control scanning driving circuit includes a second capacitor, a ratio of the second stabilizing capacitor to the second capacitor of the light emitting control scanning driving circuit satisfies the following relationship: GH1 / EH1 <C6 / C2<GH1 / EH2 Among them, C6 represents the second stable capacitor, C2 represents the second capacitor of the light-emitting control scanning driving circuit, GH1 is the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit within one frame, EH1 is the duration of the effective level of the light-emitting control signal output by the light-emitting control scanning driving circuit within one frame, and EH2 is the duration of the invalid level of the light-emitting control scanning driving circuit within one frame time.

6. The display substrate according to claim 4, wherein: The ratio of the first stable capacitor to the first scanning capacitor satisfies the following relationship: GOL / GOW <C24 / C21<GH1 / EH2 Wherein, GOL / GOW is the aspect ratio of the output transistor of the gate scan driving circuit.

7. The display substrate according to claim 5, wherein: The ratio of the second stabilizing capacitor to the second capacitor of the light emitting control scanning driving circuit satisfies the following relationship: EOL / EOW <C6 / C2<GH1 / EH2 Wherein, EOL / EOW is the aspect ratio of the output transistor of the light emitting control scanning driving circuit.

8. The display substrate according to claim 4, wherein: The ratio of the first stable capacitor to the first scanning capacitor satisfies the following relationship: (GSW / GSL) / (GOW / GOL) <C24 / C21<GH1 / EH2 Wherein, GOW / GOL is the width-to-length ratio of the output transistor of the gate scanning driving circuit, and GSW / GSL is the width-to-length ratio of any switch transistor of the gate scanning driving circuit.

9. The display substrate according to claim 5, wherein: The ratio of the second stabilizing capacitor to the second capacitor of the light emitting control scanning driving circuit satisfies the following relationship: (ESW / ESL) / (EOW / EOL) <C6 / C2<GH1 / EH2 Wherein, EOW / EOL is the width-to-length ratio of the output transistor of the light emitting control scanning driving circuit, and ESW / ESL is the width-to-length ratio of any switch transistor of the light emitting control scanning driving circuit.

10. The display substrate according to claim 1, wherein: The light emitting control scanning driving circuit further includes: a fourth stabilizing capacitor and a second connecting portion; Among them, the first plate of the fourth stabilizing capacitor is electrically connected to the second connecting portion, the second plate of the fourth stabilizing capacitor is electrically connected to the first power line, and the second plate of the fourth stabilizing capacitor includes a first part and a second part, and an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the base substrate.

11. The display substrate according to claim 3, wherein: The plurality of capacitors also include: a fourth stabilizing capacitor, wherein a first electrode plate of the fourth stabilizing capacitor is connected to the second node, and a second electrode plate of the fourth stabilizing capacitor is electrically connected to the first power line; The plurality of connection parts further include: a second connection part including the second node.

12. The display substrate according to claim 3, wherein: The plurality of transistors further comprises: an eleventh transistor, wherein a gate of the sixth transistor is connected to a second electrode of the eleventh transistor, a first electrode of the first capacitor is connected to a second electrode of the eleventh transistor, a gate of the eleventh transistor is connected to the second power line to receive the second voltage, and a first electrode of the eleventh transistor is connected to the second node; a twelfth transistor, wherein the gate of the tenth transistor is connected to the second electrode of the twelfth transistor, the first electrode of the second capacitor is connected to the second electrode of the twelfth transistor, the gate of the twelfth transistor is connected to the second power line to receive the second voltage, and the first electrode of the twelfth transistor is connected to the first node.

13. The display substrate according to any one of claims 1 to 3, wherein: The duration of the effective level of the light emitting control signal output by the light emitting control scanning driving circuit in one frame is longer than the duration of the effective level of the gate scanning signal output by the gate scanning driving circuit in one frame.

14. The display substrate according to claim 1, wherein: The light emitting control scanning driving circuit includes a plurality of transistors, the first shielding layer covers at least one transistor in the light emitting control scanning driving circuit, and the second shielding layer covers at least one transistor among a plurality of transistors in the light emitting control scanning driving circuit except the at least one transistor; The second shielding layer is also arranged on a side of the gate scanning driving circuit away from the base substrate, and the second shielding layer covers at least one transistor in the gate scanning driving circuit.

15. The display substrate according to claim 2, wherein: The light emitting control scanning driving circuit includes a plurality of transistors, a first portion of the second electrode plate of the third stabilizing capacitor is located on the first shielding layer, and a second portion of the second electrode plate of the third stabilizing capacitor is located on the second shielding layer. The light emitting control scanning driving circuit further includes a fourth stabilizing capacitor, wherein a first portion of a second electrode plate of the fourth stabilizing capacitor is located at the first shielding layer, and a second portion of the second electrode plate of the fourth stabilizing capacitor is located at the second shielding layer. The first shielding layer and the second shielding layer are sequentially arranged on a side of the light emitting control scanning driving circuit away from the base substrate; The first shielding layer covers at least one transistor in the light emitting control scanning driving circuit, and the second shielding layer covers at least one transistor among a plurality of transistors in the light emitting control scanning driving circuit except the at least one transistor; The second shielding layer is also arranged on a side of the gate scanning driving circuit away from the base substrate, and the second shielding layer covers at least one transistor in the gate scanning driving circuit.

16. The display substrate according to claim 14, wherein: The first shielding layer and the second shielding layer are connected to the first power line to receive a first voltage.

17. The display substrate according to claim 14, wherein the light emission control scanning driving circuit comprises a plurality of cascaded light emission control shift register units, wherein the light emission control shift register units comprise a plurality of transistors, wherein: For each of the light emitting control shift register units, the first blocking layer covers at least one transistor in the light emitting control shift register unit, and the second blocking layer covers at least one transistor among a plurality of transistors in the light emitting control shift register unit except the at least one transistor.

18. The display substrate according to claim 14, wherein: The light emission control scanning driving circuit further includes a second power line or a third power line extending along the first direction, The display substrate further includes a first power line extending along the first direction; The orthographic projection of the second power line or the third power line on the base substrate is located between the orthographic projection of the transistor included in the light emission control scanning driving circuit on the base substrate and the orthographic projection of the gate scanning driving circuit on the base substrate; The orthographic projection of the first power line on the base substrate is located on a side of the orthographic projection of the light emitting control scanning driving circuit on the base substrate away from the display area.

19. The display substrate according to claim 18, wherein: The second power line, the third power line and the first power line are located on a side of the first shielding layer away from the second shielding layer in a direction perpendicular to the base substrate.

20. The display substrate according to claim 18, wherein: The boundary of the first shielding layer on the light emitting control scanning driving circuit, where the orthographic projection is close to the display area, is located on the side where the orthographic projection of the second power line or the third power line on the base substrate is away from the display area; An orthographic projection of a boundary of the first shielding layer away from the display area on the base substrate overlaps with an orthographic projection of the first power line on the base substrate.

21. The display substrate according to claim 20, wherein: The light emission control scanning driving circuit includes a plurality of output transistors configured to output light emission control signals to the light emission control transistors of the display area row by row. The orthographic projection of the boundary of the first shielding layer close to the display area on the base substrate is located between the orthographic projections of the plurality of output transistors on the base substrate and the orthographic projections of the second power line or the third power line on the base substrate.

22. The display substrate according to claim 18, wherein: The orthographic projection of the boundary of the second shielding layer close to the display area on the base substrate overlaps with the orthographic projection of the gate scanning driving circuit on the base substrate; An orthographic projection of a boundary of the second shielding layer on a side away from the display area on the base substrate overlaps with an orthographic projection of the first power line on the base substrate.

23. The display substrate according to claim 22, wherein: The orthographic projection of the boundary of the second shielding layer close to the display area on the base substrate overlaps with the orthographic projection of the output transistor of the gate scanning driving circuit that outputs the gate scanning signal on the base substrate; or The orthographic projection of a boundary of the second shielding layer close to the display area on the base substrate overlaps with the orthographic projection of a boundary of the gate scanning driving circuit close to the display area on the base substrate.

24. The display substrate according to claim 18, wherein: An absolute value of a second voltage provided by the second power line is greater than an absolute value of a first voltage provided by the first power line.

25. The display substrate according to claim 17, wherein: Corresponding to each of the light emitting control shift register units, the first blocking layer includes a plurality of periodically arranged first openings, and the second blocking layer includes a plurality of periodically arranged second openings, so that the first blocking layer and the second blocking layer respectively cover at least part of the transistors of the light emitting control shift register unit.

26. The display substrate according to claim 25, wherein: The density of the first openings ranges from 10% to 50%, and the density of the second openings ranges from 10% to 50%.

27. The display substrate according to claim 25, wherein: The first opening and the second opening are in a square shape, and the size range of the first opening and the second opening is 10 μm*10 μm to 20 μm*20 μm.

28. The display substrate according to claim 17, wherein: Corresponding to each of the light emitting control shift register units, the first blocking layer includes a plurality of non-periodically arranged first openings, and the second blocking layer includes a plurality of non-periodically arranged second openings, so that the first blocking layer and the second blocking layer respectively cover at least part of the transistors of the light emitting control shift register unit.

29. The display substrate according to claim 28, wherein: The density of the first openings is in the range of 10% to 25%, and the density of the second openings is in the range of 10% to 25%.

30. The display substrate according to claim 28, wherein: The size of the first opening and the size of the second opening are positively correlated with the areas of the transistors respectively corresponding thereto.

31. The display substrate according to claim 25 or 28, wherein: The orthographic projections of the edge of the first opening and the edge of the second opening on the base substrate do not overlap.

32. The display substrate according to claim 31, wherein: The orthographic projections of the edges of the first openings on the base substrate and the orthographic projections of the edges of the second openings on the base substrate are arranged alternately.

33. The display substrate according to claim 18, further comprising: a first planarization layer and a second planarization layer, Wherein, the first planarization layer is located on a side of the first shielding layer away from the second shielding layer in a direction perpendicular to the base substrate, and the second planarization layer is located between the first shielding layer and the second shielding layer in a direction perpendicular to the base substrate; Wherein, the second planarization layer is the organic insulating layer.

34. The display substrate according to claim 33, wherein: The second shielding layer is connected to the first shielding layer through a plurality of via holes penetrating the second planarization layer; The light emission control scanning driving circuit includes a plurality of cascaded light emission control shift register units, and the light emission control shift register unit includes a plurality of transistors, wherein: For each of the light emitting control shift register units, the first shielding layer covers at least one transistor in the light emitting control shift register unit, and the second shielding layer covers at least one transistor among a plurality of transistors in the light emitting control shift register unit except the at least one transistor; Corresponding to each of the light emitting control shift register units, the first shielding layer includes a plurality of periodically arranged first openings, and the second shielding layer includes a plurality of periodically arranged second openings, so that the first shielding layer and the second shielding layer respectively cover at least part of the transistors of the light emitting control shift register unit; In a second direction perpendicular to the first direction, the plurality of via holes are located between the first opening and the second opening.

35. The display substrate according to claim 34, wherein: The via hole is circular or square in shape, and the aperture of the via hole ranges from 3 μm to 5 μm.

36. The display substrate according to claim 34, further comprising a supporting layer, wherein: The supporting layer is located on a side of the second shielding layer away from the first shielding layer, and an orthographic projection of the supporting layer on the base substrate overlaps with an orthographic projection of an edge of a column of via holes away from the display area among the plurality of via holes on the base substrate.

37. The display substrate according to claim 33, further comprising: In a direction perpendicular to the base substrate, a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer and a fourth insulating layer are sequentially arranged between the base substrate and the first shielding layer; The semiconductor layer includes an active layer of the multiple transistors, the first conductive layer includes gates of the multiple transistors and first electrodes of multiple capacitors, the second conductive layer includes second electrodes of the multiple capacitors, and the third conductive layer includes multiple connecting parts, a first clock signal line, a second clock signal line, a second power line and a third power line.

38. The display substrate according to claim 37, wherein: A plurality of stable capacitors are formed between the first shielding layer and the second shielding layer and the third conductive layer respectively; wherein, The first shielding layer and the second shielding layer respectively serve as second plates of the plurality of stable capacitors, and the first plates of the plurality of stable capacitors are the third conductive layer.

39. The display substrate according to claim 37, wherein: The portion of the first blocking layer away from the display area includes a first portion and a second portion located on a side of the first planarization layer away from the base substrate, and the portion of the second blocking layer away from the display area includes a first portion and a second portion located on a side of the second planarization layer away from the base substrate.

40. The display substrate according to claim 39, wherein: The first power line includes a portion of the third conductive layer away from the display area, a first portion of the first shielding layer, and a first portion of the second shielding layer, and the portion of the third conductive layer away from the display area, the first portion of the first shielding layer, and the first portion of the second shielding layer are in direct contact.

41. The display substrate according to claim 40, wherein: The included angle between the second portion of the first shielding layer and the third conductive layer is in the range of 20° to 30°, and the included angle between the second portion of the second shielding layer and the third conductive layer is in the range of 25° to 40°.

42. The display substrate according to claim 33, wherein: The first planarization layer and the second planarization layer further include a groove arranged between the light emission control scanning driving circuit and the gate scanning driving circuit. The first planarization layer includes a first portion located at a side of the groove away from the display area and covering the light emitting control scanning driving circuit and a second portion covering the gate scanning driving circuit; The second planarization layer includes a first portion located at a side of the groove away from the display area and covering the light emitting control scanning driving circuit and a second portion covering the gate scanning driving circuit; The orthographic projection of a boundary of the first shielding layer on a side close to the display area on the base substrate falls within the orthographic projection of the first portion of the second planarization layer on the base substrate; The orthographic projection of the first portion of the second planarization layer on the base substrate falls within the orthographic projection of the first portion of the first planarization layer on the base substrate; The second shielding layer extends from a region corresponding to the light emitting control scanning driving circuit to a region corresponding to the gate scanning driving circuit and covers the slot.

43. The display substrate according to claim 42, wherein: The width B of the orthographic projection of the second shielding layer covering the groove on the base substrate along a second direction perpendicular to the first direction is expressed as follows: B=A+k1*P1+k2*Q1+k3*P2+k4*Q2, P1=d1*tan(c1), P2=d2*tan(c2), wherein A represents the width of the orthographic projection of the groove on the substrate along the second direction, P1 represents the width of the orthographic projection of the first slope of the second blocking layer on the substrate, Q1 represents the width of the orthographic projection of the first platform of the second blocking layer on the substrate, P2 represents the width of the orthographic projection of the second slope of the second blocking layer on the substrate, Q2 represents the width of the orthographic projection of the second platform of the second blocking layer on the substrate, d1 represents the thickness of the first planarization layer, d2 represents the thickness of the second planarization layer, c1 represents the slope angle of the first planarization layer, c2 represents the slope angle of the second planarization layer, k1, k2, k3, k4 are coefficients, wherein 1<k1≤2, 1<k2≤2, 1<k3≤2, 1<k4≤2.

44. The display substrate according to claim 42, wherein: At a position of the first shielding layer close to the groove, an angle between the first shielding layer and the second shielding layer is in a range of 25° to 40°.

45. The display substrate according to claim 37, further comprising a fifth insulating layer and a sixth insulating layer, in, The fifth insulating layer is located between the first blocking layer and the third conductive layer in a direction perpendicular to the base substrate, and the sixth insulating layer is located between the second blocking layer and the third conductive layer in a direction perpendicular to the base substrate.

46. ​​The display substrate according to claim 45, wherein: The fifth insulating layer includes the first planarization layer, and the sixth insulating layer includes the first planarization layer and the second planarization layer.

47. The display substrate according to claim 46, wherein: The thickness of the first planarization layer and the second planarization layer are respectively in the range of 1.0 μm to 2.0 μm.

48. The display substrate according to claim 31, further comprising: a pixel defining layer, comprising a first portion located in the display area, and a second portion located on a side of the second shielding layer away from the base substrate, wherein an orthographic projection of the first portion of the pixel defining layer close to a boundary of the peripheral area on the base substrate partially overlaps with an orthographic projection of the gate scanning driving circuit on the base substrate, and an orthographic projection of the second portion of the pixel defining layer on the base substrate partially overlaps with an orthographic projection of the second opening of the second shielding layer on the base substrate; A cathode layer, located on a side of the pixel defining layer away from the substrate; A first encapsulation layer is located on a side of the cathode layer away from the substrate; A second packaging layer is located on a side of the first packaging layer away from the substrate; and The third packaging layer is located on a side of the second packaging layer away from the substrate.

49. The display substrate according to claim 48, wherein: The distance between the first shielding layer and the boundary of the display area is in the range of 95 μm to 105 μm.

50. The display substrate according to claim 48, further comprising: The touch control structure is located on a side of the third packaging layer away from the base substrate.

51. The display substrate according to claim 50, wherein: The touch control structure includes a plurality of touch control wirings respectively connected to the touch control driving electrodes and the touch control sensing electrodes. Wherein, the touch driving electrodes and the touch sensing electrodes are partially located in the display area, The orthographic projections of the first shielding layer and the second shielding layer on the base substrate at least partially overlap with the orthographic projection of the touch trace on the base substrate.

52. The display substrate according to claim 51, wherein: The display substrate further includes: a first planarization layer and a second planarization layer; The first planarization layer and the second planarization layer further include a groove disposed between the light emission control scanning driving circuit and the gate scanning driving circuit; At least a portion of the touch control wiring has an orthographic projection on the base substrate falling into the groove.

53. The display substrate according to claim 14, wherein: The first shielding layer further includes a third portion, the orthographic projection of the third portion on the base substrate overlaps and contacts with the orthographic projection of the signal line of the gate scanning driving circuit on the base substrate, The signal line of the gate scanning driving circuit is configured to provide a clock signal to the gate scanning driving circuit.

54. The display substrate according to claim 1, wherein: The output end of the gate scan drive circuit is electrically connected to at least one data writing transistor in the display area, the gate scan drive circuit is configured to output a gate scan signal, and the data writing transistor is configured to control the writing of a data signal in response to the gate scan signal. The output end of the light emitting control scan drive circuit is electrically connected to at least one light emitting control transistor in the display area, the light emitting control scan drive circuit is configured to output a light emitting control signal, and the light emitting control transistor is configured to control the light emitting element to emit light in response to the light emitting control signal. The first power line is electrically connected to the cathode of at least one light emitting element in the display area.

55. A display device, comprising the display substrate according to any one of claims 1-53.

56. A method for manufacturing a display substrate as claimed in claim 1, comprising: Providing the substrate; The gate scanning driving circuit, the light emitting control scanning driving circuit and the first power line are formed on the base substrate. The output end of the gate scan driving circuit is electrically connected to at least one data writing transistor in the display area, and the data writing transistor is configured to control the writing of a data signal in response to a gate scan signal; the output end of the light emitting control scan driving circuit is electrically connected to at least one light emitting control transistor in the display area, and the light emitting control transistor is configured to control the light emitting element to emit light in response to a light emitting control signal; and the first power line is electrically connected to a cathode of at least one light emitting element in the display area; The gate scanning driving circuit comprises a first stabilizing capacitor, a first plate of the first stabilizing capacitor is electrically connected to an output end of the gate scanning driving circuit, and a second plate of the first stabilizing capacitor is electrically connected to the first power line; The light-emitting control scanning driving circuit includes a second stabilizing capacitor, a first plate of the second stabilizing capacitor is electrically connected to the output end of the light-emitting control scanning driving circuit, a second plate of the second stabilizing capacitor is electrically connected to the first power line, and the second plate of the second stabilizing capacitor includes a first part and a second part, and an organic insulating layer is provided between the first part and the second part in a direction perpendicular to the substrate.

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