Group iii nitride laminated substrate and semiconductor element

Abstract

The present application relates to a group III nitride laminated substrate and a semiconductor element. Provided is a technology capable of improving the quality of a GaN layer formed on a base substrate. A group III nitride laminated substrate has a base substrate, a first layer formed on the base substrate and composed of aluminum nitride, and a second layer formed on the first layer and composed of gallium nitride, the second layer having a thickness of 10 μm or less, a half-value width of (0002) diffraction based on an X-ray rocking curve measurement of 100 seconds or less, and a half-value width of (10-12) diffraction based on an X-ray rocking curve measurement of 200 seconds or less.

Description

TECHNICAL FIELD

[0001] The present application relates to a Group III nitride laminated substrate and a semiconductor element. BACKGROUND

[0002] A Group III nitride laminated substrate (hereinafter also referred to as a wafer) in which a GaN layer is formed on a base substrate belonging to a dissimilar substrate such as a sapphire substrate is used as a material for manufacturing a semiconductor element such as a light emitting diode (LED) (for example, refer to Patent Document 1). With the development of large diameter of the wafer and miniaturization of the semiconductor element, the influence of, for example, a decrease in photolithography precision caused by warping of the wafer is becoming large.

[0003] For example, in order to reduce warping of the wafer, it is conceivable to thin the GaN layer formed on the base substrate. However, there is a concern that the quality of the GaN layer such as crystallinity is reduced due to thinning of the GaN layer. A technology capable of forming a high-quality GaN layer even if it is thinned is desired.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENTS

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-225648 SUMMARY

[0007] Problem to be solved by the invention

[0008] An object of the present application is to provide a technology capable of improving the quality of a GaN layer formed on a base substrate.

[0009] Solution for solving the problem

[0010] According to one embodiment of the present application, a Group III nitride laminated substrate is provided, which has:

[0011] a base substrate;

[0012] a first layer formed on the aforementioned base substrate and composed of aluminum nitride; and

[0013] a second layer formed on the aforementioned first layer and composed of gallium nitride,

[0014] the aforementioned second layer has a thickness of 10 μm or less, a half value width of (0002) diffraction based on X-ray rocking curve measurement is 100 seconds or less, and a half value width of (10-12) diffraction based on X-ray rocking curve measurement is 200 seconds or less.

[0015] According to another embodiment of the present application, a semiconductor element is provided,

[0016] It has at least a part of the aforementioned second layer as an active layer.

[0017] According to another aspect of the present application, there is provided a Group III nitride laminated substrate having:

[0018] a base substrate; and

[0019] a first layer formed on the aforementioned base substrate and composed of aluminum nitride,

[0020] the aforementioned first layer has a surface used as a base for growing a second layer,

[0021] the second layer is composed of gallium nitride, has a thickness of 10 μm or less, a half-value width of (0002) diffraction based on X-ray rocking curve measurement of 100 seconds or less, and a half-value width of (10-12) diffraction based on X-ray rocking curve measurement of 200 seconds or less.

[0022] Effects of the invention

[0023] There is provided a technology capable of improving the quality of a GaN layer formed on a base substrate. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is an exemplary schematic cross-sectional view of a wafer of the first embodiment of the present application.

[0025] Figure 2 is a flowchart showing an example of a manufacturing method of the wafer of the first embodiment.

[0026] Figure 3 is an exemplary schematic cross-sectional view of a wafer of the second embodiment.

[0027] Figure 4 is a schematic cross-sectional view showing a first example of a semiconductor element of the second embodiment.

[0028] Figure 5 is a schematic cross-sectional view showing a second example of a semiconductor element of the second embodiment.

[0029] Figure 6 is a flowchart showing an example of a manufacturing method of a semiconductor element of the second embodiment.

[0030] Figure 7 is a graph showing the crystallinity of a GaN layer of the example.

[0031] Figure 8 is a graph showing the surface flatness of a GaN layer of the example.

[0032] Figure 9is a graph showing in-plane deviation of the thickness of the GaN layer of the example.

[0033] Figure 10 is a graph showing in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer of the example.

[0034] Figure 11 is a graph showing warping of the wafer having the GaN layer of the example.

[0035] Figure 12 is a graph showing crystallinity of the GaN layer of the comparative example.

[0036] Figure 13 is a graph showing surface flatness of the GaN layer of the comparative example.

[0037] Reference signs

[0038] 10…base substrate, 11…main surface (of the base substrate), 20…AlN layer, 21…surface (of the AlN layer), 30…GaN layer, 31…surface (of the GaN layer), 40…group III nitride layer, 41…light emitting layer, 42…p-type layer, 50…electrode, 90…group III nitride layer-stacked substrate, 100…group III nitride layer-stacked substrate, 150…group III nitride layer-stacked substrate, 200…semiconductor element DETAILED DESCRIPTION

[0039] <First Embodiment>

[0040] A group III nitride layer-stacked substrate 100 (hereinafter also referred to as a wafer 100) according to a first embodiment of the present application will be described. Figure 1 is an exemplary schematic cross-sectional view of the wafer 100. The wafer 100 has a base substrate 10, an AlN layer 20 composed of aluminum nitride (AlN), and a GaN layer 30 composed of gallium nitride (GaN). The wafer 100 of the present embodiment is characterized in that, even if thin, the GaN layer 30 grown on top of the AlN layer 20 has high quality, as will be described in detail below.

[0041] In the present embodiment, as the base substrate 10, a sapphire substrate can be exemplified as preferable. As the sapphire substrate, a sapphire substrate having a surface, i.e., a main surface 11, tilted in the a-axis or m-axis direction in a range of 0.1° or more and 0.6° or less from the C-plane is preferably used. Note that the sapphire substrate can be a flat substrate having a flat main surface 11, which does not belong to a patterned sapphire substrate (PSS).

[0042] In order to improve the productivity when manufacturing semiconductor elements using the wafer 100, as the base substrate 10, a large-area base substrate capable of forming a plurality of semiconductor elements in-plane is preferably used. The diameter of the sapphire substrate used as the base substrate 10 is preferably 2 inches (50.8 mm) or more, more preferably 4 inches (100 mm) or more, and further preferably 6 inches (150 mm) or more. The thickness of the sapphire substrate having a diameter of 2 inches is, for example, 300 μm or more and 500 μm or less (typically, 430 μm), the thickness of the sapphire substrate having a diameter of 4 inches is, for example, 600 μm or more and 1000 μm or less (typically, 900 μm), and the thickness of the sapphire substrate having a diameter of 6 inches is, for example, 1000 μm or more and 1500 μm or less (typically, 1300 μm).

[0043] The AlN layer 20 is formed on the base substrate 10, and more specifically, is formed by hetero-epitaxial growth on the main surface 11 of the base substrate 10 (in contact with the main surface 11 and directly above the main surface 11). The AlN layer 20 functions as a nucleus generation layer for growing the GaN layer 30.

[0044] In order to improve the crystallinity of the AlN layer 20, the thickness of the AlN layer 20 is preferably 0.1 μm or more. Further, in order to suppress cracks generated in the AlN layer 20, the thickness of the AlN layer 20 is preferably 10 μm or less, and further, in order to reduce warping of the wafer 100, 1 μm or less is more preferable.

[0045] Specifically, the AlN layer 20 preferably has high crystallinity as follows. The half-value width of the X-ray rocking curve of the (0002) plane of the AlN layer 20 is preferably 100 seconds or less, and the half-value width of the X-ray rocking curve of the (10-12) plane of the AlN layer 20 is preferably 300 seconds or less. The surface 21 of the AlN layer 20 is preferably Al-polar. Note that, in the present specification, the "half-value width" means full width at half maximum (FWHM).

[0046] The GaN layer 30 is formed on the AlN layer 20, and more specifically, is formed by hetero-epitaxial growth on the surface 21 of the AlN layer 20 (in contact with the surface 21 and directly above the surface 21). In other words, the GaN layer 30 is formed on the base substrate 10 with the AlN layer 20 interposed therebetween. The GaN layer 30 of the present embodiment has high quality as described below.

[0047] (Crystallinity of GaN layer)

[0048] The GaN layer 30 exhibits high crystallinity. Specifically, the GaN layer 30 has a thickness of less than 10 μm, a half-width of less than 100 seconds for the (0002) plane as determined by X-ray rocking curves, and a half-width of less than 200 seconds for the (10-12) plane as determined by X-ray rocking curves.

[0049] Previously, when forming a GaN layer with improved crystallinity on a sapphire substrate with an AlN layer in between, operations involving the growth of a GaN layer thicker than approximately 10 μm were performed. This is because the thicker the GaN layer, the better its crystallinity. However, when forming a GaN layer using conventional methods, even with a 10 μm thick GaN layer, the half-width at half-maximum (WHM) of the X-ray rocking curve on the (0002) plane of the GaN layer only decreases to about 200 seconds, and the WHM of the X-ray rocking curve on the (10-12) plane of the GaN layer only decreases to about 300 seconds (see reference). Figure 12 ).

[0050] In contrast, the GaN layer 30 of this embodiment, even with a thickness of 10 μm or less, exhibits high crystallinity with a half-width of 100 seconds or less for the X-ray rocking curve of the (0002) plane and a half-width of 200 seconds or less for the X-ray rocking curve of the (10-12) plane (see reference). Figure 7 ).

[0051] It should be noted that regarding the crystallinity of GaN layer 30, there is a tendency that the thinner the GaN layer 30, the lower the crystallinity; in other words, there is a tendency that the thicker the GaN layer 30, the higher the crystallinity. By making the thickness of GaN layer 30 ≥ 0.8 μm, it is possible to make the half-width of the (0002) plane ≤ 100 s and the half-width of the (10-12) plane ≤ 200 s (refer to...). Figure 7 Furthermore, by making the thickness of the GaN layer 30 1 μm or more, the half-width of the (0002) plane can be made 80 seconds or less, and the half-width of the (10-12) plane can be made 180 seconds or less. Furthermore, by making the thickness of the GaN layer 30 1.5 μm or more, the half-width of the (0002) plane can be made 70 seconds or less, and the half-width of the (10-12) plane can be made 170 seconds or less.

[0052] (Surface flatness of GaN layer)

[0053] The GaN layer 30 exhibits high surface flatness. Specifically, the surface 31 of the GaN layer 30 preferably has a surface roughness of less than 0.5 nm, more preferably less than 0.4 nm, based on the root mean square (rms) value obtained by atomic force microscopy (AFM) of a 5 μm square area (see reference). Figure 8 ).

[0054] Note that, regarding the surface flatness of the GaN layer 30, there is a tendency that the surface flatness deteriorates sharply if the GaN layer 30 is too thin. By making the thickness of the GaN layer 30 0.8 μm or more, the high surface flatness as described above can be obtained (see Figure 8 ).

[0055] (In-plane uniformity of film thickness of GaN layer)

[0056] The GaN layer 30 has high in-plane uniformity of film thickness. Specifically, when the thickness of the GaN layer 30 is 10 μm or less, the in-plane deviation of the thickness of the GaN layer 30 is 4% or less (see Figure 9 ). The in-plane deviation of the thickness of the GaN layer 30 is defined as follows. A square lattice is set at regular intervals (preferably, intervals of 1 mm or more and 2 mm or less) on the surface of a wafer that is the measurement target, and the film thickness of the GaN layer 30 is measured at each lattice point. As the method of measuring the film thickness of the GaN layer 30 at each point, a method based on cross-sectional observation using an electron microscope or the like, ellipsometry, or the like is preferably used. Note that, near the end surface of the wafer, it is often the case that the measurement result cannot be accurately obtained due to the influence of the bevel shape of the wafer end portion, the influence of diffuse reflection of light, or the like. In such a case, it is preferable to remove the measurement data obtained at measurement points arranged within about 1 to 3 mm from the wafer end portion from the calculation below. In this specification, the average value and the standard deviation are found for the film thickness measurement data after the lattice point intervals are set to 1 mm and the measurement data in a region within 2 mm from the outer periphery of the wafer is removed, and the value (%) obtained by dividing the standard deviation by the average value is taken as the in-plane deviation of the thickness.

[0057] (In-plane uniformity of impurity concentration of GaN layer)

[0058] When an impurity is added to the GaN layer 30, the GaN layer 30 has high in-plane uniformity of impurity concentration. Specifically, when the thickness of the GaN layer 30 is 10 μm or less, the in-plane deviation of the impurity concentration in the GaN layer 30 is 4% or less (see Figure 10 ). Correspondingly, when an impurity such as an n-type impurity for controlling the carrier concentration is added to the GaN layer 30, the in-plane deviation of the carrier concentration can be made 4% or less (see Figure 10 ).

[0059] The in-plane deviation of the impurity concentration and the in-plane deviation of the carrier concentration in the GaN layer 30 are respectively defined as follows. The measurement of the impurity concentration generally uses secondary ion mass spectrometry (SIMS). Furthermore, the measurement of the carrier concentration generally uses capacitance-voltage measurement (CV measurement), hole measurement, or the like. In the measurement of the impurity concentration and the measurement of the carrier concentration, an orthogonal coordinate passing through the center of the wafer is set on the surface of the wafer that is the measurement target, and measurement is performed on this coordinate axis. One axis of the orthogonal coordinate preferably coincides with the off direction of the wafer. In this specification, for the SIMS measurement data measured at intervals of 1 cm on this orthogonal coordinate axis, the average value and the standard deviation are found, and the value (%) obtained by dividing the standard deviation by the average value is taken as the in-plane deviation of the impurity concentration. Furthermore, for the CV measurement data or the hole measurement data measured at intervals of 1 cm on this orthogonal coordinate axis, the average value and the standard deviation are found, and the value (%) obtained by dividing the standard deviation by the average value is taken as the in-plane deviation of the carrier concentration. In the measurement of the impurity concentration and the measurement of the carrier concentration, as with the measurement of the film thickness, in the case where the measurement points are arranged within 2 mm from the outer periphery of the wafer, the measurement data obtained at the measurement points are removed from the above calculation. Note that, although a method of finding the deviation of the impurity concentration and the deviation of the carrier concentration by directly measuring the impurity concentration and the carrier concentration, respectively, is described, in the case where an impurity (conductive impurity) for controlling the carrier concentration is added, the deviation of the carrier concentration can be estimated from the deviation of the impurity concentration, and conversely, the deviation of the impurity concentration can be estimated from the deviation of the carrier concentration.

[0060] As described above, the GaN layer 30 of the present embodiment has high quality in that it has at least one of high crystallinity, high surface flatness, high in-plane uniformity of film thickness, and high in-plane uniformity of impurity concentration (carrier concentration), preferably two or more of these, more preferably three or more of these, and further preferably all four of these.

[0061] (Warping of the wafer)

[0062] The wafer 100 warps due to the difference in the coefficient of thermal expansion between the base substrate 10 (in this example, a sapphire substrate) and the GaN layer 30 and the like stacked on the base substrate 10. The thicker the GaN layer 30, the greater the warping of the wafer 100. When a plurality of semiconductor elements are manufactured from the wafer 100, in order to suppress a decrease in the lithography precision and the like caused by the warping, it is preferable that the warping not be too large.

[0063] In the wafer 100 of the present embodiment, by making the thickness of the GaN layer 30 10 μm or less, the warping of the wafer 100 can be made, for example, 140 μm or less (see FIG. 6). In the case where the thickness of the GaN layer 30 is 10 μm or less, the warping of the wafer 100 is 140 μm or less, and thus the warping of the wafer 100 can be suppressed. Figure 11). It is preferable to appropriately select the diameter and thickness of the base substrate 10 so that warping is suppressed like this. As the diameter and thickness when a sapphire substrate is used as the base substrate 10, the above-mentioned values can be exemplified.

[0064] Warping of the wafer 100 is defined as follows. The wafer to be measured is placed on a flat plate or stage, and the distance (height) of the surface of the wafer from the surface of the plate or stage is measured. An orthogonal coordinate passing through the center of the wafer is set on the surface of the wafer, and the measurement is performed on this coordinate axis. One axis of the orthogonal coordinate is preferably coincident with the direction of deviation of the wafer. In this specification, the above-mentioned height measurement is performed at intervals of 1 mm on this orthogonal coordinate axis. As with the previous film thickness measurement, when the measurement points are arranged within 2 mm of the outer periphery of the wafer, the measurement data obtained at these measurement points is omitted from the following calculation. A straight line passing through the outermost points on each axis is taken as a new reference line, and the distance between the measurement point on this axis that is farthest from the reference line and the reference line is defined as the warping with respect to this axis. This measurement is performed on both of the orthogonal axes, and the average of the two warpings obtained is taken as the warping of the wafer.

[0065] Next, the manufacturing method of the wafer 100 will be described. In the first embodiment, a case where the wafer 100 is manufactured in the form of a GaN template in which the outermost surface is a GaN layer 30, and a case where a semiconductor element is manufactured using the wafer (GaN template) 100 will be exemplified.

[0066] Figure 2 is a flowchart showing an example of the manufacturing method of the wafer 100 of the first embodiment. The manufacturing method of this example has a substrate preparation step S10, an AlN layer formation step S20, a heat treatment step S30, and a GaN layer formation step S40.

[0067] First, in the substrate preparation step S10, a base substrate 10 is prepared. As the base substrate 10, a sapphire substrate is preferably used. Next, in the AlN layer formation step S20, an AlN layer 20 is formed by growing AlN on the main surface 11 of the base substrate 10. As the growth method of the AlN layer 20, for example, hydride vapor phase epitaxy (HVPE) can be used. As the aluminum (Al) source gas, for example, aluminum monochloride (AlCl) gas can be used, and in addition, for example, aluminum trichloride (AlCl3) gas can be used. As the nitrogen (N) source gas, for example, ammonia (NH3) gas can be used. These source gases can be mixed and supplied with a carrier gas using hydrogen (H2 gas), nitrogen (N2 gas), or a mixed gas thereof.

[0068] As the growth conditions of the AlN layer 20, the following conditions can be exemplified. Note that the V / III ratio refers to the ratio of the supply amount of the Group V (N) source gas to the supply amount of the Group III (Al) source gas.

[0069] Growth temperature: 900 to 1300°C

[0070] V / III ratio: 0.2 to 200

[0071] Growth rate: 0.5 to 3000 nm / min

[0072] In order to prevent AlN from adhering to the nozzle of the gas supply pipe that introduces various gases into the growth chamber of the HVPE device, hydrogen chloride (HCl) gas can be circulated. As the supply amount of HCl gas, an amount that is 0.1 to 100 times the amount of AlCl gas or AlCl3 gas can be exemplified.

[0073] In the AlN layer forming step S20, by controlling the crystal growth conditions, annealing treatment, and the like, an AlN layer 20 having high crystallinity as described above can be obtained. Specifically, by appropriately adjusting the growth conditions (temperature, growth rate, raw material supply amount, and the like) at the time of growth of the AlN layer 20, for example, the crystallinity of the AlN layer 20 can be improved. Further, after the AlN layer 20 is grown, for example, annealing treatment is performed at a temperature of 1400°C or higher and 1700°C or lower in an atmosphere containing N2 gas, whereby the crystallinity of the AlN layer 20 can be improved.

[0074] Note that, while this operation can improve the crystallinity of the AlN layer 20, there is a tendency for a compressive strain caused by a difference in lattice constant and a difference in thermal expansion coefficient between the substrate substrate 10 (in this case, a sapphire substrate) to be introduced in the AlN layer 20 formed along a direction parallel to the surface 21 (e.g., the a-axis direction).

[0075] Next, in the heat treatment step S30, the AlN layer 20 is subjected to heat treatment. The heat treatment step S30 is performed in an atmosphere containing H2 gas (hereinafter referred to as a hydrogen-containing atmosphere). The H2 gas can be supplied mixed with a non-active gas such as N2 gas or argon gas (Ar gas). This heat treatment can be performed in the growth chamber of the HVPE device or in another heat treatment device.

[0076] By performing this heat treatment in a hydrogen-containing atmosphere, the surface 21 can be modified so that the compressive strain introduced into the surface 21 of the AlN layer 20 is alleviated. The mechanism by which the compressive strain is alleviated is not yet clear, but it is believed that the mechanism is that, in the heat treatment step S30, hydrogen is present in the atmosphere, and thus the occurrence of point defects in the AlN crystal is promoted. It is believed that the nitrogen atoms in the AlN bond with hydrogen at the surface, form ammonia, and are detached, thereby forming a large number of nitrogen vacancies in the AlN, which function as voids of atomic sites, and thus the strain of the GaN layer 30 grown on the AlN layer 20 can be alleviated.

[0077] Further, the heat treatment step S30 is started in an atmosphere substantially free of ammonia. Specifically, for example, it is performed without supplying NH3gas. When the heat treatment is performed in an atmosphere containing ammonia, formation of the above-mentioned point defects (nitrogen vacancies) is suppressed, and thus it is difficult to relax the strain of the GaN layer 30. Further, when the heat treatment is performed in the growth chamber of the HVPE apparatus, the NH3gas introduced in the AlN layer formation step S20 can remain in the growth chamber, and thus it is preferable to exhaust (or replace) the gas in the growth chamber before performing the heat treatment. Note that, in the present specification, substantially free of ammonia means, for example, that the partial pressure of NH3gas in the growth chamber is less than 1% relative to the total pressure. Note that, as described above, it is considered that, in the heat treatment step S30, the nitrogen atoms in the AlN are bonded to hydrogen on the surface and are released as ammonia, but the ammonia generated by the release is extremely small. Thus, the partial pressure of NH3gas in the growth chamber does not become 1% or more of the total pressure due to this ammonia. In this way, the heat treatment step S30 is performed in an atmosphere substantially free of ammonia.

[0078] The heat treatment step S30 is preferably performed at a temperature (hereinafter also referred to as heat treatment temperature) of, for example, 900°C or higher and 1300°C or lower. When the heat treatment temperature is less than 900°C, the surface 21 is difficult to modify. In contrast, by making the heat treatment temperature 900°C or higher, the surface 21 can be easily modified. On the other hand, when the heat treatment temperature exceeds 1300°C, there is a possibility that the surface 21 is decomposed. In contrast, by making the heat treatment temperature 1300°C or lower, decomposition of the surface 21 can be suppressed.

[0079] The heat treatment step S30 is preferably performed for a time (hereinafter also referred to as heat treatment time) of, for example, 10 minutes or longer and 120 minutes or shorter. When the heat treatment time is less than 10 minutes, the surface 21 is difficult to modify. In contrast, by making the heat treatment time 10 minutes or longer, the surface 21 can be easily modified. On the other hand, when the heat treatment time exceeds 120 minutes, there is a possibility that the flatness of the surface 21 is reduced. In contrast, by making the heat treatment time 120 minutes or shorter, reduction in the flatness of the surface 21 can be suppressed. More preferably, the heat treatment time is, for example, 30 minutes or longer and 90 minutes or shorter.

[0080] Next, in the GaN layer formation step S40, a GaN layer 30 is formed by growing GaN on the surface 21 of the AlN layer 20. As a method of growing the GaN layer 30, for example, the HVPE method can be used. As a gallium (Ga) source gas, for example, gallium monochloride (GaCl) gas can be used. As a nitrogen (N) source gas, for example, NH3gas can be used. These source gases can be mixed with a carrier gas using H2gas, N2gas, or a mixed gas thereof and supplied.

[0081] As the growth conditions of the GaN layer 30, the following conditions can be exemplified.

[0082] Growth temperature: 900 to 1000°C

[0083] V / III ratio: 1 to 1000

[0084] Growth rate: 100 to 2000 nm / min

[0085] By the AlN layer formation process S20 and the heat treatment process S30, the AlN layer 20 having the above-described high crystallinity and having the surface 21 modified as above can be obtained. In the GaN layer formation process S40, by forming the GaN layer 30 on such an AlN layer 20, the GaN layer 30 having the above-described high quality can be obtained.

[0086] In the GaN layer formation process S40, the GaN layer 30 is formed at a low temperature of 1000°C or lower (preferably 950°C or lower). Thereby, compared to the case where the GaN layer 30 is formed at a high temperature exceeding 1000°C, the in-plane direction temperature deviation of the GaN layer 30 at the time of growth is easily suppressed, and thus the in-plane uniformity of the film thickness of the GaN layer 30 can be improved. Note that in the present embodiment, the crystallinity of the AlN layer 20 which becomes the growth substrate of the GaN layer 30 is high, and thus even if the GaN layer 30 is grown at a low temperature of 1000°C or lower, the GaN layer 30 having the above-described high crystallinity can be obtained.

[0087] At the time of growth of the GaN layer 30, impurities can be added as needed. By suppressing the in-plane direction temperature deviation of the GaN layer 30 at the time of growth, the in-plane uniformity of the impurity concentration in the GaN layer 30 can be improved. If it is a case where an impurity such as an n-type impurity for controlling the carrier concentration is added to the GaN layer 30, the in-plane uniformity of the carrier concentration in the GaN layer 30 can be improved. Note that a stacked structure in which, for example, a lower side (substrate substrate side) portion in the GaN layer 30 is not doped and an upper side portion in the GaN layer 30 is doped with an impurity can be adopted as needed.

[0088] In order to improve the crystallinity of the GaN layer 30 and improve the surface flatness of the GaN layer 30, the thickness of the GaN layer 30 is preferably 0.8 μm or more. The upper limit of the thickness of the GaN layer 30 can be appropriately selected, and for example, in order not to make the warpage of the wafer 100 too large, it is preferably 10 μm or less.

[0089] The wafer (GaN template) 100 can be manufactured by the above operation. Thereafter, various processes such as a process of forming other Group III nitride layers on the GaN layer 30, a process of forming electrodes, and the like are performed in accordance with the structure of the semiconductor element to be manufactured, whereby the semiconductor element is manufactured. Further, the division of each semiconductor element is further performed.

[0090] <Second Embodiment>

[0091] Next, the semiconductor element 200 of the second embodiment will be described. In the second embodiment, a manner of manufacturing a Group III nitride layer-stacked substrate 90 (hereinafter also referred to as a wafer 90) in the form of an AlN template in which the outermost surface is an AlN layer 20, and manufacturing the semiconductor element 200 using the wafer 90 is exemplified.

[0092] Figure 3 is an illustrative schematic cross-sectional view of the wafer 90. The wafer 90 has the base substrate 10 and the AlN layer 20. The wafer (AlN template) 90 can also be regarded as a stacked substrate up to the AlN layer 20 of the wafer (GaN template) 100 described in the first embodiment.

[0093] If described more specifically, the wafer 90 is a stacked substrate in which the AlN layer 20 has the above-described high crystallinity and the surface 21 of the AlN layer 20 is modified by performing the above-described heat treatment. Thus, the wafer 90 is configured as an AlN template capable of forming the above-described high-quality GaN layer 30 on the AlN layer 20. In other words, the wafer 90 is a Group III nitride stacked substrate in which the AlN layer 20 has the surface 21 used as a base for growing the GaN layer 30 having a thickness of 10 μm or less and a half-value width of (0002) diffraction based on X-ray rocking curve measurement of 100 seconds or less and a half-value width of (10-12) diffraction based on X-ray rocking curve measurement of 200 seconds or less.

[0094] Figure 4 and Figure 5 are schematic cross-sectional views each representing a first example and a second example of the semiconductor element 200 of the second embodiment. In order to improve the productivity of the semiconductor element 200, a plurality of semiconductor elements 200 are formed on the wafer 100, and each semiconductor element 200 is divided. Figure 4 and Figure 5 each exemplify one semiconductor element 200 that is divided.

[0095] As the semiconductor element 200 of the first example, a light emitting diode (LED) is exemplified. Figure 4is a schematic cross-sectional view showing a first example of a semiconductor element 200 (hereinafter also referred to as LED 200). The LED 200 has a base substrate 10, an AlN layer 20, a GaN layer 30 which is an n-type layer to which an n-type impurity is added, a light emitting layer 41 which is composed of a Group III nitride, a p-type layer 42 which is composed of a Group III nitride and to which a p-type impurity is added, an n-side electrode 51 which is electrically connected to the GaN layer 30, and a p-side electrode 52 which is electrically connected to the p-type layer 42. The light emitting layer 41 and the p-type layer 42 are collectively referred to as a Group III nitride layer 40. Further, the n-side electrode 51 and the p-side electrode 52 are collectively referred to as an electrode 50.

[0096] The light emitting layer 41 is composed of, for example, a multiple quantum well structure in which an indium gallium nitride (InGaN) well layer and a GaN barrier layer are alternately stacked. The p-type layer 42 is composed of, for example, a stack of a p-type aluminum gallium nitride (AlGaN) clad layer and a p-type GaN contact layer.

[0097] As a second example of the semiconductor element 200, a high electron mobility transistor (HEMT) is exemplified. Figure 5 is a schematic cross-sectional view showing a second example of the semiconductor element 200 (hereinafter also referred to as HEMT 200). The HEMT 200 has a base substrate 10, an AlN layer 20, a GaN layer 30 which is a channel layer, an AlGaN layer 40 which is a barrier layer, and a source electrode 51, a gate electrode 52, and a drain electrode 53 which are formed on the AlGaN layer 40. The AlGaN layer 40 is also referred to as a Group III nitride layer 40. Further, the source electrode 51, the gate electrode 52, and the drain electrode 53 are collectively referred to as an electrode 50.

[0098] In order to improve the withstand voltage, a high-resistance impurity such as iron or carbon can be added to a lower layer portion among the GaN layer 30 possessed by the HEMT 200.

[0099] In both the first example and the second example, the GaN layer 30 possessed by the semiconductor element 200 has high quality even though the GaN layer 30 is thin (even if it is thicker, it is 10 μm or less). Thus, effects such as the following can be obtained.

[0100] In the GaN layer 30 possessed by the semiconductor element 200, the GaN layer 30 has high crystallinity and high surface flatness even though the GaN layer 30 is thin. Thus, the crystallinity of the Group III nitride layer 40 grown on the GaN layer 30 can be improved, and therefore, the performance of the semiconductor element 200 can be improved.

[0101] In both the first example and the second example, the GaN layer 30 possessed by the semiconductor element 200 has high in-plane uniformity of film thickness. Thus, a performance deviation between the plurality of semiconductor elements 200 formed on the wafer 100 can be suppressed.

[0102] When the GaN layer 30 of the semiconductor element 200 has an impurity added thereto, specifically, when the GaN layer 30 of the LED 200 of the first example has an n-type impurity added thereto, or when the GaN layer 30 of the HEMT 200 of the second example has a high-resistance impurity added thereto, the in-plane uniformity of the impurity concentration is high. Thus, it is possible to suppress a performance variation among the plurality of semiconductor elements 200 formed on the wafer 100.

[0103] The GaN layer 30 of the semiconductor element 200 has high quality, and thus can be used as at least a part of an operation layer of an operation current of the semiconductor element 200, specifically, can be used as an n-type layer of the LED 200 of the first example, or can be used as a channel layer of the HEMT 200 of the second example. The GaN layer 30 has high quality even when an impurity such as an n-type impurity is added thereto, and thus can be used as an operation layer of the semiconductor element 200.

[0104] The semiconductor element 200 is formed using the Group III nitride layered substrate 150 (hereinafter also referred to as a wafer 150) in which the base substrate 10, the AlN layer 20, the GaN layer 30, and the Group III nitride layer 40 are layered, in both the first example and the second example. When the plurality of semiconductor elements 200 are formed on the wafer 150, in order to suppress a decrease in lithography precision or the like caused by warping of the wafer 150 (in other words, warping of the wafer 100), it is preferable that the warping is not too large. The GaN layer 30 of the semiconductor element 200 of the present embodiment has high crystallinity even when it is thin. Thus, it is possible to suppress the warping of the wafer 150 by thinning the GaN layer 30, and thus it is possible to suppress a decrease in lithography precision or the like caused by the warping. In other words, it is possible to suppress a performance variation among the plurality of semiconductor elements 200 formed on the wafer 100 (the wafer 150).

[0105] Note that, for each of the LED 200 of the first example and the HEMT 200 of the second example, the structure of the Group III nitride layer 40 and the structure of the electrode 50 formed on the GaN layer 30 can be appropriately changed as needed.

[0106] Note that, as the semiconductor element 200 manufactured using the wafer 90 (in other words, manufactured using the wafer 100, or manufactured using the wafer 150), an LED and a HEMT are exemplified, and other kinds of semiconductor elements can be manufactured as needed.

[0107] Note that, as the semiconductor element 200 manufactured using the wafer 90 (in other words, manufactured using the wafer 100 or manufactured using the wafer 150), in the case of manufacturing an LED or the like, the final element structure can be a structure in which a support substrate (circuit substrate) is provided on the upper side of the GaN layer 30 and the base substrate 10 (and the AlN layer 20) is removed. In this case, the semiconductor element 200 also has the GaN layer 30 as at least a part of the active layer.

[0108] Next, the manufacturing method of the semiconductor element 200 will be described. In the second embodiment, a method in which the wafer 90 is manufactured in the form of an AlN template in which the outermost surface is the AlN layer 20, and the semiconductor element is manufactured using the wafer (AlN template) 90 is exemplified.

[0109] Figure 6 is a flowchart showing an example of the manufacturing method of the semiconductor element 200 of the second embodiment. The manufacturing method of this example has the following steps: a substrate preparation step S10, an AlN layer formation step S20, a heat treatment step S30, a GaN layer formation step S40, a Group III nitride layer formation step S50, and an electrode formation step S60.

[0110] In the first embodiment, a method in which the formation of the AlN layer 20 in the AlN layer formation step S20 and the heat treatment in the heat treatment step S30 are continued until the formation of the GaN layer 30 in the GaN layer formation step S40, and thus the wafer 100 as a GaN template is manufactured in the form of a series of crystal growth (for example, crystal growth based on the HVPE method) is exemplified.

[0111] In the second embodiment, a method in which, after the wafer 90 as an AlN template is manufactured up to the heat treatment in the heat treatment step S30, the formation of the GaN layer 30 in the GaN layer formation step S40 and the formation of the Group III nitride layer 40 in the Group III nitride layer formation step S50 are performed in the form of a series of crystal growth (for example, crystal growth based on the metal organic vapor phase epitaxy (MOVPE) method), and thus the wafer 150 for forming the semiconductor element 200 is manufactured is exemplified. Note that, in the first embodiment, the wafer 100 can also be manufactured by, for example, performing the formation of the AlN layer 20 in the AlN layer formation step S20 using the HVPE method, and performing the formation of the GaN layer 30 in the GaN layer formation step S40 using the MOVPE method.

[0112] The substrate preparation step S10, the AlN layer formation step S20, and the heat treatment step S30 are the same as in the first embodiment. By performing up to the heat treatment step S30, the wafer (AlN template) 90 is manufactured.

[0113] Next, in the GaN layer forming step S40, a GaN layer 30 is formed by growing GaN on the AlN layer 20 of the wafer 90. As a growth method of the GaN layer 30, for example, a MOVPE method can be used. As a gallium (Ga) source gas, for example, a trimethyl gallium (Ga(CH3)3, TMG) gas can be used. As a nitrogen (N) source gas, for example, an NH3gas can be used. These source gases can be mixed and supplied with a carrier gas using an H2gas, an N2gas, or a mixed gas thereof. At the time of growth of the GaN layer 30, impurities can be added according to the structure of the semiconductor element 200 to be manufactured. The impurities can be added to a part of the thickness of the GaN layer 30 as needed. The GaN layer 30 having high quality can be obtained as in the first embodiment. In the second embodiment, at the stage until the GaN layer forming step S40 is performed, a wafer 100 as an intermediate structure is obtained as shown in FIG. 2. Figure 1

[0114] As the growth conditions of the GaN layer 30, the following conditions can be exemplified.

[0115] Growth temperature: 900 to 1000°C

[0116] V / III ratio: 500 to 8000

[0117] Growth rate: 10 to 100 nm / min

[0118] Next, in the Group III nitride layer forming step S50, a Group III nitride layer 40 is formed by growing a Group III nitride on the GaN layer 30. The wafer 150 is formed by such an operation. By forming the Group III nitride layer 40 on the GaN layer 30 having high quality, the quality of the Group III nitride layer 40 can be improved, and the performance of the semiconductor element 200 can be improved.

[0119] The layer constitution of the Group III nitride layer 40 can be appropriately selected according to the structure of the semiconductor element 200 to be manufactured. If more specifically described, the Group III nitride layer 40 is constituted by one layer or a plurality of layers using a Group III nitride, and each layer constituting the Group III nitride layer 40 can contain at least one of, for example, aluminum (Al), gallium (Ga), and indium (In) as a Group III element. The composition of the each layer can be appropriately selected according to the structure of the semiconductor element 200.

[0120] ​As a method of growing the Group III nitride layer 40, for example, a MOVPE method can be used. As an Al source gas, for example, a trimethylaluminum (Al(CH3)3, TMA) gas can be used. As a Ga source gas, for example, a trimethylgallium (Ga(CH3)3, TMG) gas can be used. As an In source gas, for example, a trimethylindium (In(CH3)3, TMG) gas can be used. As a nitrogen (N) source gas, for example, an NH3gas can be used. These source gases can be mixed and supplied with a carrier gas using an H2gas, an N2gas, or a mixed gas thereof. The amount of supply of the source gases is appropriately adjusted according to the composition of each layer constituting the Group III nitride layer 40. During the growth of each layer of the Group III nitride layer 40, impurities can be added according to the structure of the semiconductor element 200.

[0121] Next, in the electrode forming step S60, one or more electrodes 50 are formed according to the structure of the semiconductor element 200. Note that according to the structure of the semiconductor element 200, before the electrodes 50 are formed, a structure such as a recess can be formed in the wafer 150. The semiconductor element 200 is manufactured by the above operations. Thereafter, the plurality of semiconductor elements 200 formed in the wafer 150 are divided into individual semiconductor elements 200.

[0122] <EMBODIMENT>

[0123] Next, the results of experiments on the embodiments of the present application will be described. A wafer 100 (hereinafter also simply referred to as a wafer) having a base substrate 10 (hereinafter also simply referred to as a base substrate), an AlN layer 20 (hereinafter also simply referred to as an AlN layer), and a GaN layer 30 (hereinafter also simply referred to as a GaN layer) was manufactured by the method described in the first embodiment. By changing the thickness of the GaN layer, how the crystallinity of the GaN layer, the surface flatness of the GaN layer, the in-plane uniformity of the film thickness of the GaN layer, the in-plane uniformity of the impurity concentration (carrier concentration) in the GaN layer, and the warpage of the wafer respectively changed were investigated.

[0124] As the base substrate, a C-plane sapphire substrate having a diameter of 4 inches and a thickness of 900 μm was used. The thickness of the AlN layer was set to 0.35 μm. In the GaN layer, silicon (Si) was added as an n-type impurity at a concentration of 3 x 1018cm-3 (over the entire thickness). 18 cm -3 The thickness of the GaN layer was changed to 0.4 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 2 μm, 3 μm, 5 μm, 7 μm, 9 μm, and 10 μm.

[0125] Further, a comparative example was conducted. In the comparative example, a method of forming a conventional low-temperature grown GaN buffer layer on a sapphire substrate was employed. Specifically, the sapphire substrate was introduced into a MOVPE apparatus, the apparatus was replaced with nitrogen gas, and then the substrate temperature was set to 1100°C, and surface cleaning was performed for 10 minutes in a hydrogen atmosphere. Next, the substrate temperature was set to a low temperature of 550°C, TMG and ammonia were introduced into the apparatus, and a GaN buffer layer was grown to a thickness of 30 nm. Thereafter, the substrate temperature was set to 1050°C while ammonia was flowed, and a GaN layer 30 identical to that of the example was grown. The growth temperature of the GaN layer 30 in the comparative example was higher than that of the example because, in the method of the comparative example, it was difficult to obtain a GaN layer 30 of sufficient quality.

[0126] (Crystallinity of GaN layer)

[0127] Figure 7 is a graph showing the crystallinity of the GaN layer of the example, Figure 12 is a graph showing the crystallinity of the GaN layer of the comparative example. As the crystallinity, the half-value width of (0002) diffraction measured based on an X-ray rocking curve and the half-value width of (10-12) diffraction measured based on an X-ray rocking curve were measured. In Figure 7 and Figure 12 In the graphs of

[0128] Both the example and the comparative example had the same tendency that the thicker the GaN layer, the smaller the half-value width of X-ray diffraction, in other words, the thicker the GaN layer, the better the crystallinity, but in the comparative example Figure 12 even when the GaN layer was thickened to 10 μm, the half-value width of the (0002) plane was only reduced to around 190 seconds and 200 seconds, and the half-value width of the (10-12) plane was only reduced to around 290 seconds and 300 seconds.

[0129] On the other hand, in the example Figure 7 even when the thickness of the GaN layer was as thin as 0.8 μm, the half-value width of the (0002) plane was 95 seconds, which was below 100 seconds, and the half-value width of the (10-12) plane was 190 seconds, which was below 200 seconds. In the example, by making the thickness of the GaN layer 0.8 μm or more, even when the thickness of the GaN layer was 10 μm or less, the half-value width of the (0002) plane was made to be 100 seconds or less, and the half-value width of the (10-12) plane was made to be 200 seconds or less. In the example, when the GaN layer was further thickened to 10 μm, the half-value width of the (0002) plane was reduced to 55 seconds, which was around 50 seconds, and the half-value width of the (10-12) plane was reduced to 105 seconds, which was around 100 seconds.

[0130] Note that, as a measured value of the thickness of the GaN layer of the example in the range of 10 μm or less, the minimum value of the half-value width of the (0002) plane was 53 seconds when the thickness of the GaN layer was 9 μm, and the minimum value of the half-value width of the (10-12) plane was 105 seconds when the thickness of the GaN layer was 10 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 50 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 100 seconds can be cited.

[0131] The crystallinity of the GaN layer of the example tends to greatly increase up to the thickness of the GaN layer is thickened to about 1.5 μm. When the thickness of the GaN layer was 1 μm, the half-value width of the (0002) plane was 76 seconds, which was 80 seconds or less, and the half-value width of the (10-12) plane was 175 seconds, which was 180 seconds or less. By making the thickness of the GaN layer 1 μm or more, the half-value width of the (0002) plane can be made 80 seconds or less, and the half-value width of the (10-12) plane can be made 180 seconds or less. Further, when the thickness of the GaN layer was 1.5 μm, the half-value width of the (0002) plane became 68 seconds and 70 seconds or less, and the half-value width of the (10-12) plane was 160 seconds, which was 170 seconds or less. By making the thickness of the GaN layer 1.5 μm or more, the half-value width of the (0002) plane can be made 70 seconds or less, and the half-value width of the (10-12) plane can be made 170 seconds or less.

[0132] The GaN layer of the example shows the above-described high crystallinity even if impurities are added (even if, for example, impurities are added at a concentration of, for example, 1 x 10 16 cm -3 or more, for example, 1 x 10 17 cm -3 or more, for example, 1 x 10 18 cm -3 or more. Thus, in the case where no impurities are added, it can be said that the high crystallinity equal to or higher than that degree is shown. Note that, in order to suppress the decrease in crystallinity, the concentration of the impurities added to the GaN layer is preferably set to, for example, 1 x 10 19 cm -3 or less.

[0133] (Surface planarity of GaN layer)

[0134] Figure 8 is a graph showing the surface planarity of the GaN layer of the example, Figure 13is a graph showing surface flatness of GaN layers of Comparative Examples. As the surface flatness, the rms value (hereinafter, also simply referred to as rms) of surface roughness was found by AFM measurement for a 5 μm square region of the surface of the GaN layer. In Figure 8 and Figure 13 , the horizontal axis represents the thickness of the GaN layer, and the vertical axis represents the rms.

[0135] It was observed that in both the Examples and the Comparative Examples, the rms sharply decreased until the GaN layer became a certain degree of thickness, and was substantially constant for a thickness of the degree or more. In the Comparative Example Figure 13 , the rms was 0.5 nm or less for a thickness of the GaN layer of 2 μm or more, but the rms was 3.1 nm for a thickness of the GaN layer of 1.5 μm, and the rms was 92 nm for a thickness of the GaN layer of 0.8 μm.

[0136] On the other hand, in the Example Figure 8 , the rms was 0.33 nm for a thickness of the GaN layer of 0.8 μm, and the rms was preferably 0.5 nm or less, and more preferably 0.4 nm or less, by making the thickness of the GaN layer 0.8 μm or more. The rms was 3 nm for a thickness of the GaN layer of 0.6 μm, and the rms was 10 nm for a thickness of the GaN layer of 0.4 μm.

[0137] Note that the minimum value of the rms was 0.21 nm for a thickness of the GaN layer of 1.2 μm, among the measured values of the thickness of the GaN layer in the range of 10 μm or less in the Example. As a reference level of the minimum value of the rms, for example, 0.2 nm can be cited.

[0138] As described above, the GaN layer of the Example has high crystallinity and high surface flatness compared to the GaN layer of the Comparative Example, and thus can be preferably used as a base layer for growing a Group III nitride layer.

[0139] (In-plane uniformity of film thickness of GaN layer)

[0140] Figure 9 is a graph showing the in-plane deviation of the thickness of the GaN layer of the Example. Figure 9 , the horizontal axis represents the thickness of the GaN layer, and the vertical axis represents the in-plane deviation of the thickness. The in-plane deviation of the thickness has a tendency to be smaller as the GaN layer is thinner. By making the thickness of the GaN layer 10 μm or less, the in-plane deviation of the thickness can be 4% or less.

[0141] Note that the minimum value of the in-plane deviation of the thickness of the GaN layer was 0.5% when the thickness of the GaN layer was 1 μm, in the case of the measured value of the thickness of the GaN layer of the embodiment in the range of 10 μm or less. As a reference level of the minimum value of the in-plane deviation of the thickness of the GaN layer, for example, 0.5% can be cited, and in addition, for example, 0.4% can be cited.

[0142] (In-plane uniformity of impurity concentration in GaN layer)

[0143] Figure 10 is a graph showing the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer of the embodiment. In the present embodiment, the in-plane deviation of the n-type carrier concentration in the GaN layer was measured, in which n-type impurities were added as impurities in the GaN layer. The in-plane deviation of the n-type carrier concentration in the GaN layer can also be interpreted as the in-plane deviation of the n-type impurity concentration in the GaN layer. Figure 10 In the graph, the horizontal axis represents the thickness of the GaN layer, and the vertical axis represents the deviation of the n-type carrier concentration, that is, the in-plane deviation of the n-type impurity concentration. The in-plane deviation of the impurity concentration (carrier concentration) has a tendency to be smaller as the GaN layer is thinner. By making the thickness of the GaN layer 10 μm or less, the in-plane deviation of the impurity concentration (carrier concentration) can be made 4% or less.

[0144] Note that the minimum value of the in-plane deviation of the impurity concentration (carrier concentration) was 0.54% when the thickness of the GaN layer was 1.2 μm, in the case of the measured value of the thickness of the GaN layer of the embodiment in the range of 10 μm or less (and 0.8 μm or more). As a reference level of the minimum value of the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer, for example, 0.5% can be cited, and in addition, for example, 0.4% can be cited.

[0145] (Warp of wafer)

[0146] Figure 11 is a graph showing the warp of the wafer having the GaN layer of the embodiment. Figure 11 In the graph, the horizontal axis represents the thickness of the GaN layer, and the vertical axis represents the warp of the wafer. The warp of the wafer has a tendency to be smaller as the GaN layer is thinner. By making the thickness of the GaN layer 10 μm or less, the warp of the wafer can be preferably 140 μm or less, and more preferably 135 μm or less.

[0147] Note that the minimum value of the warp of the wafer was 12 μm when the thickness of the GaN layer was 0.8 μm, in the case of the measured value of the thickness of the GaN layer of the embodiment in the range of 10 μm or less (and 0.8 μm or more). As a reference level of the minimum value of the warp of the wafer, for example, 10 μm can be cited.

[0148] The GaN layer and the wafer having the GaN layer of the embodiment also have the following characteristics. The crystallinity of the GaN layer has a tendency to decrease as the GaN layer is thinned, but on the other hand, the in-plane deviation of the thickness of the GaN layer, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer, and the warpage of the wafer are each reduced as the GaN layer is thinned (see Figures 9-11

[0149] For example, by making the thickness of the GaN layer 7 μm or less, the in-plane deviation of the thickness of the GaN layer is preferably 3.5% or less, more preferably 3% or less, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer is preferably 3.5% or less, more preferably 3% or less, and the warpage of the wafer is preferably 110 μm or less, more preferably 105 μm or less. Note that, as a measured value of the thickness of the GaN layer of the embodiment in the range of 7 μm or less, the minimum value of the half-value width of the (0002) plane is 55 seconds when the thickness of the GaN layer is 3 μm, and the minimum value of the half-value width of the (10-12) plane is 112 seconds when the thickness of the GaN layer is 7 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 50 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 105 seconds can be cited.

[0150] Further, for example, by making the thickness of the GaN layer 5 μm or less, the in-plane deviation of the thickness of the GaN layer is preferably 3% or less, more preferably 2.5% or less, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer is preferably 3% or less, more preferably 2.5% or less, and the warpage of the wafer is preferably 80 μm or less, more preferably 75 μm or less. Note that, as a measured value of the thickness of the GaN layer of the embodiment in the range of 5 μm or less, the minimum value of the half-value width of the (0002) plane is 55 seconds when the thickness of the GaN layer is 3 μm, and the minimum value of the half-value width of the (10-12) plane is 123 seconds when the thickness of the GaN layer is 5 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 50 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 115 seconds can be cited.

[0151] ​Further, for example, by making the thickness of the GaN layer 3 μm or less, the in-plane deviation of the thickness of the GaN layer can be preferably 2.5% or less, more preferably 2% or less, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer can be preferably 2.5% or less, more preferably 2% or less, and the warpage of the wafer can be preferably 50 μm or less, more preferably 45 μm or less. Note that, as a measured value in the range where the thickness of the GaN layer of the example is 3 μm or less, the minimum value of the half-value width of the (0002) plane is 55 seconds when the thickness of the GaN layer is 3 μm, and the minimum value of the half-value width of the (10-12) plane is 143 seconds when the thickness of the GaN layer is 2 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 50 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 135 seconds can be cited.

[0152] Further, for example, by making the thickness of the GaN layer 2 μm or less, the in-plane deviation of the thickness of the GaN layer can be preferably 2% or less, more preferably 1.5% or less, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer can be preferably 2% or less, more preferably 1.5% or less, and the warpage of the wafer can be preferably 40 μm or less, more preferably 35 μm or less. Note that, as a measured value in the range where the thickness of the GaN layer of the example is 2 μm or less, the minimum value of the half-value width of the (0002) plane is 62 seconds when the thickness of the GaN layer is 2 μm, and the minimum value of the half-value width of the (10-12) plane is 143 seconds when the thickness of the GaN layer is 2 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 55 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 135 seconds can be cited.

[0153] Further, for example, by making the thickness of the GaN layer 1.5 μm or less, the in-plane deviation of the thickness of the GaN layer can be preferably 1.5% or less, more preferably 1% or less, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer can be preferably 1.5% or less, more preferably 1% or less, and the warpage of the wafer can be preferably 35 μm or less, more preferably 30 μm or less. Note that, as a measurement value in the range where the thickness of the GaN layer according to the embodiment is 1.5 μm or less, the minimum value of the half-value width of the (0002) plane is 68 seconds when the thickness of the GaN layer is 1.5 μm, and the minimum value of the half-value width of the (10-12) plane is 160 seconds when the thickness of the GaN layer is 1.5 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 60 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 155 seconds can be cited.

[0154] Further, for example, by making the thickness of the GaN layer 1.2 μm or less, the in-plane deviation of the thickness of the GaN layer can be preferably 1% or less, more preferably 0.8% or less, the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer can be preferably 1% or less, more preferably 0.8% or less, and the warpage of the wafer can be preferably 30 μm or less, more preferably 25 μm or less. Note that, as a measurement value in the range where the thickness of the GaN layer according to the embodiment is 1.2 μm or less, the minimum value of the half-value width of the (0002) plane is 70 seconds when the thickness of the GaN layer is 1.2 μm, and the minimum value of the half-value width of the (10-12) plane is 166 seconds when the thickness of the GaN layer is 1.2 μm. In this thickness range, as a reference level of the minimum value of the half-value width of the (0002) plane, for example, 65 seconds can be cited. Further, as a reference level of the minimum value of the half-value width of the (10-12) plane, for example, 160 seconds can be cited.

[0155] Note that, as the reference level of the minimum value of the half-value width of the (0002) plane, the reference level of the minimum value of the half-value width of the (10-12) plane, the reference level of the minimum value of the rms, the reference level of the minimum value of the in-plane deviation of the thickness of the GaN layer, the reference level of the minimum value of the in-plane deviation of the impurity concentration (carrier concentration) in the GaN layer, and the reference level of the minimum value of the warpage of the wafer exemplified in the above description, there is a possibility that each can be further reduced.

[0156] [Other Embodiments]

[0157] The present application is not limited to the above-described embodiments, and various changes can be made thereto without departing from the spirit thereof. Further, the various embodiments can be appropriately combined.

[0158] For example, in the above-described embodiments, a manner in which the base substrate 10 is preferably a sapphire substrate is exemplified, but as the base substrate 10, a silicon carbide (SiC) substrate, for example, can also be used. When a GaN layer is formed on a SiC substrate with an AlN layer formed as a nucleation layer interposed therebetween, by forming the AlN layer with high crystallinity as described above and subjecting the AlN layer to heat treatment as described above, it is also possible to improve the quality of the GaN layer.

[0159] <Preferred Embodiments of the Invention>

[0160] Hereinafter, preferred embodiments of the present invention will be described.

[0161] (Note 1)

[0162] A Group III nitride laminated substrate, comprising:

[0163] a base substrate (having a diameter of 2 inches or more);

[0164] a first layer formed on the base substrate and composed of aluminum nitride; and

[0165] a second layer formed on the first layer and composed of gallium nitride,

[0166] the second layer has a thickness of 10 μm or less, a half-value width of (0002) diffraction based on X-ray rocking curve measurement of 100 seconds or less, and a half-value width of (10-12) diffraction based on X-ray rocking curve measurement of 200 seconds or less.

[0167] (Note 2)

[0168] The Group III nitride laminated substrate according to Note 1, wherein the second layer has a thickness of 0.8 μm or more.

[0169] (Note 3)

[0170] The Group III nitride laminated substrate according to any one of Notes 1 to 2, wherein a surface of the second layer has a surface roughness of 0.5 nm or less (more preferably 0.4 nm or less) in terms of a root mean square value in a 5 μm square region as measured by an atomic force microscope.

[0171] (Note 4)

[0172] The Group III nitride laminated substrate according to any one of Notes 1 to 3, wherein an in-plane deviation of the thickness of the second layer is 4% or less.

[0173] (Note 5)

[0174] The Group III nitride laminated substrate according to any one of the Embodiments 1 to 4, wherein an impurity is added to the second layer, and an in-plane variation of the impurity concentration in the second layer is 4% or less.

[0175] (Embodiment 6)

[0176] The Group III nitride laminated substrate according to any one of the Embodiments 1 to 5, wherein an impurity (n-type impurity) for controlling a carrier concentration is added to the second layer, and an in-plane variation of the carrier concentration (n-type carrier concentration) in the second layer is 4% or less.

[0177] (Embodiment 7)

[0178] The Group III nitride laminated substrate according to any one of the Embodiments 1 to 6, wherein a warpage of the Group III nitride laminated substrate is 140 μm or less (more preferably 135 μm or less).

[0179] (Embodiment 8)

[0180] The Group III nitride laminated substrate according to any one of the Embodiments 1 to 7, wherein a thickness of the second layer is 7 μm or less.

[0181] (Embodiment 9)

[0182] The Group III nitride laminated substrate according to Embodiment 8, wherein an in-plane variation of the thickness of the second layer is 3.5% or less (more preferably 3% or less).

[0183] (Embodiment 10)

[0184] The Group III nitride laminated substrate according to Embodiment 8 or 9, wherein an impurity (an impurity for controlling a carrier concentration) is added to the second layer, and an in-plane variation of the impurity concentration (carrier concentration) in the second layer is 3.5% or less (more preferably 3% or less).

[0185] (Embodiment 11)

[0186] The Group III nitride laminated substrate according to any one of the Embodiments 8 to 10, wherein a warpage of the Group III nitride laminated substrate is 110 μm or less (more preferably 105 μm or less).

[0187] (Embodiment 12)

[0188] The Group III nitride laminated substrate according to any one of the Embodiments 1 to 11, wherein a thickness of the second layer is 5 μm or less.

[0189] (Embodiment 13)

[0190] The Group III nitride laminated substrate according to the supplementary note 12, wherein the in-plane deviation of the thickness of the second layer is 3% or less (more preferably 2.5% or less).

[0191] (Supplementary Note 14)

[0192] The Group III nitride laminated substrate according to the supplementary note 12 or 13, wherein an impurity (an impurity for controlling a carrier concentration) is added to the second layer, and the in-plane deviation of the impurity concentration (carrier concentration) in the second layer is 3% or less (more preferably 2.5% or less).

[0193] (Supplementary Note 15)

[0194] The Group III nitride laminated substrate according to any one of the supplementary notes 12 to 14, wherein the warpage of the Group III nitride laminated substrate is 80 μm or less (more preferably 75 μm or less).

[0195] (Supplementary Note 16)

[0196] The Group III nitride laminated substrate according to any one of the supplementary notes 1 to 15, wherein the thickness of the second layer is 3 μm or less.

[0197] (Supplementary Note 17)

[0198] The Group III nitride laminated substrate according to the supplementary note 16, wherein the in-plane deviation of the thickness of the second layer is 2.5% or less (more preferably 2% or less).

[0199] (Supplementary Note 18)

[0200] The Group III nitride laminated substrate according to the supplementary note 16 or 17, wherein an impurity (an impurity for controlling a carrier concentration) is added to the second layer, and the in-plane deviation of the impurity concentration (carrier concentration) in the second layer is 2.5% or less (more preferably 2% or less).

[0201] (Supplementary Note 19)

[0202] The Group III nitride laminated substrate according to any one of the supplementary notes 16 to 18, wherein the warpage of the Group III nitride laminated substrate is 50 μm or less (more preferably 45 μm or less).

[0203] (Supplementary Note 20)

[0204] The Group III nitride laminated substrate according to any one of the supplementary notes 1 to 19, wherein the thickness of the second layer is 2 μm or less.

[0205] (Supplementary Note 21)

[0206] The Group III nitride laminated substrate according to the supplementary note 20, wherein the in-plane deviation of the thickness of the second layer is 2% or less (more preferably 1.5% or less).

[0207] (Supplementary Note 22)

[0208] The Group III nitride laminated substrate according to the supplementary note 20 or 21, wherein an impurity (an impurity for controlling a carrier concentration) is added to the second layer, and the in-plane deviation of the impurity concentration (carrier concentration) in the second layer is 2% or less (more preferably 1.5% or less).

[0209] (Supplementary Note 23)

[0210] The Group III nitride laminated substrate according to any one of the supplementary notes 20 to 22, wherein the warpage of the Group III nitride laminated substrate is 40 μm or less (more preferably 35 μm or less).

[0211] (Supplementary Note 24)

[0212] The Group III nitride laminated substrate according to any one of the supplementary notes 1 to 23, wherein the thickness of the second layer is 1.5 μm or less.

[0213] (Supplementary Note 25)

[0214] The Group III nitride laminated substrate according to the supplementary note 24, wherein the in-plane deviation of the thickness of the second layer is 1.5% or less (more preferably 1% or less).

[0215] (Supplementary Note 26)

[0216] The Group III nitride laminated substrate according to the supplementary note 24 or 25, wherein an impurity (an impurity for controlling a carrier concentration) is added to the second layer, and the in-plane deviation of the impurity concentration (carrier concentration) in the second layer is 1.5% or less (more preferably 1% or less).

[0217] (Supplementary Note 27)

[0218] The Group III nitride laminated substrate according to any one of the supplementary notes 24 to 26, wherein the warpage of the Group III nitride laminated substrate is 35 μm or less (more preferably 30 μm or less).

[0219] (Supplementary Note 28)

[0220] The Group III nitride laminated substrate according to any one of the supplementary notes 1 to 27, wherein the thickness of the second layer is 1.2 μm or less.

[0221] (Supplementary Note 29)

[0222] The Group III nitride laminated substrate according to the above item 28, wherein the in-plane deviation of the thickness of the second layer is 1% or less (more preferably 0.8% or less).

[0223] (item 30)

[0224] The Group III nitride laminated substrate according to the above item 28 or 29, wherein an impurity (an impurity for controlling a carrier concentration) is added to the second layer, and the in-plane deviation of the impurity concentration (carrier concentration) in the second layer is 1% or less (more preferably 0.8% or less).

[0225] (item 31)

[0226] The Group III nitride laminated substrate according to any one of the above items 28 to 30, wherein the warpage of the Group III nitride laminated substrate is 30 μm or less (more preferably 25 μm or less).

[0227] (item 32)

[0228] The Group III nitride laminated substrate according to any one of the above items 1 to 31, wherein the thickness of the second layer is 1 μm or more, the half-value width of (0002) diffraction measured based on an X-ray rocking curve is 80 seconds or less, and the half-value width of (10-12) diffraction measured based on an X-ray rocking curve is 180 seconds or less.

[0229] (item 33)

[0230] The Group III nitride laminated substrate according to any one of the above items 1 to 27, wherein the thickness of the second layer is 1.5 μm or more, the half-value width of (0002) diffraction measured based on an X-ray rocking curve is 70 seconds or less, and the half-value width of (10-12) diffraction measured based on an X-ray rocking curve is 170 seconds or less.

[0231] (item 34)

[0232] The Group III nitride laminated substrate according to any one of the above items 1 to 33, wherein the base substrate is a sapphire substrate. The sapphire substrate is preferably, for example, 2 inches in diameter and 300 μm or more and 500 μm or less in thickness, or, for example, 4 inches in diameter and 600 μm or more and 1000 μm or less in thickness, or, for example, 6 inches in diameter and 1000 μm or more and 1500 μm or less in thickness.

[0233] (item 35)

[0234] The Group III nitride laminated substrate according to any one of the provisos 1 to 34 is used for manufacturing a semiconductor element, and the aforementioned second layer is used as at least a part of an operation layer of the semiconductor element.

[0235] (Proviso 36)

[0236] A semiconductor element having at least a part of an operation layer of the aforementioned second layer of the Group III nitride laminated substrate according to any one of the provisos 1 to 35.

[0237] (Proviso 37)

[0238] A Group III nitride laminated substrate comprising:

[0239] a base substrate (diameter of 2 inches or more); and

[0240] a first layer formed on the aforementioned base substrate and composed of aluminum nitride,

[0241] the aforementioned first layer has a surface used as a base for growing a second layer,

[0242] the second layer is composed of gallium nitride, has a thickness of 10 μm or less, has a half-value width of (0002) diffraction of 100 seconds or less as measured based on an X-ray rocking curve, and has a half-value width of (10-12) diffraction of 200 seconds or less as measured based on an X-ray rocking curve. The first layer preferably has a surface used as a base for growing the second layer according to any one of the provisos 2 to 33.

Claims

1. A Group III nitride laminated substrate, comprising: a base substrate; a first layer formed on the base substrate and composed of aluminum nitride; and a second layer formed on the first layer and composed of gallium nitride, the second layer having a thickness of 10 μm or less, a half-value width of (0002) diffraction based on an X-ray rocking curve of 100 seconds or less, and a half-value width of (10-12) diffraction based on an X-ray rocking curve of 200 seconds or less, a surface of the first layer being Al-polar, the surface being in contact with the second layer, the first layer having a thickness of 0.1 μm or more, a half-value width of an X-ray rocking curve of (0002) plane of the first layer being 100 seconds or less, and a half-value width of an X-ray rocking curve of (10-12) plane being 300 seconds or less. The surface of the second layer has a surface roughness of 0.5 nm or less in terms of a root mean square value in a 5 μm square region as measured by an atomic force microscope. An in-plane deviation of the thickness of the second layer is 4% or less. An impurity is added to the second layer, and an in-plane deviation of the impurity concentration in the second layer is 4% or less. An impurity for controlling a carrier concentration is added to the second layer, and an in-plane deviation of the carrier concentration in the second layer is 4% or less. The Group III nitride laminated substrate has a warpage of 140 μm or less. The thickness of the second layer is 3 μm or less. An in-plane deviation of the thickness of the second layer is 2.5% or less.

2. The Group III nitride layered substrate of claim 1, wherein, An impurity is added to the second layer, and an in-plane deviation of the impurity concentration in the second layer is 2.5% or less.

3. The Group III nitride layered substrate of claim 1 or 2, wherein The Group III nitride laminated substrate has a warpage of 50 μm or less.

4. The Group III nitride layered substrate of claim 1 or 2, wherein 11. The Group III nitride laminated substrate according to claim 1 or 2, which is used for manufacturing a semiconductor element, the second layer being used as at least a part of an active layer of the semiconductor element.

5. The Group III nitride layered substrate of claim 1 or 2, wherein 12. A semiconductor element having at least a part of an active layer composed of the second layer of the Group III nitride laminated substrate according to any one of claims 1 to 11.

6. The Group III nitride layered substrate of claim 1 or 2, wherein 13. A Group III nitride laminated substrate, comprising: a base substrate; and a first layer formed on the base substrate and composed of aluminum nitride, the first layer having a surface used as a base for growing a second layer, the second layer being composed of gallium nitride and having a thickness of 10 μm or less, a half-value width of (0002) diffraction based on an X-ray rocking curve of 100 seconds or less, and a half-value width of (10-12) diffraction based on an X-ray rocking curve of 200 seconds or less, a surface of the first layer being Al-polar, the surface being in contact with the second layer, the first layer having a thickness of 0.1 μm or more, a half-value width of an X-ray rocking curve of (0002) plane of the first layer being 100 seconds or less, and a half-value width of an X-ray rocking curve of (10-12) plane being 300 seconds or less.

7. The Group III nitride layered substrate of Claim 1 or 2, wherein ​ 8. The Group III nitride layered substrate of claim 7, wherein, ​ 9. The Group III nitride layered substrate of claim 7, wherein, ​ 10. The Group III nitride layered substrate of Claim 7, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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