Oscillation circuit

Abstract

The oscillation circuit includes a first current source circuit, a second current source circuit, a resistor, a first capacitor, a second capacitor, a first comparison circuit, a second comparison circuit, and an RS latch. Depending on the signal level of the output signal of the RS latch, the output current of the second current source circuit is input to the first capacitor or the second capacitor, a reference voltage determined by the output current of the first current source circuit and the resistance value of the resistor and the voltage of the first capacitor are input to the first comparison circuit, the reference voltage and the voltage of the second capacitor are input to the second comparison circuit, and a signal output from the first comparison circuit and a signal output from the second comparison circuit are input to the RS latch.

Description

Technical Field

[0001] The present invention relates to an oscillating circuit. Background Art

[0002] Conventionally, a relaxation-type oscillation circuit is known as an oscillation circuit that does not use a crystal oscillator. Figure 9 This is a circuit diagram of a relaxation oscillator circuit 801, an example of a conventional oscillator circuit. Relaxation oscillator circuit 801 includes a CR oscillator circuit 802 having a resistor RV, capacitors C1 and C2, inverters INV1 and INV2, and a comparator circuit COMP; a bandgap reference circuit 803; and a voltage-to-current conversion circuit 804. The oscillation frequency of relaxation oscillator circuit 801 is determined by comparing the voltages of capacitors C1 and C2, charged via resistor RV connected to the output terminal of inverter INV1, with a reference voltage Vref in the comparator circuit COMP.

[0003] Bandgap reference circuit 803 outputs a temperature-independent reference voltage to voltage-to-current conversion circuit 804. Voltage-to-current conversion circuit 804 converts the voltage output from bandgap reference circuit 803 into a current and supplies a bias current to comparator circuit COMP. Comparator circuit COMP controls its response speed based on the amount of bias current supplied.

[0004]

Prior art literature

[0005] [Patent Literature]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-005109. Summary of the Invention

[0007] [Problems to be solved by the invention]

[0008] The power consumption of existing oscillation circuits still needs to be improved. The present invention aims to provide an oscillation circuit with low power consumption.

[0009]

Solutions to Solve the Problem

[0010] The oscillation circuit of the present invention is configured as follows: it includes a first current source circuit, a second current source circuit, a resistor, a first capacitor, a second capacitor, a first comparison circuit, a second comparison circuit, and an RS latch; depending on the signal level of the output signal of the RS latch, the output current of the second current source circuit is input to the first capacitor or the second capacitor, a reference voltage determined by the first current source circuit and the resistor and the voltage of the first capacitor are input to the first comparison circuit, the reference voltage and the voltage of the second capacitor are input to the second comparison circuit, and the signal output from the first comparison circuit and the signal output from the second comparison circuit are input to the RS latch.

[0011] Effects of the invention

[0012] According to the oscillation circuit of the present invention, a low-power oscillation circuit can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit diagram of an oscillation circuit according to a first embodiment of the present invention.

[0014] Figure 2 This is a circuit diagram of a first current source circuit according to a first embodiment of the present invention.

[0015] Figure 3 This is a timing chart illustrating the operation of the startup circuit according to the first embodiment of the present invention.

[0016] Figure 4 This is a circuit diagram of a second current source circuit according to the first embodiment of the present invention.

[0017] Figure 5 This is a circuit diagram of a comparison circuit according to the first embodiment of the present invention.

[0018] Figure 6 This is a timing chart illustrating the overall operation of the first embodiment of the present invention.

[0019] Figure 7 This is a circuit diagram of a first current source circuit according to a second embodiment of the present invention.

[0020] Figure 8 This is a circuit diagram of a second current source circuit according to a second embodiment of the present invention.

[0021] Figure 9 This is a circuit diagram of an existing oscillation circuit. DETAILED DESCRIPTION

[0022] [First embodiment]

[0023] Figure 1A circuit diagram of an oscillation circuit 1 as an example of an oscillation circuit according to a first embodiment of the present invention is shown.

[0024] Oscillation circuit 1 includes an enable signal input terminal ENINP; an output terminal OSCOUT; switches 10 to 15; inverters 20 and 21; a three-input NAND circuit 22; a resistor 25; capacitors 30 and 31; an RS latch 40; current source circuits 100 and 200; and comparator circuits 300 and 400. Switches 10 to 15 are turned on (connected state) when a control signal applied to the control terminal is at a high level, and are turned off (disconnected state) when the control signal applied to the control terminal is at a low level.

[0025] Current source circuits 100 and 200 each have a power supply terminal, an output terminal IOUT, an enable signal input terminal ENIN, and a startup signal output terminal STUP. Comparator circuits 300 and 400 each have a non-inverting input terminal INP, an inverting input terminal INN, an output terminal OUT, and an enable signal input terminal EN. RS latch 40 includes a two-input NAND circuit 23 and a three-input NAND circuit 24, three input terminals Ta1, Ta2, and Ta3, and one output terminal Ta4. The connection descriptions for power supply VDD and power supply GND are partially omitted.

[0026] In the current source circuit 100, the power supply terminal is connected to the power supply VDD, and the output terminal IOUT is connected to the power supply GND via the resistor 25. In the current source circuit 200, the power supply terminal is connected to the power supply VDD, and the output terminal IOUT is connected to the power supply GND via the switch 14 and the capacitor 30, and is connected to the power supply GND via the switch 15 and the capacitor 31.

[0027] The non-inverting input terminal INP of the comparator circuit 300 is connected to the output terminal IOUT of the current source circuit 100. The inverting input terminal INN of the comparator circuit 300 is connected to the connection point P1 between the switch 14 and the capacitor 30. When the voltage input to the inverting input terminal INN is greater than the voltage input to the non-inverting input terminal INP, the comparator circuit 300 outputs a low-level voltage from the output terminal OUT. When the voltage input to the non-inverting input terminal INP is greater than the voltage input to the inverting input terminal INN, the comparator circuit 300 outputs a high-level voltage from the output terminal OUT.

[0028] The non-inverting input terminal INP of the comparator circuit 400 is connected to the output terminal IOUT of the current source circuit 100. The inverting input terminal INN of the comparator circuit 400 is connected to the connection point P2 between the switch 15 and the capacitor 31. Similar to the comparator circuit 300, the comparator circuit 400 outputs a low-level voltage from the output terminal OUT when the voltage input to the inverting input terminal INN is greater than the voltage input to the non-inverting input terminal INP. When the voltage input to the non-inverting input terminal INP is greater than the voltage input to the inverting input terminal INN, the output terminal OUT outputs a high-level voltage.

[0029] The output terminal OUT of the comparison circuit 300 is connected to the input terminal Ta1 of the RS latch 40. The output terminal OUT of the comparison circuit 400 is connected to the input terminal Ta2 of the RS latch 40. The output terminal Ta4 of the RS latch 40 is connected to the control terminal of the switch 12, the control terminal of the switch 14, and the input terminal of the inverter 21. The output terminal of the inverter 21 is connected to the control terminal of the switch 10, the control terminal of the switch 15, and the output terminal OSCOUT.

[0030] The internal connections of RS latch 40 are described. Input terminal Ta1 is connected to the first input terminal of two-input NAND circuit 23. The output terminal of two-input NAND circuit 23 is connected to the first input terminal of three-input NAND circuit 24. Input terminal Ta2 is connected to the second input terminal of three-input NAND circuit 24. The output terminal of three-input NAND circuit 24 is connected to the second input terminal of two-input NAND circuit 23 and output terminal Ta4. Input terminal Ta3 is connected to the third input terminal of three-input NAND circuit 24.

[0031] The connection of switches 10 to 13 is described below. The first terminal of switch 10 and the first terminal of switch 11 are connected to the first terminal of capacitor 30. The second terminal of switch 10 and the second terminal of switch 11 are connected to the second terminal of capacitor 30. The second terminal of capacitor 30 is connected to power supply GND. The first terminal of switch 12 and the first terminal of switch 13 are connected to the first terminal of capacitor 31, and the second terminal of switch 12 and the second terminal of switch 13 are connected to the second terminal of capacitor 31. The second terminal of capacitor 31 is connected to power supply GND.

[0032] The enable signal input terminal ENINP is connected to the enable signal input terminal ENIN of the current source circuit 100, the enable signal input terminal ENIN of the current source circuit 200, and the first input terminal of the three-input NAND circuit 22. The startup signal output terminal STUP of the current source circuit 100 is connected to the second input terminal of the three-input NAND circuit 22. The startup signal output terminal STUP of the current source circuit 200 is connected to the third input terminal of the three-input NAND circuit 22. The output terminal of the three-input NAND circuit 22 is connected to the control terminal of the switch 11, the control terminal of the switch 13, and the input terminal of the inverter 20 via the connection point P0. The output terminal of the inverter 20 is connected to the input terminal Ta3 of the RS latch 40, the EN input terminal of the comparison circuit 300, and the EN input terminal of the comparison circuit 400.

[0033] Figure 2 A circuit diagram of a current source circuit 100 as a first current source circuit is shown.

[0034] The current source circuit 100 includes an enable signal input terminal ENIN; an output terminal IOUT; a startup signal output terminal STUP; P-channel MOS transistors MP100, MP101, and MP102 (hereinafter referred to as "PMOS transistors"); N-channel MOS transistors MN100 and MN101 (hereinafter referred to as "NMOS transistors"); switches 101 and 102; an inverter 103; a resistor 104; and a startup circuit 110. The current source circuit 100 comprises NMOS transistors MN100 and MN101, which operate in the weak inversion region, forming a micro-current source circuit that operates in the weak inversion region. The resistor 104 is set to a relatively high resistance value so that the transistors MN100 and MN101 operate in the weak inversion region.

[0035] Switches 101 and 102 are turned on when the control signal applied to the control terminal is high, and turned off when it is low. The correspondence between the control signal applied to the control terminal and the on / off state can be adjusted by inverting the control signal applied to the control terminal using an inverter.

[0036] Startup circuit 110 includes: an input terminal Ta10; two output terminals Ta11 and Ta12; PMOS transistors MP110 and MP111; inverters 114, 115, and 116; switches 111 and 112; and a capacitor 113. Switches 111 and 112 are turned on when a control signal applied to the control terminal is at a high level, and are turned off when the control signal applied to the control terminal is at a low level.

[0037] The connections of the current source circuit 100 will be described. The enable signal input terminal ENIN is connected to the input terminal Ta10 and the input of the inverter 103. The output of the inverter 103 is connected to the control terminal of the switch 101 and the control terminal of the switch 102. The source terminal of the PMOS transistor MP100 is connected to the power supply VDD. The drain terminal of the PMOS transistor MP100 is connected to the drain terminal of the NMOS transistor MN100, the gate terminal of the NMOS transistor MN100, the output terminal Ta11, the gate terminal of the NMOS transistor MN101, and the first terminal of the switch 101. The gate terminal of the PMOS transistor MP100 is connected to the gate terminal of the PMOS transistor MP101, the drain terminal of the PMOS transistor MP101, the drain terminal of the NMOS transistor MN101, the gate terminal of the PMOS transistor MP102, and the second terminal of the switch 102. The source terminal of the NMOS transistor MN100 is connected to the power supply GND. The source terminal of the PMOS transistor MP101 is connected to the power supply VDD. The source terminal of the NMOS transistor MN101 is connected to the power supply GND via the resistor 104. The source terminal of the PMOS transistor MP102 is connected to the power supply VDD. The drain terminal of the PMOS transistor MP102 is connected to the output terminal IOUT. The second terminal of the switch 101 is connected to the power supply GND. The first terminal of the switch 102 is connected to the power supply VDD.

[0038] The connections of the startup circuit 110 will be described. Input terminal Ta10 is connected to the input terminal of inverter 114 and the control terminal of switch 112. The output of inverter 114 is connected to the gate terminal of PMOS transistor MP110 and the control terminal of switch 111 via connection point P11. The source terminal of PMOS transistor MP110 is connected to power supply VDD. The drain terminal of PMOS transistor MP110 is connected to the gate terminal of PMOS transistor MP111, the input terminal of inverter 115, the first terminal of capacitor 113, and the first terminal of switch 111 via connection point P12. The source terminal of PMOS transistor MP111 is connected to the second terminal of switch 112. The drain terminal of PMOS transistor MP111 is connected to output terminal Ta11. The output of inverter 115 is connected to the input of inverter 116. The output of inverter 116 is connected to startup signal output terminal STUP via second output terminal Ta12. The second terminal of capacitor 113 is connected to power supply GND. A first terminal of the switch 112 is connected to the power supply VDD and the source terminal of the PMOS transistor MP110. A second terminal of the switch 111 is connected to the power supply GND.

[0039] Figure 3 1 is a timing chart showing the operations of the startup circuit 110 and the startup circuit 210 . Figure 3The horizontal axis represents time, and the vertical axis represents the signal levels of each part of the startup circuit. Figure 3 The upper half of the timing chart shows the operation of the startup circuit 110 , and the lower half shows the operation of the startup circuit 210 .

[0040] use Figure 3 The operation of the startup circuit 110 is described below. In a state where a low level signal is input to the input terminal Ta10 of the startup circuit 110 (for example, Figure 3 At T0 (time T0), connection point P11 reaches a high level, switch 111 turns on (connected state), switch 112 turns off (disconnected state), and PMOS transistor MP110 turns off. Switch 111 short-circuits both ends of capacitor 113, causing the voltage at connection point P12 to reach the power supply GND level. While PMOS transistor MP111 is on, switch 112 is off, causing the voltage at output terminal Ta11 to reach the power supply GND level. A low-level signal is output from output terminal Ta12.

[0041] In a state where a High-level signal is input to the input terminal Ta10 of the startup circuit 110 (for example, Figure 3 At T1), the connection point P11 becomes a low level, and the switch 111 is turned off, the switch 112 is turned on, and the PMOS transistor MP110 is turned on. The capacitor 113 is charged by the current from the PMOS transistor MP110, and the voltage at the connection point P12 rises from the power supply GND level. At T15, the voltage at the connection point P12 exceeds the threshold voltage Vth(MP111) of the PMOS transistor MP111. Figure 3 During the period from T1 to T15, that is, during the period when the switch 112 and the PMOS transistor MP111 are on, a voltage serving as an activation signal is output from the output terminal Ta11.

[0042] When the voltage at connection point P12 exceeds the threshold voltage Vth(MP111) of PMOS transistor MP111, PMOS transistor MP111 turns off, and no voltage serving as an activation signal is output from output terminal Ta11. Furthermore, while the voltage at connection point P12 exceeds the threshold voltage Vth(MP111) of PMOS transistor MP111, a high-level signal is output from output terminal Ta12 as an activation signal.

[0043] Figure 4 A circuit diagram of a current source circuit 200 as a second current source circuit is shown.

[0044] Similar to current source circuit 100, current source circuit 200 comprises NMOS transistors MN200 and MN201 (which operate in the weak inversion region), forming a micro current source circuit that operates in the weak inversion region. Current source circuit 200 differs from current source circuit 100 in that it includes startup circuit 210 in place of startup circuit 110. The remaining components are substantially the same. Therefore, any overlapping descriptions of current source circuit 100 will be omitted.

[0045] Startup circuit 210 differs from startup circuit 110 in that it includes capacitor 213, whose capacitance value is different from that of capacitor 113, instead of capacitor 113. The other components are essentially the same. Specifically, startup circuit 210, like startup circuit 110, includes: one input terminal Ta20; two output terminals Ta21 and Ta22; a PMOS transistor; an inverter; and a switch. Furthermore, capacitor 213 is included instead of capacitor 113.

[0046] As described above, the current source circuit 100 and the current source circuit 200 have substantially the same circuit configuration, except for the capacitor 113 of the current source circuit 100 and the capacitor 213 of the current source circuit 200. Therefore, the change in the output current of the current source circuit 200 with respect to the temperature change is the same as the change in the output current with respect to the temperature change of the current source circuit 100. The capacitor 213, which serves as the second capacitor, has a larger capacitance than the capacitor 113, which serves as the first capacitor.

[0047] use Figure 3 The operation of the startup circuit 210 will be described. The startup circuit 210 performs the same operation as the startup circuit 110, except for the time required from the start of charging of the capacitor 213 until the voltage exceeds the threshold voltage Vth (211) of the PMOS transistor MP211. In the startup circuit 210, the capacitance value of the capacitor 213 is set to be larger than the capacitance value of the capacitor 113. Therefore, the time required from the start of charging of the capacitor 213 until the voltage exceeds the threshold voltage Vth (211) of the PMOS transistor MP211 is longer than the time required from the start of charging of the capacitor 113 until the voltage exceeds the threshold voltage Vth (111) of the PMOS transistor MP111. Therefore, the period (T1 to T2) during which the startup signal is output from the output terminal Ta21 is longer than the period (T1 to T15) during which the startup signal is output from the output terminal Ta11 of the startup circuit 110. In addition, the time until the threshold voltage of the inverter 215 in the startup circuit 210 is exceeded (not shown here) and the startup signal of a high level is output from the output terminal Ta22 is longer than the time until the threshold voltage of the inverter 115 in the startup circuit 110 is exceeded (not shown here) and the startup signal of a high level is output from the output terminal Ta12.

[0048] Figure 5 A circuit diagram of a comparison circuit 300 as a first comparison circuit is shown.

[0049] Comparator circuit 300 includes a non-inverting input terminal INP; an inverting input terminal INN; an enable signal input terminal EN; an output terminal OUT; PMOS transistors MP300 and MP301; NMOS transistors MN300, MN301, and MN302; inverters 305, 306, and 307; current source circuits I300 and I301; and switches 301, 302, 303, and 304. Switches 301 to 304 are turned on when a control signal applied to the control terminal is at a high level, and are turned off when the control signal applied to the control terminal is at a low level.

[0050] The connections of the comparator circuit 300 will be described. The non-inverting input terminal INP is connected to the gate terminal of the PMOS transistor MP300. The inverting input terminal INN is connected to the gate terminal of the PMOS transistor MP301. In the current source circuit I300, the first terminal is connected to the power supply VDD, and the second terminal is connected to the first terminal of the switch 303. The second terminal of the switch 303 is connected to the source terminal of the PMOS transistor MP300 and the source terminal of the PMOS transistor MP301. The drain terminal of the PMOS transistor MP300 is connected to the drain terminal and gate terminal of the NMOS transistor MN300, the gate terminal of the NMOS transistor MN301, and the first terminal of the switch 301. The drain terminal of the PMOS transistor MP301 is connected to the drain terminal of the NMOS transistor MN301, the gate terminal of the NMOS transistor MN302, and the first terminal of the switch 302.

[0051] In current source circuit I301, a first terminal is connected to power supply VDD, and a second terminal is connected to the drain of NMOS transistor MN302, the input terminal of inverter 306, and the second terminal of switch 304. The first terminal of switch 304 is connected to power supply VDD. The output terminal of inverter 306 is connected to the input terminal of inverter 307. The output terminal of inverter 307 is connected to output terminal OUT. The source terminal of NMOS transistor MN300, the source terminal of NMOS transistor MN301, the source terminal of NMOS transistor MN302, the second terminal of switch 301, and the second terminal of switch 302 are each connected to power supply GND.

[0052] The enable signal input terminal EN is connected to the control terminal of the switch 303 and the input terminal of the inverter 305. The output terminal of the inverter 305 is connected to the control terminals of the switches 301, 302, and 304.

[0053] The comparison circuit 300 outputs a High-level signal from the output terminal OUT when a Low-level signal is input to the enable signal input terminal EN, and outputs a High-level or Low-level signal from the output terminal OUT depending on the signals input to the in-phase input terminal INP and the inverting input terminal INN when a High-level signal is input to the enable signal input terminal EN.

[0054] The comparison circuit 400 as the second comparison circuit has the same configuration as the comparison circuit 300 , and therefore its description is omitted.

[0055] Reference Figure 1 、 Figure 2 、 Figure 4 and Figure 6 , explaining the operation of the oscillation circuit 1. Figure 6 The horizontal axis represents time, and the vertical axis represents the signal level of each signal.

[0056] <When ENINP = Low>

[0057] When a low level signal is input to the enable signal input terminal ENINP ( Figure 6 At T0, the current source circuits 100 and 200 output a low-level signal from the startup signal output terminal STUP. A low-level signal is input to each input terminal of the three-input NAND circuit 22. The three-input NAND circuit 22 outputs a high-level signal from its output terminal, so the connection point P0 becomes high. As a result, switches 11 and 13 become conductive. In addition, a low-level signal is input to the enable signal input terminal EN of the comparison circuits 300 and 400 and the input terminal Ta3 of the RS latch 40. The comparison circuits 300 and 400 each output a high-level signal from the output terminal OUT. A high-level signal is input to the input terminal Ta1 and the input terminal Ta2 of the RS latch 40.

[0058] Since a low-level signal is input to input terminal Ta3 of RS latch 40, a high-level signal is output from output terminal Ta4. Oscillation circuit 1 outputs a low-level signal from OSCOUT. Switches 12 and 14 are turned on, while switches 13 and 15 are turned off.

[0059] <When ENINP = High>

[0060] Next, the operation when a High-level signal is input to enable signal input terminal ENINP will be described. At time T1, a High-level signal is input to enable signal input terminal ENINP. Since capacitor 113 of startup circuit 110 is smaller than capacitor 213 of startup circuit 210, current is first output from output terminal IOUT of current source circuit 100 between times T1 and T2, and a High-level signal is output from startup signal output terminal STUP of current source circuit 100.

[0061] The output terminal IOUT of the current source circuit 100 is connected to the power supply GND via the resistor 25. Therefore, a voltage determined by the current value output by the current source circuit 100 and the resistor 25 appears across the resistor 25. The voltage across the resistor 25 is input as a reference voltage Vref to the non-inverting input terminal INP of the comparator circuits 300 and 400.

[0062] As long as the resistor 25 and the resistor 104 of the current source circuit 100 are made of the same material, the reference voltage Vref is determined only by the size ratio of the NMOS transistor MN100 to the NMOS transistor MN101 , and the reference voltage Vref exhibits a first-order proportional relationship with temperature.

[0063] Next, in the startup circuit 210 , the voltage at the first terminal of the capacitor 213 exceeds a predetermined voltage, current is output from the output terminal IOUT of the current source circuit 200 , and a High-level signal is output from the startup signal output terminal STUP of the current source circuit 200 (time T2 ).

[0064] At time T2, all the signals input to the input terminals of three-input NAND circuit 22 are high-level signals, and the signal at connection point P0 changes from a high-level signal to a low-level signal. Consequently, switches 11 and 13 are turned off. Furthermore, the signal at connection point P0 is inverted by inverter 20. The signal input to enable signal input terminal EN of comparator circuits 300 and 400 changes from a low-level signal to a high-level signal. High-level signals are output from output terminals OUT of comparator circuits 300 and 400.

[0065] In the two-input NAND circuit 23, a High-level signal is input to both input terminals, and a Low-level signal is output from the output terminal. In the three-input NAND circuit 24, the Low-level signal output from the two-input NAND circuit 23 is input to the first input terminal. The signal output from the output terminal Ta4 remains at a High level. The signal output from the output terminal OSCOUT remains at a Low level.

[0066] Furthermore, at time T2, switch 14 is turned on, while switches 10 and 11 are turned off. Therefore, capacitor 30 is charged by the current of current source circuit 200, and the voltage at connection point P1 begins to rise. When the voltage at connection point P1 exceeds reference voltage Vref (time T3), comparator circuit 300 changes the signal at output terminal OUT from a high level to a low level. The signal at input terminal Ta1 of RS latch 40 changes from a low level to a high level. The signal level of the signal output from RS latch 40 changes from a high level to a low level. The signal level of the signal output from output terminal OSCOUT changes from a low level to a high level.

[0067] The change in the signal level of the output signal of RS latch 40 turns off switches 12 and 14 and turns on switches 10 and 15. The voltage at connection point P1 becomes zero, and the output of comparison circuit 300 becomes a High-level signal (time T4).

[0068] At time T4, capacitor 31 is charged by the current of current source circuit 200, and the voltage at connection point P2 begins to rise. When the voltage at connection point P2 exceeds reference voltage Vref (time T5), comparator circuit 400 changes the signal at output terminal OUT from a high level to a low level. The signal level of the signal input to input terminal Ta2 of RS latch 40 changes from a high level to a low level. The signal level of the signal output from RS latch 40 changes from a low level to a high level. The signal level of the signal output from output terminal OSCOUT changes from a high level to a low level.

[0069] In response to the change in the signal level of the output signal from RS latch 40, switches 12 and 14 are turned on, while switches 10 and 15 are turned off. The voltage at connection point P2 reaches zero, and the signal level of the signal output from comparison circuit 400 reaches a high level (time T6). Furthermore, at time T6, capacitor 30 is charged by the current from current source circuit 200, and the voltage at connection point P1 begins to rise. This state is identical to the state at time T2 described above. Oscillator circuit 1 then repeats the oscillation operation from the state at time T2 to the state at time T6.

[0070] Here, current source circuits 100 and 200 are micro current source circuits. Micro current source circuits generally have two stable operating points: one at which the output current reaches zero, and the other at which the desired output current is obtained.

[0071] In order to avoid the point where the output current becomes zero and to achieve a stable operating point, the current source circuits 100 and 200 include startup circuits 110 and 210 .

[0072] Here, in the oscillation circuit 1, the current source circuit 100 is configured to start before the current source circuit 200 starts. Figure 6 Time T2, so Figure 1 Switches 10 and 13, which were shown short-circuiting capacitors 30 and 31, are now open, and charging of capacitor 30 begins. At time T3, voltage P1 (the voltage at the inverting input terminal INN) of capacitor 30 exceeds reference voltage Vref (the voltage at the non-inverting input terminal INP), causing voltage Ta1 (the voltage at the output terminal of comparator circuit 300) to reverse, thereby initiating oscillation. On the other hand, if current source circuit 200 is activated before current source circuit 100 is activated to begin charging capacitors 30 or 31, the voltage at the non-inverting input terminal INP will not reach reference voltage Vref. In this case, the voltage at output terminal OUT of comparator circuits 300 and 400 will not reverse, and oscillation will not begin.

[0073] In the oscillation circuit 1 , to reliably start oscillation, the capacitance value of the capacitor 213 of the starting circuit 210 is set larger than the capacitance value of the capacitor 113 of the starting circuit 110 so that the current source circuit 100 starts before the current source circuit 200 .

[0074] According to the oscillation circuit of this embodiment, an oscillation circuit with a small circuit scale and low power consumption can be obtained.

[0075] [Second embodiment]

[0076] The oscillation circuit of this embodiment is substantially the same as the oscillation circuit of the first embodiment except for the configuration of the current source circuit. Therefore, in this embodiment, the description will focus on the current source circuit having the different configuration.

[0077] Figure 7 1 is a circuit diagram of a current source circuit 100a included in an oscillation circuit according to a second embodiment of the present invention. Figure 8 2 is a circuit diagram of a current source circuit 200 a included in an oscillation circuit according to a second embodiment of the present invention.

[0078] The current source circuit 100a is substantially identical to the current source circuit 100 except for the following differences: the source terminal of the NMOS transistor MN101 is short-circuited to the power supply GND; the resistor 104a is connected between the drain terminal and the gate terminal of the NMOS transistor MN100; and the gate terminal of the NMOS transistor MN101 is connected to the gate terminal of the NMOS transistor MN100 via the drain terminal of the NMOS transistor MN100 and the resistor 104a.

[0079] The current generated by current source circuit 100 is affected by the substrate bias effect of NMOS transistor MN101. This is because the current flowing through resistor 104, connected between the source terminal of NMOS transistor MN101 and power supply GND, causes the backgate voltage to fall below the source terminal voltage. The threshold voltage Vth of NMOS transistor MN100 and the threshold voltage Vth of NMOS transistor MN101 are not completely equal due to the substrate bias effect of NMOS transistor MN101.

[0080] The current source circuit 100a, serving as the first current source circuit, is configured without the resistor 104 connected between the source terminal of the NMOS transistor MN101 and the power supply GND, thereby preventing the substrate bias effect from occurring in the NMOS transistor MN101. The current source circuit 100a, which includes a configuration that prevents the substrate bias effect from occurring in the NMOS transistor MN101, can cancel out the threshold voltages of the NMOS transistors MN100 and MN101.

[0081] The difference between current source circuit 200a, which serves as the second current source circuit, and current source circuit 100a is the same as the difference between current source circuit 200 and current source circuit 100, and therefore, description thereof will be omitted. According to the oscillation circuit of this embodiment, the current source circuit 100a includes an NMOS transistor MN101 that does not produce a substrate bias effect, and the current source circuit 200a includes an NMOS transistor MN201 that does not produce a substrate bias effect, thereby reducing the influence of temperature.

[0082] As described above, according to the oscillation circuit of this embodiment, an oscillation circuit having a small circuit scale and low power consumption can be obtained.

[0083] Furthermore, the present invention is not limited to the above-described embodiments. In practice, the present invention may be implemented in various ways other than the above-described examples, and various omissions, substitutions, and modifications may be made without departing from the gist of the invention. For example, each switch described in the embodiments of the invention may be composed of a PMOS transistor or an NMOS transistor. These embodiments and their variations are included within the scope and gist of the invention and are encompassed by the invention set forth in the claims and their equivalents.

[0084]

Number Description

[0085] 1: Oscillation circuit; 25: Resistor; 30, 31: Capacitor; 40: RS latch; 100, 100a, 200, 200a: Current source circuit; 110, 210: Startup circuit; 300, 400: Comparator circuit; ENIN: Enable signal input terminal.

Claims

1. An oscillation circuit, characterized in that: The device comprises a first current source circuit, a second current source circuit, a resistor, a first capacitor, a second capacitor, a first comparison circuit, a second comparison circuit, and an RS latch. inputting the output current of the second current source circuit to the first capacitor or the second capacitor according to the signal level of the output signal of the RS latch, inputting a reference voltage determined by the output current of the first current source circuit and the resistance value of the resistor and the voltage of the first capacitor into the first comparison circuit, inputting the reference voltage and the voltage of the second capacitor into the second comparison circuit, inputting a signal output from the first comparison circuit and a signal output from the second comparison circuit into the RS latch, The first current source circuit and the second current source circuit have an enable signal input terminal and a startup circuit. The activation signal of the activation circuit of the first current source circuit is output before the activation signal of the activation circuit of the second current source circuit is output.

2. The oscillator circuit according to claim 1, wherein: The first current source circuit and the second current source circuit have the same output current change with respect to temperature change.

3. The oscillator circuit according to claim 2, wherein: The first current source circuit and the second current source circuit include a micro-current source having a transistor operating in a weak inversion region.

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