A self-switching well switch circuit

Abstract

The present invention discloses a self-switching well switch circuit, including a first high-voltage PMOS tube, the first high-voltage PMOS tube is connected in series with an ISW ​​signal interface, the first high-voltage PMOS tube is connected in parallel with a second high-voltage PMOS tube and a third high-voltage PMOS tube, and the second high-voltage PMOS tube is connected in series with an INP signal interface. The present invention uses only one switch tube to realize the opening of a high-side switch. Compared with the high-side switch turned on by ordinary current, only 1 / 4 of the switch tube area is required to achieve the same on-resistance. At the same time, the switch can automatically complete the switching of the well potential, that is, the well potential can follow the higher voltage in the input / output, and there is no shutoff leakage current. The circuit can be turned on in proportion to the VGS of the current-controlled switch, thereby improving the channel matching and temperature characteristics of each current-controlled switch, and has a simple structure and reduces manufacturing costs.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, in particular to a self-switching well switch circuit. Background Art

[0002] With the rapid development of science and technology, my country's various industries have made great progress, and the requirements for various industries have become more and more stringent. For the use of power management chips, sometimes a high-side switch is required. The switch can be used to transmit high-voltage signals and can also be used as a switch tube to control the circuit. The high-side switch must have an anti-backflow function. Because the voltage at both ends of the switch is uncertain, the high-side switch is required to have no leakage when the voltage at both ends is inconsistent. A typical application is the switch tube in Boost, whose well potential can be switched to prevent leakage.

[0003] Although the existing switches can realize the high-side switch function, the disadvantage is that if you want to achieve equal on-resistance, you need to use four times the area of ​​a single tube with the same on-resistance. If the common-mode voltage of the high-side switch is very high, the four times area is very considerable, which will greatly increase the chip area and increase the cost. Summary of the invention

[0004] The object of the present invention is to provide a self-switching well switch circuit to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a self-switching well switch circuit, comprising a first high-voltage PMOS tube, the first high-voltage PMOS tube is connected in series with an ISW ​​signal interface, the first high-voltage PMOS tube gate is connected in parallel with a first resistor, the first high-voltage PMOS tube is connected in parallel with a second high-voltage PMOS tube and a third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in series with the third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in parallel with a first diode, the second high-voltage PMOS tube gate is connected in series with a third resistor, the third resistor is connected in series with the third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in series with an INP signal interface, the third high-voltage PMOS tube is connected in parallel with a second diode, the third high-voltage PMOS tube is connected in series with a second resistor, the second resistor is connected in series with the second high-voltage PMOS tube, and the high-voltage PMOS tube is connected in series with an INN signal interface.

[0006] Furthermore, the first high-voltage PMOS tube is a high-voltage PMOS tube with a symmetrical structure, which is a MOS tube that can transport current through the flow of holes.

[0007] Furthermore, the second high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure, which is a MOS tube that can transport current through the flow of holes.

[0008] Furthermore, the third high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure, which is a MOS tube that can transport current through the flow of holes.

[0009] Furthermore, the first diode is the body diode of the second high-voltage PMOS tube. Before the VDD overvoltage causes damage to the second high-voltage PMOS tube, the first diode first breaks down in reverse to provide a bias voltage for the body of P1. ISW will draw a constant current to the ground without a large current. The ISW current biases the gate voltage of P1 to ensure that P1 is turned on.

[0010] Furthermore, the second diode is the body diode of the third high-voltage PMOS tube. Before the VDD overvoltage causes damage to the third high-voltage PMOS tube, the second diode first reversely breaks down to provide a bias voltage for the body of P2. ISW will draw a constant current to the ground without a large current. The ISW current biases the gate voltage of P2 to ensure that P2 is turned on.

[0011] Further, the first high-voltage PMOS tube is P1, the second high-voltage PMOS tube is P2, the third high-voltage PMOS tube is P3, the first resistor is R1, the second resistor is R2, the first diode is DP2, and the second diode is DP3.

[0012] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0013] 1. The present invention uses only one switch tube to realize the opening of the high-side switch. Compared with the high-side switch turned on by ordinary current, only 1 / 4 of the switch tube area is required to achieve the same on-resistance. At the same time, the switch can automatically complete the switching of the well potential, that is, the well potential can follow the higher voltage in the input / output, and there is no shut-off leakage current. In addition, the circuit can realize the proportional opening of the VGS of the current-controlled switch, thereby improving the channel matching and temperature characteristics of each current-controlled switch. The structure is simple and the manufacturing cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0015] Figure 1 is a circuit array block diagram of the present invention as a whole; DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] See also Figure 1 The present invention provides a technical solution: a self-switching well switch circuit, comprising a first high-voltage PMOS tube, the first high-voltage PMOS tube is connected in series with an ISW ​​signal interface, the first high-voltage PMOS tube gate is connected in parallel with a first resistor, the first high-voltage PMOS tube is connected in parallel with a second high-voltage PMOS tube and a third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in series with the third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in parallel with a first diode, the second high-voltage PMOS tube gate is connected in series with a third resistor, the third resistor is connected in series with the third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in series with an INP signal interface, the third high-voltage PMOS tube is connected in parallel with a second diode, the third high-voltage PMOS tube is connected in series with a second resistor, the second resistor is connected in series with the second high-voltage PMOS tube, and the high-voltage PMOS tube is connected in series with an INN signal interface.

[0018] The first high-voltage PMOS tube is a high-voltage PMOS tube with a symmetrical structure, which is a MOS tube that can transport current through the flow of holes.

[0019] The second high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure, which is a MOS tube that can carry current through the flow of holes.

[0020] The third high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure, which is a MOS tube that can transport current through the flow of holes.

[0021] The first diode is the body diode of the second high-voltage PMOS tube. Before the VDD overvoltage damages the second high-voltage PMOS tube, the first diode first breaks down in reverse to provide a bias voltage for the body of P1. ISW will draw a constant current to the ground without a large current. The ISW current biases the gate voltage of P1 to ensure that P1 is turned on.

[0022] The second diode is the body diode of the third high-voltage PMOS tube. Before the VDD overvoltage damages the third high-voltage PMOS tube, the second diode first breaks down in reverse to provide a bias voltage for the body of P2. ISW will draw a constant current to the ground without a large current. The ISW current biases the gate voltage of P2 to ensure that P2 is turned on.

[0023] The first high-voltage PMOS tube is P1, the second high-voltage PMOS tube is P2, the third high-voltage PMOS tube is P3, the first resistor is R1, the second resistor is R2, the first diode is DP2, and the second diode is DP3.

[0024] The specific implementation method is as follows: when in use, since P1, P2, and P3 are all thin-gate oxide tubes, and the INP and INN voltages are uncertain, the switch is turned on in a current-on manner, and the current ISW flows through R1 to form a voltage drop, turning on P1 to achieve switch conduction. First, it is assumed that the INP voltage is higher than INN. At this time, due to the existence of the P2 tube body diode, the voltage of the node N1 is close to the voltage of INP. At this time, if ISW has no current, the body voltage of the P1 tube is INP. At this time, due to the absence of ISW current, the source terminal voltage and the gate terminal voltage of P1 are equal to the body voltage, P1 is turned off, and no leakage current is generated; and when the switch tube needs to be turned on, ISW draws a current ISW, and ISW flows through R1 to form a voltage drop. Since the N1 node voltage is INP, and the P2 tube gate voltage is the INN voltage, when the INP and INN voltage difference is large, P2 is in a linear on state, and the ISW current flows from INP through the P2 channel and then through R1 to form a voltage drop VON, and the R1 resistance value and the ISW current value are adjusted. When VON is greater than the P1 turn-on voltage, P1 is turned on; conversely, when INN is higher than INP, due to the presence of the P3 tube body diode, the voltage of node N1 is close to the voltage of INN. At this time, if ISW has no current, the body voltage of P1 is INN. At this time, due to the absence of ISW current, the source terminal voltage and gate terminal voltage of P1 are equal to the body voltage, P1 is turned off, and no leakage current is generated; and when the switch tube needs to be turned on, ISW draws a current ISW, and ISW flows through R1 to form an electric Voltage drop. Since the voltage of N1 node is INN, and the gate voltage of P3 is INP voltage, P3 is in linear on state when the voltage difference between INN and INP is large. ISW current flows from INN through the channel of P3 and then through R1 to form voltage drop VON. Adjust the resistance value of R1 and the ISW current value. When VON is greater than the turn-on voltage of P1, P1 is turned on. When changing, stable shutdown can also be guaranteed without leakage. Take INP as an example where INN is first higher than INN and then INN is higher than INP to describe the change process.In the stage where INP is higher than INN, the voltage of node N1 is the INP voltage, and one end of INP is the source of P1. At this time, the positive electrode of the parasitic body diode is INN, and the negative electrode is connected to INP. At this time, P1 is turned off. Since INP is higher than INN, this diode is in a reverse biased state and no leakage will occur. After that, the potentials of INP and INN are exchanged, and INN is higher than INP. At this time, since the parasitic diode cannot reverse immediately, there will be a little leakage, but since the N1 voltage is still the voltage INP` before INP, and at this time the INP on the gate voltage of P3 is already lower than the voltage of INP`, the P3 tube is turned on, and at this moment the N1 node voltage quickly becomes the voltage of INN, and the P1 tube also completes the well potential The positive pole of the parasitic diode is connected to INP and the negative pole is connected to INN. Since INN is higher than INP, a reverse-biased diode is formed. At this time, the switch state is stable and no leakage occurs. This circuit uses only one switch tube to realize the opening of the high-side switch. Compared with the high-side switch turned on by ordinary current, only 1 / 4 of the switch tube area is required to achieve the same on-resistance. At the same time, the switch can automatically complete the switching of the well potential, that is, the well potential can follow the higher voltage in the input / output, and there is no shut-off leakage current. In addition, the circuit can realize the VGS proportional opening of the current-controlled switch, improve the channel matching and temperature characteristics of each current-controlled switch, and has a simple structure and reduces manufacturing costs. ;

[0025] Working principle of the present invention:

[0026] Refer to the instruction manual Figure 1 The present invention uses only one switch tube to realize the opening of the high-side switch. Compared with the high-side switch turned on by ordinary current, only 1 / 4 of the switch tube area is required to achieve the same on-resistance. At the same time, the switch can automatically complete the switching of the well potential, that is, the well potential can follow the higher voltage in the input / output, and there is no shut-off leakage current. Moreover, the circuit can realize the proportional opening of the VGS of the current-controlled switch, thereby improving the channel matching and temperature characteristics of each current-controlled switch. The structure is simple and the manufacturing cost is reduced.

[0027] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0028] Finally, it should be noted that the above is only a preferred embodiment of the present invention. If all PMOS are replaced with NMOS, the circuit is also established, and it is not used to limit the present invention. Although the present invention is described in detail with reference to the above embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A self-switching well switch circuit, comprising a first high-voltage PMOS tube, characterized in that: The gate of the first high-voltage PMOS tube is connected to the ISW signal interface, the gate of the first high-voltage PMOS tube is connected to the first end of the first resistor, the second end of the first resistor is connected to the substrate of the first high-voltage PMOS tube, the first end of the first high-voltage PMOS tube is connected to the first end of the second high-voltage PMOS tube, the second end of the first high-voltage PMOS tube is connected to the first end of the third high-voltage PMOS tube, and the second end of the second high-voltage PMOS tube and the second end of the third high-voltage PMOS tube are connected to the substrate of the first high-voltage PMOS tube, the second end of the second high-voltage PMOS tube is connected to the second end of the third high-voltage PMOS tube, and the first end of the second high-voltage PMOS tube is connected to the anode of the first diode. The cathode of the first diode is connected to the second end of the second high-voltage PMOS tube, the gate of the second high-voltage PMOS tube is connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the third high-voltage PMOS tube, the first end of the second high-voltage PMOS tube is connected to the INP signal interface, the first end of the third high-voltage PMOS tube is connected to the anode of the second diode, the cathode of the second diode is connected to the second end of the third high-voltage PMOS tube, the gate of the third high-voltage PMOS tube is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the second high-voltage PMOS tube, and the first end of the third high-voltage PMOS tube is connected to the INN signal interface; The first high-voltage PMOS tube is a high-voltage PMOS tube with a symmetrical structure; The second high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure; The first high-voltage PMOS tube is P1, the second high-voltage PMOS tube is P2, the third high-voltage PMOS tube is P3, the first resistor is R1, the second resistor is R2, the first diode is DP2, and the second diode is DP3.

2. A self-switching well switch circuit according to claim 1, characterized in that: The third high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure.

3. The self-switching well switch circuit according to claim 1, characterized in that: The first diode is a body diode of the second high-voltage PMOS tube.

4. The self-switching well switch circuit according to claim 1, characterized in that: The second diode is a body diode of the third high-voltage PMOS tube.

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