Level conversion circuit, PCB and chip
By shaping the waveform of the shaping unit, increasing the voltage of the boost unit, and suppressing the transient negative voltage of the suppression unit, the problem of signal mis-triggering in the traditional level conversion circuit is solved, and the stable and accurate transmission of the signal in different voltage environments is achieved.
Patent Information
- Application Number
- CN202510701366.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-09-05
AI Technical Summary
Traditional level conversion circuits generate transient negative voltage spikes during the level rise process, resulting in signal mis-triggering and logic disorder, limiting their application in high-speed, high-reliability scenarios.
The shaping unit is used to shape the waveform of the input signal, the boost unit boosts the signal to the target operating voltage, the conversion unit performs level conversion, and the suppression unit suppresses transient negative voltage spikes.
Ensure stable transmission and accuracy of signals in different voltage environments, avoid transient negative voltage spikes exceeding the logic threshold of downstream circuits, and improve the stability and accuracy of level conversion.
Smart Images
Figure CN120601879A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a level conversion circuit, a PCB board and a chip. Background Art
[0002] In integrated circuit design, level conversion circuits are used to achieve signal transmission between different voltage domains and are key modules in systems such as high-speed interfaces and power management. Traditional level conversion circuits typically use a combination of inverters and latches to achieve level conversion through phase adjustment and state latching. However, due to the coupling between circuit parasitic parameters and switching timing, the output of traditional level conversion circuits will generate transient negative voltage spikes during the level rise process. The transient negative voltage may exceed the logic threshold of the downstream circuit, causing the signal to be falsely triggered, resulting in disordered circuit timing logic and even functional abnormalities, which seriously restricts its application in high-speed, high-reliability scenarios. Summary of the Invention
[0003] The present invention aims to improve at least one technical problem in the background technology.
[0004] A first aspect of the present invention provides an embodiment of a level conversion circuit, comprising: a shaping unit, a boosting unit, a conversion unit and a suppression unit; the shaping unit is electrically connected to the boosting unit, the boosting unit is electrically connected to the conversion unit and the suppression unit, and the conversion unit is electrically connected to the suppression unit; the shaping unit is used to perform waveform shaping on an input signal, the boosting unit is used to boost the high level of the input signal to a target operating voltage, the conversion unit is used to convert the input signal into a level signal, and the suppression unit is used to suppress transient negative voltage spikes generated during the level conversion process.
[0005] The beneficial effects of the present invention are as follows: in the level conversion circuit of the present invention, the shaping unit first shapes the waveform of the input signal to remove noise interference, make the signal more regular, and provide high-quality input for subsequent processing; then the boost unit is used to increase the high level of the input signal to the target operating voltage to achieve adaptation to different voltage domains. On this basis, the conversion unit can convert the input signal into a level signal that meets the requirements of the target voltage domain, ensuring stable transmission of the signal under different voltage environments; the suppression unit effectively suppresses the transient negative voltage spike generated in the level conversion to prevent it from exceeding the logic threshold of the downstream circuit, thereby ensuring the accuracy and stability of the signal during the level conversion process.
[0006] As some sub-solutions of the above technical solution, the shaping unit includes a first shaping part and a second shaping part, the output end of the first shaping part is connected to the input end of the second shaping part, and the output end of the second shaping part is electrically connected to the boost unit.
[0007] As some sub-solutions of the above technical solution, the first shaping part includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3 and a fourth field effect transistor M4; the second shaping part includes a fifth field effect transistor M5 and a sixth field effect transistor M6; the gates of the first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3 and the fourth field effect transistor M4 are all connected to the input signal terminal IN, the source of the first field effect transistor M1 is connected to the low voltage terminal VREG, the drain of the first field effect transistor M1 is connected to the source of the second field effect transistor M2 and The source of the fifth field effect transistor M5 is connected; the drain of the second field effect transistor M2 is connected to the drain of the third field effect transistor M3, the gate of the fifth field effect transistor M5, the gate of the sixth field effect transistor M6 and the boost unit; the source of the third field effect transistor M3 is connected to the drain of the fourth field effect transistor M4 and the source of the sixth field effect transistor M6; the source of the fourth field effect transistor M4 is connected to the ground terminal VSS; the drain of the fifth field effect transistor M5 is connected to the ground terminal VSS, and the drain of the sixth field effect transistor M6 is connected to the low voltage terminal VREG.
[0008] As some sub-solutions of the above technical solution, the boost unit includes a first diode D1, a second diode D2, a first capacitor C1 and a second capacitor C2; the anode of the first diode D1 is connected to the low voltage terminal VREG, the cathode of the first diode D1 is connected to one end of the first capacitor C1 and the anode of the second diode D2; the other end of the first capacitor C1 is connected to the gate of the fifth field-effect transistor M5; the cathode of the second diode D2 is connected to one end of the second capacitor C2, the conversion unit and the suppression unit, and the other end of the second capacitor C2 is connected to the ground terminal VSS.
[0009] As some sub-solutions of the above technical solution, the conversion unit includes an inverting part and a latch part; the input end of the inverting part is connected to the boosting unit, and the output end of the inverting part is connected to the input end of the latch part; the input end of the latch part is connected to the boosting unit, and the output end of the latch part is connected to the inhibition unit.
[0010] As some sub-solutions of the above technical solution, the inverting part includes a seventh field effect transistor M7 and an eighth field effect transistor M8; the latch part includes a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11 and a twelfth field effect transistor M12; the source of the seventh field effect transistor M7 is connected to the low voltage terminal VREG, the gate of the seventh field effect transistor M7 is connected to the cathode of the second diode D2, the gate of the eighth field effect transistor M8, the gate of the eleventh field effect transistor M11 and the suppression unit; the drain of the seventh field effect transistor M7 is connected to the drain of the eighth field effect transistor M8 and the drain of the twelfth field effect transistor M11 2; the source of the eighth field effect transistor M8 is connected to the ground terminal VSS; the drain of the ninth field effect transistor M9 and the source of the tenth field effect transistor M10 are connected to the high voltage terminal VCC, the gate of the ninth field effect transistor M9 is connected to the drain of the tenth field effect transistor M10, the drain of the twelfth field effect transistor M12, the suppression unit and the output signal terminal OUT; the source of the ninth field effect transistor M9 is connected to the gate of the tenth field effect transistor M10 and the drain of the eleventh field effect transistor; the source of the eleventh field effect transistor M11 and the source of the twelfth field effect transistor M12 are connected to the ground terminal VSS.
[0011] As some sub-solutions of the above technical solution, the suppression unit includes an acceleration part and a suppression part; the acceleration part is connected to the cathode of the second diode D2, the drain of the tenth field effect transistor M10 and the output end OUT; the suppression part is connected to the drain of the tenth field effect transistor M10.
[0012] As some sub-solutions of the above technical solution, the acceleration unit includes a thirteenth field-effect transistor M13; the suppression unit includes a first resistor R1 and a third capacitor C3; the gate of the thirteenth field-effect transistor M13 is connected to the cathode of the second diode D2, the drain of the thirteenth field-effect transistor M13 is connected to one end of the first resistor R1 and the output signal end OUT, and the source of the thirteenth field-effect transistor M13 is connected to the ground end VSS; the other end of the first resistor R1 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the ground end VSS.
[0013] A second aspect of the present invention provides a PCB board, on which any level conversion circuit as described above is printed.
[0014] The PCB board according to the embodiment of the second aspect of the present invention also has corresponding beneficial effects because it includes the level conversion circuit of the above technical solution.
[0015] A third aspect of the present invention provides a chip, which uses any of the above-mentioned level conversion circuits to achieve operation control.
[0016] The chip according to the embodiment of the third aspect of the present invention also has corresponding beneficial effects because it includes the level conversion circuit of the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:
[0018] Figure 1 A circuit block diagram of the level conversion circuit provided by the present invention;
[0019] Figure 2 This is an application circuit diagram of the level conversion circuit provided by the present invention.
[0020] In the accompanying drawings: 1-shaping unit; 11-first shaping part; 12-second shaping part; 2-boosting unit; 3-conversion unit; 31-inverting part; 32-latch part; 4-suppression unit; 41-acceleration part; 42-suppression part. DETAILED DESCRIPTION
[0021] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.
[0022] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.
[0023] In the description of the present invention, "several" means an indefinite quantity, "multiple" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, and "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" is solely for the purpose of distinguishing technical features and should not be understood to indicate or imply relative importance, or to implicitly indicate the number or order of the technical features indicated. "And / or" throughout the text represents three parallel solutions. For example, "A and / or B" means a solution where A satisfies, a solution where B satisfies, or a solution where both A and B satisfy.
[0024] In the description of the present invention, if there is a short sentence containing multiple parallel features, the attributive defines the closest feature. For example, "B, C, and E are arranged on A, and are connected to D" means that B is arranged on A and E is connected to D, and does not constitute a limitation on C. However, attributives that express the relationship between features, such as "spaced arrangement" or "circular arrangement", do not fall into this category. If the word "all" is preceded by an attributive, it means that all features in the short sentence are limited. For example, "B, C, and D are all arranged on A" means that B, C, and D are all arranged on A. In a sentence with an omitted subject, the omitted subject is the subject of the previous sentence, that is, "B is arranged on A, including C" means that B is arranged on A and A includes C.
[0025] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.
[0026] The following combination Figures 1 to 2 Embodiments of the present invention are described.
[0027] A level conversion circuit in this embodiment includes: a shaping unit 1, a boost unit 2, a conversion unit 3 and a suppression unit 4; the shaping unit 1 is electrically connected to the boost unit 2, the boost unit 2 is electrically connected to the conversion unit 3 and the suppression unit 4, and the conversion unit 3 is electrically connected to the suppression unit 4; the shaping unit 1 is used to shape the waveform of the input signal, the boost unit 2 is used to boost the high level of the input signal to a target operating voltage, the conversion unit 3 is used to convert the input signal into a level signal, and the suppression unit 4 is used to suppress transient negative voltage spikes generated during the level conversion process.
[0028] In the level conversion circuit of the present invention, the shaping unit 1 first shapes the waveform of the input signal to remove noise interference, make the signal more regular, and provide high-quality input for subsequent processing; then the boost unit 2 is used to raise the high level of the input signal to the target operating voltage to achieve adaptation to different voltage domains. On this basis, the conversion unit 3 can convert the input signal into a level signal that meets the requirements of the target voltage domain, ensuring stable transmission of the signal under different voltage environments; the suppression unit 4 effectively suppresses the transient negative voltage spike generated in the level conversion to prevent it from exceeding the logic threshold of the downstream circuit, thereby ensuring the accuracy and stability of the signal during the level conversion process.
[0029] Specifically, the shaping unit 1 includes a first shaping part 11 and a second shaping part 12 , the output end of the first shaping part 11 is connected to the input end of the second shaping part 12 , and the output end of the second shaping part 12 is electrically connected to the boost unit 2 .
[0030] Specifically, the first shaping unit 11 includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3 and a fourth field effect transistor M4; the second shaping unit 12 includes a fifth field effect transistor M5 and a sixth field effect transistor M6; the gates of the first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3 and the fourth field effect transistor M4 are all connected to the input signal terminal IN, the source of the first field effect transistor M1 is connected to the low voltage terminal VREG, the drain of the first field effect transistor M1 is connected to the source of the second field effect transistor M2 and the drain of the fifth field effect transistor M6. The source of the field effect transistor M5 is connected; the drain of the second field effect transistor M2 is connected to the drain of the third field effect transistor M3, the gate of the fifth field effect transistor M5, the gate of the sixth field effect transistor M6 and the boost unit 2; the source of the third field effect transistor M3 is connected to the drain of the fourth field effect transistor M4 and the source of the sixth field effect transistor M6; the source of the fourth field effect transistor M4 is connected to the ground terminal VSS; the drain of the fifth field effect transistor M5 is connected to the ground terminal VSS, and the drain of the sixth field effect transistor M6 is connected to the low voltage terminal VREG.
[0031] Specifically, when the input signal changes from 0 to 1, the working process of the shaping unit 1 is:
[0032] When the input signal is 0, the first field effect transistor M1 and the second field effect transistor M2 are turned on, and the third field effect transistor M3 and the fourth field effect transistor M4 are turned off. Since the first field effect transistor M1 is turned on, its source is connected to the low voltage terminal VREG, and current flows from VREG through the first field effect transistor M1 to its drain, making the source potential of the second field effect transistor M2 and the source potential of the fifth field effect transistor M5 close to the low voltage terminal VREG. At the same time, the drain potential of the sixth field effect transistor M6 is also close to the low voltage terminal VREG. At this time, the output level is the level signal of the low voltage terminal VREG; when the input signal starts to change from 0 to 1, the fourth field effect transistor M4 first meets the conduction condition and turns on. Because the source of the fourth field effect transistor M4 is connected to the ground terminal VSS, its conduction will cause the third field effect transistor M4 to turn on. The source potential of the transistor M3 decreases; as the input signal continues to increase, the gate-source voltage of the third field-effect transistor M3 gradually increases, and the third field-effect transistor M3 gradually turns on; when the third field-effect transistor M3 is fully turned on, the drain potential of the third field-effect transistor M3 is pulled down, and this low potential causes the gate potential of the fifth field-effect transistor M5 to decrease, turning the fifth field-effect transistor M5 on; at the same time, the gate potential of the sixth field-effect transistor M6 also decreases, turning the sixth field-effect transistor M6 off; at this time, the drain of the fifth field-effect transistor M5 is connected to the ground terminal VSS, and the output level is flipped from the level signal of the low voltage terminal VREG to the level signal of the ground terminal VSS;
[0033] When the input signal is 1, the first field effect transistor M1 and the second field effect transistor M2 are turned off, and the third field effect transistor M3 and the fourth field effect transistor M4 are turned on, so that the gate potential of the fifth field effect transistor M5 is higher, and the fifth field effect transistor M5 is turned off; and the gate potential of the sixth field effect transistor M6 is higher, and the sixth field effect transistor M6 is turned on. The drain of the sixth field-effect transistor M6 is connected to the low-voltage terminal VREG, and the output level is a signal at the ground terminal VSS. When the input signal begins to change from 1 to 0, the first field-effect transistor M1 first meets the conduction condition and turns on. Since the source of the first field-effect transistor M1 is connected to the low-voltage terminal VREG, its conduction causes the source potential of the second field-effect transistor M2 and the source potential of the fifth field-effect transistor M5 to increase. As the input signal continues to decrease, the gate voltage of the second field-effect transistor M2 gradually increases, and the second field-effect transistor M2 gradually turns on. When the second field-effect transistor M2 is fully turned on, the drain potential of the second field-effect transistor M2 is pulled high. This high potential increases the gate potential of the fifth field-effect transistor M5, eventually turning off the fifth field-effect transistor M5. At the same time, the gate potential of the sixth field-effect transistor M6 also increases, turning on the sixth field-effect transistor M6. At this time, because the drain of the sixth field-effect transistor M6 is connected to the low-voltage terminal VREG, the output level flips from the ground terminal VSS to the low-voltage terminal VREG.
[0034] In the process of the input signal changing from 0 to 1 and from 1 to 0, different flip thresholds are achieved through the conduction sequence and state changes of the first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3, the fourth field effect transistor M4, the fifth field effect transistor M5 and the sixth field effect transistor M6, so that the shaping unit 1 can effectively suppress noise and interference in the input signal;
[0035] The shaping unit 1 shapes the input signal, making the rising and falling edges of the signal steeper and the high and low levels clearer. At the same time, it removes burrs and irregular fluctuations in the signal, making the signal waveform more standard, and providing a good working foundation for the boost unit 2 and the suppression unit 4.
[0036] Specifically, the boost unit 2 includes a first diode D1, a second diode D2, a first capacitor C1 and a second capacitor C2; the anode of the first diode D1 is connected to the low voltage terminal VREG, the cathode of the first diode D1 is connected to one end of the first capacitor C1 and the anode of the second diode D2; the other end of the first capacitor C1 is connected to the gate of the fifth field effect transistor M5; the cathode of the second diode D2 is connected to one end of the second capacitor C2, the conversion unit 3 and the suppression unit 4, and the other end of the second capacitor C2 is connected to the ground terminal VSS.
[0037] The working principle of boost unit 2 is as follows:
[0038] The first diode D1, the second diode D2, the first capacitor C1 and the second capacitor C2 form a diode-capacitor charge pump structure;
[0039] When the input signal is at a low level, the gate voltage of the fifth field effect transistor M5 of the shaping unit 1 is low, and the fifth field effect transistor M5 is turned on. At this time, the first diode D1 is turned on, and the low voltage terminal VREG charges the first capacitor C1 through the first diode D1. The voltage on the upper plate of the first capacitor C1 rises rapidly to a high level, and the voltage on the lower plate of the first capacitor C1 is at a low level. At this time, the voltage difference between the upper and lower plates of the first capacitor C1 can be regarded as the voltage of the low voltage terminal VREG.
[0040] When the input signal jumps from a low level to a high level, the first field-effect transistor M1 of the shaping unit 1 is turned off, the second field-effect transistor M2 is turned on, and the gate voltage of the fifth field-effect transistor M5 increases as the input signal rises, thereby driving the voltage of the lower plate of the first capacitor C1 to increase; since the voltage across the first capacitor C1 cannot change suddenly, the voltage on the upper plate of the first capacitor C1 synchronously increases to VREG+ΔV; at this time, the second diode D2 is turned on, and the charge on the upper plate of the first capacitor C1 is transferred to the second capacitor C2 through the second diode D2, and the voltage across the second capacitor C2 is increased; finally, the cathode voltage of the second diode D2 is stabilized at the low voltage terminal VREG voltage + input high level voltage, realizing low voltage to high voltage conversion;
[0041] The second capacitor C2 acts as an energy storage capacitor, smoothing output voltage fluctuations during the charge transfer process, ensuring that the conversion unit 3 and the suppression unit 4 receive stable high-voltage inputs. Even if the input signal has certain noise or fluctuations, the boost unit 2 can still maintain the stability of the output voltage through the cumulative effect of the charge pump, providing a reliable voltage foundation for subsequent level conversion.
[0042] The boost unit 2 of the present invention uses a capacitive charge transfer mechanism and does not require a multi-stage inverter or level shifter cascade. A single stage can boost a low voltage input to a target high voltage. Compared with the traditional multi-stage cascade solution, it reduces chip area, lowers power consumption, and shortens signal delay.
[0043] Specifically, the conversion unit 3 includes an inverting part 31 and a latch part 32; the input end of the inverting part 31 is connected to the boost unit 2, and the output end of the inverting part 31 is connected to the input end of the latch part 32; the input end of the latch part 32 is connected to the boost unit 2, and the output end of the latch part 32 is connected to the suppression unit 4.
[0044] Specifically, the inverting unit 31 includes a seventh field effect transistor M7 and an eighth field effect transistor M8; the latch unit 32 includes a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, and a twelfth field effect transistor M12; the source of the seventh field effect transistor M7 is connected to the low voltage terminal VREG, the gate of the seventh field effect transistor M7 is connected to the cathode of the second diode D2, the gate of the eighth field effect transistor M8, the gate of the eleventh field effect transistor M11, and the suppression unit 4; the drain of the seventh field effect transistor M7 is connected to the drain of the eighth field effect transistor M8 and the gate of the twelfth field effect transistor M12 The eighth field effect transistor M8 is connected; the source of the eighth field effect transistor M8 is connected to the ground terminal VSS; the drain of the ninth field effect transistor M9 and the source of the tenth field effect transistor M10 are connected to the high voltage terminal VCC, the gate of the ninth field effect transistor M9 is connected to the drain of the tenth field effect transistor M10, the drain of the twelfth field effect transistor M12, the suppression unit 4 and the output signal terminal OUT; the source of the ninth field effect transistor M9 is connected to the gate of the tenth field effect transistor M10 and the drain of the eleventh field effect transistor; the source of the eleventh field effect transistor M11 and the source of the twelfth field effect transistor M12 are connected to the ground terminal VSS.
[0045] The inverting unit 31, as a pre-processing module of the conversion unit 3, directly receives the high-voltage signal output by the boosting unit 2, performs phase adjustment on the boosted signal, and provides a trigger signal for the latch unit 32. When the boosting unit 2 outputs a high level, the gate voltage of the seventh field-effect transistor M7 is higher than its threshold voltage. Since the seventh field-effect transistor M7 is a PMOS transistor, it will be cut off. The gate voltage of the eighth field-effect transistor M8 is higher than the threshold voltage. Since the eighth field-effect transistor M8 is an NMOS transistor, it will be turned on and output a low level to the phase-locked unit. Conversely, when the boosting unit 2 outputs a low level, the seventh field-effect transistor M7 is turned on and the eighth field-effect transistor M8 is turned off, and the inverting unit 31 outputs a high level to the phase-locked unit. Through the "voltage follower-inverting" characteristic of the inverting unit 31, the high-voltage signal of the boosting unit 2 is converted into a complementary signal suitable for processing by the latch unit 32, ensuring that the trigger signal of the latch unit 32 is inversely proportional to the input signal, providing a clear logic level for subsequent latching actions.
[0046] The latch section 32 adopts a cross-coupling structure to achieve stable level conversion from the low voltage domain to the high voltage domain. Specifically:
[0047] When the boost unit 2 outputs a high level, the inverting part 31 outputs a low level, turning off the eleventh field effect transistor M11 and turning on the twelfth field effect transistor M12. After the twelfth field effect transistor M12 is turned on, the drain of the tenth field effect transistor M10 is pulled down to ground, turning on the ninth field effect transistor M9. The turned-on ninth field effect transistor M9 pulls the output signal terminal OUT up to the level signal of the high voltage terminal VC C, completing the low-to-high level conversion.
[0048] Conversely, when the boost unit 2 outputs a low level, the inverting unit 31 outputs a high level, turning on the eleventh field-effect transistor M11 and turning off the twelfth field-effect transistor M12. After the eleventh field-effect transistor M11 is turned on, it pulls the source of the ninth field-effect transistor M9 to ground, turning on the tenth field-effect transistor M10. The turned-on tenth field-effect transistor M10 pulls the output signal terminal OUT down to 0V, completing the conversion from high level to low level.
[0049] Furthermore, the drain of the ninth field-effect transistor M9 and the source of the tenth field-effect transistor M10 are directly connected to the high-voltage terminal VCC, so that the latch unit 32 can operate stably under high voltage, avoiding driving failure caused by insufficient input voltage in traditional solutions; and the source of the seventh field-effect transistor M7 of the inverting unit 31 is connected to the low-voltage terminal VREG; the inverting unit 31 and the phase-locked unit form a "low-voltage input-high-voltage output" cross-voltage domain conversion, which can cover a wide voltage range using only a single-stage circuit without the need for multi-stage cascade.
[0050] Specifically, the suppression unit 4 includes an acceleration part 41 and a suppression part 42; the acceleration part 41 is connected to the cathode of the second diode D2, the drain of the tenth field effect transistor M10 and the output end OUT; the suppression part 42 is connected to the drain of the tenth field effect transistor M10.
[0051] Specifically, the acceleration unit 41 includes a thirteenth field-effect transistor M13; the suppression unit 42 includes a first resistor R1 and a third capacitor C3; the gate of the thirteenth field-effect transistor M13 is connected to the cathode of the second diode D2, the drain of the thirteenth field-effect transistor M13 is connected to one end of the first resistor R1 and the output signal end OUT, and the source of the thirteenth field-effect transistor M13 is connected to the ground end VSS; the other end of the first resistor R1 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the ground end VSS.
[0052] Specifically, the working principle of the suppression unit 42 is as follows: in the initial stage of level conversion, a transient negative voltage spike is generated; at this time, the first resistor R1 and the third capacitor C3 of the suppression unit 42 form an RC low-pass filter circuit; when a negative voltage spike appears at the output signal terminal OUT, the third capacitor C3 is charged or discharged through the first resistor R1. Since the voltage across the capacitor cannot change suddenly, the third capacitor C3 absorbs part of the energy of the negative voltage spike and stores it in the capacitor; the first resistor R1 acts to limit the current, preventing excessive current from damaging the circuit; in this way, the first resistor R1 and the third capacitor C3 can effectively smooth the waveform of the output signal, suppress the transient negative voltage spike, and reduce interference with subsequent circuits;
[0053] Specifically, the operating principle of the acceleration unit 41 is as follows: the gate of the thirteenth field-effect transistor M13 is connected to the cathode of the second diode D2 of the boost unit 2, allowing the thirteenth field-effect transistor M13 to sense the high-voltage signal output by the boost unit 2. When the level conversion is nearly complete and the target level needs to be quickly established, the high-voltage signal output by the boost unit 2 causes the gate voltage of the thirteenth field-effect transistor M13 to increase. When the gate voltage exceeds the threshold voltage of the thirteenth field-effect transistor M13, the thirteenth field-effect transistor M13 turns on, providing a low-impedance conduction path for the output signal terminal OUT. At this time, current can quickly flow through the thirteenth field-effect transistor M13 to the ground terminal VSS or obtain energy from the high-voltage power supply terminal VCC, thereby accelerating the speed at which the output signal terminal OUT reaches the target level.
[0054] The principle of the cooperation between the acceleration unit 41 and the suppression unit 42 is as follows:
[0055] In the early stage of level conversion, the suppression unit 42 plays a major role in absorbing and buffering the energy of transient negative voltage spikes, suppressing transient negative voltage spikes, and protecting the stability of the circuit; but as the level conversion proceeds, when the output signal approaches the target level, the acceleration unit 41 begins to play a role, providing a fast charging and discharging path for the output signal through its low-impedance conduction path, thereby accelerating the speed at which the output signal reaches the target level; through the coordinated work of the acceleration unit 41 and the suppression unit 42, the suppression unit 4 can effectively handle various problems in the level conversion process according to the actual needs of the circuit at different working stages; and the suppression unit 4 has a simple structure and is easy to integrate with the existing level conversion circuit.
[0056] A second aspect of the present invention provides a PCB board, on which any level conversion circuit as described above is printed.
[0057] A third aspect of the present invention provides a chip, which uses any of the above-mentioned level conversion circuits to achieve operation control.
[0058] The above specifically describes the preferred embodiments of the present invention, but the present disclosure is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.
Claims
1. A level conversion circuit, characterized in that: include: A shaping unit, a boost unit, a conversion unit and a suppression unit; the shaping unit is electrically connected to the boost unit, the boost unit is electrically connected to the conversion unit and the suppression unit, and the conversion unit is electrically connected to the suppression unit; the shaping unit is used to perform waveform shaping on the input signal, the boost unit is used to boost the high level of the input signal to the target operating voltage, the conversion unit is used to convert the input signal into a level signal, and the suppression unit is used to suppress transient negative voltage spikes generated during the level conversion process.
2. The level conversion circuit according to claim 1, wherein: The shaping unit includes a first shaping part and a second shaping part. The output end of the first shaping part is connected to the input end of the second shaping part. The output end of the second shaping part is electrically connected to the boost unit.
3. The level conversion circuit according to claim 2, wherein: The first shaping unit includes a first field effect transistor (FET) M1, a second field effect transistor (FET) M2, a third field effect transistor (FET) M3, and a fourth field effect transistor (FET) M4; the second shaping unit includes a fifth field effect transistor (FET) M5 and a sixth field effect transistor (FET) M6; the gates of the first field effect transistor (FET) M1, the second field effect transistor (FET) M2, the third field effect transistor (FET) M3, and the fourth field effect transistor (FET) M4 are all connected to the input signal terminal (IN); the source of the first field effect transistor (FET) M1 is connected to the low voltage terminal (VREG); the drain of the first field effect transistor (FET) M1 is connected to the source of the second field effect transistor (FET) M2 and the source of the fifth field effect transistor (FET) M5; the drain of the second field effect transistor (FET) M2 is connected to the drain of the third field effect transistor (FET) M3, the gate of the fifth field effect transistor (FET) M5, the gate of the sixth field effect transistor (FET) M6, and the boost unit; the source of the third field effect transistor (FET) M3 is connected to the drain of the fourth field effect transistor (FET) M4 and the source of the sixth field effect transistor (FET) M6; and the source of the fourth field effect transistor (FET) M4 is connected to the ground terminal (VSS); The drain of the fifth field effect transistor M5 is connected to the ground terminal VSS, and the drain of the sixth field effect transistor M6 is connected to the low voltage terminal VREG.
4. The level conversion circuit according to claim 3, wherein: The boost unit includes a first diode D1, a second diode D2, a first capacitor C1, and a second capacitor C2; the anode of the first diode D1 is connected to the low voltage terminal VREG, the cathode of the first diode D1 is connected to one end of the first capacitor C1 and the anode of the second diode D2; the other end of the first capacitor C1 is connected to the gate of the fifth field-effect transistor M5; the cathode of the second diode D2 is connected to one end of the second capacitor C2, the conversion unit, and the suppression unit, and the other end of the second capacitor C2 is connected to the ground terminal VSS.
5. The level conversion circuit according to claim 4, wherein: The conversion unit includes an inverting part and a latch part; the input end of the inverting part is connected to the boosting unit, and the output end of the inverting part is connected to the input end of the latch part; the input end of the latch part is connected to the boosting unit, and the output end of the latch part is connected to the suppression unit.
6. The level conversion circuit according to claim 5, wherein: The inverting unit includes a seventh field-effect transistor M7 and an eighth field-effect transistor M8; the latch unit includes a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, and a twelfth field-effect transistor M12; the source of the seventh field-effect transistor M7 is connected to the low-voltage terminal VREG, the gate of the seventh field-effect transistor M7 is connected to the cathode of the second diode D2, the gate of the eighth field-effect transistor M8, the gate of the eleventh field-effect transistor M11, and the suppression unit; the drain of the seventh field-effect transistor M7 is connected to the drain of the eighth field-effect transistor M8 and the gate of the twelfth field-effect transistor M12; the source of the eighth field-effect transistor M8 is connected to the ground terminal VSS; The drain of the ninth field effect transistor M9 and the source of the tenth field effect transistor M10 are connected to the high voltage terminal VCC, the gate of the ninth field effect transistor M9 is connected to the drain of the tenth field effect transistor M10, the drain of the twelfth field effect transistor M12, the suppression unit and the output signal terminal OUT; the source of the ninth field effect transistor M9 is connected to the gate of the tenth field effect transistor M10 and the drain of the eleventh field effect transistor; the source of the eleventh field effect transistor M11 and the source of the twelfth field effect transistor M12 are connected to the ground terminal VSS.
7. The level conversion circuit according to claim 6, wherein: The suppression unit includes an acceleration part and a suppression part; the acceleration part is connected to the cathode of the second diode D2, the drain of the tenth field effect transistor M10 and the output end OUT; the suppression part is connected to the drain of the tenth field effect transistor M10.
8. The level conversion circuit according to claim 7, wherein: The acceleration unit includes a thirteenth field-effect transistor M13; the suppression unit includes a first resistor R1 and a third capacitor C3; the gate of the thirteenth field-effect transistor M13 is connected to the cathode of the second diode D2, the drain of the thirteenth field-effect transistor M13 is connected to one end of the first resistor R1 and the output signal end OUT, and the source of the thirteenth field-effect transistor M13 is connected to the ground end VSS; the other end of the first resistor R1 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the ground end VSS.
9. A PCB board, characterized in that: The level conversion circuit according to any one of claims 1 to 8 is printed on the PCB board.
10. A chip, characterized in that: The chip uses the level conversion circuit described in any one of claims 1 to 8 to achieve operation control.