A Flash chip storage method and device

Abstract

The purpose of the present application is to provide a storage method and device for a Flash chip, which determines the memory capacity of the Flash chip and the memory capacity of the remaining blocks; determines the target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and performs an erasing process on the target block; divides the target block after the erasure process equally according to the amount of written data and the memory capacity of the target block, determines the target write address of the target block after the erasure process; and completes the storage process of the written data according to the target write address. This effectively prolongs the service life of the Flash chip and accurately erases the erasable blocks.

Description

Technical Field

[0001] The present application relates to the computer field, and in particular to a storage method and device for a Flash chip. Background Art

[0002] When writing a large amount of data to a Flash chip, the entire block needs to be erased multiple times, which reduces the read and write life of the Flash chip and causes the device to reach the end of its life cycle prematurely. In order to extend the life of the device, the existing storage methods are as follows:

[0003] 1) Based on the conventional fixed-erasure Flash chip memory, a verification mechanism is added to determine the erased blocks through verification, and then find an unused block again, which can extend the service life of the device. The disadvantage is that there will be insufficient code space, or if there is data in the remaining blocks, the entire block will be erased and code errors will occur;

[0004] 2) After erasing a block, divide the block into n equal parts and write the data of each part multiple times. The disadvantage is that if the data written is almost the same size as the block when erasing the same block, the added value of the service life will be negligible, and the service life will hardly be extended. Summary of the invention

[0005] One purpose of the present application is to provide a storage method and device for a Flash chip, so as to solve the problems in the prior art that a code error occurs when a block storing data is erased and the amount of written data is close to the block volume, so that the service life of the Flash chip cannot be effectively extended.

[0006] According to one aspect of the present application, a storage method of a Flash chip is provided, the method comprising:

[0007] Determine the memory capacity of the Flash chip and the memory capacity of the remaining blocks;

[0008] Determine a target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and perform erasing processing on the target block;

[0009] Dividing the erased target block equally according to the amount of written data and the memory capacity of the target block, and determining a target write address of the erased target block;

[0010] The storage process of the write data is completed according to the target write address.

[0011] Optionally, erasing the target block includes:

[0012] The target block is added to a storage object queue, and it is determined whether the number of target blocks in the storage object queue reaches an upper limit value. If so, all target blocks in the storage object queue are cleared.

[0013] Optionally, after erasing the target block, the step further includes:

[0014] The erased target block is marked with a specified identifier.

[0015] Optionally, before determining whether the number of target blocks in the storage object queue reaches an upper limit, the step includes:

[0016] The upper limit value is determined according to the memory capacity of the Flash chip.

[0017] Optionally, the evenly dividing the erased target block according to the amount of written data and the memory capacity of the target block, and determining the target write address of the erased target block includes:

[0018] Evenly divide the memory capacity of the target block after the erasure process according to integer multiples of the data amount of the written data, and determine multiple write addresses of the target block after the erasure process according to the evenly divided memory capacity of the target block after the erasure process;

[0019] A target write address among a plurality of write addresses is determined based on the data amount of the write data.

[0020] Optionally, after determining a plurality of write addresses of the target block after erasure according to the memory capacity of the target block after erasure after equal division, the method further comprises:

[0021] It is determined whether there is an unusable write address among the multiple write addresses, and if so, the unusable write address is marked with a first preset identifier.

[0022] Optionally, the determining a target write address among a plurality of write addresses based on the amount of the write data includes:

[0023] Eliminate the write addresses with the first preset identifier from the multiple write addresses;

[0024] A target write address among the remaining write addresses is determined based on the data amount of the write data.

[0025] Optionally, completing the storage processing of the write data according to the target write address includes:

[0026] The write data is stored in the target write address, and it is determined whether the stored write data is verified successfully. If so, the storage process of the write data is completed.

[0027] According to another aspect of the present application, a device for storing a Flash chip is also provided, wherein the device comprises:

[0028] A data acquisition module is used to determine the memory capacity of the Flash chip and the memory capacity of the remaining blocks;

[0029] A data processing module, used for determining a target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and performing an erasing process on the target block;

[0030] The data equalization module is further used to evenly divide the target block after the erasure process according to the data amount of the written data and the memory capacity of the target block, and determine the target write address of the target block after the erasure process;

[0031] A data storage module is used to complete the storage processing of the written data according to the target write address.

[0032] According to yet another aspect of the present application, a computer-readable medium is provided, on which computer-readable instructions are stored. The computer-readable instructions can be executed by a processor to implement any of the methods described above.

[0033] According to another aspect of the present application, a device for storing a Flash chip is also provided, wherein the device includes:

[0034] one or more processors; and

[0035] A memory storing computer readable instructions, which, when executed, cause the processor to perform the operations of any of the methods described above.

[0036] Compared with the prior art, the present application determines the memory capacity of the Flash chip and the memory capacity of the remaining blocks; determines the target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and performs erasing processing on the target block; divides the target block after erasing processing equally according to the amount of written data and the memory capacity of the target block, determines the target writing address of the target block after erasing processing; and completes the storage processing of the written data according to the target writing address. Thus, the service life of the Flash chip is effectively extended, and the erasable blocks are accurately erased. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0038] Figure 1A schematic diagram of a Flash chip storage method provided according to one aspect of the present application is shown;

[0039] Figure 2 A schematic diagram of a method for using a Flash chip in an embodiment of the present application is shown;

[0040] Figure 3 A schematic diagram of a device framework structure for storage of a Flash chip proposed according to another aspect of the present application is shown.

[0041] The same or similar reference numerals in the drawings represent the same or similar components. DETAILED DESCRIPTION

[0042] The present application is described in further detail below in conjunction with the accompanying drawings.

[0043] In a typical configuration of the present application, the terminal, the device of the service network and the trusted party all include one or more processors (CPU), input / output interfaces, network interfaces and memories.

[0044] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0045] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory media such as modulated data signals and carrier waves.

[0046] Figure 1A storage method of a Flash chip provided according to one aspect of the present application is shown, wherein the method includes: S100, determining the memory capacity of the Flash chip and the memory capacity of the remaining blocks; S200, determining the target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and performing an erasing process on the target block; S300, dividing the target block after the erasure process according to the amount of written data and the memory capacity of the target block, and determining the target write address of the target block after the erasure process; S400, completing the storage process of the written data according to the target write address. This effectively prolongs the service life of the Flash chip and accurately erases the erasable blocks.

[0047] Specifically, in S100, the memory capacity of the Flash chip and the memory capacity of the remaining blocks are determined. Here, when determining the memory capacity of the Flash chip, the blocks in use can be determined. In this application, the blocks in use are excluded, and the unused blocks are used as the remaining blocks for subsequent erasing and writing processes, and the memory capacity of the remaining blocks is determined by querying.

[0048] In S200, a target block is determined according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and the target block is erased. Here, the target block is a data block that needs to be erased, and the target block is selected according to the amount of written data and the memory capacity of the remaining blocks, and the target block is erased.

[0049] In S300, the target block after the erasure process is evenly divided according to the amount of the write data and the memory capacity of the target block, and the target write address of the target block after the erasure process is determined. Here, the evenly divided target block after the erasure process can be used to store the write data, and the memory capacity of each address of the evenly divided target block is a multiple relationship with the amount of the write data, so that the target write address that can be used to store the write data can be determined from the multiple write addresses after the target block is evenly divided according to the amount of the write data.

[0050] In S400, the storage processing of the written data is completed according to the target write address. Here, by completing the storage processing of the written data according to the target write address, it is avoided that some blocks are not used once and some blocks are forced to be used multiple times, which can effectively extend the service life of the Flash chip.

[0051] In one embodiment of the present application, in S200, the target block is added to the storage object queue, and it is determined whether the number of target blocks in the storage object queue has reached the upper limit. If so, all target blocks in the storage object queue are cleared. Here, the storage objects in the storage object queue are all blocks that can be used for writing. The storage objects in the storage object queue are used cyclically, and the target blocks after each erasure process are placed at the end of the storage object queue; optionally, the storage object queue is a circular queue to avoid repeated erasure of the same block. Next, it is determined whether the target blocks in the storage object queue have reached the maximum value of the storage object queue. If so, it indicates that all the remaining blocks have been completely erased and written. At this time, all target blocks in the queue are cleared, and the new erased target blocks are counted in the next round of storage object queues.

[0052] In an embodiment of the present application, after the target block is erased, the erased target block is marked with a designated identifier. Here, the designated identifier can be freely preset, and a designated byte can be used as the designated identifier, such as 0x5A.

[0053] In a preferred embodiment of the present application, the target block to be erased is marked with 0x5A, and the remaining block data that can be used is arranged using a circular queue method. At this time, it is known that there are 10 blocks left, starting from 0, and each time a block is erased, the marked storage object queue is increased by 1 until the maximum number is 9, when the value of the storage object queue returns to 0. In this way, the erased remaining blocks are marked repeatedly to avoid repeated erasure of the same block, effectively extending the service life of the Flash chip.

[0054] In one embodiment of the present application, before determining whether the number of target blocks in the storage object queue has reached an upper limit, the upper limit is determined according to the memory capacity of the Flash chip. Here, the number of remaining blocks can be obtained based on the memory capacity of the Flash chip, and the number of all remaining blocks is the upper limit.

[0055] In one embodiment of the present application, in S300, the memory capacity of the target block after the erasure process is evenly divided according to the integer multiples of the amount of data to be written, and multiple write addresses of the target block after the erasure process are determined according to the memory capacity of the target block after the erasure process after the even division; the target write address among the multiple write addresses is determined based on the amount of data to be written. Here, the object of even division is the block of the Flash chip, the memory capacity of the target block after the erasure process is divided by the amount of data to be written, and the calculation result is obtained, and the result is rounded to obtain the number of evenly divided shares of the memory capacity of the target block after the erasure process. In the actual application scenario, the amount of data to be written can be the sum of the byte length of the written data, the number of header bytes and the number of blocks, and the sum of the number of check bytes. Then, multiple write addresses are determined according to the memory capacity of the target block after the erasure process after even division, and each target block after even division is set as a write address, and then the target write address of the write data storage is determined based on the amount of data to be written and the memory capacity corresponding to each write address. For example, if the block size is 4K and 1000 bytes need to be written each time, it can be divided into 4 equal parts of 1024 bytes. In this way, the number of data writes each time can be increased by equal division, that is, erase once and write four times. For this, there are n erased and written blocks, and each block is divided into N equal parts. The write address each time is the m equal addresses of the N in the block, which can be recorded as n*N+m.

[0056] In one embodiment of the present application, after determining multiple write addresses of the target block after the erasure process according to the memory capacity of the target block after the erasure process after the equal division, it is determined whether there is an unusable write address among the multiple write addresses, and if so, the unusable write address is marked with a first preset identifier. Here, multiple write addresses can be used to determine whether there is an unusable write address in a verification manner, and if so, the unusable write address is marked with a first preset identifier to avoid mistakenly erasing a block that already stores non-erasable data, resulting in errors in the code of the entire Flash chip.

[0057] In one embodiment of the present application, in S300, the write addresses with the first preset identifier in the multiple write addresses are eliminated; and the target write address in the remaining write addresses is determined based on the data volume of the write data. Here, if all the original write addresses obtained after equal division in a single target block are marked by the first preset identifier and are all unusable write addresses, a new block is reselected to divide multiple usable write addresses according to the data volume of the write data, and the target write address is selected from the multiple write addresses of the new block. Through the above method, it is avoided that the block that already has non-erasable data is mistakenly erased, resulting in errors in the code of the entire Flash chip, and at the same time, it is avoided that some blocks are not used at all and some blocks are forced to be used multiple times, and the memory capacity of all blocks is maximized. Each time the data is written, the write address is adaptively adjusted according to the data volume of the write data, which can effectively extend the service life of the Flash chip.

[0058] In one embodiment of the present application, in S400, the write data is stored in the target write address, and it is determined whether the stored write data is successfully verified. If so, the storage process of the write data is completed. Here, after the write data is stored in the target write address, the stored write data is verified, and when the verification is successful, the storage process of the write data is completed.

[0059] Figure 2 A schematic flow chart of a Flash chip usage method in an embodiment of the present application is shown, wherein each block (Block) contains four target write positions, each write position contains data (Data), forming a block storage on the left, it is known that the four storage positions above correspond to the block 1 (Block1) in normal use, then all the remaining blocks are objects that can be stored, and all the remaining blocks are used as multiple target blocks. After erasing the entire target block each time, the block is added to the storage object queue and marked, and the next write data is written from the block other than the marked block. When the four addresses in a single target block are all written, the target block is erased to 0xFF, and the fifth write is written from the next new block, that is, write four times and erase once. This cycle is repeated to avoid the error of erasing the block that already has indelible data, resulting in errors in the code of the entire Flash chip, and at the same time avoids some blocks from being used once, and some blocks are forced to be used multiple times, maximizing the memory capacity of all blocks, and each time the data is written, the write address is adaptively adjusted according to the data amount of the written data, which can effectively extend the service life of the Flash chip.

[0060] The embodiment of the present application further provides a computer-readable medium on which computer-readable instructions are stored. The computer-readable instructions can be executed by a processor to implement the aforementioned storage method of a Flash chip.

[0061] Corresponding to the method described above, the present application also provides a terminal, which includes a terminal capable of executing the above Figure 1 or Figure 2 The modules or units of the method steps described in the various embodiments may be implemented by hardware, software, or a combination of hardware and software, which is not limited in the present application. For example, in one embodiment of the present application, a storage device for a Flash chip is also provided, wherein the device includes:

[0062] one or more processors; and

[0063] A memory storing computer-readable instructions, wherein the computer-readable instructions, when executed, cause the processor to perform the operations of the aforementioned Flash chip storage method.

[0064] For example, when the computer-readable instructions are executed, the one or more processors are caused to: determine the memory capacity of the Flash chip and the memory capacity of the remaining blocks; determine the target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and erase the target block; divide the target block after the erasure process equally according to the amount of written data and the memory capacity of the target block, and determine the target write address of the target block after the erasure process; and complete the storage process of the written data according to the target write address.

[0065] Figure 3 A schematic diagram of a device framework structure for storage of a Flash chip proposed according to another aspect of the present application is shown, wherein the device includes: a data acquisition module 100, used to determine the memory capacity of the Flash chip and the memory capacity of the remaining blocks; a data processing module 200, used to determine the target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and to perform an erasing process on the target block; a data equalization module 300, also used to equalize the target block after the erasure process according to the amount of written data and the memory capacity of the target block, and determine the target write address of the target block after the erasure process; a data storage module 400, used to complete the storage process of the written data according to the target write address. This effectively prolongs the service life of the Flash chip and accurately erases the erasable blocks.

[0066] It should be noted that the contents executed by the data acquisition module 100, data processing module 200, data equal distribution module 300 and data storage module 400 are respectively the same or correspondingly the same as the contents in the above-mentioned S100, S200, S300 and S400, and will not be repeated here for the sake of simplicity.

[0067] In a preferred embodiment of the present application, the data acquisition module 100 is further configured to determine the upper limit value according to the memory capacity of the Flash chip before judging whether the number of target blocks in the storage object queue reaches the upper limit value.

[0068] In a preferred embodiment of the present application, the data processing module 200 is further configured to mark the erased target block with a designated identifier after erasing the target block.

[0069] In a preferred embodiment of the present application, the data equalization module 300 is further used to remove the write addresses with a first preset identifier from the multiple write addresses; and determine the target write address from the remaining write addresses based on the data amount of the write data.

[0070] It should be noted that the contents executed by the data acquisition module 100, the data processing module 200 and the data equal distribution module 300 are respectively the same or correspondingly the same as those in the above method embodiments, and for the sake of brevity, they are not repeated here.

[0071] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0072] It should be noted that the present application can be implemented in software and / or a combination of software and hardware, for example, can be implemented using an application specific integrated circuit (ASIC), a general purpose computer or any other similar hardware device. In one embodiment, the software program of the present application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of the present application (including relevant data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the present application can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0073] In addition, a part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. The program instruction for calling the method of the present application may be stored in a fixed or removable recording medium, and / or transmitted through a data stream in a broadcast or other signal-bearing medium, and / or stored in a working memory of a computer device that runs according to the program instruction. Here, according to an embodiment of the present application, a device is included, the device including a memory for storing computer program instructions and a processor for executing program instructions, wherein, when the computer program instruction is executed by the processor, the device is triggered to run the method and / or technical solution based on the aforementioned multiple embodiments according to the present application.

[0074] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or basic features of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present application is limited by the attached claims rather than the above description, so it is intended to include all changes that fall within the meaning and scope of the equivalent elements of the claims in the present application. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in the device claim can also be implemented by one unit or device through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

Claims

1. A storage method of a Flash chip, wherein: The method comprises: Determine the memory capacity of the Flash chip and the memory capacity of the remaining blocks; Determine a target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and perform erasing processing on the target block; Dividing the erased target block equally according to the amount of written data and the memory capacity of the target block, and determining a target write address of the erased target block; Complete storage processing of the write data according to the target write address; The step of equally dividing the erased target block according to the amount of written data and the memory capacity of the target block, and determining the target write address of the erased target block includes: Evenly divide the memory capacity of the target block after the erasure process according to integer multiples of the data amount of the written data, and determine multiple write addresses of the target block after the erasure process according to the evenly divided memory capacity of the target block after the erasure process; Determine whether there is an unusable write address among the multiple write addresses, and if so, mark the unusable write address with a first preset identifier; Eliminate the write addresses with the first preset identifier from the multiple write addresses; A target write address among the remaining write addresses is determined based on the data amount of the write data.

2. The method according to claim 1, wherein: Erasing the target block includes: The target block is added to a storage object queue, and it is determined whether the number of target blocks in the storage object queue reaches an upper limit value. If so, all target blocks in the storage object queue are cleared.

3. The method according to claim 1, wherein: After the target block is erased, the method further comprises: The erased target block is marked with a specified identifier.

4. The method according to claim 2, wherein: Before determining whether the number of target blocks in the storage object queue reaches an upper limit value, the method includes: The upper limit value is determined according to the memory capacity of the Flash chip.

5. The method according to claim 1, wherein: The step of completing the storage processing of the write data according to the target write address includes: The write data is stored in the target write address, and it is determined whether the stored write data is verified successfully. If so, the storage process of the write data is completed.

6. A device for storing a Flash chip, wherein: The device comprises: A data acquisition module is used to determine the memory capacity of the Flash chip and the memory capacity of the remaining blocks; A data processing module, used for determining a target block according to the memory capacity of the Flash chip and the memory capacity of the remaining blocks, and performing an erasing process on the target block; The data equalization module is further used to evenly divide the target block after the erasure process according to the data amount of the written data and the memory capacity of the target block, and determine the target write address of the target block after the erasure process; A data storage module, used to complete the storage processing of the written data according to the target write address; The data distribution includes: Evenly divide the memory capacity of the target block after the erasure process according to integer multiples of the data amount of the written data, and determine multiple write addresses of the target block after the erasure process according to the evenly divided memory capacity of the target block after the erasure process; Determine whether there is an unusable write address among the multiple write addresses, and if so, mark the unusable write address with a first preset identifier; Eliminate the write addresses with the first preset identifier from the multiple write addresses; A target write address among the remaining write addresses is determined based on the data amount of the write data.

7. A computer-readable medium having computer-readable instructions stored thereon, wherein the computer-readable instructions can be executed by a processor to implement the method according to any one of claims 1 to 5.

8. A storage device for a Flash chip, wherein: The device comprises: one or more processors; and A memory storing computer readable instructions which, when executed, cause the processor to perform the operations of the method as claimed in any one of claims 1 to 5.

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