Portable storage device and method of operating a portable storage device

Abstract

A portable storage device and a method of operating the same are provided. The portable storage device includes a plurality of nonvolatile memory devices storing data, a storage controller, and a bridge chip set. The bridge chip set is connected to a first connector of a host through a cable assembly; detects a resistance of the cable assembly; provides USB type information of the first connector to the storage controller based on the detected resistance; and provides USB version information associated with an established USB connection to the storage controller after the USB connection is established with the host. The storage controller selects one of a plurality of operation modes based on the USB type information, the USB version information, and a request mode from the host indicating random or sequential access of the data; selects a clock signal having a maximum frequency, the selected clock signal consuming less power than an available maximum power level associated with the selected operation mode at the maximum frequency; and performs power throttling based on the selected clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0154154, filed on November 27, 2019, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Exemplary embodiments generally relate to storage devices, and more specifically, to portable storage devices and methods of operating portable storage devices. Background Technology

[0004] Data transfer standards (such as Universal Serial Bus (USB)) are industrial data bus standards used for transferring digital data between electronic devices. The currently used USB 3.1 type offers transfer speeds approximately ten times faster than the USB 2.0 type. Therefore, the USB 3.1 type is commonly used for transferring high-definition content. Portable storage devices can connect to a variety of hosts that support various USB connectors. Summary of the Invention

[0005] An exemplary embodiment provides a portable storage device that is compatible with various host devices and capable of performing power throttling.

[0006] An exemplary embodiment provides a method for operating a portable storage device that is compatible with various host devices and capable of performing power throttling.

[0007] According to an exemplary embodiment, a storage device includes: a plurality of non-volatile storage devices configured to store data, a storage controller, and a bridge chipset. The storage controller is configured to control the plurality of non-volatile storage devices. The bridge chipset is connected to a first connector of a host computer via a cable assembly. The bridge chipset detects the resistance of the cable assembly; based on the detected resistance, provides the storage controller with Universal Serial Bus (USB) type information of the first connector; and after establishing a USB connection with the host, provides the storage controller with USB version information associated with the established USB connection. The storage controller selects one of a plurality of operating modes based on the USB type information, the USB version information, and a request mode from the host indicating random or sequential access to the data; selects a clock signal with a maximum frequency, the selected clock signal consuming less power than the maximum available power level associated with the selected operating mode at the maximum frequency; and performs power throttling based on the selected clock signal.

[0008] According to an example embodiment, a method of operating a portable storage device including a plurality of nonvolatile memory devices configured to store data, a storage controller configured to control the plurality of nonvolatile memory devices, and a bridge chip set connected to a first connector of a host through a cable assembly connected to a second connector of the bridge chip set is provided. According to the method, a resistance of the cable assembly is detected by the bridge chip set; based on the detected resistance, universal serial bus (USB) type information of the first connector is determined; after a USB connection is established between the host and the portable storage device, USB version information associated with the established USB connection is provided to the storage controller; one of a plurality of operation modes is selected by the storage controller based on the USB type information, the USB version information, and a request mode from the host indicating a random access to the data or a sequential access to the data; and power throttling is performed based on the selected operation mode.

[0009] According to an example embodiment, a portable storage device includes a plurality of nonvolatile memory devices configured to store data, a storage controller configured to control the plurality of nonvolatile memory devices, and a bridge chipset connected to a first connector of a host through a cable assembly. The bridge chipset is configured to detect a resistance of the cable assembly, provide universal serial bus (USB) type information of the first connector to the storage controller based on the detected resistance, and provide USB version information associated with an established USB connection to the storage controller after the USB connection is established with the host. The bridge chipset includes a connection detector configured to detect the resistance of the cable assembly via a first pin among a plurality of pins in a second connector of the portable storage device. The second connector is connected to the cable assembly. The storage controller includes an interface unit configured to perform an interface connection between the host and the nonvolatile memory devices, and a power controller configured to select one of the plurality of operation modes based on the USB type information, the USB version information, and a request mode indicating a random access to the data or a sequential access to the data, select a clock signal having a maximum frequency, the selected clock signal consuming a power less than an available maximum power level associated with the selected operation mode at the maximum frequency, and perform power throttling based on the selected clock signal. The bridge chipset is configured to provide the USB type information to the storage controller through a first general purpose input / output (GPIO) pin of the connection detector, wherein the first GPIO pin is hardwired to a second GPIO pin of the storage controller, and write the USB version information into a register in a peripheral component interconnect express (PCIe) interface in the interface unit.

[0010] According to an example embodiment, a portable storage device includes a plurality of nonvolatile memory devices configured to store data, a storage controller configured to control the plurality of nonvolatile memory devices, and a bridge chipset connected to a first connector of a host through a cable assembly. The bridge chipset is configured to detect a resistance of the cable assembly, provide connection information of the first connector to the storage controller based on the detected resistance, and provide version information associated with an established connection to the storage controller after the connection with the host is established. The storage controller is configured to select one of a plurality of operation modes based on the connection information, the version information, and a request pattern from the host indicating a random access to the data or a sequential access to the data, select a clock signal having a maximum frequency, the selected clock signal consuming a power less than an available maximum power level associated with the selected operation mode at the maximum frequency, and perform power throttling based on the selected clock signal.

[0011] Accordingly, the portable storage device can optimize power by adaptively controlling power based on a USB type of a first connector of a host connected via a cable assembly, USB version information between the portable storage device and the host, and a request pattern from the host. In addition, the portable storage device can improve performance by controlling a frequency of a clock signal at a start phase of an initialization operation. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other features of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings in which:

[0013] Figure 1 is a block diagram illustrating a storage system according to an example embodiment.

[0014] Figure 2 illustrates an example of a cable assembly in Figure 1 according to an example embodiment.

[0015] Figure 3A illustrates a first connector in Figure 1 according to an example embodiment.

[0016] Figure 3B illustrates a plug in Figure 2 according to an example embodiment.

[0017] Figure 3C is a table illustrating types of a cable assembly in Figure 1 according to an example embodiment.

[0018] Figure 4is a block diagram illustrating an example of a host in Figure 1

[0019] Figure 5 is a block diagram illustrating an example of a portable storage device in Figure 1

[0020] Figure 6 is a block diagram illustrating an example of a storage controller in Figure 5

[0021] Figure 7 is an example of an interface unit in a storage controller of Figure 6

[0022] Figure 8A is an example of a power controller in a storage controller of Figure 6

[0023] Figure 8B is a block diagram illustrating an example of control logic in Figure 8A

[0024] Figure 9 is an example of a lookup table (LUT) in Figure 8A

[0025] Figure 10 is an operation of a storage controller in Figure 5

[0026] Figure 11 is a timing diagram illustrating an operation of a storage controller in Figure 5

[0027] Figure 12 is an operation of a connection detector in Figure 5

[0028] Figure 13 is a block diagram illustrating one of a plurality of nonvolatile memory devices in a portable storage device in Figure 5

[0029] Figure 14 is a block diagram illustrating an array of storage units in Figure 13

[0030] Figure 15 is a perspective view of one of a plurality of storage blocks of Figure 14

[0031] ​​​​​​​​​​​​​Figure 16 is a block diagram illustrating a storage system according to an example embodiment. Figure 15 is an equivalent circuit diagram of a storage block.

[0032] Figure 17 is a flowchart illustrating a method of operating a portable storage device according to an example embodiment.

[0033] Figure 18 is a block diagram illustrating a storage system according to an example embodiment. DETAILED DESCRIPTION

[0034] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the drawings.

[0035] It will be understood that the terms "first," "second," "third," etc. are used herein to distinguish one element from another, and the elements are not limited by the terms. Thus, a "first" element in one example embodiment can be described as a "second" element in another example embodiment.

[0036] It should be understood that the description of features or aspects within each example embodiment is generally applicable to other similar features or aspects in other example embodiments, unless the context clearly dictates otherwise.

[0037] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] Herein, when one value is described as being about equal to another value, or substantially the same as or substantially equal to another value, it will be understood that: the values are the same; the values are equal to each other within a margin of error; or the values are close enough to be functionally equal to each other as would be understood by one of ordinary skill in the art, if measurably unequal. For example, the term "about" as used herein includes the recited value, and means within an acceptable range of deviation from the particular value, taking into account measurement issues and errors associated with measuring the particular quantity (i.e., limitations of the measurement system), as would be determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations as would be understood by one of ordinary skill in the art. Further, it should be understood that although a parameter can be described herein as having "about" a particular value, according to an example embodiment, the parameter can be exactly the particular value or close to the particular value within a margin of error as would be understood by one of ordinary skill in the art.

[0039] Figure 1 is a block diagram illustrating a storage system according to an example embodiment.

[0040] Referring toFigure 1 The storage system 10 can include a host 100 and a portable storage device 200.

[0041] The host 100 and the portable storage device 200 can be electrically connected to each other through a universal serial bus (USB) cable assembly 30, and can communicate with each other. The USB cable assembly 30 can also be referred to as a cable assembly 30.

[0042] In an exemplary embodiment, the host 100 can be connected to the cable assembly 30 through a first connector 110, and the portable storage device 200 can be connected to the cable assembly 30 through a second connector 210.

[0043] The host 100 can include at least one of, for example, a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop computer, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device.

[0044] In an exemplary embodiment, the host 100 can include at least one of various medical devices such as, for example, various portable medical measurement devices (for example, a blood glucose measurement device, a heartbeat measurement device, or a body temperature measurement device), a magnetic resonance angiography (MRA) device, a magnetic resonance imaging (MRI) device, a computed tomography (CT) device, an imaging device, or an ultrasonic device. In an exemplary embodiment, the host 100 can include, for example, a navigation device, a global navigation satellite system (GNSS) receiver, an event data recorder (EDR), a flight data recorder (FDR), a car infotainment device, sailing electronic devices (for example, sailing navigation devices or gyro compasses), avionics, security devices, vehicular head units, industrial or home robots, drones, automatic teller machines (ATMs), or point of sale (POS) devices.

[0045] The first connector 110 can also be referred to as a first receptacle, and the second connector 210 can also be referred to as a second receptacle.

[0046] The host 100 can provide a command CMD and an address ADDR to the portable storage device 200 through the cable assembly 30, and can exchange data DTA with the portable storage device 200 through the cable assembly 30.

[0047] In Figure 1In the present embodiment, the portable storage device 200 is illustrated as a solid state drive (SSD) device as an example. However, the example embodiments are not limited thereto. For example, according to the example embodiments, the portable storage device 200 can be any kind of portable storage device.

[0048] The portable storage device 200 can include a bridge chipset 220 (which can also be referred to as bridge chipset circuitry herein), a storage controller 300 (which can also be referred to as storage controller circuitry herein), and a storage medium 400. The storage medium 400 can include a plurality of non-volatile memory devices. The plurality of non-volatile memory devices can be used as a storage medium of the portable storage device 200.

[0049] In the example embodiments, the plurality of non-volatile memory devices 400a-400k (see FIG. 1) can each include a flash memory or a vertical NAND memory device. The storage controller 300 can control each of the plurality of non-volatile memory devices 400a-400k. Figure 5

[0050] When the bridge chipset 220 is connected to the first connector 110 of the host 100 through the cable assembly 30, the bridge chipset 220 can receive power from the host 100 and can detect a resistance of the cable assembly 30. In addition, the bridge chipset 220 can determine a USB type of the cable assembly 30 and / or the first connector 110 based on the detected resistance, and can provide USB type information indicating the determined USB type to the storage controller 300.

[0051] The bridge chipset 220 can notify the storage controller 300 of the USB type information based on the detected resistance by selectively switching a general purpose input / output (GPIO) pin.

[0052] In addition, when a USB connection between the portable storage device 200 and the host 100 is established (e.g., when a USB link is established between the host 100 and the portable storage device 200), the bridge chipset 220 can provide USB version information indicating USB protocol information between the host 100 and the portable storage device 200 to the storage controller 300.

[0053] The storage controller 300 can perform power throttling within a power level associated with an operation involved in a request mode based on the USB type information, the USB version information, and a request mode from the host 100 indicating a random access to data or a sequential access to data. The storage controller 300 can select one of a plurality of operation modes based on the USB type information, the USB version information, and the request mode, and can perform power throttling to adjust a power level consumed in an operation corresponding to the selected operation mode.​

[0054] That is, the storage controller 300 can select the maximum frequency of the clock signal to be provided to the hardware modules in the storage controller 300 such that the power target level associated with the selected operating mode is not exceeded. In other words, the power consumed by the selected clock signal with the maximum frequency is less than or equal to the power target level (maximum available power level) supported by the selected operating mode.

[0055] Figure 2 Showing according to an exemplary embodiment Figure 1 Example of cable assembly 30.

[0056] Reference Figure 2 The cable assembly 30 may include a cable 31, a first overmold 33, a second overmold 33-1, a first plug 35, and a second plug 35-1.

[0057] The first plug 35 can be connected to the cable 31 through the first covering mold 33, and the second plug 35-1 can be connected to the cable 31 through the second covering mold 33-1.

[0058] Figure 3A Showing according to an exemplary embodiment Figure 1 The first connector 110 in the middle. Figure 3B Showing according to an exemplary embodiment Figure 2 The plug in.

[0059] Reference Figure 3A The first connector 110, which can be connected to the first plug 35, may include 24 pins A1 to A12 and B1 to B12. Pins may also be referred to as contacts.

[0060] The first set of pins A1 to A12 and the second set of pins B1 to B12 can be arranged symmetrically with respect to the center portion of the first plug 35.

[0061] For example, the first connector 110 may include: first GND pins A1, A12, B1 and B12, first USB 3.1 transmitter pins A2, A3, B2 and B3, first USB 3.1 receiver pins A10, A11, B10 and B11, first VBUS pins A4, A9, B4 and B9, first CC (configuration channel) pins A5 and B5, first USB 2.0 signal pins A6, A7, B6 and B7, and first side pins A8 and B8.

[0062] Reference Figure 3B The first plug 35 or the second plug 35-1 may include 24 pins A1 to A12 and B1 to B12 corresponding to the respective pins of the first connector 110.

[0063] For example, the first plug 35 or the second plug 35-1 can include second GND pins A1, A12, B1, and B12, second USB 3.1 transmitter pins A2, A3, B2, and B3, second USB 3.1 receiver pins A10, A11, B10, and B11, second VBUS pins A4, A9, B4, and B9, a second CC pin A5, a VCONN pin B5, second USB 2.0 signal pins A6 and A7, and second side pins A8 and B8.

[0064] The first USB 3.1 transmitter pins A2, A3, B2, and B3 of the first connector 110 can be connected to the second USB 3.1 receiver pins A10, A11, B10, and B11 of the first plug 35, and the first USB 3.1 receiver pins A10, A11, B10, and B11 of the first connector 110 can be connected to the second USB 3.1 transmitter pins A2, A3, B2, and B3 of the first plug 35, so as to transmit or receive data between the first connector 110 and the first plug 35 or the second plug 35-1 according to the USB 3.1 protocol. The first CC pins A5 and B5 of the first connector 110 can be connected to the second CC pin A5 or the VCONN pin B5 of the first plug 35 or the second plug 35-1.

[0065] The configuration of the first connector 110 and the first plug 35 or the second plug 35-1 is an example according to the USB Type-C. The configuration of the first connector 110 and the first plug 35 or the second plug 35-1 can be changed according to the USB type.

[0066] In an exemplary embodiment, the pin assignment of the second connector 210 can be the same as or similar to the pin assignment of the first connector 110.

[0067] In an exemplary embodiment, the host 100 supporting the USB interface can define the insertion direction of the first plug 35 connected to the first connector 110 by measuring the voltage of the CC pin (identification pin) of the host 100, and determine whether the portable storage device 200 connected to the first connector 110 through the cable assembly 30 is used as a USB device or a USB host.

[0068] That is, the CC (CC1 or CC2) pin can be used for at least one of detecting the connection of the portable storage device 200 through the cable assembly 30, determining the insertion direction of the first plug 35, and managing the configuration of the storage system 10 (for example, managing the configuration of the host 100 and the portable storage device 200).

[0069] As such, in order to identify the insertion direction of the first plug 35 by measuring the voltage of the CC pin and determine whether the external device connected to the first connector 110 and the cable assembly 30 is a USB device or a USB host, a specific current can be always applied to the CC pin. The specific current that can be provided by the host 100 can vary according to the USB type of the first connector 110.

[0070] Figure 3C is a table illustrating the type of the cable assembly in Figure 1 according to an exemplary embodiment.

[0071] Referring to Figure 3C , the (USB) type of the cable assembly 30 complies with "TYPE C to C" as indicated by reference numeral 36, "TYPE C to STANDARD A" as indicated by reference numeral 37, or "TYPE C to RECEPTACLE B" as indicated by reference numeral 38.

[0072] In an exemplary embodiment, Figure 1 the cable assembly 30 in does not comply with the USB type. In this case, the bridge chip set 220 can detect the resistance of the cable assembly 30, can provide the connection information of the first connector 110 to the storage controller 300 based on the detected resistance, and can provide the version information associated with the established connection to the storage controller 300 after the connection with the host 100 is established. The storage controller 300 independent of the host 100 can select a clock signal having a maximum frequency, which consumes a power less than or equal to the available maximum power level associated with the selected initialization mode at the maximum frequency, and can perform an initialization operation based on the selected clock signal within an internal reference time interval.

[0073] Figure 4 is a block diagram illustrating the host 100 in Figure 1 according to an exemplary embodiment.

[0074] Referring to Figure 4 , the host 100 can include a central processing unit (CPU) 120, a read-only memory (ROM) 125, a main memory 130, a storage interface 140, a user interface 150, and a bus 160.

[0075] The bus 160 can refer to a transmission path that transmits data between the CPU 120, the ROM 125, the main memory 130, the storage interface 140, and the user interface 150 of the host 100.

[0076] The ROM 125 can store various application programs. For example, an application program supporting a storage protocol such as an Advanced Technology Attachment (ATA), a Small Computer System Interface (SCSI), an Embedded Multimedia Card (eMMC), and / or a Unix File System (UFS) protocol can be stored.

[0077] The main memory 130 can temporarily store data or programs.

[0078] The user interface 150 can be a physical or virtual medium for exchanging information between a user and the host 100, a computer program, etc., and can include physical hardware and logical software. For example, the user interface 150 can include an input device that allows a user to manipulate the host 100, and an output device for outputting a result of processing of the user's input.

[0079] The CPU 120 can control the overall operation of the host 100. The CPU 120 can generate a command for storing data in the portable storage device 200 or a request (or a command) for reading data from the portable storage device 200 by using an application stored in the ROM 125, and can transmit the command or the request to the portable storage device 200 via the storage interface 140.

[0080] Figure 5 is a block diagram illustrating an example of the portable storage device 200 in the host 100 according to an exemplary embodiment. Figure 1

[0081] Referring to FIG. 1, Figure 5 The portable storage device 200 can include a second connector 210 connected to the cable assembly 30, a bridge chipset 220, a storage controller 300, and a storage medium 400.

[0082] The storage medium 400 can include a plurality of nonvolatile storage devices 400a~400k (where k is an integer greater than 2). The storage controller 300 can be connected to the plurality of nonvolatile storage devices 400a~400k through a plurality of channels CHG1~CHGk (where k is an integer greater than 2), respectively.

[0083] The second connector 210 can include a plurality of pins, and the plurality of pins can include a cable bus power (VBUS) pin 211 for power supply, CC1 and CC2 pins 212 and 213 for exchanging setting information with the host 100, and a ground pin 214.

[0084] The bridge chipset 220 can be connected to the second connector 210. The bridge chipset 220 can include an interface converter 230 (which can also be referred to as an interface converter circuit herein) and a connection detector 240 (which can also be referred to as a connection detector circuit herein).​

[0085] The interface converter 230 can perform interface conversion between the host 100 and the storage controller 300. For example, the interface converter 230 can convert the interface of the host 100 to the interface conforming to the plurality of nonvolatile memory devices 400a~400k, or can convert the interface conforming to the plurality of nonvolatile memory devices 400a~400k to the interface of the host 100.

[0086] The connection detector 240 is connected to the CC1 pin 212, detects the resistance of the cable assembly 30 and the first connector 110 in response to the power applied to the cable assembly 30 when the cable assembly 30 is connected to the first connector 110 of the host 100, determines the USB type of the cable assembly 30 and the first connector 110 based on the detected resistance, and provides the USB type information UTI indicating the USB type of the cable assembly 30 and the first connector to the storage controller 300.

[0087] When the cable assembly 30 is connected to the first connector 110 of the host 100 and power is applied to the cable assembly 30, a specific current applied to the CC1 pin of the first connector 110 is provided to the CC1 pin 212 through the cable assembly 30, and a current-based voltage is induced at the CC1 pin 212. The connection detector 240 can detect the resistance of the cable assembly 30 and the first connector 110 by detecting the voltage of the CC1 pin 212.

[0088] The connection detector 240 can determine the USB type of the cable assembly 30 and the first connector 110 based on a comparison of the detected resistance with a threshold value. In an exemplary embodiment, when the detected resistance is less than or equal to the threshold value, the connection detector 240 can determine the USB type of the first connector 110 as USB Type-C, and when the detected resistance is greater than the threshold value, the connection detector 240 can determine the USB type of the first connector 110 as USB Type-A.

[0089] In an exemplary embodiment, the connection detector 240 can provide the USB type information UTI to the power controller 360 of the storage controller 300 through the first GPIO pin 221. The connection detector 240 can selectively switch the voltage of the first GPIO pin 221 based on the detected resistance.

[0090] When the detected resistance is less than or equal to the threshold value, the connection detector 240 can inform the storage controller 300 that the USB type of the first connector 110 is USB Type-C by maintaining the voltage level of the first GPIO pin 221 at a first level.

[0091] When the detected resistance is greater than the threshold value, the connection detector 240 can inform the storage controller 300 that the USB type of the first connector 110 is USB A type by switching the voltage of the first GPIO pin 221 from the first level to the second level.

[0092] The storage controller 300 can include a power controller 360 (which can also be referred to as a power controller circuit herein) and an interface unit 350 (which can also be referred to as an interface circuit herein). The interface unit 350 can include a register 352. The register 352 can be a vendor specific register (VSR).

[0093] The power controller 360 can be connected to the second GPIO pin 301 of the storage controller 300. The second GPIO pin 301 can be hardwired to the first GPIO pin 221 through the wire 290.

[0094] After establishing a connection with the host 100, the connection detector 240 can provide the storage controller 300 with USB version information UVI associated with the established connection.

[0095] The connection detector 240 can write the USB version information UVI into the register 352, and can obtain the USB version information UVI by referring to the register 352 in response to a write event in the register 352. The bridge chipset 220 and the storage controller 300 can communicate with each other via sideband communication through the first GPIO pin 221 and the second GPIO pin 301. The connection detector 240 and the register 352 in the interface unit 350 can communicate with each other via in-band communication and through a non-volatile memory express (NVMe) interface.

[0096] Figure 6 is a block diagram illustrating an example of the storage controller 300 in the Figure 5 according to an exemplary embodiment.

[0097] Referring to Figure 6 , the storage controller 300 can include a processor 310, an error-correcting code (ECC) engine 320 (which can also be referred to as an ECC engine circuit herein), a buffer 330 (which can also be referred to as a buffer circuit herein), a randomizer 335 (which can also be referred to as a randomizer circuit herein), a ROM 340, an interface unit 350 (which can also be referred to as an interface circuit herein), a power controller 360 (which can also be referred to as a "power controller circuit" herein), and a "non-volatile memory (NVM) controller 345" (which can also be referred to as an NVM controller circuit herein), which are connected to each other through a bus 305.

[0098] The processor 310 controls overall operations of the storage controller 300. The processor 310 can include a plurality of cores.

[0099] The plurality of cores can perform a control operation associated with the nonvolatile storage devices 400a~400k. At least one core of the plurality of cores can process a command provided from the host 100, at least one core of the plurality of cores can perform address mapping and garbage collection using a flash translation layer (FTL), and at least one core of the plurality of cores can control the nonvolatile storage devices 400a~400k through the NVM controller 345.

[0100] The storage units of the nonvolatile storage devices 400a~400k can have physical characteristics in which a threshold voltage distribution varies due to reasons such as program pass time, temperature, program disturbance, read disturbance, etc. For example, due to the above reasons, data stored in the nonvolatile storage devices 400a~400k can be corrupted.

[0101] The storage controller 300 corrects such errors using various error correction techniques. For example, the storage controller 300 can include an ECC engine 320. The ECC engine 320 can correct errors occurring in data stored in the nonvolatile storage devices 400a~400k.

[0102] The ROM 340 stores various information for the operation of the storage controller 300 in firmware. The buffer 330 can store data provided from the nonvolatile storage devices 400a~400k.

[0103] The randomizer 335 randomizes data to be stored in the nonvolatile storage devices 400a~400k. For example, the randomizer 335 can randomize data to be stored in the nonvolatile storage devices 400a~400k in units of word lines.

[0104] Data randomization can be performed to process data so that the program state of the storage units connected to the word line has the same proportion.

[0105] For example, if the storage units connected to one word line are multi-level cells (MLC) that store 2 bits of data per cell, each storage unit has one of an erased state and a first to third program state.

[0106] In this case, the randomizer 335 can randomize the data such that, among the memory cells connected to one word line, the number of memory cells having the erase state, the number of memory cells having the first programmed state, the number of memory cells having the second programmed state, and the number of memory cells having the third programmed state are the same as or substantially the same as each other. For example, the memory cells in which the randomized data is stored have programmed states in the number of which are equal to each other.

[0107] The randomizer 335 also de-randomizes the data read from the non-volatile memory devices 400a~400k.

[0108] The interface unit 350 can perform interfacing between the host 100 and the non-volatile memory devices 400a~400k.

[0109] The interface unit 350 includes the register 352, and the register 352 can store the USB version information UVI.

[0110] The power controller 360 can receive the USB type information UTI, can receive the command CMD and the address ADDR, can determine a request mode based on the command CMD and the address ADDR, can select one of a plurality of operation modes based on the USB type information UTI, the USB version information UVI, and the request mode, and can perform power throttling to adjust a power level consumed in the selected operation mode.

[0111] The NVM controller 345 can receive the command CMD and the address ADDR, and can control the non-volatile memory devices 400a~400k based on the command CMD and the address ADDR.

[0112] Figure 7 An example of the interface unit 350 in the storage controller 300 according to an exemplary embodiment is shown. Figure 6 An example of the interface unit 350 in the storage controller 300 according to an exemplary embodiment is shown.

[0113] Referring to Figure 7 , the interface unit 350 can include a Peripheral Component Interconnect Express (PCIe) interface 351, a Non-Volatile Memory (NVMe) interface 353, and an interface controller 355. The PCIe interface 351 can include the register 352.

[0114] The interface controller 355 can control the PCIe interface 351 and the NVMe interface 353.

[0115] The PCIe interface 351 can be a communication path that transmits and receives commands and data according to a PCIe protocol. The NVMe interface 353 can be a communication path that transmits and receives commands and data according to an NVMe protocol. The PCIe protocol can support the NVMe protocol. Accordingly, the NVMe interface 353 can transmit / receive commands and data via the PCIe interface 351.

[0116] Figure 8A An example of a power controller 360 in the storage controller 300 according to an exemplary embodiment is shown. Figure 6

[0117] Referring to Figure 8A , the power controller 360 can include a control logic 361 (which can also be referred to herein as a control logic circuit), a power throttle lookup table (LUT) 370, a clock generator 380 (which can also be referred to herein as a clock generator circuit), and a selection circuit 390. The power throttle LUT 370 can also be referred to as a LUT.

[0118] The clock generator 380 can include phase-locked loop (PLL) circuits 381 and 383, and the selection circuit 390 can include multiplexers (MUXs) 391, 392, 393, and 394.

[0119] In Figure 8A , for ease of explanation, a processor 310 including a plurality of cores 311, 312, and 313, and an NVM controller 345 are also shown.

[0120] The core 311 can process a command provided from the host 100, the core 312 can perform address mapping and garbage collection using an FTL, and the core 313 can control the non-volatile memory devices 400a ~ 400k through the NVM controller 345.

[0121] The control logic 361 can access the LUT 370 according to the USB type information UTI, the USB version information UVI, and a request pattern based on the command CMD and the address ADDR, and can generate selection signals SSI, SS2, SS3, and SS4 by referring to entries in the LUT 370.

[0122] The LUT 370 can store information about power targets associated with a plurality of operation modes. In an exemplary embodiment, the LUT 370 can store information about frequencies of clock signals provided to the cores 311, 312, and 313, the system bus 305, and the NVM controller 345 in each of the plurality of operation modes.

[0123] ​The PLL circuit 381 can generate a base clock signal CLK1 having a first frequency, and generate divided clock signals CLKD11 and CLKD12 by dividing the base clock signal CLK1.

[0124] The PLL circuit 383 can generate a base clock signal CLK2 having a second frequency, and generate divided clock signals CLKD21 and CLKD22 by dividing the base clock signal CLK2.

[0125] The multiplexer 391 can select one of the base clock signal CLK1 and the divided clock signals CLKD11 and CLKD12 as a first selected clock signal SCLK1 in response to a first selection signal SS1, and can supply the first selected clock signal SCLK1 to the cores 311 and 313.

[0126] The multiplexer 392 can select one of the base clock signal CLK1 and the divided clock signals CLKD11 and CLKD12 as a second selected clock signal SCLK2 in response to a second selection signal SS2, and can supply the second selected clock signal SCLK2 to the system bus 305.

[0127] The multiplexer 393 can select one of the base clock signal CLK2 and the divided clock signals CLKD21 and CLKD22 as a third selected clock signal SCLK3 in response to a third selection signal SS3, and can supply the third selected clock signal SCLK3 to the core 312.

[0128] The multiplexer 394 can select one of the base clock signal CLK2 and the divided clock signals CLKD21 and CLKD22 as a fourth selected clock signal SCLK4 in response to a fourth selection signal SS4, and can supply the fourth selected clock signal SCLK4 to the NVM controller 345.

[0129] Figure 8B is a block diagram illustrating an example of control logic 361 in Figure 8A according to example embodiments.

[0130] Referring to Figure 8B , the control logic 361 can include a first detector 362 (which can also be referred to herein as a first detector circuit), a second detector 364 (which can also be referred to herein as a second detector circuit), and a selection signal generator 366 (which can also be referred to herein as a selection signal generator circuit).

[0131] The first detector 362 can generate a table selection signal TSS for selecting one of a plurality of sub-tables included in the LUT 370 based on the USB type information UTI and the USB version information UVI. The second detector 364 can detect a request mode based on the command CMD and the address ADDR to generate an entry selection signal ESS for selecting one of a plurality of entries of the selected sub-table. The selection signal generator 366 can generate the selection signals SS1, SS2, SS3, and SS4 by referring to contents stored in the selected entry of the selected sub-table.

[0132] Figure 9 An example of the LUT 370 in the memory 360 according to an exemplary embodiment is illustrated. Figure 8A

[0133] Referring to Figure 9 The LUT 370 can include a plurality of sub-tables 370a, 370b, and 370c corresponding to the USB type information UTI and the USB version information UVI.

[0134] The first sub-table 370a can include entries 371a, 372a, and 373a corresponding to the operation modes associated with the request mode when the USB type information UTI corresponds to the USB Type-C.

[0135] The entry 371a can store operating frequencies FREQ11, FREQ12, and FREQ13 of the clock signals respectively supplied to the cores 311 and 313, the system bus 305, and the cores 312 and the NVM controller 345 when the request mode indicates the sequential write operation SEQ_WR_SLC to the single-level cell. The entry 372a can store operating frequencies FREQ21, FREQ22, and FREQ23 of the clock signals respectively supplied to the cores 311 and 313, the system bus 305, and the cores 312 and the NVM controller 345 when the request mode indicates the sequential write operation SEQ_WR_TLC to the triple-level cell. The entry 373a can store operating frequencies FREQ31, FREQ32, and FREQ33 of the clock signals respectively supplied to the cores 311 and 313, the system bus 305, and the cores 312 and the NVM controller 345 when the request mode indicates the sequential read operation SEQ_RD.

[0136] The second sub-table 370b can include entries 371b, 372b, and 373b corresponding to the operation modes associated with the request mode when the USB type information UTI corresponds to the USB Type-A and the USB version information UVI corresponds to the USB 3.0 or higher.

[0137] ​Item 371b can store the operating frequencies FREQ41, FREQ42, and FREQ43 of the clock signals provided to cores 311 and 313, system bus 305, and core 312 and NVM controller 345, respectively, when the request mode indicates a sequential write operation SEQ_WR_SLC to single-level cells. Item 372b can store the operating frequencies FREQ51, FREQ52, and FREQ53 of the clock signals provided to cores 311 and 313, system bus 305, and core 312 and NVM controller 345, respectively, when the request mode indicates a sequential write operation SEQ_WR_TLC to triple-level cells. Item 373b can store the operating frequencies FREQ61, FREQ62, and FREQ63 of the clock signals provided to cores 311 and 313, system bus 305, and core 312 and NVM controller 345, respectively, when the request mode indicates a sequential read operation SEQ_RD.

[0138] Third sub-table 370c can include items 371c, 372c, and 373c corresponding to the operating modes associated with the request mode when USB type information UTI corresponds to USB A type and USB version information UVI corresponds to USB 2.0.

[0139] Item 371c can store the operating frequencies FREQ71, FREQ72, and FREQ73 of the clock signals provided to cores 311 and 313, system bus 305, and core 312 and NVM controller 345, respectively, when the request mode indicates a sequential write operation SEQ_WR_SLC to single-level cells. Item 372c can store the operating frequencies FREQ81, FREQ82, and FREQ83 of the clock signals provided to cores 311 and 313, system bus 305, and core 312 and NVM controller 345, respectively, when the request mode indicates a sequential write operation SEQ_WR_TLC to triple-level cells. Item 373c can store the operating frequencies FREQ91, FREQ92, and FREQ93 of the clock signals provided to cores 311 and 313, system bus 305, and core 312 and NVM controller 345, respectively, when the request mode indicates a sequential read operation SEQ_RD.

[0140] Figure 9 Each of sub-tables 370a, 370b, and 370c in Table 370 can also store information regarding the frequencies of the clock signals in the random write operation and the random read operation.

[0141] The control logic 361 can generate the selection signals SS1, SS2, SS3, and SS4 by referring to information on operating frequencies of the clock signals associated with each of the operation modes, and can supply the selection signals SS1, SS2, SS3, and SS4 to the multiplexers 391, 392, 393, and 394, respectively.

[0142] When the USB type information UTI corresponds to the USB Type-C, the control logic 361 generates the selection signals SS1, SS2, SS3, and SS4 such that clock signals having frequencies associated with the operation mode corresponding to the maximum power target among the plurality of operation modes are selected.

[0143] When the USB type information does not correspond to the USB Type-C and the USB version information corresponds to the USB 3.0 or higher, the control logic 361 generates the selection signals SS1, SS2, SS3, and SS4 such that clock signals having frequencies associated with the operation mode corresponding to the intermediate power target among the plurality of operation modes are selected. The intermediate power target can be greater than the minimum power target and can be less than the maximum power target.

[0144] When the USB type information UTI corresponds to the USB Type-A and the USB version information does not correspond to the USB 3.0 or higher, the control logic 361 generates the selection signals SS1, SS2, SS3, and SS4 such that clock signals having frequencies associated with the operation mode corresponding to the minimum power target among the plurality of operation modes are selected.

[0145] Figure 10 The operation of the storage controller 300 in the portable storage device 200 according to an exemplary embodiment is illustrated. Figure 5

[0146] Referring to FIG. 1, Figures 5 to 10 In an exemplary embodiment, when the portable storage device 200 is powered, the power controller 360 performs an initialization operation by setting the power target to a first power target corresponding to a default value (S110). The power controller 360 selects a first initialization mode corresponding to the first power target among a plurality of initialization modes. When the portable storage device 200 is powered, in one example, because the power controller 360 cannot obtain the USB type information of the first connector 110 and the USB version information associated with the established connection, the power controller 360 performs the initialization operation by setting the first power target among a plurality of power targets. The first power target can have the minimum power level among the plurality of power targets.

[0147] ​The connection detector 240 in the bridge chipset 220 detects the resistance of the cable assembly 30 by detecting the voltage of the CC1 pin 212 (S120). The connection detector 240 determines whether the voltage of the CC1 pin 212 is less than or equal to a threshold based on a comparison of the voltage of the CC1 pin 212 with the threshold (S130).

[0148] When the voltage of the CC1 pin 212 is less than or equal to the threshold (YES in S130), the USB type of the cable assembly 30 is USB Type-C, and the power controller 360 performs an initialization operation by setting the power target to a second power target (high) (S140). The power controller 360 selects a second initialization mode of the plurality of initialization modes corresponding to the second power target. The second power target can have a maximum power level among the plurality of power targets.

[0149] When the voltage of the CC1 pin 212 is greater than the threshold (NO in S130), the USB type of the cable assembly 30 is USB Type-A, and thus the connection detector 240 determines that the USB version information (e.g., USB link) corresponds to USB 3.0 or higher (S150).

[0150] When the USB version information corresponds to USB 3.0 or higher (YES in S150), the power controller 360 performs an initialization operation by setting the power target to a third power target (medium) (S160). The power controller 360 selects a third initialization mode of the plurality of initialization modes corresponding to the third power target. The third power target can have a power level greater than the minimum power level and less than the maximum power level, and thus the third power target can also be referred to as an intermediate or medium power target.

[0151] When the USB version information does not correspond to USB 3.0 or higher (NO in S150), the power controller 360 maintains the first initialization mode.

[0152] The controller 360 selects one of a plurality of operation modes based on the power target level in the selected initialization mode and a requested mode from the host 100, and performs power throttling based on the selected operation mode (S170).

[0153] Figure 11 is a timing diagram illustrating an initialization operation of the storage controller 300 in Figure 5 according to an exemplary embodiment.

[0154] Referring to Figures 5 to 9 and Figure 11When the portable storage device 200 is powered at a first time point T11, the connection detector 240 detects the resistance of the cable assembly 30 by detecting the voltage of the CC1 pin 212 to determine the USB type of the cable assembly 30. The USB type of the cable assembly 30 can be detected at a second time point T12.

[0155] When the USB type of the cable assembly 30 corresponds to USB Type-C (as indicated by reference numeral 375), an open operation is completed at a fourth time point T14. In this case, the power target is set to the second power target (high).

[0156] The connection detector 240 detects USB version information at a third time point T13.

[0157] When the USB type of the cable assembly 30 corresponds to USB Type-A and the USB version information corresponds to USB 3.0 or higher (as indicated by reference numeral 376), an open operation is completed at a fifth time point T15. In this case, the power target is set to the third power target (medium).

[0158] When the USB type of the cable assembly 30 corresponds to USB Type-A and the USB version information corresponds to USB 2.0 (as indicated by reference numeral 377), an open operation is completed at a sixth time point T16. In this case, the power target is set to the first power target (low).

[0159] Figure 12 Operation of the connection detector 240 in the portable storage device 200 according to an exemplary embodiment is illustrated. Figure 5

[0160] Referring to Figures 5 to 9 and Figure 12 , the portable storage device 200 is powered at a first time point T21.

[0161] After the power supply, during a first time interval INT11 from a second time point T22 to a fourth time point T24, the bridge chip set 220 (connection detector 240) is used to maintain the voltage of the first GPIO pin 221 at a first level (high level). At a third time point T23 in the first time interval INT11, the reset of the storage controller 300 is released, and the storage controller 300 starts operation. The bridge chip set 220 changes the voltage level of the first GPIO pin 221 to a second level different from the first level at the fourth time point T24, maintains the voltage level of the first GPIO pin 221 to the second level (low level) during a second time interval INT12 from the fourth time point T24 to a fifth time point T25, and changes the voltage level of the first GPIO pin 221 to the first level at the fifth time point T25.​

[0162] The power controller 360, in response to the voltage of the first GPIO pin 221 changing to the first level at the fifth time point T25, is ready to detect the voltage of the second GPIO pin 301, and the power controller 360 determines the USB type of the cable assembly 30 based on the voltage level of the second GPIO pin 301 after a third time interval INT13 has elapsed from the fifth time point T25 to the sixth time point T26.

[0163] When the voltage of the CC1 pin 212 is less than or equal to the threshold value, the connection detector 240 can inform the storage controller 300 that the USB type of the first connector 110 is USB Type-C by maintaining the voltage level of the first GPIO pin 221 at the first level during the third time interval INT13.

[0164] When the voltage of the CC1 pin 212 is greater than the threshold value, the connection detector 240 can inform the storage controller 300 that the USB type of the first connector 110 is USB Type-A by changing the voltage level of the first GPIO pin 221 to the second level and maintaining the voltage level of the first GPIO pin 221 at the second level during the third time interval INT13.

[0165] During a fourth time interval INT14 from a seventh time point T27 to an eighth time point T28, the connection detector 240 changes or maintains the voltage level of the first GPIO pin 221 to the second level, changes the voltage level of the first GPIO pin 221 to the first level at the eighth time point T28, and writes the USB version information UVI into the register 352 in the PCIe interface 351. The storage controller 300 determines the USB version of the first connector 110 in response to the write event in the register 352 at a ninth time point T29. That is, the connection detector 240 can inform the storage controller 300 of the USB type of the first connector 110 and / or the cable assembly 30 by changing the voltage level of the first GPIO pin 221 to the first level or by maintaining the voltage level of the first GPIO pin 221 at the second level during the third time interval INT13.

[0166] The time interval from the time point at which power is applied to the ninth time point T29 can correspond to an internal reference time interval, and the internal reference time interval can be less than or equal to 10 seconds.

[0167] Figure 13 is a block diagram illustrating one of the plurality of nonvolatile memory devices in the portable storage device 200 according to an exemplary embodiment. For the convenience of explanation, Figure 5 Figure 13 ​Only the non-volatile storage device 400a is shown. In an exemplary embodiment, Figure 5 The non-volatile storage devices 400a to 400k in the portable storage device 200 can all have Figure 13 The configuration shown.

[0168] Reference Figure 13 The non-volatile storage device 400a includes a memory cell array 430, an address decoder 460, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 450, and a voltage generator 470.

[0169] The memory cell array 430 can be coupled to the address decoder 460 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. Furthermore, the memory cell array 430 can be coupled to the page buffer circuit 410 via multiple bit lines BL. The memory cell array 430 may include multiple memory cells coupled to multiple word lines WL and multiple bit lines BL. The memory cell array 430 may also include multiple memory cells coupled to multiple word lines WL stacked in a vertical direction perpendicular to the substrate.

[0170] Figure 14 This illustrates an exemplary embodiment. Figure 13 Block diagram of the storage cell array 430.

[0171] Reference Figure 14 The storage cell array 430 may include multiple storage blocks BLK1 to BLKz (where z is an integer greater than 2). In an exemplary embodiment, by Figure 13 The address decoder 460 selects storage blocks BLK1 to BLKz. For example, the address decoder 460 can select the storage block BLK that corresponds to the block address among storage blocks BLK1 to BLKz.

[0172] Figure 15 This illustrates an exemplary embodiment. Figure 14 A perspective view of one of the storage blocks BLK1 to BLKz. In an exemplary embodiment, Figure 14 Storage blocks BLK1 to BLKz can all have Figure 15 The configuration of the storage block BLKi is shown.

[0173] Reference Figure 15 The storage block BLKi includes a structure extending along a first direction D1 to a third direction D3.

[0174] A substrate 611 is provided. For example, the substrate 611 can have a well of a first type (e.g., a first conductivity type). For example, the substrate 611 can have a p-well formed by implanting a Group 3 element such as boron (B). A plurality of doped regions 811 to 814 extending along a first direction D1 is disposed in / on the substrate 611. For example, the plurality of doped regions 811 to 814 can have a second type (e.g., a second conductivity type) different from the first type of the substrate 611. In an exemplary embodiment, the first doped region 811 to the fourth doped region 814 have an n-type.

[0175] In a region of the substrate 611 between the first doped region 811 and the second doped region 812, a plurality of insulating materials 612 extending along a second direction D2 is sequentially disposed along a third direction D3. For example, the plurality of insulating materials 612 can be disposed along the third direction D3 and can be spaced apart at a certain distance. Exemplarily, the insulating materials 612 can include an insulating material such as an oxide layer. However, the insulating materials 612 are not limited thereto.

[0176] In the region of the substrate 611 between the first doped region 811 and the second doped region 812, a plurality of columnar structures 613 penetrating the insulating materials 612 along the third direction D3 is sequentially disposed along the second direction D2. For example, the plurality of columnar structures 613 can penetrate the insulating materials 612 to contact the substrate 611.

[0177] For example, each columnar structure 613 can include a plurality of materials. For example, a channel layer 614 of each columnar structure 613 can include a silicon material having the first type. For example, the channel layer 614 of each columnar structure 613 can include a silicon material having the same type as the substrate 611. In an exemplary embodiment, the channel layer 614 of each columnar structure 613 includes a p-type silicon. An inner material 615 of each columnar structure 613 includes an insulating material. For example, the inner material 615 of each columnar structure 613 can include an insulating material such as silicon oxide. However, the inner material 615 is not limited thereto. For example, the inner material 615 of each columnar structure 613 can include an air gap.

[0178] In the region between the first doped region 811 and the second doped region 812, an insulating layer 616 is disposed along an exposed surface of the insulating materials 612, an exposed surface of the columnar structures 613, and an exposed surface of the substrate 611. Exemplarily, the insulating layer 616 disposed on the exposed surface of the uppermost insulating material 612 in the third direction D3 can be removed.

[0179] A plurality of first conductive materials 711 to 791 is disposed on the exposed surface of the insulating layer 616 between the first doped region 811 and the second doped region 812. For example, the first conductive material 711 extending along the second direction D2 is disposed between the substrate 611 and the insulating material 612 adjacent to the substrate 611.

[0180] The first conductive material extending along the first direction D1 is disposed between the insulating layer 616 at the top of a particular insulating material among the insulating materials 612 and the insulating layer 616 at the bottom of the particular insulating material 612 among the insulating materials 612. For example, a plurality of first conductive materials 721 to 781 extending along the first direction D1 is disposed between the insulating materials 612, and it can be understood that the insulating layer 616 is disposed between the insulating materials 612 and the first conductive materials 721 to 781. The first conductive materials 721 to 791 can include a metallic material.

[0181] In the region between the second doped region 812 and the third doped region 813, the same structure as that on the first doped region 811 and the second doped region 812 can be disposed. In the region between the second doped region 812 and the third doped region 813, a plurality of insulating materials 612 extending along the first direction D1, a plurality of columnar materials 613 arranged sequentially along the second direction D2 and penetrating the plurality of insulating materials 612 along the third direction D3, an insulating layer 616 disposed on the exposed surface of the plurality of insulating materials 612 and the exposed surface of the plurality of columnar materials 613, and a plurality of first conductive materials 713 to 793 extending along the first direction D1 are disposed.

[0182] In the region between the third doped region 813 and the fourth doped region 814, the same structure as that on the first doped region 811 and the second doped region 812 can be disposed. In the region between the third doped region 813 and the fourth doped region 814, a plurality of insulating materials 612 extending along the first direction D1, a plurality of columnar materials 613 arranged sequentially along the second direction D2 and penetrating the plurality of insulating materials 612 along the third direction D3, an insulating layer 616 disposed on the exposed surface of the plurality of insulating materials 612 and the exposed surface of the plurality of columnar materials 613, and a plurality of first conductive materials 713 to 793 extending along the first direction D1 are disposed.

[0183] A drain electrode 820 is provided on each of the plurality of pillars 613. On the drain electrode 820, a second conductive material 831 to 833 extending along the first direction D1 is provided. The second conductive materials 831 to 833 are arranged along the second direction D2 and are spaced apart at a certain distance. The second conductive materials 831 to 833 are connected to the drain electrode 820 in the corresponding region, respectively. The drain electrode 820 and the second conductive materials 831 to 833 extending along the first direction D1 can be connected by respective contact plugs. The second conductive materials 831 to 833 can include a metallic material. The second conductive materials 831 to 833 can include a conductive material such as polysilicon. However, the second conductive materials 831 to 833 are not limited thereto.

[0184] Figure 16 is an equivalent circuit diagram of a memory block BLKi according to an exemplary embodiment. Figure 15

[0185] Figure 16 The memory block BLKi can be formed in a three-dimensional structure (or a vertical structure) on a substrate. For example, a plurality of memory cell strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0186] Referring to Figure 16 , the memory block BLKi can include memory cell strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory cell strings NS11 to NS33 can include a string selection transistor SST, a plurality of memory cells MC1 to MC12, and a ground selection transistor GST.

[0187] The string selection transistor SST can be connected to a corresponding string selection line SSL1 to SSL3. The plurality of memory cells MC1 to MC12 can be connected to corresponding word lines WL1 to WL12, respectively. The ground selection transistor GST can be connected to a corresponding ground selection line GSL1 to GSL3. The string selection transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST can be connected to the common source line CSL.

[0188] Word lines (for example, WL1) having the same height can be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 can be separated.

[0189] Referring back to Figure 13 , the control circuit 450 can receive a command (signal) CMD and an address (signal) ADDR from the memory controller 300 and control an erase operation, a program operation, and a read operation of the nonvolatile memory device 400a based on the command signal CMD and the address signal ADDR.

[0190] ​For example, the control circuit 450 can generate a control signal CTL for controlling the voltage generator 470 based on the command signal CMD, and can generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 can supply the row address R_ADDR to the address decoder 460, and supply the column address C_ADDR to the data input / output circuit 420. In addition, the control circuit 450 can generate a control signal PCTL for controlling the page buffer circuit 410.

[0191] The address decoder 460 can be coupled to the memory cell array 430 through a plurality of word lines WL, a plurality of bit lines BL, and a ground selection line GSL.

[0192] The voltage generator 470 can generate a word line voltage VWL using a first operating voltage VOP1 for an operation of the nonvolatile memory device 400a based on the control signal CTL. The word line voltage VWL can be applied to the plurality of word lines WL through the address decoder 460.

[0193] The page buffer circuit 410 can be coupled to the memory cell array 430 through a plurality of bit lines BL. The page buffer circuit 410 can include a plurality of page buffers. In an exemplary embodiment, one page buffer can be connected to one bit line, or one page buffer can be connected to two or more bit lines. The page buffer circuit 410 can temporarily store data to be programmed in a selected page or data read out from the selected page. The page buffer circuit 410 can be controlled in response to a control signal PCTL from the control circuit 450.

[0194] The data input / output circuit 420 can be coupled to the page buffer circuit 410 through a data line DL. During a program operation, the data input / output circuit 420 can receive program data DTA from the memory controller 300, and supply the program data DTA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 can supply read data DTA stored in the page buffer circuit 410 to the memory controller 300 based on the column address C_ADDR received from the control circuit 450.

[0195] Figure 17 is a flowchart illustrating a method of operating a portable storage device according to an exemplary embodiment.

[0196] Referring to Figures 1 to 17A method of operating a portable storage device 200 including a plurality of nonvolatile memory devices 400a to 400k for storing data, a storage controller 300 for controlling the plurality of nonvolatile memory devices 400a to 400k, and a bridge chipset 220 connected to a first connector 110 of a host 100 through a cable assembly 30 connected to a second connector 210 of the bridge chipset 220 is provided.

[0197] According to the method in the exemplary embodiment, when power is supplied to the portable storage device 200, the bridge chipset 220 detects resistance of the cable assembly 30 (S210). The connection detector 240 in the bridge chipset 220 detects the resistance of the cable assembly 30 by detecting a voltage of the CC1 pin 212 of the second connector 210.

[0198] The connection detector 240 in the bridge chipset 220 determines a USB type of the first connector 110 based on the detected resistance (S220), and provides USB type information UTI associated with the USB type of the first connector 110 to a power controller 360 in the storage controller 300. After a USB connection is established between the portable storage device 200 and the host 100, the connection detector 240 in the bridge chipset 220 provides USB version information UVI associated with the established USB connection to the storage controller 300 (S230).

[0199] The power controller 360 selects one of a plurality of operation modes based on the USB type information UTI, the USB version information UVI, and a command-and-address-based request mode (S240). For example, the power controller 360 selects one of sub-tables 370a, 370b, and 370c based on the USB type information UTI and the USB version information UVI, and selects one of a plurality of operation modes in the selected sub-table based on the request mode.

[0200] The power controller 360 performs power throttling based on the selected operation mode such that a power target level associated with the selected operation mode is not exceeded (S250).

[0201] The power throttling can be associated with an operation of selecting a frequency of a clock signal having high performance to be provided to hardware elements such as cores 311, 312, and 313, a system bus 305, and an NVM controller 345 such that a power target level associated with the selected operation mode is not exceeded, according to the USB type information, the USB version information, and the request mode. The clock signal having high performance can mean a clock signal capable of optimizing power.

[0202] Accordingly, the portable storage device 200 can optimize power by adaptively controlling power based on a USB type of the first connector 110 of the host 100 connected via the cable assembly, USB version information between the portable storage device 200 and the host 100, and a request mode from the host.

[0203] Figure 18 is a block diagram illustrating a storage system according to an exemplary embodiment.

[0204] Referring to Figure 18 , the storage system 1000 includes a host 1100 and a portable storage device 1200.

[0205] The host 1100 and the portable storage device 1200 can be connected to each other by a cable assembly 1010.

[0206] The host 1100 includes an application 1110, a device driver 1120, a host controller 1130, a buffer random access memory (RAM) 1140, and a storage interface 1101. The host controller 1130 includes a command manager 1131, a host direct memory access (DMA) 1132, and a power manager 1133.

[0207] In operation, system-level commands (e.g., write commands) are generated by the application 1110 and the device driver 1120 of the host 1100 and then provided to the command manager 1131 of the host controller 1130.

[0208] The command manager 1131 can be used to generate respective portable storage device commands (e.g., respective commands or command sets consistent with a protocol implemented by the storage system 1000) provided to the portable storage device 1200 using the device driver 1120.

[0209] The commands generated by the command manager 1131 can also be provided to the host DMA 1132, which sends the commands to the portable storage device 1200 via the storage interface 1101. The storage interface 1101 can include a first connector (e.g., the first connector 110) and can be connected to the cable assembly 1010 by the first connector 110.

[0210] The portable storage device 1200 includes a non-volatile memory device (NVM) 1210, a device controller 1230, a buffer RAM 1240, and a host interface 1201. The device controller 1230 can include a central processing unit (CPU) 1231, a device DMA 1232, a flash DMA 1233, a command manager 1234, a buffer manager 1235, a flash translation layer (FTL) 1236, a flash manager 1237, and a power controller (PCON) 1238.

[0211] A command transmitted from the host 1100 to the portable storage device 1200 can be provided to the device DMA 1232 via the host interface 1201. The host interface 1201 can include a second connector (e.g., the second connector 210) and a bridge chip set (BCS) 1205. The bridge chip set 1205 can employ the bridge chip set 220 in Figure 5

[0212] The device DMA 1232 can then transfer the received command to the command manager 1234. The command manager 1234 can be used to allocate storage space in the buffer RAM 1240 to receive corresponding write data via the buffer manager 1235. Once the portable storage device 1200 is ready to receive the write data, the command manager 1234 can transfer a transmission "ready" signal to the host 1100.

[0213] Upon receiving the transmission ready signal, the host 1100 transfers the write data to the portable storage device 1200. The write data can be sent to the portable storage device 1200 using the host DMA 1132 and the storage interface 1101.

[0214] The portable storage device 1200 can then store the received write data in the buffer RAM 1240 using the device DMA 1232 and the buffer manager 1235. The write data stored in the buffer RAM 1240 can then be provided to the flash manager 1237 via the flash DMA 1233. The flash manager 1237 can be used to program the write data according to the addresses of the non-volatile memory device 1210 derived from the address mapping table by the flash translation layer 1236.

[0215] Once the transmission and programming of the write data are completed, the portable storage device 1200 can send a response to the host 1100 to inform the host 1100 that the write command has been successfully executed. Based on the received response signal, the host 1100 indicates to the device driver 1120 and the application 1110 that the command is completed, and thereafter will terminate the execution of the operation corresponding to the command.

[0216] ​As described above, the host 1100 and the portable storage device 1200 can exchange data and corresponding control signal(s) (e.g., a ready signal and a response signal) via data lines (e.g., data lines DIN and DOUT) of the data segment. In addition, the host 1100 can provide a command CMD and an address ADDR to the portable storage device 1200.

[0217] The power controller 1238 can employ a power controller 360 in Figure 8A

[0218] Accordingly, in the portable storage device 1200 in the storage system 1000, the bridge chipset 1205 can detect a resistance of the cable assembly 1010 in response to power applied to the portable storage device 1200 from the host 1100 through the cable assembly 1010, and can determine a USB type of the first connector 110 based on the detected resistance.

[0219] In addition, when a USB connection is established between the host 1100 and the portable storage device 1200, the portable storage device 1200 can obtain USB version information. The power controller 1238 can select one of a plurality of operation modes based on the USB type, the USB version information, and a request mode from the host 1100, and can perform power throttling based on the selected operation mode. Accordingly, the portable storage device 1200 can improve performance by adaptively controlling power.

[0220] The portable storage device or the storage system according to exemplary embodiments can be packaged using various package types or package configurations.

[0221] Exemplary embodiments of the present disclosure can be applied to various portable storage devices and various electronic devices connected to the portable storage devices.

[0222] ​As is conventional in the art of the present disclosure, the exemplary embodiments are described in terms of functional blocks, units, and / or modules, and are illustrated in the attached drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, and the like, which can be formed using semiconductor-based fabrication techniques or other implementation techniques. In the case of blocks, units, and / or modules that are implemented by microprocessors or similar, they can be programmed with software (e.g., microcode) to perform the various functions discussed herein, and they can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by special purpose hardware, or can be implemented as a combination of special purpose hardware and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs some functions. In addition, each block, unit, and / or module of the exemplary embodiments can be physically separated or combined in to two or more interacting and discrete blocks, units, and / or modules without departing from the scope of the present invention. Furthermore, blocks, units, and / or modules of the exemplary embodiments can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the present disclosure.

[0223] As those skilled in the art will appreciate, the various aspects of the present disclosure can be implemented as a system, method or computer program product. Accordingly, aspects of the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, built-in software, microcode, etc.) or an embodiment combining software aspects and hardware aspects (in general, any combination of hardware and software aspects can be made herein, which can be referred to collectively as a "circuit," "module," "unit" or "system"). Furthermore, aspects of the present disclosure can take the form of a computer program product on one or more computer readable medium(s) having computer readable program code embodied therewith. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a tangible, non-transitory computer-readable medium. The terms "computer readable medium" and "computer program product" can include any medium that can store or transfer information for use by or in connection with the computers or processors hereof. The computer-readable medium can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium. The computer-readable medium can also be paper or another suitable medium upon which the computer program code can be printed or otherwise stored.

[0224] In this document, the term "circuitry" can refer to analog circuitry or digital circuitry. In the case of digital circuitry, the digital circuitry can be hardwired to perform the respective tasks of the circuitry, such as a digital processor executing instructions to perform the respective tasks of the circuitry. Examples of such processors include application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs).

[0225] In exemplary embodiments of the present disclosure, a three-dimensional (3D) memory array is provided. The 3D memory array is formed monolithically in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above the substrate or within the substrate. The term "monolithic" indicates that the layers of each level of the array are deposited directly on the layers of each next level of the array. In exemplary embodiments of the present disclosure, the 3D memory array includes vertically oriented vertical NAND strings such that at least one memory cell is located above another memory cell. The at least one memory cell can include a charge trapping layer. Suitable configurations of a three-dimensional memory array are described in the following patent documents, which are incorporated herein by reference: U.S. Patents Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0226] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A portable storage device comprising: a plurality of non-volatile memory devices configured to store data; a storage controller configured to control the plurality of non-volatile memory devices; and a bridge chipset connected to a first connector of a host through a cable assembly, wherein the bridge chipset is configured to: detect a resistance of the cable assembly; provide, to the storage controller, universal serial bus (USB) type information of the first connector based on the detected resistance; and provide, to the storage controller, USB version information associated with an established USB connection after the USB connection is established with the host, wherein the storage controller is configured to: select one of a plurality of operating modes based on the USB type information, the USB version information, and a request mode from the host indicating a random access to the data or a sequential access to the data; select a clock signal having a maximum frequency, the selected clock signal consuming less power than an available maximum power level associated with the selected operating mode at the maximum frequency; and perform power throttling based on the selected clock signal.

2. The portable storage device of claim 1, wherein: the bridge chipset comprises a connection detector configured to detect the resistance of the cable assembly via a first pin of a plurality of pins in a second connector of the portable storage device, wherein the second connector is connected to the cable assembly and the first pin corresponds to a first configuration channel (CC) pin among the plurality of pins in the second connector; the first CC pin is used for at least one of detecting a connection of the portable storage device, determining a plug-in direction of a plug, and managing a configuration of the portable storage device and the host; and the bridge chipset is configured to provide the USB type information to the storage controller through a first general purpose input / output (GPIO) pin.

3. The portable storage device of claim 2, wherein the connection detector is further configured to: hold a voltage level of the first GPIO pin hardwired to a second GPIO pin of the storage controller at a first level during a first time interval after power is applied; change the voltage level of the first GPIO pin to a second level different from the first level during a second time interval succeeding the first time interval; and change the voltage level of the first GPIO pin to the first level at a point in time in a third time interval succeeding the second time interval, wherein the storage controller is further configured to: determine the USB type information based on a voltage level of the second GPIO pin after the third time interval elapses; write the USB type information into a register in the storage controller for a fourth time interval succeeding the third time interval; and determine the USB version information in response to a write event in the register. ​ ​ 4. The portable storage device of claim 3, wherein, The connection detector is further configured to inform the storage controller of a USB type of the first connector being a USB Type-C based on a comparison of a voltage of the first CC pin to a threshold by maintaining the voltage level of the first GPIO pin at the first level during the third time interval.

5. The portable storage device of claim 3, wherein, The connection detector is further configured to inform the storage controller of a USB type of the first connector being a USB Type-A based on a comparison of a voltage of the first CC pin to a threshold by changing the voltage level of the first GPIO pin from the first level to the second level during the third time interval.

6. The portable storage device of claim 1, wherein, The storage controller comprises: an interface unit configured to perform an interface connection between the host and the non-volatile storage device; and a power controller configured to select one of the plurality of operating modes based on the USB type information, the USB version information, and the request mode to perform power throttling, wherein a connection detector disposed in the bridge chipset is configured to: provide the USB type information to the storage controller through a first general purpose input / output (GPIO) pin of the connection detector, wherein the first GPIO pin is hardwired to a second GPIO pin of the storage controller; and write the USB version information into a register in a peripheral component interconnect express (PCIe) interface in the interface unit.

7. The portable storage device of claim 6, wherein the bridge chipset and the storage controller are configured to communicate with each other via sideband communication through the first GPIO pin and the second GPIO pin; and the connection detector and the register in the PCIe interface are configured to communicate with each other via in-band communication and through a quick non-volatile memory express (NVMe) interface.

8. The portable storage device of claim 6, wherein, The power controller is further configured to: select the clock signal with the maximum frequency based on the USB type information, the USB version information in the register, and the request mode; and perform the power throttling to adjust a power level consumed in the selected operating mode.

9. The portable storage device of claim 6, wherein the power controller comprises a lookup table comprising a plurality of sub-tables storing information about power targets associated with the plurality of operating modes respectively according to the USB type information, the USB version information in the register, and the request mode; the power controller is further configured to select one of the plurality of sub-tables based on the USB type information and the USB version information; and the power controller is further configured to select one of a plurality of entries in the selected sub-table based on the request mode to perform the power throttling.

10. The portable storage device of claim 9, wherein, The power controller is further configured to: select one of the plurality of sub-tables in response to the USB type information indicating that the USB type of the first connector corresponds to a USB Type-C; and The power throttling is performed by selecting an entry corresponding to the request pattern from among entries of the selected sub-table.

11. The portable storage device of claim 9, wherein, The power controller is further configured to: determine whether the USB version information corresponds to USB 3.0 or higher, in response to the USB type information indicating that the first connector does not correspond to USB Type-C; select one of the plurality of sub-tables, in response to the USB version information corresponding to USB 3.0 or higher; and perform the power throttling by selecting an entry corresponding to the request pattern from among entries of the selected sub-table.

12. The portable storage device of claim 9, wherein, The power controller is further configured to: determine whether the USB version information corresponds to USB 3.0 or higher, in response to the USB type information indicating that the first connector does not correspond to USB Type-C; select one of the plurality of sub-tables, in response to the USB version information not corresponding to USB 3.0 or higher; and perform the power throttling by selecting an entry corresponding to the request pattern from among entries of the selected sub-table.

13. The portable storage device of claim 9, wherein, The storage controller further includes a plurality of cores configured to perform control operations associated with the non-volatile storage device, wherein the power controller further includes: a clock generator configured to generate a base clock signal and generate a divided clock signal by dividing the base clock signal, and provide the base clock signal and the divided clock signal as the selected clock signals to the plurality of cores; a selection circuit configured to select the selected clock signals provided to the plurality of cores in response to a selection signal; and control logic configured to generate the selection signal based on the USB type information, the USB version information, and the request pattern.

14. The portable storage device of claim 13, wherein, The control logic includes: a first detector configured to generate a table selection signal for selecting one of the sub-tables based on the USB type information and the USB version information; a second detector configured to detect the request pattern based on a command and an address from the host, and generate an entry selection signal for selecting one of a plurality of entries in the selected sub-table; and a selection signal generator configured to generate the selection signal by referring to the selected entry in the selected sub-table.

15. The portable storage device of claim 14, wherein, The control logic is further configured to generate the selection signal such that a clock signal having a frequency associated with an operation mode corresponding to a maximum power target among the plurality of operation modes is selected, in response to the USB type information indicating that the first connector corresponds to USB Type-C.

16. The portable storage device of claim 14, wherein, The control logic is further configured to, in response to the USB type information indicating that the first connector does not correspond to USB Type-C and the USB version information corresponding to USB 3.0 or higher, generate the selection signal such that a clock signal having a frequency associated with an operation mode corresponding to an intermediate power target among the plurality of operation modes is selected, wherein the intermediate power target is greater than a minimum power target and less than a maximum power target.

17. The portable storage device of claim 1, wherein, The plurality of non-volatile memory devices each include a memory cell array, and the memory cell array includes a plurality of memory cells coupled to a plurality of word lines stacked in a vertical direction perpendicular to a substrate. 18.A method of operating a portable storage device, comprising: detecting a resistance of a cable assembly in a bridge chip set, wherein the portable storage device includes a plurality of non-volatile memory devices configured to store data, a storage controller configured to control the plurality of non-volatile memory devices, and the bridge chip set connected to a first connector of a host through the cable assembly connected to a second connector of the bridge chip set; based on the detected resistance, determining universal serial bus (USB) type information of the first connector; after a USB connection is established between the host and the portable storage device, providing USB version information associated with the established USB connection to the storage controller; in the storage controller, selecting one of a plurality of operation modes based on the USB type information, the USB version information, and a request mode from the host indicating random access to the data or sequential access to the data; and performing power throttling based on the selected operation mode.

19. The method of claim 18, wherein, The bridge chip set is configured to: provide the USB type information to the storage controller through a first general purpose input / output pin; and write the USB version information into a register in a peripheral component interconnect express (PCIe) interface in an interface unit included in the storage controller. 20.A portable storage device, comprising: a plurality of non-volatile memory devices configured to store data; a storage controller configured to control the plurality of non-volatile memory devices; and a bridge chip set connected to a first connector of a host through a cable assembly, wherein the bridge chip set is configured to: detect a resistance of the cable assembly; based on the detected resistance, provide connection information of the first connector to the storage controller; and after a connection is established with the host, provide version information associated with the established connection to the storage controller, wherein the storage controller is configured to: select one of a plurality of operation modes based on the connection information, the version information, and a request mode from the host indicating random access to the data or sequential access to the data; and perform power throttling based on the selected operation mode. selecting a clock signal having a maximum frequency, the selected clock signal consuming less power than an available maximum power level associated with the selected mode of operation at the maximum frequency; and performing power throttling based on the selected clock signal.

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