A cell structure of a ferroelectric memory and a method for preparing the same

Abstract

The present invention provides a unit structure of a ferroelectric memory and a preparation method thereof, wherein the unit structure of the ferroelectric memory comprises a substrate, two n+ regions, a source, a drain, a first oxide layer, a second oxide layer, a third oxide layer, a ferroelectric film and a gate; a first oxide layer is deposited on the substrate, a first rectangular window and a second rectangular window are etched on the first oxide layer, two n+ regions, a source and a drain are formed at the first rectangular window and the second rectangular window, a second oxide layer is deposited on the first oxide layer, the source and the drain, a third rectangular window is arranged in the second oxide layer, a ferroelectric film is deposited in the third rectangular window, a third oxide layer is deposited on the second oxide layer and the ferroelectric film, and a gate is deposited on the third oxide layer. The unit structure of the ferroelectric memory of the present invention helps to improve the retention performance of the ferroelectric field effect transistor memory, so as to realize the practical application of the ferroelectric field effect transistor memory.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic device design and preparation, and in particular to a unit structure of a ferroelectric memory and a preparation method thereof. Background Art

[0002] As a new type of non-volatile memory, ferroelectric memory has the advantages of low power consumption, high density, high speed, radiation resistance and non-volatility. It is particularly in line with the aerospace field's requirements for electronic equipment to be radiation-resistant, miniaturized, low power consumption and have a long life. Therefore, it is considered to have great potential for space applications.

[0003] The two main types of ferroelectric memory are ferroelectric capacitor memory and ferroelectric field effect transistor memory. The currently commercially available ferroelectric memory is ferroelectric capacitor memory, but it has shortcomings such as destructive reading and complex cell structure. Compared with ferroelectric capacitor memory, ferroelectric field effect transistor memory has more advantages such as simple cell structure, higher storage density and compliance with the law of proportional reduction of ultra-large-scale integrated circuits, and has become the focus of ferroelectric researchers. However, ferroelectric field effect transistors have not yet been put into practical use due to their poor retention performance. Theoretical studies have shown that under appropriate conditions, there is no problem in achieving the retention performance of ferroelectric field effect transistors that can reach the ten years of commercial use. The reasons why the retention performance of ferroelectric field effect transistors cannot meet commercial requirements may be that the design of the cell structure is unreasonable, the materials used in each part of the cell structure are not suitable, and the preparation process is not perfect. Summary of the invention

[0004] In view of the problems existing in the prior art, the purpose of the present invention is to provide a cell structure of a ferroelectric memory and a preparation method thereof, aiming to solve the problem of poor retention performance of ferroelectric field effect transistor memory, that is, to solve the problem that the retention performance of ferroelectric field effect transistor memory is difficult to reach commercial goals through reasonable cell structure design and appropriate preparation method, in order to realize the practical application of ferroelectric field effect transistor memory.

[0005] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are particularly adopted:

[0006] The present invention provides a method for preparing a cell structure of a ferroelectric memory, comprising the following steps:

[0007] Uniformly depositing a first oxide layer on the upper surface of the substrate;

[0008] A first rectangular window and a second rectangular window with a width of D2 and penetrating in the width direction of the first oxide layer are symmetrically etched on the first oxide layer at a distance from the wide side D1 thereof, so that the upper surface of the substrate is exposed at the first rectangular window and the second rectangular window, and the distance between adjacent sides of the first rectangular window and the second rectangular window is D3;

[0009] Implant n-type impurities at the first rectangular window and the second rectangular window by ion implantation, and form two n+ regions by high temperature diffusion to form two heavily doped n-type regions;

[0010] Removing n-type impurities that have not diffused into the substrate from the first rectangular window and the second rectangular window, and depositing a conductive layer flush with the first oxide layer at the first rectangular window and the second rectangular window to form a source and a drain;

[0011] Uniformly depositing a second oxide layer on the first oxide layer and the source electrode and the drain electrode;

[0012] Etching a third rectangular window with a width of S1 and a length of L1 in the central area of ​​the second oxide layer;

[0013] Depositing a ferroelectric film flush with the second oxide layer at the third rectangular window, and performing annealing and polarization treatment on the ferroelectric film;

[0014] uniformly depositing a third oxide layer on the second oxide layer and the ferroelectric thin film;

[0015] A conductive material is deposited in a rectangular area with a width of S2 and a length of L2 set on the third oxide layer to form a gate.

[0016] Preferably, the substrate is a p-type Si substrate.

[0017] Preferably, the third rectangular window coincides with the center of the second oxide layer, the width direction of the third rectangular window is consistent with the length direction of the second oxide layer, and the width S1 of the third rectangular window is smaller than the adjacent edge distance D3, and the length L1 of the third rectangular window is smaller than the width of the second oxide layer.

[0018] Preferably, the gate coincides with the center of the ferroelectric film, and the width direction of the gate is consistent with the width direction of the ferroelectric film.

[0019] Preferably, the width S2 of the gate is greater than the width S1 of the third rectangular window and less than the adjacent edge distance D3, and the length L2 of the gate is greater than the length L1 of the third rectangular window.

[0020] Preferably, before the step of uniformly depositing the third oxide layer on the second oxide layer and the ferroelectric film, the ferroelectric film is firstly polarized.

[0021] Preferably, the first oxide layer, the second oxide layer and the third oxide layer are made of different oxide insulating materials.

[0022] Preferably, the first oxide layer, the second oxide layer and the third oxide layer are made of the same oxide insulating material.

[0023] The present invention also provides a cell structure of a ferroelectric memory, which includes: a substrate, two heavily doped n-type regions, a source electrode, a drain electrode, a first oxide layer, a second oxide layer, a third oxide layer, a ferroelectric film and a gate electrode;

[0024] A first oxide layer is deposited on the substrate, a first rectangular window and a second rectangular window are etched on the first oxide layer, the two heavily doped n-type regions are formed in the substrate at the first rectangular window and the second rectangular window, and a source and a drain are respectively arranged at the first rectangular window and the second rectangular window, the second oxide layer is deposited on the first oxide layer, the source and the drain, a third rectangular window is arranged in the second oxide layer, the ferroelectric film is deposited in the third rectangular window, the third oxide layer is deposited on the second oxide layer and the ferroelectric film, and a gate is deposited on the third oxide layer.

[0025] In summary, the various components of the unit structure constitute a MOS structure, but it is different from the traditional MOS structure. The difference is that the oxide layer is composed of the first oxide layer, the second oxide layer, the third oxide layer and the ferroelectric film, and the ferroelectric film is surrounded by the first oxide layer, the second oxide layer and the third oxide layer, thereby improving the relevant performance of the unit structure of the entire ferroelectric memory.

[0026] In addition, the present invention also provides a novel annealing method for ferroelectric thin films, namely, placing a ferroelectric memory unit with a prepared ferroelectric thin film in a closed cavity with adjustable atmosphere, repeatedly irradiating the ferroelectric thin film with a laser of a specific wavelength at a certain time interval for a period of time, and simultaneously applying an electric field perpendicular to the plane of the ferroelectric thin film to the ferroelectric thin film, wherein the applied electric field is a constant electric field or an alternating electric field, or a combination of a constant electric field and an alternating electric field. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0028] Figure 1 A schematic diagram of the front view and top view of the ferroelectric memory unit after the first oxide layer is deposited according to an embodiment of the present invention;

[0029] Figure 2A schematic diagram of the front view and top view of the ferroelectric memory unit after etching the first rectangular window and the second rectangular window provided in an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of the front view and top view of the structure of a ferroelectric memory unit after two heavily doped n-type regions are manufactured according to an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the front view and top view of the structure of a ferroelectric memory unit after the drain and source are manufactured according to an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of the front view and top view of the ferroelectric memory unit after the second oxide layer is deposited according to an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of the front view and top view of the ferroelectric memory unit after etching the third rectangular window provided by an embodiment of the present invention;

[0034] Figure 7 A schematic diagram of the front view and top view of the structure of a ferroelectric memory cell after depositing a ferroelectric thin film provided by an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of the front view and top view of the structure of a ferroelectric memory unit after depositing a third oxide layer provided by an embodiment of the present invention;

[0036] Fig. 9 The schematic diagram of the front view and top view of the ferroelectric memory unit after the gate is manufactured according to the embodiment of the present invention.

[0037] Reference numerals:

[0038] 1-first oxide layer, 2-second oxide layer, 3-third oxide layer, 4-substrate, 5-first rectangular window, 6-second rectangular window, 7-third rectangular window, 8-heavily doped n-type region, 9-source, 10-drain, 11-ferroelectric film, 12-gate. DETAILED DESCRIPTION

[0039] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and specific implementation methods. In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0040] In order to more clearly explain the technical solution of the present invention, it is described in the form of specific embodiments below.

[0041] Example

[0042] In a first aspect, an embodiment of the present invention provides a ferroelectric memory cell structure, wherein the ferroelectric memory cell structure comprises:

[0043] A p-type Si substrate 4, two heavily doped n-type regions 8, a source 9, a drain 10, a first oxide layer 1, a second oxide layer 2, a third oxide layer 3, a ferroelectric film 11 and a gate 12, wherein the p-type Si substrate 4 is an n-type lightly doped cubic Si, and the various components of the unit structure constitute a MOS structure, but are different from the traditional MOS structure, the difference being that the oxide layer is composed of the first oxide layer 1, the second oxide layer 2, the third oxide layer 3 and the ferroelectric film 11, and the ferroelectric film 11 is surrounded by the first oxide layer 1, the second oxide layer 2, and the third oxide layer 3, as shown in FIG. Fig. 9 shown.

[0044] In a second aspect, in order to realize the ferroelectric memory cell structure provided by the present invention, an embodiment of the present invention provides a method for preparing a ferroelectric memory cell structure:

[0045] 1) The first oxide layer 1 is uniformly deposited on the upper surface of the p-type Si substrate 4. The ferroelectric memory cell structure after the first oxide layer 1 is deposited is as follows: Figure 1 As shown;

[0046] 2) A first rectangular window 5 and a second rectangular window 6 having a width of D2 and penetrating in the width direction of the first oxide layer 1 are symmetrically etched on the first oxide layer 1 at a distance from the wide side D1 thereof, so that the upper surface of the p-type Si substrate 4 is exposed at the first rectangular window 5 and the second rectangular window 6. The distance between the adjacent sides of the first rectangular window 5 and the second rectangular window 6 is D3. The ferroelectric memory cell structure after etching the first rectangular window 5 and the second rectangular window 6 is as follows: Figure 2 As shown;

[0047] 3) A sufficient dose of n-type impurities is ion-implanted into the first rectangular window 5 and the second rectangular window 6, and two n+ regions, i.e., heavily doped n-type regions 8, are formed by high-temperature diffusion for a certain period of time. The ferroelectric memory cell structure after the two n+ regions are formed is as follows: Figure 3 As shown;

[0048] 4) removing the n-type impurities that have not diffused into the p-type Si substrate 4 at the first rectangular window 5 and the second rectangular window 6, and depositing a conductive layer flush with the first oxide layer 1 at the first rectangular window 5 and the second rectangular window 6 to form the source 9 and the drain 10. The ferroelectric memory cell structure after the source 9 and the drain 10 are manufactured is as follows: Figure 4 As shown;

[0049] 5) uniformly depositing a second oxide layer 2 on the first oxide layer 1, the source electrode 9 and the drain electrode 10. The ferroelectric memory cell structure after depositing the second oxide layer 2 is as follows: Figure 5 As shown;

[0050] 6) etching a third rectangular window 7 with a width of S1 and a length of L1 in the central area of ​​the second oxide layer 2, the third rectangular window 7 coincides with the center of the second oxide layer 2, the width direction of the third rectangular window 7 is consistent with the length direction of the second oxide layer 2, and the width S1 is less than D3, and the length L1 is less than the width of the second oxide layer. The ferroelectric memory unit structure after etching the third rectangular window 7 is as follows: Figure 6 As shown;

[0051] 7) A ferroelectric film 11 flush with the second oxide layer 2 is deposited at the third rectangular window 7, and the ferroelectric film 11 is annealed and polarized. The ferroelectric memory cell structure after the ferroelectric film 11 is deposited is as follows: Figure 7 As shown;

[0052] 8) The third oxide layer 3 is uniformly deposited on the second oxide layer 2 and the ferroelectric film 11. The ferroelectric memory cell structure after the third oxide layer 3 is deposited is as follows: Figure 8 As shown, and preferably before depositing the third oxide layer 3, the ferroelectric film 11 is polarized;

[0053] 9) A conductive material is deposited on a rectangular area with a width of S2 and a length of L2 set on the third oxide layer 3 to form the gate 12. The gate 12 coincides with the center of the ferroelectric film 11. The width direction of the gate 12 is consistent with the width direction of the ferroelectric film 11. The width S2 is greater than the width S1 and less than D3. The length L2 is greater than the length L1. The ferroelectric memory cell structure after the gate 12 is manufactured is as follows: Fig. 9 shown.

[0054] The first oxide layer 1, the second oxide layer 2 and the third oxide layer 3 can be made of the same oxide insulating material or different oxide insulating materials. Figure 1-Figure 9 In the figure, the structure located at the upper part is a schematic diagram of the front view structure of the ferroelectric memory unit, and the structure located at the lower part is a schematic diagram of the top view structure of the ferroelectric memory unit, which is explained here.

[0055] On the third aspect, the annealing treatment of the ferroelectric film 11 provided in the embodiment of the present invention adopts a novel annealing method, and the specific operating steps are: placing the ferroelectric memory unit with the prepared ferroelectric film 11 in a closed cavity with adjustable atmosphere, using a laser of a specific wavelength to repeatedly irradiate the ferroelectric film 11 for a period of time at a certain time interval, and at the same time applying an electric field perpendicular to the plane of the ferroelectric film 11 to the ferroelectric film 11, and the applied electric field is a constant electric field or an alternating electric field, or a combination of a constant electric field and an alternating electric field.

[0056] The design structure provided by the present invention makes the ferroelectric film 11 surrounded by an oxide layer, reducing or even avoiding the influence of leakage current on the ferroelectric polarization retention performance. At the same time, this surrounding structure gives the ferroelectric film 11 appropriate stress constraints, which improves the coercive field of the ferroelectric film 11 to a certain extent, which can improve the ferroelectric polarization retention performance. In the design structure provided by the present invention, the length and width of the gate 12 are both larger than the length and width of the ferroelectric film 11, and the ferroelectric film 11 is completely covered, reducing the influence of the edge effect on the ferroelectric polarization.

[0057] In the preparation method provided by the present invention, the annealing method of the ferroelectric film 11 is adopted to make the ferroelectric film 11 in a relatively independent high-temperature state during the annealing treatment, thereby avoiding the entire ferroelectric memory cell structure being in a high-temperature environment for annealing the ferroelectric film 11, thereby avoiding the performance degradation of other parts of the ferroelectric memory cell structure that may occur under the high temperature of the traditional ferroelectric film 11 furnace annealing, that is, achieving the compatibility of the annealing process of the ferroelectric film 11 with the CMOS process; at the same time, before depositing the third oxide layer 3, the ferroelectric film 11 is polarized, which can provide the ferroelectric film 11 with a stress constraint that is conducive to the maintenance of ferroelectric polarization, thereby further improving the ferroelectric polarization retention performance.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a cell structure of a ferroelectric memory, characterized in that: The steps include: Uniformly depositing a first oxide layer on the upper surface of the substrate; A first rectangular window and a second rectangular window with a width of D2 and penetrating in the width direction of the first oxide layer are symmetrically etched on the first oxide layer at a distance from the wide side D1 thereof, so that the upper surface of the substrate is exposed at the first rectangular window and the second rectangular window, and the distance between adjacent sides of the first rectangular window and the second rectangular window is D3; Implant n-type impurities at the first rectangular window and the second rectangular window by ion implantation, and form two n+ regions by high temperature diffusion to form two heavily doped n-type regions; Removing n-type impurities that have not diffused into the substrate from the first rectangular window and the second rectangular window, and depositing a conductive layer flush with the first oxide layer at the first rectangular window and the second rectangular window to form a source and a drain; Uniformly depositing a second oxide layer on the first oxide layer and the source electrode and the drain electrode; Etching a third rectangular window with a width of S1 and a length of L1 in the central area of ​​the second oxide layer; Depositing a ferroelectric film flush with the second oxide layer at the third rectangular window, and performing annealing and polarization treatment on the ferroelectric film; uniformly depositing a third oxide layer on the second oxide layer and the ferroelectric thin film; A conductive material is deposited in a rectangular area with a width of S2 and a length of L2 set on the third oxide layer to form a gate.

2. The preparation method according to claim 1, characterized in that: The third rectangular window coincides with the center of the second oxide layer, the width direction of the third rectangular window is consistent with the length direction of the second oxide layer, the width S1 of the third rectangular window is smaller than the adjacent edge distance D3, and the length L1 of the third rectangular window is smaller than the width of the second oxide layer.

3. The preparation method according to claim 1, characterized in that: The gate coincides with the center of the ferroelectric film, and the width direction of the gate is consistent with the width direction of the ferroelectric film.

4. The preparation method according to claim 1, characterized in that: The width S2 of the gate is greater than the width S1 of the third rectangular window and less than the adjacent edge distance D3, and the length L2 of the gate is greater than the length L1 of the third rectangular window.

5. The preparation method according to claim 1, characterized in that: Before the step of uniformly depositing the third oxide layer on the second oxide layer and the ferroelectric film, the ferroelectric film is firstly polarized.

6. The preparation method according to claim 1, characterized in that: The first oxide layer, the second oxide layer and the third oxide layer are made of different oxide insulating materials.

7. The preparation method according to claim 1, characterized in that: The first oxide layer, the second oxide layer and the third oxide layer are made of the same oxide insulating material.

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