Semiconductor memory device including a capacitor

Abstract

Semiconductor memory devices and operating methods are provided. A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a substrate and including a plurality of peripheral circuits, a horizontal semiconductor layer disposed on the peripheral logic structure, a plurality of stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layer, a plurality of electrode isolation regions extending in the first direction and a second direction and separating the plurality of stack structures, the electrode isolation regions connected to the horizontal semiconductor layer, and a plurality of through structures disposed in the peripheral logic structure to penetrate the stack structures in the first direction, one side of each of the through structures connected to a through channel contact, wherein the electrode pads form a capacitance with at least one of the electrode isolation regions or at least one of the through structures, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0144018, filed on November 12, 2019, and all the benefits thereof, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor memory devices, and more specifically, to three-dimensional (3D) semiconductor memory devices that include capacitors and have improved reliability and integration. Background Technology

[0004] To meet consumer demand for high performance and low prices, it is necessary to increase the integration density of semiconductor memory devices. Since integration density is a crucial factor determining the price of semiconductor memory devices, increasing it is essential. The integration density of two-dimensional (2D) (or planar) semiconductor memory devices is determined by the area occupied by each memory cell; therefore, the integration density can be highly influenced by the level of fine patterning technology.

[0005] However, the need for expensive equipment to fabricate intricate patterns presents a significant limitation in improving the integration density of 2D semiconductor memory devices. Therefore, memory devices in which memory cells are arranged in three dimensions have been proposed. Summary of the Invention

[0006] Embodiments of this disclosure provide a semiconductor memory device including a vertical channel structure with improved reliability and integration.

[0007] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of this disclosure.

[0008] According to embodiments of the present disclosure, a three-dimensional (3D) semiconductor memory device includes: a peripheral logic structure disposed on a substrate and including a plurality of peripheral circuits; a horizontal semiconductor layer disposed on the peripheral logic structure; a plurality of stacked structures in which a molding layer and electrode pads are alternately stacked on the horizontal semiconductor layer in a first direction; a plurality of electrode isolation regions extending in a first direction and in a second direction and separating the plurality of stacked structures, the electrode isolation regions being connected to the horizontal semiconductor layer; and a plurality of through structures disposed in the peripheral logic structure to penetrate the stacked structures in the first direction, one side of each of the plurality of through structures being connected to a through-channel contact, wherein the electrode pads form capacitances with at least one electrode isolation region of the plurality of electrode isolation regions or at least one through structure of the plurality of through structures.

[0009] According to another embodiment of this disclosure, a three-dimensional (3D) semiconductor memory device includes: a plurality of stacked structures in which a molding layer and electrode pads are alternately stacked on a horizontal semiconductor layer in a first direction, the plurality of stacked structures including a memory cell array region and a peripheral region; a plurality of electrode isolation regions extending in a second direction, the electrode isolation regions being spaced apart from each other in a third direction to separate the plurality of stacked structures; and

[0010] Multiple through structures are disposed in the peripheral region between at least two adjacent electrode isolation regions and penetrate the stacked structure in a first direction. One side of each of the multiple through structures is connected to a through-hole channel contact. In the peripheral region, the stacked structures are stacked upward in a second direction and a third direction to have the same width.

[0011] According to another embodiment of the present disclosure, a three-dimensional (3D) semiconductor memory device includes: at least one peripheral region in which a molding layer and electrode pads are alternately arranged on a horizontal semiconductor layer; a plurality of electrode isolation regions extending in the peripheral region in word line and bit line directions and spaced apart from each other; a molding region disposed between two adjacent electrode isolation regions in the plurality of electrode isolation regions; and a plurality of through structures that vertically penetrate the molding region, wherein the electrode pads form a capacitor with at least one of the plurality of through structures or one of the electrode isolation regions.

[0012] Other features and embodiments will be apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0013] The above and other embodiments and features of this disclosure will become more apparent from the detailed description of the embodiments of this disclosure with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram of a semiconductor memory device according to some embodiments of the present disclosure.

[0015] Figure 2 This is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure.

[0016] Figure 3 This is a circuit diagram illustrating one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments of the present disclosure.

[0017] Figure 4 This is a layout diagram of a semiconductor memory device according to some embodiments of the present disclosure.

[0018] Figure 5A and Figure 5B It is shown Figure 4 Plan view of some of the multiple stacked structures shown.

[0019] Figure 6 It is shown Figure 4 A plan view of one of the stacked structures shown.

[0020] Figure 7 It is along Figure 6 A cross-sectional view taken from line A-A'.

[0021] Figure 8A It shows Figure 6 Y is a portion of the peripheral region FR of a semiconductor memory device.

[0022] Figure 8B It is along Figure 8A The cross-sectional view taken from line B1-B1'.

[0023] Figure 9A The peripheral region of a semiconductor memory device according to some embodiments of the present disclosure is shown.

[0024] Figure 9B It is along Figure 9A The cross-sectional view taken from line B2-B2'.

[0025] Figure 10A The peripheral region of a semiconductor memory device according to some embodiments of the present disclosure is shown.

[0026] Figure 10B and Figure 10C It is along Figure 10A The cross-sectional view taken from line B3-B3'.

[0027] Figure 11 yes Figure 1 A block diagram of an exemplary peripheral circuit.

[0028] Figure 12 This is a block diagram of a storage device including a 3D semiconductor memory device according to some embodiments of the present disclosure. Detailed Implementation

[0029] Figure 1 This is a block diagram of a semiconductor memory device according to some embodiments of the present disclosure.

[0030] Reference Figure 1 The semiconductor memory device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0031] The semiconductor memory device 10 may include, for example, NAND flash memory, vertical NAND (VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc., but this disclosure is not limited thereto.

[0032] In the following description, semiconductor memory device 1 is described as, for example, VNAND flash memory; however, this disclosure is not limited thereto. That is, this disclosure can also be applied to other non-volatile memories.

[0033] The memory cell array 20 may include multiple memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include multiple memory cells. The memory cell blocks BLK1 to BLKn may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, one or more serial select lines SSL, and one or more ground select lines GSL.

[0034] Specifically, memory cell blocks BLK1 to BLKn can be connected to the row decoder 33 via word line WL, serial select line SSL, and ground select line GSL. Furthermore, memory cell blocks BLK1 to BLKn can be connected to the page buffer 35 via bit line BL.

[0035] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from outside the semiconductor memory device 10, and can exchange data DATA with external devices (not shown) outside the semiconductor memory device 10. Peripheral circuitry 30 may include control logic 37, a line decoder 33, and a page buffer 35.

[0036] Although not specifically shown, the peripheral circuitry 30 may also include various sub-circuits such as input / output (I / O) circuitry, voltage generating circuitry for generating various voltages required to operate the semiconductor memory device 10, and error correction circuitry for correcting errors in the data DATA read from the memory cell array 20.

[0037] Control logic 37 can be connected to line decoder 33, voltage generation circuit, and I / O circuit. Control logic 37 can control the general operation of semiconductor memory device 10. Control logic 37 can generate various internal control signals for use by semiconductor memory device 10 in response to control signal CTRL.

[0038] For example, control logic 37 can control the level of the voltage supplied to word line WL and bit line BL during memory operations such as programming or erasing operations.

[0039] The row decoder 33 can select at least one of the memory cell blocks BLK1 to BLKn in response to the address ADDR, and can select at least one of the word lines WL, at least one of the serial select lines SSL, and at least one of the ground select lines GSL of the selected memory cell block. The row decoder 33 can send a voltage on the word line WL of the selected memory cell block for performing memory operations.

[0040] Page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can be used as a write driver or a sense amplifier. Specifically, during programming operations, page buffer 35 can be used as a write driver, and a voltage corresponding to the data DATA to be stored in memory cell array 20 can be applied to bit line BL. During read operations, page buffer 35 can be used as a sense amplifier, and the data DATA stored in memory cell array 20 can be sensed.

[0041] Figure 2 This is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure.

[0042] Reference Figure 2 Semiconductor memory devices may include a peripheral logic structure (PS) and a cell array structure (CS).

[0043] The cell array structure CS can be stacked on the peripheral logic structure PS. That is, in a planar diagram, the peripheral logic structure PS and the cell array structure CS can overlap each other. Semiconductor memory devices can have a cell-over-peri (COP) structure.

[0044] For example, the cell array structure CS may include Figure 1 The memory cell array 20. The peripheral logic structure PS may include... Figure 1 30. Peripheral circuit.

[0045] The cell array structure CS may include multiple memory cell blocks BLK1 to BLKn disposed on the peripheral logic structure PS.

[0046] Figure 3 This is a circuit diagram illustrating one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments of the present disclosure.

[0047] Reference Figure 3 According to some embodiments of the present disclosure, a memory cell block may include a common source line CSL, multiple bit lines BL0 to BL2, and multiple cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0048] Cell strings CSTR can be connected in parallel to each bit line BL0 to BL2. Cell strings CSTR can also be connected to a common source line CSL. That is, cell strings CSTR can be positioned between the common source line CSL and the bit lines BL0 to BL2. Multiple common source lines CSL can be arranged in a two-dimensional configuration. The same voltage can be applied to multiple common source lines CSL, or multiple common source lines CSL can be electrically controlled individually.

[0049] For example, each cell string (CSTR) may include series-connected string select transistors (SST1 and SST2), series-connected memory cells (MCTs), and a ground select transistor (GST). Each memory cell (MST) includes a data storage element.

[0050] For example, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series. The second string select transistor SST2 may be connected to one of the bit lines BL0 to BL2, and the ground select transistor GST may be connected to the common source line CSL. The memory cell MCT may be connected in series between the first string select transistor SST1 and the ground select transistor GST.

[0051] Each cell string in the CSTR may also include a dummy cell DMC connected between the first string select transistor SST1 and the memory cell MCT. Although not specifically shown, the dummy cell DMC may also be connected between the ground select transistor GST and the memory cell MCT. The ground select transistor GST may include a plurality of metal-oxide-semiconductor (MOS) transistors connected in series. In another example, each cell string in the CSTR may include only one string select transistor.

[0052] In some embodiments, the first string select transistor SST1 can be controlled via the first string select line SSL1, and the second string select transistor SST2 can be controlled via the second string select line SSL2. The memory cell MCT can be controlled via multiple word lines WL0 to WLn, and the dummy cell DMC can be controlled via the dummy word line DWL. The ground select transistor GST can be controlled via the ground select line GSL. The common source line CSL can be commonly connected to the source of the ground select transistor GST of the cell string CSTR.

[0053] Each cell string in a CSTR may include multiple memory cells MCTs, which are spaced at different distances from the common source line CSL. Multiple word lines (WL0 to WLn and DWL) may be positioned between the common source line CSL and bit lines BL0 to BL2.

[0054] The gate electrodes of memory cells MCTs that are substantially at the same distance from the common source line CSL can be commonly connected to one of the word lines (WL0 to WLn and DWL) and therefore can be in an equipotential state. Even if the gate electrodes of the memory cells MCTs are set at substantially the same level as the common source line CSL, they can be controlled independently if these gate electrodes are arranged in different rows or different columns.

[0055] Ground select lines GSL0 to GSL2 and serial select lines SSL1 and SSL2 may extend in the same direction as the word lines (WL0 to WLn and DWL). Ground select lines GSL0 to GSL2 and serial select lines SSL1 and SSL2 are set at substantially the same level and are electrically isolated.

[0056] Figure 4 This is a layout diagram of a semiconductor memory device according to some embodiments of the present disclosure, and Figure 5A and Figure 5B It is shown Figure 4 Plan view of some of the multiple stacked structures shown. Figure 6 It is shown Figure 4 A plan view of one of the stacked structures shown, and Figure 7 It is along Figure 6 A cross-sectional view taken from line A-A'.

[0057] The semiconductor memory device 10 may include a peripheral logic structure PS and a cell array structure CS.

[0058] The peripheral logic structure PS may include one or more peripheral circuits TR and multiple lower connection wirings 116. The peripheral circuits TR may be formed on the substrate 100. The peripheral circuits TR may be included in... Figure 1 The page buffer 35 may be included in or may be included in Figure 1In line decoder 33. (See later.) Figure 11 Describe the peripheral circuit TR in detail.

[0059] Substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, substrate 100 may be a silicon substrate, or may include another material, such as, for example, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto.

[0060] A peripheral logic insulating film 110 may be formed on the substrate 100. The peripheral logic insulating film 110 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0061] The lower connection wiring 116 may be formed in the peripheral logic insulating film 110. The lower connection wiring 116 may include multiple wirings. The lower connection wiring 116 may include multiple layers, and at least one wiring may be arranged in each layer. The lower connection wiring 116 may be connected to the peripheral circuit TR.

[0062] The cell array structure CS may include multiple horizontal semiconductor layers 150 disposed on the peripheral logic structure PS, and multiple first to fourth stacked structures ST0 to ST3 disposed on each horizontal semiconductor layer 150.

[0063] A horizontal semiconductor layer 150 may be disposed on the peripheral logic structure PS. The horizontal semiconductor layer 150 may extend along the top surface of the peripheral logic structure PS.

[0064] Each horizontal semiconductor layer 150 may include a lower support semiconductor layer (LSB) and a common source plate (CSP) disposed on the LSB. The horizontal semiconductor layer 150 may include at least one of, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The horizontal semiconductor layer 150 may have at least one of a single-crystal structure, an amorphous crystal structure, and a polycrystalline structure.

[0065] Common source plate CSP can be used as Figure 3 The common source line CSL.

[0066] Alternatively, each horizontal semiconductor layer 150 may consist only of a common source plate CSP.

[0067] A common source line extending in direction D2 can be formed in the horizontal semiconductor layer 150 instead of a two-dimensional (2D) planar common source plate.

[0068] A filler insulating film (not shown) may be formed on the peripheral logic structure PS. The filler insulating film may fill the gaps between the horizontal semiconductor layers 150. The filler insulating film may include, for example, silicon oxide, but this disclosure is not limited thereto.

[0069] Multiple first to fourth stacked structures ST0 to ST3 may be disposed on each horizontal semiconductor layer 150. The first to fourth stacked structures ST0 to ST3 may be arranged to be spaced apart from each other in direction D1.

[0070] Figure 4 The illustration shows four stacked structures arranged on each horizontal semiconductor layer 150, but the present disclosure is not limited thereto. In some embodiments, two or more stacked structures may be provided on each horizontal semiconductor layer 150.

[0071] Each of the first to fourth stacked structures ST0 to ST3 may include a memory cell array region (MCR) and a peripheral region (FR). The memory cell array region (MCR) may correspond to... Figure 1 The memory cell array 20, and the peripheral region FR can correspond to the capacitor region in which capacitors used in the peripheral circuit 30 are formed.

[0072] For example, such as Figure 5A As shown, the stacked structure ST0 may include a memory cell array region MCR0 and at least one peripheral region FR0.

[0073] Reference Figure 5A The peripheral region FR0 can extend in direction D2 (or word line direction) and can be set to be a distance D from the memory cell array region MCR0 in direction D1 (or bit line direction).

[0074] Reference Figure 5A The peripheral region FR0 can be formed into a capacitor with a predetermined capacitance, and thus can be electrically connected to the peripheral circuitry for the memory cell array region MCR0.

[0075] In another example, such as Figure 5B As shown, the stacked structure ST0 may include only one memory cell array region MCR0.

[0076] Reference Figure 5B The peripheral region FR1 can extend in direction D2 (or word line direction) and can be configured to be at a predetermined distance from the memory cell array regions MCR0 and MCR1 in direction D1 (or bit line direction).

[0077] Reference Figure 5BThe peripheral region FR1 can form a capacitor with a predetermined capacitance, and is therefore electrically connected to the peripheral circuitry for the memory cell array regions MCR0 and MCR1. That is, the memory cell array regions MCR0 and MCR1 are connected to the capacitor in the peripheral region FR1, and can therefore be used exclusively.

[0078] Reference Figure 5B The peripheral region FR2 can form a capacitor with a predetermined capacitance, and is therefore electrically connected to the peripheral circuitry for the memory cell array regions MCR1 and MCR2. That is, the memory cell array regions MCR1 and MCR2 are connected to the capacitor in the peripheral region FR2, and can therefore be used exclusively.

[0079] Although not specifically shown, multiple peripheral regions FR can be provided for a single memory cell array region MCR. For example, two peripheral regions spaced apart from each other can be provided near the single memory cell array region MCR, namely a first peripheral region "FR A" with a first capacitor and a second peripheral region "FR B" with a second capacitor. In this case, the peripheral circuitry 30 below the memory cell array region MCR can be connected to one of the first peripheral region "FR A" or the second peripheral region "FR B", or connected in series or in parallel with the first peripheral region "FR A" and the second peripheral region "FR B", depending on the required capacitance.

[0080] In the following text, the stacked structure ST1 will be used as an example, referring to... Figure 6 and Figure 7 A three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure is described. The following description of the stacked structure ST1 can be directly applied to the stacked structures ST2, ST3, and ST0.

[0081] Reference Figure 6 and Figure 7 The stacked structure ST1 includes a memory cell array region MCR and a peripheral region FR. The stacked structure ST1 may include multiple electrode pads (EP1 to EP7) stacked in direction D3. The stacked structure ST1 may also include an interlayer insulating film disposed between the electrode pads (EP1 to EP7). The stacked structure ST1 is shown as including seven electrode pads, but this disclosure is not limited thereto.

[0082] Electrode pads (EP1 to EP7) may include gate electrodes contained in the string select transistors (SST1 and SST2) and the ground select transistor GST. Electrode pads (EP1 to EP7) may also include word lines for memory cells MCT.

[0083] For example, the stacked structure ST1 may include a fourth electrode pad EP4 and a fifth electrode pad EP5 that are adjacent to each other in direction D3. The fifth electrode pad EP5 may be disposed on the fourth electrode pad EP4.

[0084] The fourth electrode pad EP4 may protrude beyond the fifth electrode pad EP5 in direction D1. That is, the first sidewalls of the fourth electrode pad EP4 and the fifth electrode pad EP5 facing the stacked structure ST2 may be spaced apart from each other by a predetermined width in direction D1.

[0085] The fourth electrode pad EP4 may protrude beyond the fifth electrode pad EP5 in direction D2. That is, the second sidewalls of the fourth electrode pad EP4 and the fifth electrode pad EP5 may be spaced apart from each other by a predetermined width in direction D2.

[0086] In some embodiments, the protrusion width between the first sidewalls of the fourth electrode pad EP4 and the fifth electrode pad EP5 in direction D1 may be the same as or different from the protrusion width between the second sidewalls of the fourth electrode pad EP4 and the fifth electrode pad EP5 in direction D2.

[0087] The stacked structure ST1 may include a cell region CR and a first cell extension region CER1 extending from the cell region CR in direction D1. The stacked structure ST1 may also include a second cell extension region CER2 extending from the cell region CR in direction D2.

[0088] Multiple electrode isolation regions (WLCs) can be disposed in the stacked structure ST1. The electrode isolation regions (WLCs) can extend in the direction D2.

[0089] The stacked structure ST1 may include multiple electrode isolation trenches EST. The electrode isolation region WLC may fill the electrode isolation trenches EST.

[0090] For example, the electrode isolation region WLC may include an insulating material for filling the electrode isolation trench EST. The electrode isolation region WLC may include, for example, silicon oxide.

[0091] In another example, the electrode isolation region WLC may include a liner formed along the sidewall of the electrode isolation trench EST and a filling film disposed on the liner. The liner may include an insulating material, and the filling film may include a conductive material. Alternatively, the liner may include a conductive material, and the filling film may include an insulating material.

[0092] In yet another example, the electrode isolation region WLC may not include insulating material for filling the electrode isolation trench EST. The electrode isolation region WLC may be filled with conductive material for the electrode isolation trench EST.

[0093] The electrode isolation region WLC may not be located in the first unit extension region CER1. This is for the purpose of forming... Figure 3 The replacement process for word lines WL0 to WLn uses electrode isolation trenches EST, in which electrode isolation regions WLC are formed. Specifically, the electrode isolation trenches EST are used to remove a portion of the molding film, and a portion is formed at the location where the molding film is removed. Figure 3 The character lines WL0 to WLn.

[0094] The molding film may not be completely removed from the first cell extension region CER1 of the memory cell region MCR. As a result, the molding film may remain in the first cell extension region CER1. The first cell extension region CER1 may include a first molding region EP_M1 extending in direction D2. That is, the stack structure ST1 may include the first molding regions EP_M1 disposed on both sides of the cell region CR in direction D1.

[0095] In the memory cell array region MCR, each electrode pad (EP1 to EP7) may include an electrode region EP_E and a first molding region EP_M1. The electrode region EP_E may include, for example, tungsten (W), but this disclosure is not limited thereto.

[0096] For example, each electrode pad (EP1 to EP7) may include an electrode region EP_E and a first molding region EP_M1 disposed on both sides of the electrode region EP_E in direction D1. The electrode region EP_E may be separated by a plurality of electrode isolation regions WLC extending in direction D2. The first molding region EP_M1 may extend from the electrode region EP_E in direction D1.

[0097] Multiple electrode isolation regions WLC may include a first electrode isolation region and a second electrode isolation region spaced apart from each other in direction D1. An electrode region EP_E may be located between the first and second electrode isolation regions. A portion of the electrode region EP_E may be located in a region other than the region between the first and second electrode isolation regions.

[0098] In the memory cell array region (MCR), the width of the first molded region EP_M1 of each electrode pad (EP1 to EP7) in direction D1 can decrease in direction D3 as it moves away from the peripheral logic structure PS. For example, the width of the first molded region EP_M1 of the fourth electrode pad EP4 in direction D1 can be greater than the width of the first molded region EP_M1 of the fifth electrode pad EP5 in direction D1.

[0099] For example, in the memory cell array region MCR, the first molded region EP_M1 of the fourth electrode pad EP4 may protrude beyond the first molded region EP_M1 of the fifth electrode pad EP5 by up to a predetermined width in the direction D1.

[0100] In the memory cell array region MCR, the first molding regions EP_M1 of the fourth electrode pad EP4 and the fifth electrode pad EP5 facing the sidewalls of the stacked structure ST2 can be separated from each other by a predetermined distance in the direction D1.

[0101] In the memory cell array region MCR, the sidewall profile of the stacked structure ST1 may have a stepped structure and may be defined by a first molded region EP_M1 included in each electrode pad (EP1 to EP7).

[0102] The second cell extension region CER2 of the memory cell array region MCR may include a second molding region EP_M2. For example, the second molding region EP_M2 of the fourth electrode pad EP4 may protrude in direction D2 beyond the second molding region EP_M2 of the fifth electrode pad EP5 by up to a predetermined width.

[0103] In the memory cell array region MCR, the sidewall of the second molding region EP_M2 of the fourth electrode pad EP4 can be at a predetermined distance from the sidewall of the second molding region EP_M2 of the fifth electrode pad EP5 in direction D2.

[0104] The first molding region EP_M1 and the second molding region EP_M2 may include, for example, silicon nitride, but this disclosure is not limited thereto.

[0105] In the memory cell array region MCR, multiple vertical structures VS penetrating the stacked structure ST1 can be disposed between each pair of adjacent electrode isolation regions WLC. The vertical structures VS can be connected to the horizontal semiconductor layer 150.

[0106] For example, the vertical structure VS, which serves as the channel region of the memory cell, can be electrically connected to the common source plate CSP of the horizontal semiconductor layer 150.

[0107] The vertical structure VS may include semiconductor materials such as Si, Ge, or mixtures thereof. Alternatively, the vertical structure VS may include semiconductor materials such as metal oxides. Each vertical structure VS may include a barrier insulating film (BIL), a charge storage film (CIL), and a tunnel insulating film (TIL). The barrier insulating film BIL, the charge storage film CIL, and the tunnel insulating film TIL may be separated from each other at the bottom of each vertical structure VS, and a contact support film (CSB) may be disposed between the barrier insulating film BIL, the charge storage film CIL, and the tunnel insulating film TIL. The contact support film CSB electrically connects the common source plate (CSP) of the horizontal semiconductor layer 150 to the vertical structure VS. The contact support film CSB may include semiconductor materials such as Si, Ge, or mixtures thereof.

[0108] Within the peripheral region FR, each electrode pad (EP1 to EP7) may include an electrode region EP_E and a third molding region. The electrode region EP_E may include, for example, W, but this disclosure is not limited thereto.

[0109] The peripheral region FR can be a distance D from the memory cell array region MCR in the direction D1 (or bit line direction).

[0110] In the peripheral region FR, unlike in the memory cell array region MCR, a first cell extension region CER1 and a second cell extension region CER2 may not be formed. For example... Figure 7 As shown, in the peripheral region FR, the sidewall profiles of the electrode pads (EP1 to EP7) may not have a stepped structure in direction D3. For example, the fourth electrode pad EP4 and the fifth electrode pad EP5 may have the same length in direction D2. Therefore, the length of the peripheral region FR in direction D2 (i.e., the width W1 of the peripheral region FR) can be less than the length of the memory cell array region MCR (i.e., CER2+CR+CER2) in direction D2, and the length of the peripheral region FR in direction D1 (i.e., the width W2 of the peripheral region FR) can be less than the length of the memory cell array region MCR (i.e., CER1+CR+CER1) in direction D1. In other words, the length of the peripheral region FR in the word line direction can be less than the length of the memory cell array region MCR in the word line direction.

[0111] The peripheral region FR may include at least two electrode isolation regions WLC. The distance between electrode isolation regions WLC in the peripheral region FR may be greater than the distance between electrode isolation regions WLC without a through structure. For example, the distance between electrode isolation regions WLC in the peripheral region FR may be three times greater than the distance between electrode isolation regions WLC without a through structure THV. The distance between electrode isolation regions WLC without a through structure THV may be the same as the distance between electrode isolation regions WLC with, for example, a vertical structure VS (i.e., S1).

[0112] The peripheral region FR may include multiple through-structures THV between a pair of adjacent electrode isolation regions WLC. The multiple through-structures THV may be spaced apart from each other in direction D2 and may be arranged in at least one row. Alternatively, the multiple through-structures THV may be spaced apart from each other in direction D1 and may be arranged in at least one column. Alternatively, the multiple through-structures THV may be spaced apart from each other in both directions D1 and D2 and may be arranged in at least two rows and at least two columns.

[0113] There are two schemes for forming the through-structure THV: the first scheme forms the through-structure THV before the replacement process, and the second scheme forms the through-structure THV after the replacement process. In the first scheme, a through-trench THV_T is formed between a pair of adjacent electrode isolation regions WLCs. The through-structure THV is formed by depositing oxide in the through-trench THV_T and implanting conductive material into the through-trench THV_T, followed by the replacement process. In the second scheme, a replacement process is performed on a pair of adjacent electrode isolation regions WLCs to form the through-trench THV_T, and the through-structure THV is formed by implanting conductive material into the through-trench THV_T.

[0114] In the second approach, the distance between a pair of adjacent electrode isolation regions WLC can be greater than the distance between the same pair of adjacent electrode isolation regions WLC in the first approach. Because the distance between a pair of adjacent electrode isolation regions WLC is relatively large, there may be molded areas in the middle of these adjacent electrode isolation regions WLC that are not filled with conductive material.

[0115] In the peripheral region FR, a through-structure THV can be formed using a second approach. That is, the electrode isolation region WLC can be used in the replacement process, and the through-structure THV can be formed after the replacement process using the electrode isolation region WLC. The through-structure THV can be configured to penetrate a molding layer between a pair of adjacent electrode isolation regions WLC. The molding layer can be configured to extend in direction D2 between a pair of adjacent electrode isolation regions WLC.

[0116] A first interlayer insulating film 151 may be formed on a horizontal semiconductor layer 150. The first interlayer insulating film 151 may cover the stacked structures ST1 and ST2 in the memory cell array region MCR and the peripheral region FR. The first interlayer insulating film 151 may include, for example, silicon oxide, but this disclosure is not limited thereto.

[0117] The second interlayer insulating film 152 and the third interlayer insulating film 153 may be formed sequentially on the first interlayer insulating film 15. A portion of the electrode isolation region WLC may extend into the second interlayer insulating film 152.

[0118] Bit line B1 and through-channel contact line TH_L may be disposed on stack structure ST1. Bit line BL may extend in direction D1. Bit line BL may be electrically connected in direction D1 to at least one of vertical structures VS.

[0119] The through-channel contact line TH_L may extend in direction D1. At least one of the multiple through-channel contact lines TH_L included in the stacked structure ST0 may be electrically connected to at least one of the multiple through-channel contact lines TH_L included in the stacked structure ST1.

[0120] Bit line BL and through-channel contact line TH_L can be formed on the third interlayer insulating film 153. Bit line BL can be electrically connected to the vertical structure VS via bit line pad BL_PAD and bit line plug BL_PG.

[0121] Although not specifically shown, multiple vias THV_PB can be provided between stacked structures ST0 and ST1. The vias THV_PB can be spaced apart from each other in direction D1.

[0122] The through-hole THV_PB can be electrically connected to the peripheral circuit TR of the peripheral logic structure PS. The through-hole THV_PB can also be connected to the bit line BL via a through-hole connection line.

[0123] The via THV_PB does not penetrate the stack structure ST0 and stack structure ST1. The via THV_PB can penetrate the space between the stack structure ST0 and stack structure ST1, and therefore can be electrically connected to the external circuit TR.

[0124] Figures 8A to 10C It is shown Figure 6 An enlarged view of part Y of the peripheral region FR of a semiconductor memory device.

[0125] Specifically, Figure 8A It shows Figure 6 The peripheral region FR of the semiconductor memory device, and Figure 8B It is along Figure 8A The cross-sectional view taken by line B1-B1'. For convenience, Figure 8A and Figure 8B A through-structure THV arranged in a row between a pair of adjacent electrode isolation regions WLCs and spaced regularly in direction D1 is shown, but this disclosure is not limited thereto. This disclosure is also applicable to through-structure THVs arranged in multiple rows between a pair of adjacent electrode isolation regions WLCs.

[0126] Reference Figure 8A and Figure 8B , Figure 6 The semiconductor memory device may include at least two adjacent electrode isolation regions WLC in the peripheral region FR, and a plurality of through structures THV arranged between the electrode isolation regions WLC and spaced apart from each other in the direction D2.

[0127] The peripheral region FR may include electrode isolation regions WLC and through-structure THV. In each electrode isolation region WLC, a conductive pattern and spacers WLCI surrounding both sides of the conductive pattern may be formed. The electrode isolation regions WLC may extend in directions D2 and D3 and may be spaced apart from each other in direction D1 by up to a width W3. A first side of the conductive pattern of the electrode isolation region WLC may be connected to the electrode isolation region contact line WLCL via electrode isolation region plug WLC_PG and electrode isolation pad WLC_PAD, and a second side of the conductive pattern of the electrode isolation region WLC may be connected to the common electrode plate CSP of the horizontal semiconductor layer 150.

[0128] The through-structure THV can be arranged in at least one row between the electrode isolation regions WLC and spaced regularly in direction D2. The through-structure THV can be configured to be spaced apart from the electrode isolation regions WLC by a width W4 in direction D1. The first side of the through-structure THV can be connected to the through-channel contact line TH_L, and the second side of the through-structure THV can be connected to the wiring 116 in the peripheral logic structure PS.

[0129] If a first voltage is applied via the through-channel contact line TH_L, the electrode pads (EP1 to EP7) can be bonded to the through-structure THV without the through-insulation film THI. For example, the first voltage can be the input power supply voltage VDD or the ground voltage GND.

[0130] Since the electrode isolation region WLC is electrically disconnected from the electrode pads (EP1 to EP7) due to the spacer WLCI, a second voltage can be applied via the electrode isolation region contact line WLCL. For example, the second voltage can be the ground voltage GND or the input power supply voltage VDD.

[0131] In response to a difference between the applied first and second voltages, capacitance can be generated between the conductive pattern of the electrode isolation region WLC and the electrode pads (EP1 to EP7). The capacitance can increase with the number of stacked electrode pads. The capacitance can be connected to the peripheral circuit TR via wiring 116.

[0132] Figure 9A The peripheral region of a semiconductor memory device according to some embodiments of the present disclosure is shown, and Figure 9B It is along Figure 9A The cross-sectional view taken from line B2-B2'.

[0133] Reference Figure 9A and Figure 9B The semiconductor memory device may include at least two adjacent electrode isolation regions WLC in the peripheral region FR, and a plurality of through structures THV disposed between the electrode isolation regions WLC and spaced apart from each other in the direction D2.

[0134] The peripheral region FR may include an electrode isolation region WLC and a through structure THV. A conductive pattern may be formed in the electrode isolation region WLC. The electrode isolation region WLC may extend in directions D2 and D3, and may be spaced apart from each other in direction D1 by up to a width W3. A first side of the conductive pattern of the electrode isolation region WLC may be connected to the electrode isolation region contact line WLCL via the electrode isolation region contact plug WLC_PG and the electrode isolation pad WLC_PAD, and a second side of the conductive pattern of the electrode isolation region WLC may be connected to the common electrode plate CSP of the horizontal semiconductor layer 150.

[0135] A through-channel THV can be arranged in at least one row between electrode isolation regions WLC, and spaced regularly in direction D2. The through-channel THV can be configured to be spaced apart from the electrode isolation regions WLC by a width W4 in direction D1. A first side of the through-channel THV can be connected to the through-channel contact line TH_L, and a second side of the through-channel THV can be connected to wiring 116 in the peripheral logic structure PS. Figure 8A and Figure 8B The through-structure THV is different. Figure 9A and Figure 9B The through-structure THV includes a conductive region and a through-hole insulating film THI surrounding the conductive region.

[0136] In response to applying a first voltage to the through-channel contact line TH_L and applying a second voltage different from the first voltage to the electrode isolation region contact line WLCL, capacitance is generated between the conductive patterns of the electrode insulation region WLC. The capacitance can increase with the number of stacked electrode pads. The capacitance can be connected to the peripheral circuit TR via wiring 116.

[0137] Figure 10A The peripheral region of a semiconductor memory device according to some embodiments of the present disclosure is shown, and Figure 10B and Figure 10C It is along Figure 10A The cross-sectional view taken from line B3-B3'.

[0138] Reference Figure 10A and Figure 10B The semiconductor memory device may include at least two adjacent electrode isolation regions WLC in the peripheral region FR, and a plurality of through structures THV disposed between the electrode isolation regions WLC and spaced apart from each other in directions D1 and D2.

[0139] The through-structure THV may include a first through-structure THV1 and a second through-structure THV2. The first through-structure THV1 may include a conductive region and a through-insulating film THI surrounding the conductive region, and the second through-structure THV2 may include only the conductive region. The first through-structure THV1 and the second through-structure THV2 may be arranged alternately.

[0140] In some embodiments, the first and third rows of the first through structure THV1 and the second and fourth rows of the second through structure THV2 may be configured to be spaced apart from each other in direction D1.

[0141] Although not specifically shown, in some embodiments, the rows of the first through structure THV1 and the rows of the second through structure THV2 may be arranged alternately. For example, the two rows of the first through structure THV1 and the two rows of the second through structure THV2 may be arranged alternately.

[0142] Although not specifically shown, in some embodiments, at least one column of the first through structure THV1 and at least one column of the second through structure THV2 may be arranged alternately.

[0143] The distance between the electrode isolation regions WLC can be greater than Figure 8A or Figure 9A The width is W3.

[0144] The first side of the conductive pattern of the electrode isolation region WLC can be connected to the electrode isolation region contact line WLCL via the electrode isolation region contact plug WLC_PG and the electrode isolation pad WLC_PAD, and the second side of the conductive pattern of the electrode isolation region WLC can be connected to the common electrode plate CSP of the horizontal semiconductor layer 150.

[0145] Reference Figure 10B In some embodiments, the through-structure THV can be arranged in at least one row and at least one column between electrode isolation regions WLC, and spaced regularly in direction D2. The through-structure THV can also be spaced regularly in direction D1 between electrode isolation regions WLC. The first side of the first through-structure THV1 and the first side of the second through-structure THV2 can be connected to the first through-channel contact line TH_L1 and the second through-channel contact line TH_L2, respectively, and the second side of the first through-structure THV1 and the second through-structure THV2 can be connected to the wiring 116 in the peripheral logic structure PS.

[0146] In response to applying a first voltage to the first through-channel contact line TH_L1 and applying a second voltage, different from the first voltage, to the second through-channel contact line TH_L2, the second voltage is applied to the stacked electrode pads (EP1 to EP7) via the second through-channel contact line TH_L2. That is, a capacitance can be generated between the first through-structure THV1 and the electrode pads (EP1 to EP7). The capacitance can be connected to the peripheral circuit TR via wiring 116.

[0147] Reference Figure 10C In some embodiments, the through-structures THV can be arranged in at least one row and at least one column between the electrode isolation regions WLC, and are spaced at regular intervals in direction D2. The through-structures THV can also be spaced at regular intervals in direction D1 between the electrode isolation regions WLC. A first side of the first through-structure THV1 and a first side of the second through-structure THV2 can be connected to the first through-channel contact line TH_L1 and the second through-channel contact line TH_L2, respectively, and a second side of the first through-structure THV1 and the second through-structure THV2 can be connected to the common electrode plate CSP of the horizontal semiconductor layer 150.

[0148] In response to applying a first voltage to the first through-channel contact line TH_L1 and applying a second voltage, different from the first voltage, to the second through-channel contact line TH_L2, the second voltage is applied to the electrode pads (EP1 to EP7) via the second through-channel contact line TH_L2. That is, a capacitance can be generated between the first through-structure THV1 and the electrode pads (EP1 to EP7). Furthermore, an additional capacitance can be generated between the common source plate CSP and the bottommost interlayer insulating film ILD. The capacitance generated between the first through-structure THV1 and the electrode pads (EP1 to EP7) can be connected to the peripheral circuit TR via the common source plate CSP.

[0149] Although not specifically shown, a semiconductor memory device may include multiple electrode isolation regions WLC in a peripheral region FR, and the electrode isolation regions WLC may include a first electrode isolation region WLC1 and a second electrode isolation region WLC2. The first electrode isolation region WLC1 includes a conductive pattern and spacers surrounding the conductive pattern, and the second electrode isolation region WLC2 includes a conductive pattern. The first electrode isolation region WLC1 and the second electrode isolation region WLC2 may be arranged alternately in direction D1.

[0150] In some embodiments, a first side of the first electrode isolation region WLC1 may be connected to the first electrode isolation region contact line WLCL1, a second side of the first electrode isolation region WLC1 may be connected to the common source plate CSP, a first side of the second electrode isolation region WLC2 may be connected to the second electrode isolation region contact line WLCL2, and a second side of the second electrode isolation region WLC2 may be connected to wiring 116. In response to applying a first voltage and a second voltage, which are different from each other, to the first electrode isolation region contact line WLCL1 and the second electrode isolation region contact line WLCL2 respectively, the second voltage is applied to the electrode pads (EP1 to EP7) via the second electrode isolation region WLC2. As a result, a capacitor may be formed between the first electrode isolation region WLC1 and the electrode pads (EP1 to EP7). The capacitor may be used as a capacitor in the peripheral circuit TR via wiring 116.

[0151] In some embodiments, a first side of the first electrode isolation region WLC1 can be connected to the first electrode isolation region contact line WLCL1, a second side of the first electrode isolation region WLC1 can be connected to the common source plate CSP, a first side of the second electrode isolation region WLC2 can be connected to the second electrode isolation region contact line WLCL2, and a second side of the second electrode isolation region WLC2 can be connected to the common source plate CSP. In response to applying a first voltage and a second voltage, which are different from each other, to the first electrode isolation region contact line WLCL1 and the second electrode isolation region contact line WLCL2 respectively, the second voltage is applied to the electrode pads (EP1 to EP7) via the second electrode isolation region WLC2. As a result, a capacitor can be formed between the first electrode isolation region WLC1 and the electrode pads (EP1 to EP7). The capacitor can be used as a capacitor in the peripheral circuit TR via the common source plate CSP.

[0152] Figure 11 yes Figure 1 A block diagram of an exemplary peripheral circuit.

[0153] In some embodiments, the capacitance generated between the electrode patterns of at least some through-structures (or at least some electrode isolation regions) and the stacked structure can be used as... Figure 1 The semiconductor memory device 10 includes capacitors in the peripheral circuitry 30. For example, at least some through-structures (or at least some electrode isolation regions) may be composed of the first electrodes of the capacitors, and the electrode patterns of the stacked structures may be composed of the second electrodes of the capacitors.

[0154] Reference Figure 11The exemplary peripheral circuitry 300 may include column logic 310, internal voltage generator 321, high voltage generator 322, pre-decoder 330, temperature sensor 360, command decoder 340, address decoder 370, mobile area controller 350, scheduler 380, and test / measurement circuitry 390. Figure 11 The configuration of the peripheral circuitry 300 is exemplary, and the peripheral circuitry 300 may additionally include, in addition to Figure 11 Elements other than those shown, or elements that may have the same characteristics as those shown. Figure 11 The configurations shown are different. Refer to the following... Figure 1 and Figure 11 Describe the peripheral circuit 300.

[0155] Column logic 310 generates signals for driving page buffer 35. Pre-decoder 330 generates signals for determining the timing of signals for driving row decoder 33. Internal voltage generator 321 generates voltages for use in the semiconductor memory device 10, such as voltages applied to word line WL and bit line BL, reference voltages, and supply voltages. High voltage generator 322 may include charge pumps, regulators, etc., and generates high voltages for programming or erasing memory cells of memory cell array 20. Temperature sensor 360 detects the temperature of semiconductor memory 10 and outputs a signal corresponding to the detected temperature.

[0156] Command decoder 340 latches and decodes command signals CMD received from outside the semiconductor memory device 10, and can set the operating mode of the semiconductor memory device 10 based on the decoded command signals. Address decoder 370 latches and decodes address signals ADDR received from outside the semiconductor memory device 10, and can activate memory blocks selected according to the decoded address signals. Mobility controller 350 controls the application of various voltages to strings included in the memory cell array 20. Scheduler 380 may include a processor or state machine, and can generate multiple control signals at appropriate timings according to the operating mode set by command decoder 340. Test / measurement circuitry 390 tests or measures the characteristics of semiconductor memory device 10 to provide information about the characteristics of semiconductor memory device 10 during the manufacturing process of semiconductor memory device 10. Test / measurement circuitry 390 operates according to command signals CMD. Systems including semiconductor memory device 10 can use test / measurement circuitry 390 to obtain information about the characteristics of semiconductor memory device 10 early in operation.

[0157] The components of the peripheral circuit 300 can be connected with Figure 1 The line decoder 33 and page buffer 35 are set together in Figure 2 In the peripheral logic structure PS.

[0158] Figure 12 This is a block diagram of a storage device including a 3D semiconductor memory device according to some embodiments of the present disclosure.

[0159] Reference Figure 12 In some embodiments, the storage device may be a solid-state drive (SSD) system 1000.

[0160] SSD system 1000 may include host 1100 and SSD 1200. SSD 1200 may send and receive signal SIG to host 1100 via signal connector and power PWR via power connector.

[0161] SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and multiple memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 may be VNAND flash memory devices and may be configured to... Figures 1 to 11 The embodiments are implemented accordingly. Therefore, memory devices 1230, 1240, and 1250 can have a high degree of integration.

Claims

1. A three-dimensional semiconductor memory device, comprising: The peripheral logic structure is disposed on the substrate and includes multiple peripheral circuits; A horizontal semiconductor layer is disposed on the peripheral logic structure; The memory cell array region located on the horizontal semiconductor layer and the capacitor region separated from the memory cell array region; Multiple stacked structures are located in the capacitor region, wherein a molding layer and electrode pads are alternately stacked on the horizontal semiconductor layer in a first direction. Multiple electrode isolation regions extending in the first and second directions and separating the multiple stacked structures, the electrode isolation regions being connected to the horizontal semiconductor layer; as well as Multiple through-structures are disposed within the peripheral logic structure to penetrate the stacked structure in the first direction, and one side of each of the multiple through-structures is connected to a through-channel contact. In the capacitor region, the electrode pads form a capacitor with at least one electrode isolation region among the plurality of electrode isolation regions or at least one through structure among the plurality of through structures, and The capacitor formed in the capacitor region is electrically connected to at least one of the plurality of peripheral circuits in the memory cell array region.

2. The three-dimensional semiconductor memory device according to claim 1, wherein... Each of the plurality of electrode isolation regions includes a conductive pattern and a separator surrounding the sides of the conductive pattern, and Each of the plurality of through structures includes a conductive region connected to each of the electrode pads in the electrode pads.

3. The three-dimensional semiconductor memory device according to claim 1, wherein... Each of the plurality of electrode isolation regions includes a conductive pattern connected to each of the electrode pads in the electrode pads, and Each of the plurality of through structures includes a conductive region and a through insulating film surrounding the sides of the conductive region.

4. The three-dimensional semiconductor memory device according to claim 1, wherein... The plurality of electrode isolation regions include: A first electrode isolation region and a second electrode isolation region, wherein the first electrode isolation region includes a conductive pattern and spacers surrounding the sides of the conductive pattern and thus isolating it from each of the electrode pads, and the second electrode isolation region includes a conductive pattern and thus connects to each of the electrode pads. Each of the plurality of through structures includes a conductive region and is thus connected to each of the electrode pads.

5. The three-dimensional semiconductor memory device according to claim 1, wherein... The plurality of through structures include: A first through-structure and a second through-structure, wherein the first through-structure includes a conductive region and a through-insulating film surrounding the side of the conductive region, and the second through-structure includes a conductive region and is thus connected to each of the plurality of stacked structures. The first through structure and the second through structure are alternately arranged between at least two electrode isolation regions.

6. The three-dimensional semiconductor memory device according to claim 1, wherein, The other side of each of the plurality of through structures is connected to the horizontal semiconductor layer.

7. The three-dimensional semiconductor memory device according to claim 1, wherein, The other side of each of the plurality of through structures is connected to the wiring in the peripheral logic structure.

8. The three-dimensional semiconductor memory device according to claim 1, wherein... The plurality of through structures include: A third through-structure and a fourth through-structure, wherein the other side of the third through-structure is connected to one of the horizontal semiconductor layers, and the other side of the fourth through-structure is connected to one of the wirings in the peripheral logic structure; and The third through structure and the fourth through structure are arranged alternately.

9. The three-dimensional semiconductor memory device according to claim 1, wherein, The distance between two adjacent electrode isolation regions is greater when a through structure is present than the distance between two adjacent electrode isolation regions when a through structure is absent.

10. The three-dimensional semiconductor memory device according to claim 9, wherein, In the presence of a through structure, the distance between two adjacent electrode isolation regions is three times or more than the distance between two adjacent electrode isolation regions in the absence of a through structure.

11. A three-dimensional semiconductor memory device, comprising: Multiple stacked structures, wherein molding layers and electrode pads are alternately stacked on a horizontal semiconductor layer in a first direction, the multiple stacked structures including a memory cell array region and a capacitor region separate from the memory cell array region; Multiple electrode isolation regions extending in a second direction are spaced apart from each other in a third direction to separate the multiple stacked structures. as well as Multiple through-structures are disposed in the capacitance region between at least two adjacent electrode isolation regions to penetrate the stacked structure in the first direction, and one side of each of the multiple through-structures is connected to a through-channel contact. In the capacitor region, the electrode pads form a capacitor with at least one electrode isolation region among the plurality of electrode isolation regions or at least one through structure among the plurality of through structures.

12. The three-dimensional semiconductor memory device according to claim 11, wherein, The other side of each of the plurality of through structures is connected to the horizontal semiconductor layer or the wiring below the horizontal semiconductor layer.

13. The three-dimensional semiconductor memory device of claim 11, wherein... Each of the plurality of electrode isolation regions includes: A conductive pattern and spacers, wherein the conductive pattern penetrates the stacked structure in the first direction, and the spacers surround the side of the conductive pattern; and Each of the plurality of through structures includes a conductive region connected to each of the electrode pads.

14. The three-dimensional semiconductor memory device of claim 11, wherein... Each of the plurality of electrode isolation regions includes: Conductive patterns that penetrate the stacked structure and connect to each electrode pad in the electrode pads, and Each of the plurality of through structures includes: a conductive region and a through insulating film, wherein the through insulating film surrounds the side of the conductive region and is therefore isolated from each of the electrode pads.

15. The three-dimensional semiconductor memory device of claim 11, wherein... The plurality of electrode isolation regions include: A first electrode isolation region and a second electrode isolation region, wherein the first electrode isolation region includes a conductive pattern and spacers surrounding the sides of the conductive pattern and thus isolating it from each of the electrode pads, and the second electrode isolation region includes a conductive pattern and thus connects to each of the electrode pads. In the capacitor region, the first electrode isolation region and the second electrode isolation region are arranged alternately in the third direction.

16. The three-dimensional semiconductor memory device of claim 11, wherein... The plurality of through structures include: A first through-structure and a second through-structure, wherein the first through-structure includes a conductive region and through insulating films respectively surrounding the sides of the conductive region and thus is isolated from each of the electrode pads, and the second through-structure includes a conductive region and thus connects to each of the plurality of stacked structures, and The first through structure and the second through structure are alternately arranged between the at least two adjacent electrode isolation regions.

17. The three-dimensional semiconductor memory device of claim 11, wherein... Each of the plurality of through structures includes: A first through-structure and a second through-structure, wherein the other side of the first through-structure is connected to one of the horizontal semiconductor layers, and the other side of the second through-structure is connected to one of the wirings in the peripheral logic structure, and The first through structure and the second through structure are arranged alternately.

18. The three-dimensional semiconductor memory device of claim 11, wherein... Each of the plurality of through structures is configured to penetrate the molding layer, the molding layer extending in the second direction between at least two adjacent electrode isolation regions, and The electrode pads are configured to extend in the second direction between each of the plurality of electrode isolation regions and the molding layer.

19. A three-dimensional semiconductor memory device, comprising: A memory cell array region and at least one capacitor region separated from the memory cell array region, wherein a molding layer and electrode pads are alternately arranged on a horizontal semiconductor layer in the capacitor region; Multiple electrode isolation regions extend in the capacitor region in the word line direction and the bit line direction and are spaced apart from each other; A molding region is disposed between two adjacent electrode isolation regions in the plurality of electrode isolation regions; as well as Multiple through structures, each vertically penetrating the molded area, In the capacitor region, the electrode pad forms a capacitor with at least one of the plurality of through structures or with one of the electrode isolation regions.

20. The three-dimensional semiconductor memory device according to claim 19, wherein, In the capacitor region, the electrode pads and the molding layer are stacked on the horizontal semiconductor layer in the word line direction and the bit line direction to have the same length.

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