A GaN heterojunction vertical semiconductor device with shielded gate electrode

Abstract

The present invention provides a GaN heterojunction vertical semiconductor device with a shielded gate electrode, the vertical semiconductor device includes a half-cell structure, the half-cell structure includes a GaN N-type heavily doped layer, a GaN N-type drift region layer, a barrier layer, a drain, a source and a gate, the drain, the GaN N-type heavily doped layer, the GaN N-type drift region layer and the barrier layer are stacked in sequence from bottom to top, and the source is arranged above the barrier layer. A dielectric groove is provided below the source, the dielectric groove penetrates the barrier layer in the vertical direction and extends downward into the GaN N-type drift region layer, the bottom wall of the dielectric groove is located between the upper surface and the lower surface of the GaN N-type drift region layer, and an isolation medium is provided in the dielectric groove. The half-cell structure also includes a shielded gate electrode, the gate and the shielded gate electrode are both located in the dielectric groove and arranged at intervals in the vertical direction, the shielded gate electrode is located below the gate, and the gate and the shielded gate electrode are isolated by an isolation medium. The vertical semiconductor device can reduce the switching loss of the device and improve the withstand voltage capability of the device.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor devices, in particular to a GaN heterojunction vertical semiconductor device with a shielded gate electrode. Background Art

[0002] GaN HEMT devices have the characteristics of low on-resistance, fast switching speed, high breakdown electric field, and high saturation current density, and have attracted widespread attention from researchers. Traditional GaN HEMTs are lateral devices. Due to the existence of interface states, the device current collapses in lateral devices, which increases the on-resistance of the device. In addition, in the off state, the drift region between the gate and the drain bears the withstand voltage of the GaN HEMT device. During the withstand voltage process, the electric field distribution in the drift region is uneven, and usually an electric field spike is generated on the side of the gate close to the drain, causing the device to break down prematurely, thus failing to fully utilize the wide bandgap advantage of the GaN material. At the same time, the withstand voltage of GaN lateral devices is affected by the gate-drain distance (L GD ) limit, L GD The longer the device is, the stronger its withstand voltage is, but the on-state resistance R on will increase. GD The growth will increase the device area, reduce wafer utilization, and increase device cost. Therefore, GaN HEMT devices will lose their advantages when the withstand voltage level is greater than 1200V, while GaN vertical structure devices can be used at higher withstand voltage levels.

[0003] GaN vertical semiconductor devices rely on the vertical drift region to withstand voltage. Vertical semiconductor devices use body electrons as carriers to conduct electricity through body electrons, so the problem of current collapse in lateral devices can be solved from the root. In addition, vertical semiconductor devices transfer the peak of the electric field to the body of the device, thereby avoiding the problem of premature breakdown of the device due to the concentration of the electric field near the gate in lateral devices. Vertical semiconductor devices can control the breakdown voltage of the device by changing the thickness of the drift region and the doping concentration of the drift region. Therefore, the problem of lateral devices using area in exchange for device withstand voltage can be solved, which can greatly reduce production costs.

[0004] The parasitic capacitance (C gd ) is larger, C gd A larger value will prolong the device turn-off time and lead to higher device switching loss. In addition, existing GaN vertical semiconductor devices mainly rely on the vertical drift region to withstand voltage. The doping concentration of the drift region will affect the device on-resistance and breakdown voltage. When the doping concentration of the drift region is high, R on will decrease, but the voltage withstand capability of the device will decrease. When the doping concentration of the drift region is low, the voltage withstand capability of the device will increase, but R on Will increase. Summary of the invention

[0005] The object of the present invention is to provide a GaN heterojunction vertical semiconductor device with a shielded gate electrode, which can reduce the switching loss of the device and improve the voltage resistance of the device.

[0006] To achieve the above-mentioned object, the present invention provides a GaN heterojunction vertical semiconductor device with a shielded gate electrode, comprising a half-cell structure, the half-cell structure comprising a GaN N-type heavily doped layer, a GaN N-type drift region layer, a barrier layer, a drain, a source and a gate, the drain, the GaN N-type heavily doped layer, the GaN N-type drift region layer and the barrier layer are stacked in sequence from bottom to top, and the source is arranged above the barrier layer. A dielectric groove is arranged below the source, the dielectric groove penetrates the barrier layer in the vertical direction and extends downward into the GaN N-type drift region layer, the bottom wall of the dielectric groove is located between the upper surface and the lower surface of the GaN N-type drift region layer, and an isolation medium is arranged in the dielectric groove. The half-cell structure also includes a shielded gate electrode, the gate and the shielded gate electrode are both located in the dielectric groove and arranged at intervals in the vertical direction, the shielded gate electrode is located below the gate, and the gate and the shielded gate electrode are isolated by an isolation medium.

[0007] As can be seen from the above scheme, the GaN heterojunction vertical semiconductor device introduces a shielded gate electrode under the gate, and the gate and the shielded gate electrode are separated by an isolation dielectric. The introduction of the shielded gate electrode reduces the existing parasitic capacitance C from the gate to the drain. gd becomes the parasitic capacitance C from the gate to the shield gate electrode gs The parasitic capacitance C from the shield gate electrode to the drain sd In the form of series connection, the parasitic capacitance C from the gate to the drain after series connection gd It will reduce, thus reducing the switching loss of the device. At the same time, the shielded gate electrode can also play the role of a field plate, regulating the electric field in the gate area and the drift area, and improving the voltage resistance of the device.

[0008] A preferred solution is that a floating P-GaN region is provided below the dielectric groove in the GaN N-type drift region layer, and the floating P-GaN region extends laterally from a side of the GaN N-type drift region layer close to the dielectric groove to the middle of the GaN N-type drift region layer.

[0009] A further solution is that the number of the floating P-GaN regions is more than two, and the multiple floating P-GaN regions are arranged in parallel along the longitudinal direction.

[0010] It can be seen that by introducing one or more floating P-GaN regions in the GaN N-type drift region layer, the longitudinal depth of the dielectric groove can be shortened, thereby increasing the distance from the shielded gate electrode to the drain, thereby further reducing C gd At the same time, the introduction of a floating P-GaN region can assist in depleting the drift region, optimizing the electric field distribution in the drift region, and further improving the device's withstand voltage capability.

[0011] A preferred solution is that the dielectric groove includes a groove side wall and a groove bottom wall arranged vertically, and the gate and the shielding gate electrode extend from the side wall of the half-cell structure toward the groove side wall in the horizontal direction. An isolation dielectric is arranged between the bottom wall of the gate and the top wall of the shielding gate electrode, between the bottom wall of the shielding gate electrode and the groove bottom wall of the dielectric groove, between the side wall of the gate and the groove side wall of the dielectric groove, and between the side wall of the shielding gate electrode and the groove side wall of the dielectric groove. The thickness of the isolation dielectric between the bottom wall of the gate and the top wall of the shielding gate electrode is d1, the thickness of the isolation dielectric between the bottom wall of the shielding gate electrode and the bottom wall of the dielectric groove is d2, the thickness of the isolation dielectric between the side wall of the gate and the side wall of the dielectric groove is d3, and the thickness of the isolation dielectric between the side wall of the shielding gate electrode and the side wall of the dielectric groove is d4; d2 and d4 are both greater than d1, and d2 and d4 are both greater than d3.

[0012] It can be seen from the above that the shielding gate electrode is wrapped by a thicker isolation medium, which can fully play the role of charge balance.

[0013] A preferred solution is that the shielding gate electrode is electrically connected to the source.

[0014] A preferred solution is that the GaN N-type drift region layer and the barrier layer form a heterojunction, and the heterojunction forms a two-dimensional electron gas channel near the interface of the GaN N-type drift region layer.

[0015] A preferred solution is that the material of the barrier layer is AlGaN, AlN, InN or InGaN.

[0016] A preferred solution is that the half-cell structure further includes a cap layer, which is formed above the barrier layer, and the material of the cap layer is GaN, AlN, AlGaN, InN or InGaN.

[0017] A further solution is that the half-cell structure further includes a passivation layer, the passivation layer is formed above the cap layer, and the material of the passivation layer is SiN, Al2O3, SiO2 or HfO2.

[0018] A preferred solution is that the drain electrode is in ohmic contact with the GaN N-type heavily doped layer, and the source electrode is in ohmic contact with the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a half-cell structure of a first embodiment of a GaN heterojunction vertical semiconductor device with a shielded gate electrode according to the present invention.

[0020] Figure 2 It is a schematic diagram of a half-cell structure of a second embodiment of a GaN heterojunction vertical semiconductor device with a shielded gate electrode according to the present invention.

[0021] Figure 3It is a schematic diagram of a half-cell structure of a third embodiment of a GaN heterojunction vertical semiconductor device with a shielded gate electrode according to the present invention.

[0022] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0023] A first embodiment of a GaN heterojunction vertical semiconductor device with a shielded gate electrode:

[0024] See also Figure 1 The GaN heterojunction vertical semiconductor device of this embodiment includes a plurality of half-cell structures, and the half-cell structure includes a GaN N-type heavily doped layer 11, a GaN N-type drift region layer 12, a barrier layer 13, a drain 14, a source 15, a gate 16, and a shielding gate electrode 19. Among them, the drain 14, the GaN N-type heavily doped layer 11, the GaN N-type drift region layer 12, and the barrier layer 13 are stacked in sequence from bottom to top, and the source 15 is arranged above the barrier layer 13. The material of the barrier layer 13 is a material that can form a polarization heterojunction with GaN, such as AlGaN, AlN, InN or InGaN. The drain 14 is in ohmic contact with the GaN N-type heavily doped layer 11, and the source 15 is in ohmic contact with the barrier layer 13. The GaN N-type drift region layer 12 and the barrier layer 13 form a heterojunction, and the heterojunction forms a two-dimensional electron gas channel 17 near the interface of the GaN N-type drift region layer 12. When the gate 16 voltage is connected to 0V, the two-dimensional electron gas channel 17 at the AlGaN / GaN heterojunction and the conductive channel of the AlGaN barrier layer 13 near the gate 16 side are depleted, and the device is turned off. When the gate 16 voltage is greater than the threshold voltage, the two-dimensional electron gas channel 17 near the gate 16 side is restored, and the AlGaN barrier layer 13 near the gate 16 side is inverted to form a conductive channel, and the device is turned on. The high-concentration two-dimensional electron gas polarized by the polarization effect of the AlGaN / GaN heterojunction introduces a lateral conductive channel, which can effectively improve the longitudinal current uniformity, thereby increasing the device on-current density and reducing the device on-resistance.

[0025] A dielectric groove 18 is provided below the source electrode 15, and the dielectric groove 18 penetrates the barrier layer 13 in the vertical direction and extends downward into the GaN N-type drift region layer 12, and a groove bottom wall 182 of the dielectric groove 18 is located between the upper surface 121 and the lower surface 122 of the GaN N-type drift region layer 12, and an isolation dielectric 181 is provided in the dielectric groove 18. The material of the isolation dielectric 181 is SiN, Al2O3, SiO2 or HfO2, etc.

[0026] The gate 16 and the shielding gate electrode 19 are both located in the dielectric groove 18 and spaced apart in the longitudinal direction. The shielding gate electrode 19 is located below the gate 16. The top wall of the gate 16 is coplanar with the top wall of the barrier layer 13. The gate 16 and the source 15 are staggered in the longitudinal direction.

[0027] The dielectric groove 18 includes a groove side wall 183 and a groove bottom wall 182 which are vertically arranged. The gate 16 and the shielding gate electrode 19 extend horizontally from the side wall of the half cell structure toward the groove side wall 183. The gate 16 and the shielding gate electrode 19 are isolated by an isolation dielectric 181, that is, the isolation dielectric 181 is arranged between the bottom wall 162 of the gate 16 and the top wall 193 of the shielding gate electrode 19, between the bottom wall 192 of the shielding gate electrode 19 and the groove bottom wall 182 of the dielectric groove 18, between the side wall 161 of the gate 16 and the groove side wall 183 of the dielectric groove 18, and between the side wall 191 of the shielding gate electrode 19 and the groove side wall 183 of the dielectric groove 18. The shielding gate electrode 19 is electrically connected to the source 15.

[0028] The thickness of the isolation dielectric between the bottom wall 162 of the gate 16 and the top wall 193 of the shielding gate electrode 19 is d1, the thickness of the isolation dielectric between the bottom wall 192 of the shielding gate electrode 19 and the bottom wall of the dielectric groove 18 is d2, the thickness of the isolation dielectric between the side wall 161 of the gate 16 and the groove side wall 183 of the dielectric groove 18 is d3, and the thickness of the isolation dielectric between the side wall 191 of the shielding gate electrode 19 and the groove side wall 183 of the dielectric groove 18 is d4. Both d2 and d4 are greater than d1, and both d2 and d4 are greater than d3.

[0029] The dielectric groove 18 structure introduced under the gate extends to the inside of the GaN N-type drift region layer 12 without penetrating the GaN N-type drift region layer 12, thereby increasing the distance from the shielding gate electrode 19 to the drain 14 and reducing the parasitic capacitance C sd , further reducing the parasitic capacitance C gd , reducing device energy loss.

[0030] As can be seen from the above, the GaN heterojunction vertical semiconductor device introduces a shielded gate electrode under the gate, and the gate and the shielded gate electrode are separated by an isolation dielectric. The introduction of the shielded gate electrode reduces the existing parasitic capacitance C from the gate to the drain. gd becomes the parasitic capacitance C from the gate to the shield gate electrode gs The parasitic capacitance C from the shield gate electrode to the drain sd In the form of series connection, the parasitic capacitance C from the gate to the drain after series connection gd It will reduce, thus reducing the switching loss of the device. At the same time, the shielded gate electrode can also play the role of a field plate, regulating the electric field in the gate area and the drift area, and improving the voltage resistance of the device.

[0031] Second embodiment of a GaN heterojunction vertical semiconductor device with a shielded gate electrode:

[0032] As an explanation of the second embodiment of the GaN heterojunction vertical semiconductor device with a shielded gate electrode of the present invention, only the differences from the above-mentioned first embodiment of the GaN heterojunction vertical semiconductor device with a shielded gate electrode are explained below.

[0033] See also Figure 2 In this embodiment, a floating P-GaN region 20 is provided below the dielectric groove 28 in the GaN N-type drift region layer 22. The floating P-GaN region 20 extends laterally from the side of the GaN N-type drift region layer 22 close to the dielectric groove 28 to the middle of the GaN N-type drift region layer 22. By introducing the floating P-GaN region 20 into the GaN N-type drift region layer 22, the longitudinal depth of the dielectric groove 28 can be shortened, thereby increasing the distance from the shield gate electrode 29 to the drain 24, thereby further reducing the C gd At the same time, the introduction of the floating P-GaN region 20 can assist in depleting the drift region, optimize the electric field distribution in the drift region, and further enhance the voltage resistance of the device.

[0034] A third embodiment of a GaN heterojunction vertical semiconductor device with a shielded gate electrode:

[0035] As an explanation of the third embodiment of the GaN heterojunction vertical semiconductor device with a shielded gate electrode of the present invention, only the differences from the above-mentioned second embodiment of the GaN heterojunction vertical semiconductor device with a shielded gate electrode are explained below.

[0036] See also Figure 3 In this embodiment, the half-cell structure also includes a cap layer 31 and a passivation layer 32. The cap layer 31 is formed above the barrier layer 33, and the passivation layer 32 is formed above the cap layer 31. The material of the cap layer is GaN, AlN, AlGaN, InN or InGaN, and the material of the passivation layer is SiN, Al2O3, SiO2 or HfO2.

[0037] In addition, the number of floating P-GaN regions can be more than two, and multiple floating P-GaN regions are arranged in parallel along the longitudinal direction. The length, thickness, doping concentration of the floating P-GaN region and the thickness of the isolation medium with the P-type doped barrier layer will affect the electric field distribution in the device body and the degree of reduction of off-state leakage, and the above parameters can be changed as needed. The above changes can also achieve the purpose of the present invention.

[0038] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A GaN heterojunction vertical semiconductor device with a shielded gate electrode, comprising a half-cell structure, characterized in that: The half-cell structure includes a GaN N-type heavily doped layer, a GaN N-type drift region layer, a barrier layer, a drain, a source and a gate, wherein the drain, the GaN N-type heavily doped layer, the GaN N-type drift region layer and the barrier layer are stacked in sequence from bottom to top, and the source is arranged above the barrier layer; A dielectric groove is provided below the source electrode, the dielectric groove penetrates the barrier layer in the vertical direction and extends downward into the GaN N-type drift region layer, the bottom wall of the dielectric groove is located between the upper surface and the lower surface of the GaN N-type drift region layer, and an isolation medium is provided in the dielectric groove; The half-cell structure further includes a shielding gate electrode, the gate and the shielding gate electrode are both located in the dielectric groove and spaced apart in the longitudinal direction, the shielding gate electrode is located below the gate, and the gate and the shielding gate electrode are isolated by the isolation medium; The dielectric trench comprises a trench sidewall and a trench bottom wall arranged vertically, and the gate electrode and the shielding gate electrode both extend from the sidewall of the half cell structure toward the trench sidewall in a horizontal direction; The isolation medium is disposed between the bottom wall of the gate and the top wall of the shielding gate electrode, between the bottom wall of the shielding gate electrode and the bottom wall of the dielectric groove, between the side wall of the gate and the side wall of the dielectric groove, and between the side wall of the shielding gate electrode and the side wall of the dielectric groove; The thickness of the isolation dielectric between the bottom wall of the gate and the top wall of the shielding gate electrode is d1, the thickness of the isolation dielectric between the bottom wall of the shielding gate electrode and the bottom wall of the dielectric groove is d2, the thickness of the isolation dielectric between the side wall of the gate and the side wall of the dielectric groove is d3, and the thickness of the isolation dielectric between the side wall of the shielding gate electrode and the side wall of the dielectric groove is d4; d2 and d4 are both greater than d1, and d2 and d4 are both greater than d3; A floating P-GaN region is provided in the GaN N-type drift region layer below the dielectric groove, and the floating P-GaN region extends laterally from a side of the GaN N-type drift region layer close to the dielectric groove to a middle part of the GaN N-type drift region layer; The floating P-GaN region is not in contact with the dielectric trench.

2. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to claim 1, characterized in that: The number of the floating P-GaN regions is more than two, and the plurality of floating P-GaN regions are arranged in parallel along a longitudinal direction.

3. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to claim 1, characterized in that: The shield gate electrode is electrically connected to the source.

4. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to any one of claims 1 to 3, characterized in that: The GaN N-type drift region layer and the barrier layer form a heterojunction, and the heterojunction forms a two-dimensional electron gas channel near the interface of the GaN N-type drift region layer.

5. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to any one of claims 1 to 3, characterized in that: The barrier layer is made of AlGaN, AlN, InN or InGaN.

6. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to any one of claims 1 to 3, characterized in that: The half-cell structure further includes a cap layer, which is formed above the barrier layer. The material of the cap layer is GaN, AlN, AlGaN, InN or InGaN.

7. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to claim 6, characterized in that: The half-cell structure further includes a passivation layer, which is formed above the cap layer. The material of the passivation layer is SiN, Al2O3, SiO2 or HfO2.

8. The GaN heterojunction vertical semiconductor device with a shielded gate electrode according to any one of claims 1 to 3, characterized in that: The drain electrode is in ohmic contact with the GaN N-type heavily doped layer, and the source electrode is in ohmic contact with the barrier layer.

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