Driving circuit, integrated device, battery management chip and battery management system

Abstract

The present disclosure provides a driving circuit for providing control signals for a charge control transistor and a discharge control transistor for controlling charging and discharging of a battery pack, comprising: a first driving unit for providing a voltage control signal for the discharge control transistor so as to control on and off of the discharge control transistor by the voltage control signal; and a second driving unit for providing a current control signal for the charge control transistor so as to control on and off of the discharge control transistor by the current control signal, wherein a first resistor is connected between a gate and a source of the charge control transistor, and on and off of the charge control transistor is controlled by a voltage generated by the current control signal and the first resistor. The present disclosure also provides an integrated device, a battery management chip and a battery management system.

Description

TECHNICAL FIELD

[0001] The present disclosure provides a driving circuit, an integrated device, a battery management chip and a battery management system. BACKGROUND

[0002] In a battery management system (BMS), the charging and discharging of a battery pack are usually controlled by a charging switch and a discharging switch. The charging switch and the discharging switch are driven by their driving circuits.

[0003] The charging switch and the discharging switch are usually composed of MOS transistors. When controlling the MOS transistors, it is necessary to ensure that the MOS transistors are not damaged. For an integrated driving circuit or a battery management system, it is necessary to ensure the system efficiency while reducing power consumption. SUMMARY

[0004] To solve one of the above technical problems, the present disclosure provides a driving circuit, an integrated device, a battery management chip and a battery management system.

[0005] According to one aspect of the present disclosure, a driving circuit for providing control signals for a charging control transistor and a discharging control transistor for controlling the charging and discharging of a battery pack, comprising:

[0006] a first driving unit for providing a voltage control signal for the discharging control transistor, so as to control the on and off of the discharging control transistor through the voltage control signal; and

[0007] a second driving unit for providing a current control signal for the charging control transistor, so as to control the on and off of the discharging control transistor through the current control signal, wherein a first resistor is connected between the gate and the source of the charging control transistor, and the on and off of the charging control transistor is controlled by the voltage generated by the current control signal and the first resistor.

[0008] According to the driving circuit of at least one embodiment of the present disclosure, the charging control transistor and the discharging control transistor are NMOS transistors or PMOS transistors.

[0009] According to the driving circuit of at least one embodiment of the present disclosure, the source of the charging control transistor is connected to a charger / load terminal, the gate of the charging control transistor receives the current control signal, the drain of the charging control transistor is connected to the drain of the discharging control transistor, the gate of the discharging control transistor receives the voltage control signal, and the source of the discharging control transistor is connected to a battery pack terminal.

[0010] According to at least one embodiment of the present disclosure, a driving circuit is formed by a voltage conversion unit that steps down a maximum voltage of the battery pack to a first voltage, and the first voltage is boosted to a driving voltage of the driving circuit.

[0011] According to at least one embodiment of the present disclosure, the first voltage is boosted to the driving voltage by a charge pump or a boost circuit.

[0012] According to at least one embodiment of the present disclosure, a first driving unit is formed by a source of a first PMOS transistor connected to a driving voltage of the driving circuit and a source of a second PMOS transistor connected to the driving voltage, a gate of the first PMOS transistor connected to a gate of the second PMOS transistor, a drain of the first PMOS transistor connected to the gate, a drain of the first PMOS transistor connected to a source of a third transistor, a drain of the second PMOS transistor connected to a source of a fourth PMOS transistor, a gate of the third PMOS transistor connected to a gate of the fourth PMOS transistor, a drain of the third PMOS transistor connected to the gate, a drain of the third PMOS transistor connected to a first terminal of a second resistor, a drain of the fourth PMOS transistor connected to a cathode of a first Zener diode, a second terminal of the second resistor connected to a drain of a first NMOS transistor, a source of the first NMOS transistor connected to a reference ground, a gate of the first NMOS transistor connected to an enable signal, the first NMOS transistor controlled to be turned on or off by the enable signal, an anode of the first Zener diode connected to a cathode of a second Zener diode, and an anode of the second Zener diode connected to the reference ground, a gate of a second NMOS transistor connected to the drain of the fourth PMOS transistor through a third resistor, a drain of the second NMOS transistor connected to the driving voltage, and a source of the second NMOS transistor connected to a first terminal of a fourth resistor, the gate and the source of the second NMOS transistor connected through a third Zener diode, wherein an anode of the third Zener diode is connected to the source of the second NMOS transistor, a cathode of the third Zener diode is connected to the gate of the second NMOS transistor, a drain of a third NMOS transistor is connected to the drain of the fourth PMOS transistor, a source of the third NMOS transistor is connected to the reference ground, and a gate of the third NMOS transistor is connected to the enable signal via an inverter 136, an output terminal of the inverter is also connected to a gate of a fourth NMOS transistor, a source of the fourth NMOS transistor is connected to the reference ground, a drain of the fourth NMOS transistor is connected to a second terminal of a fifth resistor, a first terminal of the fifth resistor is connected to a second terminal of the fourth resistor, and a connection point of the fourth resistor and the fifth resistor is an output terminal of a voltage control signal.

[0013] According to the driving circuit of at least one embodiment of the present disclosure, the second driving unit is: a source of the fifth PMOS transistor is connected to a driving voltage, a source of the sixth PMOS transistor is connected to the driving voltage, a gate of the fifth PMOS transistor is connected to a gate of the sixth PMOS transistor, the gate of the fifth PMOS transistor is connected to a drain of the fifth PMOS transistor, the drain of the fifth PMOS transistor is connected to a source of the seventh PMOS transistor, a drain of the sixth PMOS transistor is connected to a source of the eighth PMOS transistor, a gate of the seventh PMOS transistor is connected to a gate of the eighth PMOS transistor, a drain of the seventh PMOS transistor is connected to the gate of the seventh PMOS transistor, the drain of the seventh PMOS transistor is connected to a first end of the sixth resistor, a drain of the fourth PMOS transistor 114 is connected to a first end of the seventh resistor, a drain of the fifth NMOS transistor is connected to a second end of the sixth resistor, a source of the fifth NMOS transistor is connected to a reference ground, a gate of the fifth NMOS transistor is connected to an enable signal, and a second end of the seventh resistor provides the current control signal.

[0014] According to the driving circuit of at least one embodiment of the present disclosure, the current control signal is provided through a drain of the fourth PMOS transistor.

[0015] According to one aspect of the present disclosure, an integrated device integrates the driving circuit as recited in any of the above.

[0016] According to one aspect of the present disclosure, a battery management chip comprises:

[0017] the driving circuit as recited in any of the above;

[0018] a voltage conversion unit that converts a highest voltage of the battery pack into a driving voltage of the driving circuit.

[0019] According to the battery management chip of at least one embodiment of the present disclosure, the voltage conversion unit converts the highest voltage of the battery pack into a first voltage through voltage reduction, and the first voltage is converted into the driving voltage through voltage increase.

[0020] According to the battery management chip of at least one embodiment of the present disclosure, further comprising: a control logic unit that generates a control signal provided to the driving circuit according to a current detection signal, a temperature detection signal, and / or a battery voltage detection signal, and the driving circuit provides the current control signal and the voltage control signal according to the control signal.

[0021] According to the battery management chip of at least one embodiment of the present disclosure, further comprising a voltage collection unit that is capable of collecting a voltage of each battery in the battery pack, and providing the collected voltage to the control logic unit as the battery voltage detection signal.

[0022] According to an aspect of the present disclosure, a battery management system includes:

[0023] a drive circuit as recited in any of the above; and

[0024] a charge control transistor and a discharge control transistor, the drive circuit providing a current control signal to the charge control transistor and a voltage control signal to the discharge control transistor to control turn-on and turn-off of the charge control transistor and the discharge control transistor. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0026] Figure 1 A schematic diagram of charge and discharge switch control according to an embodiment of the present disclosure is shown.

[0027] Figure 2 A schematic diagram of charge and discharge switch control according to an embodiment of the present disclosure is shown.

[0028] Figure 3 A schematic diagram of discharge switch control circuit according to an embodiment of the present disclosure is shown.

[0029] Figure 4 A schematic diagram of charge switch control circuit according to an embodiment of the present disclosure is shown.

[0030] Figure 5 A schematic diagram of voltage conversion according to an embodiment of the present disclosure is shown.

[0031] Figure 6 A schematic diagram of voltage conversion according to an embodiment of the present disclosure is shown.

[0032] Figure 7 A schematic diagram of voltage conversion according to an embodiment of the present disclosure is shown.

[0033] Figure 8 A schematic diagram of voltage conversion according to an embodiment of the present disclosure is shown.

[0034] Figure 9 A schematic diagram of voltage conversion according to an embodiment of the present disclosure is shown.

[0035] Figure 10 A schematic diagram of voltage conversion according to an embodiment of the present disclosure is shown.

[0036] Figure 11A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown. Detailed Implementation

[0037] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0038] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0040] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0041] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0042] For descriptive purposes, the disclosure can use spatially relative terms, such as "below," "lower," "under," "downward," "down," "upper" "above," "upward," "over," "higher," and "side" (e.g., as in "sidewall") to describe the relative relationship in

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular articles "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "includes," "including," and / or "has," "having," and / or their derivatives, when used in this description, mean "comprises," "comprising," and / or "includes," "including," but do not exclude the presence of one or more additional features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "approximately," and other similar

[0044] A battery management (BMS) chip 10 is provided according to one embodiment of the present disclosure. As shown in FIG. 1, the chip 10 can be in the form of an integrated device. A driving circuit can be included in the battery management chip, and the driving circuit can provide control signals for discharge control transistors 20 and charge control transistors 30 so as to control the on and off of the discharge control transistors 20 and the charge control transistors 30, thereby performing charge and discharge control of a battery pack. Figure 1

[0045] In addition, as shown in FIG. 2, only the driving circuit device 100 can be in the form of an integrated device. Figure 2

[0046] As shown in FIG. 3, the driving circuit device 100 can be in the form of an integrated device. Figure 1 and Figure 2 ​​As shown, the series circuit of the discharge control transistor 20 and the charge control transistor 30 is connected between one end of the battery and one end of the load / charger. The discharge control transistor 20 and the charge control transistor 30 can be NMOS transistors or PMOS transistors, and the series circuit can be connected between the positive terminal of the battery and the positive terminal of the load / charger, or between the negative terminal of the battery and the load / charger.

[0047] In this disclosure, an NMOS transistor and a charging control transistor connected between a battery and the negative terminal of a load / charger will be used as examples to illustrate the charging control transistor and the discharging control transistor.

[0048] The source of the discharge control transistor 20 is connected to the battery terminal, the drain of the discharge control transistor 20 is connected to the drain of the charge control transistor 30, and the source of the charge control transistor 30 is connected to the load / charger terminal.

[0049] The battery management chip 10 or the drive circuit device 100 can provide a control signal to the gate of the discharge control transistor 20 through the DSG pin to control its conduction or disconnection, and can provide a control signal to the gate of the charge control transistor through the CHG pin to control its conduction or disconnection.

[0050] In this disclosure, the control signal provided to the discharge control transistor 20 is a voltage control signal, which controls the transistor to turn on or off. The control signal provided to the charge control transistor 30 is a current control signal, and a first resistor 40 is connected between the source and gate of the charge control transistor 30. The voltage signal generated by the current control signal in the first resistor 40 is used as the gate-source voltage of the charge control transistor 30, thereby controlling the charge control transistor 30 to turn on or off.

[0051] Figure 3 The driving circuit for the discharge control transistor is disclosed. For example... Figure 1 As shown, the driving circuit can receive the driving voltage Vdrv and the enable signal EN to generate the voltage control signal (DSG pin) of the discharge control transistor.

[0052] like Figure 3 As shown, the source of the first PMOS transistor 111 is connected to the driving voltage Vdrv, and the source of the second PMOS transistor 112 is also connected to the driving voltage Vdrv. The gate of the first PMOS transistor 111 is connected to the gate of the second PMOS transistor 112, and the drain of the first PMOS transistor 111 is connected to the gate. The drain of the first PMOS transistor 111 can be connected to the first terminal of the second resistor 121, and the drain of the second PMOS transistor 112 can be connected to the cathode of the first Zener diode 122. Alternatively, as shown... Figure 3As shown, the drain of the first PMOS transistor 111 is connected to the source of the third PMOS transistor 113, the drain of the second PMOS transistor 112 is connected to the source of the fourth PMOS transistor 114, the gate of the third PMOS transistor 113 is connected to the gate of the fourth PMOS transistor 114, the drain and the gate of the third PMOS transistor 113 are connected, and the drain of the third PMOS transistor 113 is connected to the first end of the second resistor 121, and the drain of the fourth PMOS transistor 114 is connected to the cathode of the first Zener diode 122.

[0053] The second end of the second resistor 121 is connected to the drain of the first NMOS transistor 123, the source of the first NMOS transistor 123 is connected to the reference ground. The gate of the first NMOS transistor 123 is connected to the enable signal EN, and the conduction or disconnection of the first NMOS transistor 123 is controlled by the enable signal EN.

[0054] The anode of the first Zener diode 122 can be connected to the cathode of the second Zener diode 124, and the anode of the second Zener diode 124 can be connected to the reference ground.

[0055] In addition, the gate of the second NMOS transistor 131 can be connected to the drain of the fourth PMOS transistor 114, and the drain of the fourth PMOS transistor 114 can also be connected through the third resistor 132. When the fourth PMOS transistor does not exist, it can be connected to the drain of the second PMOS transistor.

[0056] The drain of the second NMOS transistor 131 can be connected to the driving voltage Vdrv, and the source of the second NMOS transistor 131 can be connected to the first end of the fourth resistor 133, and the gate and the source of the second NMOS transistor 131 are connected through the third Zener diode 134, wherein the anode of the third Zener diode 134 is connected to the source of the second NMOS transistor 131, and the cathode of the third Zener diode 134 is connected to the gate of the second NMOS transistor 131.

[0057] The drain of the third NMOS transistor 135 can be connected to the drain of the fourth PMOS transistor 114. When the fourth PMOS transistor does not exist, it can be connected to the drain of the second PMOS transistor. The source of the third NMOS transistor 135 can be connected to the reference ground, and the gate of the third NMOS transistor 135 can be connected to the enable signal EN through the inverter 136. In this way, the conduction or disconnection of the third NMOS transistor 135 is controlled by the inverse signal of the enable signal EN.

[0058] In addition, the output end of the inverter 136 is also connected to the gate of the fourth NMOS transistor 137, and the conduction or disconnection of the fourth NMOS transistor 137 is controlled by the inverse signal of the enable signal EN.

[0059] The source of the fourth NMOS transistor 137 is connected to the reference ground, the drain of the fourth NMOS transistor 137 is connected to the second end of the fifth resistor 138, and the first end of the fifth resistor 138 is connected to the second end of the fourth resistor 133. The connection point of the fourth resistor 133 and the fifth resistor 138 can be used as the output end of the voltage control signal (DSG pin).

[0060] Figure 4 The driving circuit of the charging control transistor is shown. In the driving circuit, the source of the fifth PMOS transistor 141 is connected to the driving voltage Vdrv, and the source of the sixth PMOS transistor 142 is connected to the driving voltage Vdrv. The gate of the fifth PMOS transistor 141 is connected to the gate of the sixth PMOS transistor 142, and the gate of the fifth PMOS transistor 141 is connected to the drain of the fifth PMOS transistor 141. The drain of the fifth PMOS transistor 141 can be connected to the first end of the sixth resistor 145, and the drain of the sixth PMOS transistor 142 can be connected to the first end of the seventh resistor 146. As shown, the drain of the fifth PMOS transistor 141 is connected to the source of the seventh PMOS transistor 143, the drain of the sixth PMOS transistor 142 is connected to the source of the eighth PMOS transistor 144, the gate of the seventh PMOS transistor 143 is connected to the gate of the eighth PMOS transistor 144, the drain of the seventh PMOS transistor 143 is connected to the gate of the seventh PMOS transistor 143, and the drain of the seventh PMOS transistor 143 is connected to the first end of the sixth resistor 145. The drain of the fourth PMOS transistor 114 is connected to the first end of the seventh resistor 146. Figure 4

[0061] The drain of the fifth NMOS transistor 147 is connected to the second end of the sixth resistor 145, the source of the fifth NMOS transistor 147 is connected to the reference ground, and the gate of the fifth NMOS transistor 147 is connected to the enable signal EN, so that the conduction or disconnection of the fifth NMOS transistor 147 is controlled by the enable signal EN.

[0062] In this way, the driving circuit can provide a current control signal (CHG pin).

[0063] In addition, for the driving circuit for charging control, the circuit can not be separately provided, and the drain end of the fourth PMOS transistor 114 of the driving circuit for discharging control (CHG pin) can be used as the current control signal. Figure 3

[0064] ​​In the present disclosure, in order to reduce the power consumption of a chip or an integrated device. In the present disclosure, instead of using the highest voltage VCC of a battery as a driving voltage, the highest voltage VCC of a battery is converted into an intermediate voltage VDD, and then the driving voltage Vdrv is generated by using the intermediate voltage VDD. For example, the intermediate voltage VDD can be about 6V, and the driving voltage Vdrv can be about 12V, etc.

[0065] Figure 5 A schematic diagram of voltage conversion is shown. The voltage VDD can be converted into the driving voltage Vdrv by a charge pump circuit, or the voltage VDD can be converted into the driving voltage Vdrv by a boost circuit, for example.

[0066] In which for the conversion from VCC to VDD, Figures 6 to 10 Various implementation manners are given in the present disclosure.

[0067] Figure 6 A voltage converter according to a first embodiment of the present disclosure is shown.

[0068] As shown in Figure 6 The inductive step-down conversion unit can step down the battery voltage VCC to the voltage VDDM, and the plurality of LDO step-down conversion units can step down the voltage VDDM to the voltages V1, V2, …, Vn, respectively.

[0069] Generally, the conversion efficiency of the inductive step-down conversion unit can be close to 100%. In this way, the battery voltage can be converted into the low voltage VDDM, for example, VDDM equals to 12V, by the inductive step-down conversion unit with high efficiency. Then the voltage VDDM is converted into a lower voltage, for example, 5.5V, by the LDO step-down conversion unit. In this way, when the battery voltage is 48V for example, the conversion efficiency of the voltage converter can be 12 / 5.5. However, when the voltage converter only uses the LDO step-down conversion unit, the conversion efficiency is 48 / 5.5. Therefore, the conversion efficiency can be obviously improved by the voltage converter of the present disclosure. In the present disclosure, the voltage value of VDDM can be 5V to 12V.

[0070] And by the generated plurality of voltages V1, V2, …, Vn, different voltages can be provided for different devices in the battery management system (or external MCUs, etc.), and the voltage values can be 1.8V, 3.3V, 5V, etc. For example, the working voltage of some devices is 1.8V, the working voltage of some devices is 3.3V, and the working voltage of some devices is 5V. In this way, different working voltages can be generated according to needs to provide different voltages for devices that need different voltages.

[0071] Figure 7 A voltage converter according to a second embodiment of the present disclosure is shown.

[0072] AsFigure 7 As shown, the inductor-type buck converter can step down the battery voltage VCC to voltage VDDM, and multiple LDO buck converters can step down the voltage VDDM to voltages V2, V3, and V4 respectively (there can be more). The inductor-type boost converter can boost the voltage VDDM to voltage V1 (there can be more).

[0073] The voltage value of voltage VDDM can be from 5V to 12V, the voltage value of voltage V1 can be 12V, and the voltage values ​​of voltages V2, V3, and V4 can be 1.8V, 3.3V, 5V, etc.

[0074] By generating multiple voltages V1, V2, V3, and V4, different voltages can be provided to different devices in the battery management system (or external MCUs, etc.). For example, some devices operate at 1.8V, some at 3.3V, and some at 5V or 12V. In this way, different operating voltages can be generated as needed to provide different voltages to devices that require different voltages.

[0075] Figure 8 A voltage converter according to a third embodiment of the present disclosure is shown.

[0076] like Figure 8 As shown, the inductor-type buck converter can step down the battery voltage VCC to voltage VDDM, and multiple LDO buck converters can step down the voltage VDDM to voltages V2, V3, and V4 respectively (there can be more). The charge pump boost converter can boost the voltage VDDM to voltage V1 (there can be more).

[0077] The voltage value of voltage VDDM can be from 5V to 12V, the voltage value of voltage V1 can be 12V, and the voltage values ​​of voltages V2, V3, and V4 can be 1.8V, 3.3V, 5V, etc.

[0078] By generating multiple voltages V1, V2, V3, and V4, different voltages can be provided to different devices in the battery management system (or external MCUs, etc.). For example, some devices operate at 1.8V, some at 3.3V, and some at 5V or 12V. In this way, different operating voltages can be generated as needed to provide different voltages to devices that require different voltages.

[0079] Figure 9 A voltage converter according to a fourth embodiment of the present disclosure is shown.

[0080] like Figure 9 As shown, the inductive buck converter can step down the battery voltage VCC to voltage VDDM1, and the inductive buck converter can step down the voltage VDDM1 to voltage VDDM2.

[0081] And the multiple LDO buck conversion units can respectively buck the voltage VDDM2 to voltage V3, V4, V5 (may be more). VDDM1 can be V1, and VDDM2 can be V2.

[0082] The voltage value of the voltage VDDM1 can be 12V, the voltage value of the voltage VDDM2 can be 5.5V, and the voltage values of the voltages V3, V4, V5 can be 1.8V, 3.3V, 5V, etc.

[0083] Through the generated multiple voltages V1, V2, V3, V4, V5, different devices (or external MCUs, etc.) in the battery management system can be provided with different voltages. For example, the working voltage of some devices is 1.8V, the working voltage of some devices is 3.3V, and the working voltage of some devices is 5V or 12V. In this way, different working voltages can be generated according to needs to provide devices that require different voltages.

[0084] Figure 10 A voltage converter according to a fifth embodiment of the present disclosure is shown.

[0085] As shown in Figure 10 The inductive buck conversion unit can buck the battery voltage VCC to voltage VDDM1, and the charge pump buck conversion unit can buck the voltage VDDM1 to VDDM2.

[0086] And the multiple LDO buck conversion units can respectively buck the voltage VDDM2 to voltage V4, V5 (may be more). VDDM1 can be V1, and VDDM2 can be V2.

[0087] The voltage value of the voltage VDDM1 can be 12V, the voltage value of the voltage VDDM2 can be 6V, and the voltage values of the voltages V3, V4, V5 can be 1.8V, 3.3V, 5V, etc.

[0088] Through the generated multiple voltages V1, V2, V3, V4, V5, different devices (or external MCUs, etc.) in the battery management system can be provided with different voltages. For example, the working voltage of some devices is 1.8V, the working voltage of some devices is 3.3V, and the working voltage of some devices is 5V or 12V. In this way, different working voltages can be generated according to needs to provide devices that require different voltages.

[0089] In the embodiment of Figures 6 to 10 , multiple VDDs can be converted, but for the needs of the driving circuit, one conversion unit can be used to obtain one VDD voltage.

[0090] Figure 11A battery management system is provided. A voltage collection unit 200 can be used to collect the voltage of each battery, and a VDD generation unit (corresponding to Figures 6 to 10 the detailed description) can generate a VDD voltage to supply power to each component. A control logic unit 300 can receive the voltage collected by the voltage collection unit 200, and the control logic unit 300 generates a control signal (e.g., an enable signal EN) according to a current detection signal, a temperature detection signal, and / or a voltage signal collected by the voltage collection unit 200, etc. to provide to the driving unit 100 to control the charging control transistor and the discharging control transistor through the driving unit 100. The two ends of the battery can be connected to a charger or a load 400.

[0091] In the description of the present specification, the description of the terms "one embodiment / way", "some embodiments / ways", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment / way or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments / ways or examples. In addition, the person skilled in the art can combine and combine the different embodiments / ways or examples described in the present specification and the features of the different embodiments / ways or examples, without contradiction.

[0092] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0093] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. Other changes or modifications can be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A drive circuit for supplying control signals to charge control transistors and discharge control transistors for controlling charging and discharging of a battery pack, characterized by, The application relates to a driving circuit for a battery pack, comprising: a first driving unit providing a voltage control signal for a discharge control transistor, so as to control the on and off of the discharge control transistor through the voltage control signal; a second driving unit providing a current control signal for a charge control transistor, so as to control the on and off of the charge control transistor through the current control signal and the voltage generated by the current control signal and a first resistor connected between the gate and the source of the charge control transistor; the first driving unit comprises: a source of a first PMOS transistor connected to a driving voltage of the driving circuit, a gate connected to a gate of a second PMOS transistor, a drain connected to a first end of a second resistor, and a gate and a drain connected; a source of a second PMOS transistor connected to the driving voltage, a drain connected to a cathode of a first Zener diode; an anode of the first Zener diode connected to a cathode of a second Zener diode, and an anode of the second Zener diode connected to a reference ground; a drain of a first NMOS transistor connected to a second end of the second resistor, a source connected to the reference ground, and a gate connected to an enable signal, so as to control the on and off of the first NMOS transistor through the enable signal; a gate of a second NMOS transistor connected to the cathode of the first Zener diode through a third resistor, a drain connected to the driving voltage, a source connected to a first end of a fourth resistor and an anode of a third Zener diode, and a gate connected to a cathode of the third Zener diode; a drain of a third NMOS transistor connected to the cathode of the first Zener diode, a source connected to the reference ground, and a gate connected to an output end of an inverter, and an input end of the inverter connected to the enable signal; a gate of a fourth NMOS transistor connected to the output end of the inverter, a source connected to the reference ground, and a drain connected to a second end of a fifth resistor, a first end of the fifth resistor connected to a second end of the fourth resistor, and a connection point of the fourth resistor and the fifth resistor as an output end of the voltage control signal; the second driving unit comprises: a source of a fifth PMOS transistor connected to the driving voltage, a source of a sixth PMOS transistor connected to the driving voltage, a drain of a seventh PMOS transistor connected to a first end of a sixth resistor, a drain of a fourth PMOS transistor connected to a first end of a seventh resistor, a drain of a fifth NMOS transistor connected to a second end of the sixth resistor, a source of the fifth NMOS transistor connected to the reference ground, a gate of the fifth NMOS transistor connected to the enable signal, and a second end of the seventh resistor providing the current control signal; the driving voltage of the driving circuit is formed through a voltage conversion unit, the voltage conversion unit converts the highest voltage of the battery pack into a first voltage through voltage reduction, and the first voltage is converted into the driving voltage through voltage increase.

2. The drive circuit of claim 1, wherein The charge control transistor and the discharge control transistor are NMOS transistors or PMOS transistors.

3. The drive circuit of claim 2, wherein The source of the charging control transistor is connected to a charger / load terminal, the gate of the charging control transistor receives the current control signal, the drain of the charging control transistor is connected to the drain of the discharging control transistor, the gate of the discharging control transistor receives the voltage control signal, and the source of the discharging control transistor is connected to a battery terminal.

4. The drive circuit of claim 1, wherein The gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor, the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the gate of the seventh PMOS transistor.

5. The drive circuit of claim 4, wherein, The first voltage is converted into the driving voltage by a charge pump or a voltage boosting circuit.

6. The drive circuit of claim 1, wherein, The current control signal is provided through the drain of the fourth PMOS transistor.

7. An integrated device, comprising: The driving circuit is integrated with the driving circuit according to any one of claims 1 to 6.

8. A battery management chip, characterized by, The driving circuit according to any one of claims 1 to 6 is included. The driving circuit according to any one of claims 1 to 6 is included. A voltage conversion unit converts the highest voltage of the battery into a driving voltage of the driving circuit.

9. The battery management chip of claim 8, wherein, The voltage conversion unit converts the highest voltage of the battery into a first voltage by voltage step-down, and the first voltage is converted into the driving voltage by voltage step-up.

10. The battery management chip of claim 8, wherein, Further comprising: A control logic unit generates a control signal provided to the driving circuit according to a current detection signal, a temperature detection signal, and / or a battery voltage detection signal, and the driving circuit provides the current control signal and the voltage control signal according to the control signal.

11. The battery management chip of claim 10, wherein, Further comprising a voltage collection unit capable of collecting the voltage of each battery in the battery, and providing the collected voltage to the control logic unit as the battery voltage detection signal.

12. A battery management system, characterized by, The driving circuit according to any one of claims 1 to 6 is included. The driving circuit according to any one of claims 1 to 6 is included. A charging control transistor and a discharging control transistor, the driving circuit provides a current control signal to the charging control transistor and a voltage control signal to the discharging control transistor to control the turn-on and turn-off of the charging control transistor and the discharging control transistor. ​

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