A bidirectional DCDC power conversion circuit

Abstract

The present invention discloses a bidirectional DCDC power conversion circuit, which includes a full-bridge rectifier circuit, a transformer, a first diode, a second diode, a first capacitor, a first inductor and a switching circuit. By setting the first diode, the second diode and the primary coil of the transformer to form a clamping network and optimizing the turn ratio of the two coils on the high-voltage side of the transformer, when the bidirectional power conversion circuit works in the forward direction, the clamping network can effectively suppress the spike voltage of the switching device in the switching circuit and reduce the difficulty of selecting components for the switching circuit. When the bidirectional power conversion circuit works in the reverse direction, the clamping network, the full-bridge phase-shift circuit and the transformer jointly form a low-impedance loop and a charging loop to achieve zero-current soft switching and boost function. Compared with the existing bidirectional power conversion circuit which cannot achieve the boost function with an LC topology when working in the reverse direction, it has better adaptability, and avoids the problems of the reverse recovery characteristic and large heat generation of the clamping diode, improving the reliability of the circuit.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and in particular to a bidirectional DCDC power conversion circuit. Background Art

[0002] With the development of the battery capacity market, there is a wider demand for bidirectional ACDC charging and discharging power supplies. At present, the ACDC+DCDC two-part bidirectional switching circuit is mostly used to realize the functions of forward rectification and voltage transformation, reverse inverter and grid connection. Among them, for the existing DCDC partial conversion circuit, the LLC topology circuit can realize a wide voltage regulation range and ZVS (Zero Voltage Switch) soft switching characteristics when working in the forward direction, but it is transformed into an LC topology when working in the reverse direction, and the boost function cannot be realized, which has certain limitations. And although the traditional PSFB (Phase Shift Full Bridge) topology forward rectification work can also realize the ZVS soft switching of the high-voltage side MOS tube, and the synchronous rectification of the low-voltage side is also easy to achieve, but due to the introduction of the differential mode inductor on the low-voltage side, a clamping diode needs to be added between the high-voltage side transformer and the inductor to ensure that the low-voltage side diode spike does not exceed the standard. When the circuit works in the reverse direction, since the high-voltage side MOS tube body diode does not control the rectification work, and the clamping diode has a low resistance characteristic relative to the resonant inductor, it bears all the rectification current. Therefore, the clamping diode has a reverse recovery characteristic problem and generates more heat, requiring an additional heat sink and a diode with better reverse recovery characteristics, which increases product costs and reduces product reliability. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a bidirectional DCDC power conversion circuit to improve the circuit reliability.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A bidirectional DCDC power conversion circuit comprises a full-bridge rectifier circuit, a transformer, a first diode, a second diode, a first capacitor, a first inductor and a switch circuit;

[0006] The anode of the first diode is connected to the cathode of the second diode;

[0007] The first end of the full-bridge rectifier circuit is connected to the positive electrode of the preset first input and output end and the negative electrode of the first diode respectively, the second end is connected to the negative electrode of the preset first input and output end and the positive electrode of the second diode respectively, the third end is connected to one end of the first capacitor, and the fourth end is connected to one end of the first inductor;

[0008] The other end of the first capacitor is connected to the first end of the transformer;

[0009] The other end of the first inductor is connected to the second end of the transformer;

[0010] The primary tap of the transformer is connected to the positive electrode of the first diode;

[0011] The third end of the transformer is connected to the first input / output end of the switch circuit, and the fourth end of the transformer is connected to the second input / output end of the switch circuit.

[0012] The beneficial effects of the present invention are as follows: by setting a first diode, a second diode and a primary coil of a transformer to form a clamping network, the turns ratio of the two coils on the high-voltage side of the transformer is optimized, so that when the bidirectional power conversion circuit works in the forward direction, the clamping network can effectively suppress the peak voltage of the switching device in the switching circuit, reducing the difficulty of selecting the switching circuit device; when the bidirectional power conversion circuit works in the reverse direction, the clamping network, the full-bridge phase-shifting circuit and the transformer together form a low-impedance loop and a charging loop, realizing zero-current soft switching and boosting functions. Compared with the existing bidirectional power conversion circuit, which is an LC topology and cannot realize the boosting function when working in the reverse direction, it has better adaptability, avoids the reverse recovery characteristic problem and the problem of high heat generation of the clamping diode, and improves the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the circuit structure of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0014] Figure 2 Another circuit structure schematic diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0015] Figure 3 Another circuit structure schematic diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0016] Figure 4 A schematic logic control circuit diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0017] Figure 5 Another schematic logic control circuit diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0018] Figure 6 A schematic diagram of the circuit timing operation of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0019] Figure 7 Another circuit timing operation diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0020] Figure 8 Another circuit timing operation diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0021] Fig. 9 Another circuit structure schematic diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention;

[0022] Fig.10 The present invention is another schematic diagram of a bidirectional DCDC power conversion circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0024] Please refer to Figure 1 , an embodiment of the present invention provides a bidirectional DCDC power conversion circuit, including a full-bridge rectifier circuit, a transformer, a first diode, a second diode, a first capacitor, a first inductor and a switch circuit;

[0025] The anode of the first diode is connected to the cathode of the second diode;

[0026] The first end of the full-bridge rectifier circuit is connected to the positive electrode of the preset first input and output end and the negative electrode of the first diode respectively, the second end is connected to the negative electrode of the preset first input and output end and the positive electrode of the second diode respectively, the third end is connected to one end of the first capacitor, and the fourth end is connected to one end of the first inductor;

[0027] The other end of the first capacitor is connected to the first end of the transformer;

[0028] The other end of the first inductor is connected to the second end of the transformer;

[0029] The primary tap of the transformer is connected to the positive electrode of the first diode;

[0030] The third end of the transformer is connected to the first input / output end of the switch circuit, and the fourth end of the transformer is connected to the second input / output end of the switch circuit.

[0031] From the above description, it can be seen that the beneficial effects of the present invention are: by setting the first diode, the second diode and the primary coil of the transformer to form a clamping network, the turns ratio of the two coils on the high-voltage side of the transformer is optimized, so that when the bidirectional power conversion circuit works in the forward direction, the clamping network can effectively suppress the peak voltage of the switching device in the switching circuit, and reduce the difficulty of selecting the switching circuit device. When the bidirectional power conversion circuit works in the reverse direction, the clamping network, the full-bridge phase-shifting circuit and the transformer together form a low-impedance loop and a charging loop to achieve zero-current soft switching and boost functions. Compared with the existing bidirectional power conversion circuit, which is an LC topology and cannot achieve the boost function when working in the reverse direction, it has better adaptability and avoids the reverse recovery characteristics and high heat generation problems of the clamping diode, thereby improving the reliability of the circuit.

[0032] The working principle of the bidirectional DCDC power conversion circuit of the present invention is as follows:

[0033] When the circuit works in the forward direction, the transformer primary coils Np1 and Np2, the first diode, the second diode and the full-bridge rectifier circuit form an output circuit to output an electrical signal, and the first diode, the second diode and the transformer primary coil form a clamping circuit to suppress the turn-off voltage of the switch device in the secondary switch circuit;

[0034] When the circuit works in reverse, the transformer primary coil Np2, the first diode or the second diode, the first MOS or the second MOS tube and the first capacitor form a low-impedance first rectifier circuit that is turned on first; the transformer primary coil Np1, the first diode or the second diode, the third MOS or the fourth MOS tube and the first inductor form a high-impedance second rectifier circuit, the second rectifier circuit charges the first inductor, and when the charging current of the first inductor rises to the turns ratio current in Np2, the branch circuit where the first diode or the second diode is located drops to 0A, thereby realizing ZCS soft switching.

[0035] Further, it also includes a logic control circuit;

[0036] The logic control circuit includes a first logic circuit and a second logic circuit;

[0037] The full-bridge rectifier circuit includes a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube;

[0038] The drain of the first MOS tube is connected to the drain of the third MOS tube;

[0039] The source of the second MOS tube is connected to the source of the fourth MOS tube;

[0040] The source of the first MOS tube is connected to the drain of the second MOS tube;

[0041] The source of the third MOS tube is connected to the drain of the fourth MOS tube;

[0042] The drain of the first MOS tube is connected to the positive electrode of the preset first input and output terminal and the negative electrode of the first diode respectively;

[0043] The source of the second MOS tube is connected to the cathode of the preset first input and output terminal and the anode of the second diode respectively;

[0044] The one end of the first capacitor is connected to the source of the first MOS tube;

[0045] The one end of the first inductor is connected to the source of the third MOS tube;

[0046] The input end of the first logic circuit is connected to the gate of the first MOS transistor and the gate of the fourth MOS transistor respectively, and the output end is connected to the first control end of the switch circuit;

[0047] The input end of the second logic circuit is connected to the gate of the second MOS transistor and the gate of the third MOS transistor respectively, and the output end is connected to the second control end of the switch circuit.

[0048] It can be seen from the above description that by connecting the input end of the first logic circuit to the gate of the first MOS tube and the gate of the fourth MOS tube respectively, and connecting the input end of the second logic circuit to the gate of the second MOS tube and the gate of the third MOS tube respectively, and forming a first logic signal and a second logic signal to control the switching circuit on the secondary side of the transformer, the output of the circuit can be controlled during forward operation, thereby improving the working stability of the circuit.

[0049] Further, it also includes an enabling control circuit;

[0050] The output end of the enable control circuit is connected to the input end of the first logic control circuit and the input end of the second logic control circuit respectively.

[0051] From the above description, it can be seen that the output end of the enable control circuit is connected to the input end of the first logic control circuit and the input end of the second logic control circuit respectively. By changing the output value of the enable control circuit, the logic control circuit can output different logical operation results according to the value, thereby realizing different circuit functions and improving the practicality of the circuit.

[0052] Further, the first logic circuit includes a first AND circuit, a first OR circuit, a second AND circuit, and a second OR circuit;

[0053] The first input end of the first OR circuit is connected to the gate of the first MOS transistor, the second input end is connected to the gate of the fourth MOS transistor, and the output end is connected to the first input end of the second AND circuit;

[0054] The second input terminal of the second AND circuit is connected to the output terminal of the enable control circuit;

[0055] The first input end of the first AND circuit is connected to the gate of the first MOS transistor, the second input end is connected to the gate of the fourth MOS transistor, and the output end is connected to the first input end of the second OR circuit;

[0056] The second input terminal of the second OR circuit is connected to the output terminal of the second AND circuit, and the output terminal is connected to the first control terminal of the switch circuit.

[0057] It can be seen from the above description that the first logic control circuit obtains the control signal of the gate of the first MOS tube, the control signal of the gate of the fourth MOS tube and the input signal of the output end of the enable control circuit, and performs relevant "AND" and "OR" logic operations on the obtained signals, so that the switch control circuit on the primary side of the transformer can accurately control the output according to the result of the logic operation, thereby achieving efficient circuit control and improving the circuit working stability.

[0058] Further, the second logic circuit includes a third AND circuit, a third OR circuit, a fourth AND circuit and a fourth OR circuit;

[0059] The first input end of the third OR circuit is connected to the gate of the second MOS transistor, the second input end is connected to the gate of the third MOS transistor, and the output end is connected to the first input end of the fourth AND circuit;

[0060] The second input terminal of the fourth AND circuit is connected to the output terminal of the enable control circuit;

[0061] The first input terminal of the third AND circuit is connected to the gate of the second MOS transistor, the second input terminal is connected to the gate of the third MOS transistor, and the output terminal is connected to the first input terminal of the fourth OR circuit;

[0062] The second input terminal of the fourth OR circuit is connected to the output terminal of the fourth AND circuit, and the output terminal is connected to the second control terminal of the switch circuit.

[0063] It can be seen from the above description that the second logic control circuit obtains the control signal of the gate of the second MOS tube, the control signal of the gate of the third MOS tube and the input signal of the output end of the enable control circuit, and performs relevant "AND" and "OR" logic operations on the obtained signals, so that the switch control circuit on the primary side of the transformer can accurately control the output according to the result of the logic operation, thereby achieving efficient circuit control and improving the circuit working stability.

[0064] Furthermore, it also includes a second inductor and a second capacitor;

[0065] The positive electrode of the second input and output terminal is respectively connected to one end of the second capacitor and one end of the second inductor;

[0066] The negative electrode of the second input-output terminal is connected to the other end of the second capacitor;

[0067] The other end of the second inductor is connected to the switch circuit.

[0068] It can be seen from the above description that by setting the second capacitor and the second inductor, when the circuit works in the forward direction, the second capacitor and the second inductor form a filter circuit to filter the input signal, and when the circuit works in the reverse direction, the second inductor is used as a boost inductor to form an LLC topology loop to realize the boost function of reverse operation.

[0069] Further, the switch circuit includes a fifth MOS tube and a sixth MOS tube;

[0070] The transformer secondary tap is connected to the other end of the second inductor;

[0071] The third end of the transformer is connected to the drain of the fifth MOS tube, and the fourth end is connected to the drain of the sixth MOS tube;

[0072] The negative electrode of the second input-output terminal is connected to the source electrode of the fifth MOS tube and the source electrode of the sixth MOS tube respectively.

[0073] It can be seen from the above description that by connecting the secondary tap of the transformer to the second inductor, a rectifier circuit is formed with the fifth MOS tube and the sixth MOS tube, so that the input signal can be rectified, and when the secondary side of the transformer has a tap connection end, the secondary side circuit of the transformer can have a rectification function.

[0074] Further, the switch circuit includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube;

[0075] The third end of the transformer is connected to the source of the seventh MOS tube and the drain of the eighth MOS tube respectively;

[0076] The fourth end of the transformer is connected to the source of the ninth MOS tube and the drain of the tenth MOS tube respectively;

[0077] The other end of the second inductor is connected to the drain of the seventh MOS tube and the drain of the ninth MOS tube respectively;

[0078] The negative electrode of the second input-output terminal is connected to the source electrode of the eighth MOS tube and the source electrode of the tenth MOS tube respectively.

[0079] It can be seen from the above description that the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube together form a rectification circuit, so that the input signal can be rectified, and when the secondary side of the transformer does not have a tap connection end, the secondary side circuit of the transformer can have a rectification function.

[0080] Further, the transformer primary tap has a multi-component connector;

[0081] The tap is used to be connected to the anode of the first diode.

[0082] From the above description, it can be seen that by connecting different taps to the primary tap of the transformer, the turns ratio can be controlled, so that different turns ratios can be configured according to different device selection schemes, so that the circuit selection scheme configuration is optimized and the circuit adaptability is improved.

[0083] Further, the third end of the full-bridge rectifier circuit is connected to one end of the first capacitor, the fourth end is connected to one end of the first inductor, the other end of the first capacitor is connected to the first end of the transformer, and the other end of the first inductor is connected to the second end of the transformer as follows:

[0084] The third end of the full-bridge rectifier circuit is connected to one end of the first inductor, and the fourth end is connected to one end of the first capacitor;

[0085] The other end of the first capacitor is connected to the second end of the transformer;

[0086] The other end of the first inductor is connected to the first end of the transformer.

[0087] It can be seen from the above description that the positions of the first inductor and the first capacitor can be interchanged, so that the positions of the first inductor and the first capacitor can be adjusted according to the actual wiring requirements of the circuit, thereby reducing the difficulty of circuit wiring.

[0088] Embodiment 1

[0089] Please refer to Figure 1 , a bidirectional DCDC power conversion circuit, comprising a full-bridge rectifier circuit, a transformer, a first diode, a second diode, a first capacitor, a first inductor and a switch circuit;

[0090] The first end of the full-bridge rectifier circuit is connected to the positive electrode of the preset first input and output end and the negative electrode of the first diode respectively, the second end is connected to the negative electrode of the preset first input and output end and the positive electrode of the second diode respectively, the third end is connected to one end of the first capacitor, and the fourth end is connected to one end of the first inductor; wherein the third end is Figure 1 Point A in the Figure 1 Point B in the figure; filter capacitor C3 is connected in parallel at both ends of the first input and output terminals; the first capacitor is a DC blocking capacitor, and the first inductor is a resonant inductor; the preset first input and output terminals are Figure 1 V1 is the high voltage side voltage input and output terminal of the bidirectional DCDC power conversion circuit, and V2 is the input and output terminal of the switch circuit, that is, the low voltage side voltage input and output terminal of the bidirectional DCDC power conversion circuit;

[0091] The full-bridge rectifier circuit includes a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube form an H4-type full-bridge filter network, and according to the relationship between their driving leading and trailing, the first MOS tube is defined as an advanced upper bridge arm, the second MOS tube is defined as an advanced lower bridge arm, the third MOS tube is defined as a lagging upper bridge arm, and the fourth MOS tube is defined as a lagging lower bridge arm; the drain of the first MOS tube is connected to the drain of the third MOS tube, which is the first MOS tube of the full-bridge rectifier circuit. one end; the source of the second MOS tube is connected to the source of the fourth MOS tube, which is the third end of the full-bridge rectifier circuit; the source of the first MOS tube is connected to the drain of the second MOS tube, which is the third end of the full-bridge rectifier circuit; the source of the third MOS tube is connected to the drain of the fourth MOS tube, which is the fourth end of the full-bridge rectifier circuit; the drain of the first MOS tube is respectively connected to the positive electrode of the preset first input and output end and the negative electrode of the first diode; the source of the second MOS tube is respectively connected to the negative electrode of the preset first input and output end and the positive electrode of the second diode;

[0092] One end of the first capacitor is connected to the source of the first MOS tube; one end of the first inductor is connected to the source of the third MOS tube; the parasitic capacitance of the first MOS tube, the parasitic capacitance of the second MOS tube, the parasitic capacitance of the third MOS tube, the parasitic capacitance of the fourth MOS tube, the first capacitor and the first inductor form a resonant network to achieve ZVS soft switching of the MOS tube in the next switching cycle;

[0093] The transformer primary side is divided into a first coil Np1 and a second coil Np2 by tapping; the tap is Figure 1Point C in the figure, the end of Np2 away from the tap is the first end of the transformer, and the end of Np1 away from the tap is the second end of the transformer; the secondary side of the transformer also includes a second inductor and a second capacitor; the positive electrode of the second input and output terminal is connected to one end of the second capacitor and one end of the second inductor respectively, and the negative electrode of the second input and output terminal is connected to the other end of the second capacitor; the other end of the second inductor is connected to the switch circuit;

[0094] Specifically, the other end of the first capacitor is connected to the first end of the transformer; the other end of the first inductor is connected to the second end of the transformer; the primary tap of the transformer is connected to the positive electrode of the first diode; the positive electrode of the first diode is connected to the negative electrode of the second diode; the third end of the transformer is connected to the first end of the switching circuit, and the fourth end is connected to the second end of the switching circuit.

[0095] Embodiment 2

[0096] The difference between this embodiment and the first embodiment is that this embodiment specifically defines the switch circuit and its connection relationship;

[0097] Please refer to Figure 2 , the switch circuit includes a fifth MOS tube and a sixth MOS tube;

[0098] The secondary coil of the transformer is divided into a first coil Ns1 and a second coil Ns2 through a secondary tap; the end of Ns2 away from the tap is the third end of the transformer, and the end of Ns1 away from the tap is the fourth end of the transformer; the number of turns of Ns1 is the same as the number of turns of Ns2;

[0099] Specifically, the secondary tap of the transformer is connected to the other end of the second inductor; the third end of the transformer is connected to the drain of the fifth MOS tube, and the fourth end is connected to the drain of the sixth MOS tube; the source of the fifth MOS tube and the source of the sixth MOS tube are connected to the negative electrode of the second input-output terminal and the other end of the second capacitor;

[0100] Therefore, when the circuit works in the forward direction, the clamping circuit composed of the first diode, the second diode, Np1 and Np2 on the primary high-voltage side can effectively suppress the turn-off voltage of the fifth MOS tube and the sixth MOS tube on the low-voltage side, and the theoretical maximum peak value thereof is: Vds_pk=V1*Ns1 / Np2, so that the fifth MOS tube and the sixth MOS tube on the low-voltage side are optimally selected;

[0101] Please refer to Figure 3 , in another optional implementation, the switch circuit includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube;

[0102] The secondary side of the transformer is a single coil Ns1; the same-name terminal marks of Ns1 and Np1 are located opposite to each other; the terminal close to the same-name terminal mark is the third terminal of the transformer, and the other terminal is the fourth terminal of the transformer;

[0103] Specifically, the third end of the transformer is connected to the source of the seventh MOS tube and the drain of the eighth MOS tube respectively; the fourth end of the transformer is connected to the source of the ninth MOS tube and the drain of the tenth MOS tube respectively; the other end of the second inductor is connected to the drain of the seventh MOS tube and the drain of the ninth MOS tube respectively; the negative electrode of the second input and output end is connected to the source of the eighth MOS tube and the source of the ninth MOS tube and the second capacitor respectively;

[0104] This embodiment deforms the switch circuit on the low-voltage side according to different connection modes to achieve a deformation mode of the secondary-side rectification network, which is applicable to full-wave rectification and full-bridge rectification circuits, greatly improving the adaptability of the circuit.

[0105] Embodiment 3

[0106] The difference between this embodiment and the first or second embodiment is that this embodiment further includes a logic circuit and an enable control circuit;

[0107] Controlling the switch circuit of the secondary side of the transformer by means of the logic control circuit and the enable control circuit;

[0108] Specifically, the logic control circuit includes a first logic circuit and a second logic circuit; the input end of the first logic circuit is respectively connected to the gate of the first MOS tube and the gate of the fourth MOS tube, and the output end is connected to the first control end of the switch circuit; the input end of the second logic circuit is respectively connected to the gate of the second MOS tube and the gate of the third MOS tube, and the output end is connected to the second control end of the switch circuit; the output end of the enable control circuit is respectively connected to the input end of the first logic control circuit and the input end of the second logic control circuit;

[0109] Wherein, the first logic circuit includes a first AND circuit, a first OR circuit, a second AND circuit, and a second OR circuit;

[0110] Specifically, the first input end of the first OR circuit is connected to the gate of the first MOS tube, the second input end is connected to the gate of the fourth MOS tube, and the output end is connected to the first input end of the second AND circuit; the second input end of the second AND circuit is connected to the output end of the enable control circuit; the first input end of the first AND circuit is connected to the gate of the first MOS tube, the second input end is connected to the gate of the fourth MOS tube, and the output end is connected to the first input end of the second OR circuit; the second input end of the second OR circuit is connected to the output end of the second AND circuit, and the output end is connected to the first control end of the switch circuit; wherein the input end of the enable control circuit samples the current of the second inductor and outputs the sampling result to the second input end of the second AND circuit; the load V2 has two working modes of light load and heavy load, and the working state of the load is distinguished by a preset load switching point; please refer to Figure 4 , the signal of the gate of the first MOS tube is set to Q1, the signal of the gate of the fourth MOS tube is set to Q4, and the signal of the output end of the enable control circuit is set to EN; according to the connection relationship of the above-mentioned first logic circuit, the corresponding logical operation relationship is obtained: EN·(Q1+Q4)+Q1·Q4;

[0111] Wherein, the second logic circuit includes a third AND circuit, a third OR circuit, a fourth AND circuit and a fourth OR circuit;

[0112] Specifically, the first input end of the third OR circuit is connected to the gate of the second MOS tube, the second input end is connected to the gate of the third MOS tube, and the output end is connected to the first input end of the fourth AND circuit; the second input end of the fourth AND circuit is connected to the output end of the enable control circuit; the first input end of the third AND circuit is connected to the gate of the second MOS tube, the second input end is connected to the gate of the third MOS tube, and the output end is connected to the first input end of the fourth OR circuit; the second input end of the fourth OR circuit is connected to the output end of the fourth AND circuit, and the output end is connected to the second control end of the switch circuit;

[0113] Please refer to Figure 5 , the signal of the gate of the second MOS tube is set to Q2, and the signal of the gate of the third MOS tube is set to Q3; according to the connection relationship of the second logic circuit, the corresponding logic operation relationship is obtained as follows: EN·(Q2+Q3)+Q2·Q3;

[0114] If the operation result of the logic circuit is output to Figure 2 In the switching circuit shown;

[0115] The gate of the fifth MOS transistor is the first control terminal of the switch circuit, which is set to QB; the gate of the sixth MOS transistor is the second control terminal of the switch circuit, which is set to QA; the current of the second inductor is set to iL2;

[0116] In forward operation, after determining the effective duty cycle according to the leading bridge arm and the lagging bridge arm, when the load is in a light load working state, the sampling determines that iL2 is current discontinuous, and the logic synchronous rectification strategy is adopted, that is, EN is set to 0, and the logical relationship is obtained:

[0117] QB=Q1·Q4,QA=Q2·Q3;

[0118] Please refer to Figure 6 , that is, the low-voltage side synchronous rectification signal is controlled by the first AND circuit. In this state, the secondary output of the transformer is lightly loaded, and the iL2 inductor current is discontinuous;

[0119] When the load is in a heavy load working state, the sampling determines that iL2 is a continuous current, and the OR logic synchronous rectification is adopted, that is, EN is set to 1, and the logical relationship is obtained:

[0120] QA=(Q2+Q3)+Q2·Q3, QB=(Q1+Q4)+Q1·Q4;

[0121] Please refer to Figure 7 , that is, the low-voltage side synchronous rectification signal is controlled by the first or circuit. In this state, the secondary output of the transformer is overloaded, and the iL2 inductor current is in a continuous state;

[0122] Through logical operation, QA and QB are coordinated for synchronous rectification control to achieve efficient control of the module;

[0123] Please refer to Figure 8 When working in the reverse direction, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube do not control the rectification work, and the fifth MOS tube and the sixth MOS tube are used as circuit-type push-to-complete topology main control switches, which work in a working mode with a duty cycle D>0.5, and the theoretical effective duty cycle is: 2D-1.

[0124] Embodiment 4

[0125] The difference between this embodiment and any one of the first to third embodiments is that the primary tap of the transformer has a multi-component connector;

[0126] Please refer to Fig. 9, the tap is used to connect to the positive electrode of the first diode; point S in the figure is the common tap of Np1 and Np2, and is connected to point C; different configuration schemes of the turns ratio of Np1 to Np2 can be achieved by adjusting the position of the S point line; when the number of turns of Np1 is small, the peak suppression effect of the fifth MOS tube and the sixth MOS tube on the low-voltage side during forward operation is better; when the number of turns of Np1 is large, the current stress of the first diode and the second diode during reverse operation becomes smaller, and the circuit loss is smaller; the optimal configuration scheme can be configured according to different device selection schemes.

[0127] Embodiment 5

[0128] The difference between this embodiment and any one of the first to fourth embodiments is that the positions of the first capacitor and the first inductor are replaced;

[0129] Please refer to Fig.10 , the third end of the full-bridge rectifier circuit is connected to one end of the first capacitor, the fourth end is connected to one end of the first inductor, the other end of the first capacitor is connected to the first end of the transformer, and the other end of the first inductor is connected to the second end of the transformer.

[0130] The third end of the full-bridge rectifier circuit is connected to one end of the first inductor, and the fourth end is connected to one end of the first capacitor; the other end of the first capacitor is connected to the second end of the transformer; the other end of the first inductor is connected to the first end of the transformer;

[0131] Specifically, one end of the first inductor is connected to point A, and the other end is connected to the first end of the transformer; one end of the first capacitor is connected to point B, and the other end is connected to the second end of the transformer;

[0132] In this embodiment, the positions of the first inductor and the first capacitor are interchanged so that the positions of the first inductor and the first capacitor can be adjusted according to actual wiring requirements of the circuit, thereby reducing the difficulty of circuit wiring.

[0133] In summary, the present invention provides a bidirectional DCDC power conversion circuit, which forms a clamping network by setting a first diode, a second diode and a primary coil of a transformer, and optimizes the turns ratio of two coils Np1 and Np2 on the high-voltage side of the transformer through multiple groups of taps on the primary side of the transformer, so that the circuit can be configured with the optimal configuration scheme according to different device selection schemes, and after determining the effective duty cycle of the circuit operation by the leading and lagging bridge arm phase shift angles, the circuit is efficiently controlled in combination with the logic control circuit. When the bidirectional power conversion circuit works in the forward direction, two different output modes are realized according to the logic output result of the logic control circuit, and the clamping network can effectively suppress the peak voltage of the switching device in the switching circuit, reducing the difficulty of selecting the switching circuit device. When the bidirectional power conversion circuit works in the reverse direction, the clamping network, the full-bridge phase shift circuit and the transformer together form a low-impedance loop and a charging loop, realizing zero-current soft switching and boosting functions, and improving the reliability of the circuit. At the same time, the capacitor position and the inductor position on the high-voltage side can be replaced, and the switching circuit on the low-voltage side can be realized according to different connection methods to be suitable for full-wave rectification and full-bridge rectification circuits, which greatly improves the adaptability of the circuit.

[0134] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A bidirectional DCDC power conversion circuit, characterized in that, it includes a full-bridge rectifier circuit, a transformer, a first diode, a second diode, a first capacitor, a first inductor and a switch circuit; The positive electrode of the first diode is connected to the negative electrode of the second diode; The first end of the full-bridge rectifier circuit is respectively connected to the positive electrode of the preset first input / output terminal and the negative electrode of the first diode, the second end is respectively connected to the negative electrode of the preset first input / output terminal and the positive electrode of the second diode, the third end is connected to one end of the first capacitor, and the fourth end is connected to one end of the first inductor; The other end of the first capacitor is connected to the first end of the transformer; The other end of the first inductor is connected to the second end of the transformer; The primary tap of the transformer is connected to the positive electrode of the first diode; The third end of the transformer is connected to the first input / output terminal of the switch circuit, and the fourth end is connected to the second input / output terminal of the switch circuit; It further includes a logic control circuit; The logic control circuit includes a first logic circuit and a second logic circuit; The full-bridge rectifier circuit includes a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; The drain of the first MOS tube is connected to the drain of the third MOS tube; The source of the second MOS tube is connected to the source of the fourth MOS tube; The source of the first MOS tube is connected to the drain of the second MOS tube; The source of the third MOS tube is connected to the drain of the fourth MOS tube; The drain of the first MOS tube is respectively connected to the positive electrode of the preset first input / output terminal and the negative electrode of the first diode; The source of the second MOS tube is respectively connected to the negative electrode of the preset first input / output terminal and the positive electrode of the second diode; The one end of the first capacitor is connected to the source of the first MOS tube; The one end of the first inductor is connected to the source of the third MOS tube; The input terminals of the first logic circuit are respectively connected to the gates of the first MOS tube and the fourth MOS tube, and the output terminal is connected to the first control terminal of the switch circuit; The input terminals of the second logic circuit are respectively connected to the gates of the second MOS tube and the third MOS tube, and the output terminal is connected to the second control terminal of the switch circuit; It further includes an enable control circuit; The output terminals of the enable control circuit are respectively connected to the input terminals of the first logic circuit and the second logic circuit; The first logic circuit includes a first AND circuit, a first OR circuit, a second AND circuit and a second OR circuit; The first input terminal of the first OR circuit is connected to the gate of the first MOS tube, the second input terminal is connected to the gate of the fourth MOS tube, and the output terminal is connected to the first input terminal of the second AND circuit; The second input terminal of the second AND circuit is connected to the output terminal of the enable control circuit; The first input terminal of the first AND circuit is connected to the gate of the first MOS tube, the second input terminal is connected to the gate of the fourth MOS tube, and the output terminal is connected to the first input terminal of the second OR circuit; The second input terminal of the second OR circuit is connected to the output terminal of the second AND circuit, and the output terminal is connected to the first control terminal of the switch circuit; The second logic circuit includes a third AND circuit, a third OR circuit, a fourth AND circuit, and a fourth OR circuit; The first input terminal of the third OR circuit is connected to the gate of the second MOS transistor, the second input terminal is connected to the gate of the third MOS transistor, and the output terminal is connected to the first input terminal of the fourth AND circuit; The second input terminal of the fourth AND circuit is connected to the output terminal of the enable control circuit; The first input terminal of the third AND circuit is connected to the gate of the second MOS transistor, the second input terminal is connected to the gate of the third MOS transistor, and the output terminal is connected to the first input terminal of the fourth OR circuit; The second input terminal of the fourth OR circuit is connected to the output terminal of the fourth AND circuit, and the output terminal is connected to the second control terminal of the switch circuit; It further includes a second inductor and a second capacitor; The positive poles of the second input / output terminals are respectively connected to one end of the second capacitor and one end of the second inductor; The negative pole of the second input / output terminal is connected to the other end of the second capacitor; The other end of the second inductor is connected to the switch circuit; According to the relationship of driving lead-lag, the first MOS transistor is defined as the leading upper bridge arm, the second MOS transistor is defined as the leading lower bridge arm, the third MOS transistor is defined as the lagging upper bridge arm, and the fourth MOS transistor is defined as the lagging lower bridge arm; the signal at the output terminal of the enable control circuit is set as EN; the current of the second inductor is set as iL2; during forward operation, after determining the effective duty cycle according to the leading bridge arm and the lagging bridge arm, when the load is in a light-load working state, if sampling determines that iL2 is discontinuous current, then the AND logic synchronous rectification strategy is adopted and EN is set to 0; when the load is in a heavy-load working state, if sampling determines that iL2 is continuous current, then the OR logic synchronous rectification is adopted and EN is set to 1; during reverse operation, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor do not control the rectification operation, and the fifth MOS transistor and the sixth MOS transistor are used as the main control switches of the circuit type push-pull topology, and they work in a working mode with a duty cycle D>0.5, and the effective duty cycle is: 2D - 1.

2. A bidirectional DCDC power conversion circuit according to claim 1, characterized in that the switch circuit includes a fifth MOS transistor and a sixth MOS transistor; The secondary tap of the transformer is connected to the other end of the second inductor; The third terminal of the transformer is connected to the drain of the fifth MOS transistor, and the fourth terminal is connected to the drain of the sixth MOS transistor; The negative poles of the second input / output terminals are respectively connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor.

3. A bidirectional DCDC power conversion circuit according to claim 1, characterized in that the switch circuit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor; The third terminal of the transformer is respectively connected to the source of the seventh MOS transistor and the drain of the eighth MOS transistor; The fourth terminal of the transformer is respectively connected to the source electrode of the ninth MOS transistor and the drain electrode of the tenth MOS transistor; The other end of the second inductor is respectively connected to the drain electrode of the seventh MOS transistor and the drain electrode of the ninth MOS transistor; The negative electrode of the second input / output terminal is respectively connected to the source electrode of the eighth MOS transistor and the source electrode of the tenth MOS transistor.

4. A bidirectional DCDC power conversion circuit according to claim 1, characterized in that the primary tap of the transformer has multiple sub-taps; the sub-taps are used for connecting to the positive electrode of the first diode.

5. A bidirectional DCDC power conversion circuit according to claim 1, characterized in that The third terminal of the full-bridge rectifier circuit is connected to one end of the first capacitor, the fourth terminal is connected to one end of the first inductor, the other end of the first capacitor is connected to the first terminal of the transformer, and the other end of the first inductor is connected to the second terminal of the transformer is replaced with: The third terminal of the full-bridge rectifier circuit is connected to one end of the first inductor, and the fourth terminal is connected to one end of the first capacitor; The other end of the first capacitor is connected to the second terminal of the transformer; The other end of the first inductor is connected to the first terminal of the transformer.

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