Array substrate and its preparation process, display panel and display device

Abstract

The present invention relates to the field of display technology, and in particular, to an array substrate and a preparation process thereof, a display panel and a display device. The array substrate includes a via area and a lapped metal wire, wherein at least two via areas are provided and first via holes are formed in each of the via areas, and the two ends of the lapped metal wire extend into the first via holes in the two via areas respectively, and the via area includes a base substrate, a common electrode, a gate insulating layer, a first active layer, a passivation layer and a pixel electrode stacked in sequence in the thickness direction of the array substrate, and the lapped metal wire is located between the active layer and the passivation layer. The array substrate has a simple structure and is easy to implement. Without increasing the production process and cost, the film thickness of the via area can be increased, the distance between the lapped metal wire and the common electrode can be increased, and the facing area of ​​the two at the hole can be reduced, which effectively solves the problem of abnormal discharge in the via and improves the yield of the product.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation process thereof, a display panel and a display device. Background Art

[0002] With the progress of the TFT industry and the improvement of technology, liquid crystal displays have developed rapidly. As a mode of TFT-LCD display area structure, ADS has the advantages of wide viewing angle, high aperture ratio, low color difference, and low response time, and has been applied to more and more products, including mobile phones, computers, and LCD TVs. Usually, the ADS array generally uses a gate metal layer to make a common electrode line, a transparent conductive layer as a common electrode, and connects the common electrodes on both sides of the gate electrode line through overlapping vias (COM holes) set in the pixel area and overlapping metal lines.

[0003] In the existing ADS array substrate, the overlapping metal wire and the common electrode have an overlapping area. The photoresist is exposed and developed on the passivation layer to form an opening in the area above the common electrode containing the overlapping area, and then etched to form a COM hole. Due to the influence of dry chemical etching, the insulating layer in the area where one end of the overlapping metal wire faces the common electrode is etched away, resulting in a hole underneath. At the same time, the vertical distance between the overlapping metal wire and the common electrode is only the thickness of the insulating layer, and the spacing is small, which can easily cause abnormal discharge between the overlapping metal wire and the common electrode, causing large-scale burning of the device. In addition, the pixel density of 8K high-definition display products is large, there are many COM holes, and the yield loss is serious. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, embodiments of the present invention provide an array substrate and a preparation process thereof, a display panel and a display device.

[0005] In order to achieve the above objective, according to a first aspect of an embodiment of the present invention, an array substrate is provided.

[0006] According to an embodiment of the present invention, the array substrate comprises a via area and a lap metal wire, wherein at least two via areas are provided and first via holes are formed in each of the via areas, and both ends of the lap metal wire extend into the first via holes in the two via areas respectively, and the via area comprises a base substrate, a common electrode, a gate insulating layer, a first active layer and a passivation layer stacked in sequence in the thickness direction of the array substrate, and the lap metal wire is located between the first active layer and the passivation layer.

[0007] Furthermore, the thickness of the gate insulating layer is

[0008] Furthermore, the thickness of the first active layer is

[0009] Furthermore, the array substrate further comprises a gate electrode line, the gate electrode line divides the common electrode into two parts, the via regions are distributed on both sides of the gate electrode, and the lap metal line is used to connect the via regions distributed on both sides of the gate electrode line.

[0010] Furthermore, the first via hole is filled with a conductive medium to achieve electrical connection between the bonding metal wire and the common electrode.

[0011] Furthermore, the array substrate further comprises a common electrode line, and the common electrodes located on the same side of the gate electrode line are connected in series through the common electrode line.

[0012] Furthermore, the array substrate further includes a second active layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to the second active layer.

[0013] Furthermore, the array substrate further includes a pixel electrode and a data line, the source electrode is electrically connected to the data line, and the drain electrode is electrically connected to the pixel electrode.

[0014] In order to achieve the above objective, according to a second aspect of an embodiment of the present invention, a display panel is provided, which includes the array substrate provided by the first aspect of the embodiment of the present invention.

[0015] In order to achieve the above objective, according to a third aspect of an embodiment of the present invention, a display device is provided, which includes the display panel provided by the second aspect of the embodiment of the present invention.

[0016] In order to achieve the above-mentioned purpose, according to a fourth aspect of an embodiment of the present invention, a process for preparing an array substrate is further provided, which is used to prepare the array substrate provided by the first aspect of the embodiment of the present invention.

[0017] The manufacturing process of the array substrate according to the embodiment of the present invention comprises the following steps:

[0018] The common electrode and the gate insulating layer are sequentially formed on a base substrate;

[0019] forming an active layer on the gate insulating layer, retaining the active layer in the via region through exposure and development processes, and forming the first active layer;

[0020] forming a bonding metal line with two ends respectively located above the two first active layers;

[0021] A passivation layer is formed to cover the bonding metal line and the first active layer, and the first via hole is formed in the via hole region.

[0022] The array substrate provided by the embodiment of the present invention has a simple structure and is easy to implement. Without increasing the production process and cost, the film thickness in the via area can be increased, the distance between the overlapping metal wire and the common electrode can be increased, and the facing area between the two at the hole can be reduced, thereby effectively solving the problem of abnormal discharge in the via and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention, so that other features, purposes and advantages of the present invention become more obvious. The accompanying drawings of the exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0024] Figure 1 A schematic diagram of the structure of an array substrate and a partial enlarged diagram thereof are shown in an embodiment of the present invention;

[0025] Figure 2 for Figure 1 AA′ structure cross-sectional view in the middle (after removing the pixel electrode);

[0026] Figure 3 A structural schematic diagram of another array substrate provided by an embodiment of the present invention and a partial enlarged diagram thereof;

[0027] Figure 4 for Figure 3 BB′ structure cross-sectional view (after removing the pixel electrode); and

[0028] Figure 5 for Figure 3 The schematic diagram of the semi-finished structure of the array substrate during the preparation process is shown.

[0029] In the figure:

[0030] 1. Base substrate; 2. Gate electrode line; 3. Common electrode line; 4. Common electrode; 5. Gate insulating layer; 6. Active layer; 7. Data line; 8. Source electrode; 9. Drain electrode; 10. Passivation layer; 11. Pixel electrode; 12. First via hole; 13. Overlap metal line; 14. Active area; 15. Via area; 16. Overlap area; 17. First active layer; 18. Second active layer; 19. Second via hole. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] In the present invention, the directions or positional relationships indicated by the terms "upper", "lower", "inner", "middle", "outer", "front", "back" and the like are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0034] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0035] In addition, the terms "disposed", "connected" and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In some figures, for the convenience of explanation, the thickness of the layer and the area of ​​the region are magnified, and the size shown does not represent the actual size. Although these figures do not completely and accurately reflect the actual size of the device, they still fully reflect the relative positions between the regions and the component structures, especially the upper and lower and adjacent relationships between the component structures. The reference figures are schematic diagrams of idealized embodiments of the present invention, and the embodiments shown in the present invention should not be considered to be limited to the specific shapes of the regions shown in the figures, but include the resulting shapes, and should take into account the deviations caused by manufacturing. At the same time, in the following description, the term substrate substrate used can be understood to include a semiconductor or glass substrate that is being processed, and may include other thin film layers prepared thereon.

[0037] like Figure 1 and 2 An array substrate shown in the figure includes a base substrate 1, a gate electrode line 2, a common electrode line 3, a common electrode 4, a gate insulating layer 5, an active layer 6, a data line 7, a source electrode 8, a drain electrode 9, a passivation layer 10, a pixel electrode 11, a first via hole 12 and a bonding metal line 13, wherein the common electrode line 3 is made of a gate metal layer, the common electrode 4 is formed of a transparent conductive layer, and the common electrodes 4 on both sides of the gate electrode line 2 are connected through the first via hole 12 and the bonding metal line 13 arranged in the pixel area. Figure 2 As shown, the lap metal wire 13 and the common electrode 4 have an overlap area 16. By exposing and developing the photoresist on the passivation layer 10, an opening can be formed in the area above the common electrode 4 including the overlap area 16, and then the first via hole 12 is etched. Due to the influence of dry chemical etching, the gate insulating layer 5 in the area where one end of the lap metal wire 13 is directly opposite to the common electrode 4 will be etched away, resulting in a hole below the end of the lap metal wire 13, and the subsequent conductive medium filling process still cannot eliminate the hole. At the same time, the vertical distance between the lap metal wire 13 and the common electrode 4 is only the thickness of the gate insulating layer 5, and the spacing is small, which can easily cause abnormal discharge between the lap metal wire 13 and the common electrode 4, causing large-area burning and serious yield loss.

[0038] In order to further Figure 1 and Figure 2 By improving the array substrate in the Figure 3-5An improved array substrate structure is shown. As shown in the figure, the array substrate includes a via area 15 and a lap metal wire 13, at least two via areas 15 are provided and a first via 12 is formed in each of the via areas 15, two ends of the lap metal wire 13 extend into the first vias 12 in the two via areas 15 respectively, the via area 15 includes a base substrate 1, a common electrode 4, a gate insulating layer 5, a first active layer 17 and a passivation layer 10 which are stacked in sequence in the thickness direction of the array substrate, and the lap metal wire 13 is located between the active layer and the passivation layer 10.

[0039] In the above embodiment, the array substrate has a simple structure, and has a two-layer film structure of a gate insulating layer 5 and a first active layer 17 between the overlapping metal wire 13 and the common electrode 4, thereby increasing the film thickness of the via area 15 and increasing the distance between the overlapping metal wire 13 and the common electrode 4. As a result, when the first via 12 is formed by dry etching, a relatively small facing area can be obtained between the end of the overlapping metal wire 13 and the common electrode 4, thereby effectively solving the problem of abnormal discharge that is prone to occur at the first via 12 and improving the yield of the product.

[0040] Based on the above embodiment, the thickness of the gate insulating layer 5 is preferably The thickness of the first active layer 17 is preferably In this way, the distance between the bonding metal line 13 and the common electrode 4 can be The technicians found through testing that within the above distance range, the abnormal discharge phenomenon between the overlapping metal wire 13 and the common electrode 4 can be eliminated.

[0041] In some embodiments, the array substrate also includes a gate electrode line 2 and a common electrode line 3, the gate electrode line 2 separates the common electrode 4 into two parts, the via area 15 is distributed on both sides of the gate electrode, and the overlapping metal wire 13 is used to connect the via areas 15 distributed on both sides of the gate electrode line 2, and is connected in series between the common electrodes 4 on the same side of the gate electrode line 2 through the common electrode line 3.

[0042] In some embodiments, the first via hole 12 is filled with a conductive medium to achieve electrical connection between the bonding metal wire 13 and the common electrode 4 .

[0043] In some embodiments, the array substrate also includes a second active layer 18, a source electrode 8 and a drain electrode 9, a pixel electrode 11 and a data line 7, the source electrode 8 and the drain electrode 9 are connected to the second active layer 18, the source electrode 8 is electrically connected to the data line 7, and the drain electrode 9 is electrically connected to the pixel electrode 11.

[0044] According to the above embodiment, the array substrate may further include other necessary components or structures, and the corresponding arrangement positions and connection relationships may refer to the array substrate in the prior art. The connection relationships, operations and working principles of the structures not described are known to ordinary technicians in the field and will not be described in detail here.

[0045] The embodiment of the present invention also provides an optional array substrate preparation process correspondingly, which is used to prepare the array substrate of the above embodiment. The array substrate preparation process includes the following steps.

[0046] Step 1: The common electrode 4 and the gate insulating layer 5 are sequentially formed on a base substrate 1 .

[0047] First, a substrate 1 is provided. The substrate 1 can be a substrate 1 based on inorganic materials such as a glass substrate and a quartz substrate, or a substrate 1 using organic materials. A conductive film is deposited on the substrate. The material of the conductive film can be indium tin oxide (ITO), indium zinc oxide (IZO, Indium Zinc Oxide), etc. Then, photoresist is coated on the conductive film, and the photoresist is exposed and developed using a mask to form a photoresist pattern including a photoresist completely retained area and a photoresist completely stripped area. The photoresist completely retained area corresponds to the pattern of the common electrode 4, the gate electrode line 2, the common electrode line 3, etc. The common electrode 4, the gate electrode line 2, the common electrode line 3, etc. are formed by etching the conductive film in the photoresist completely stripped area. After stripping the photoresist in the photoresist completely retained area, a gate insulating layer 5 is deposited.

[0048] Step 2: forming an active layer on the gate insulating layer 5 , retaining the active layer in the via region 15 through exposure and development processes, and forming the first active layer 17 .

[0049] A semiconductor layer film, i.e., an active layer, is deposited on the structure formed in step 1, and photoresist is coated on the semiconductor layer film. The photoresist is exposed and developed using a mask to form a photoresist pattern including a photoresist completely retained area and a photoresist completely stripped area. The semiconductor layer film in the photoresist completely stripped area is etched to form a pattern including a via area 15. Finally, the photoresist in the photoresist completely retained area is stripped to obtain a semiconductor film retained in the via area 15, i.e., the first active layer 17.

[0050] It should be noted that the photoresist completely retained area in this step may also include an active area 14. Part of the semiconductor film in the active area 14 is retained to form a second active layer 18. Based on the second active layer 18, a source electrode 8 and a drain electrode 9 can be further configured to form a complete active area 14. The preparation process of the source electrode 8 and the drain electrode 9 is applicable to the existing technology and will not be repeated here.

[0051] In this step, the material of the active layer is preferably an oxide semiconductor material, including but not limited to one of oxide semiconductor materials such as In-Ga-Zn-O, In-Ga-O, Ga-Zn-O, In-Hf-Zn-O, In-Sn-Zn-O, In-Sn-O, In-Zn-O, Zn-Sn-O and In-Al-Zn-O.

[0052] Step 3: forming a bonding metal wire 13 with two ends respectively located above the two first active layers 17;

[0053] A metal layer is formed on the structure formed in step 2, and various metal lines are formed through further masking process, including at least overlapping metal lines 13. In this step, metal lines in other areas can also be formed at the same time, such as metal lines at the channels, etc. Those skilled in the art can design corresponding patterns as needed.

[0054] Step 4: forming a passivation layer 10 covering the bonding metal wire 13 and the first active layer 17, and forming the first via hole 12 in the via hole area 15. In this step, the passivation layer 10 is a whole insulating protective layer formed on the top of the structure formed in step 3. The material for forming the passivation layer 10 can be SiO x 、SiN x and SiNO x By performing exposure and development processes on the photoresist on the passivation layer 10 , the first via hole 12 in the via hole area 15 can be obtained, and of course, the second via hole 19 can also be formed near the active area 14 .

[0055] Step 5: A whole layer of conductive medium is formed on the structure formed in step 4 as the pixel electrode 11, and in this step, the conductive material will fill the first via hole 12 and the second via hole 19. The conductive medium filled in the first via hole 12 is used to realize the electrical connection between the common electrode 4 and the lapped metal line 13, thereby realizing the electrical connection between the common electrodes 4 on both sides of the gate electrode line 2; the conductive medium filled in the second via hole 19 can be used to realize the electrical connection between the metal line in the channel and the pixel electrode 11. Among them, the conductive medium is preferably ITO.

[0056] It should be noted that the formation of the thin film involved in the above embodiments is described by taking deposition as an example, but it is not a limitation on the implementation method of the present invention. The formation of the thin film involved in the above embodiments may include but is not limited to deposition, coating, sputtering, printing and other methods; the patterning process involved includes but is not limited to coating photoresist, sputtering, evaporation, exposure and development, etching, ashing and removal of photoresist and other operations.

[0057] The above is an exemplary description and illustration of the array substrate and its preparation method according to the embodiment of the present invention. Other structures of the array substrate and other operations of its preparation method are known to ordinary technicians in the field and will not be described in detail here. Those skilled in the art can refer to the records of the prior art for understanding and application.

[0058] The embodiment of the present invention further provides a display panel, which includes the array substrate provided by the above embodiment of the present invention. Since the display panel disclosed in the embodiment of the present invention includes the array substrate provided by the above embodiment, the display panel having the array substrate also has all the above technical effects, which will not be described one by one here.

[0059] The embodiment of the present invention further provides a display device, which includes the display panel provided by the above embodiment of the present invention. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator. Since the display device disclosed in the embodiment of the present invention includes the display panel provided by the above embodiment, the display device having the display panel also has all the above technical effects, which will not be described one by one here.

[0060] Other structures, principles and manufacturing methods of the display panel and the display device are known to those skilled in the art and will not be described in detail here.

[0061] Some embodiments in this specification are described in a progressive or parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0062] The above is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features invented herein.

Claims

1. An array substrate, characterized in that: The array substrate includes a via region and a lap metal line, wherein at least two via regions are provided and each of the via regions has a first via hole formed therein, and two ends of the lap metal line extend into the first via holes in the two via regions respectively, and the via region includes a base substrate, a common electrode, a gate insulating layer, a first active layer and a passivation layer stacked in sequence in the thickness direction of the array substrate, and the lap metal line is located between the first active layer and the passivation layer; The thickness of the gate insulating layer is The thickness of the first active layer is 2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a gate electrode line, which divides the common electrode into two parts. The via regions are distributed on both sides of the gate electrode line. The lap metal line is used to connect the via regions distributed on both sides of the gate electrode line.

3. The array substrate according to claim 1, characterized in that: The first via hole is filled with a conductive medium for realizing electrical connection between the bonding metal wire and the common electrode.

4. The array substrate according to claim 2, characterized in that: The array substrate further comprises a common electrode line, and common electrodes located on the same side of the gate electrode line are connected in series through the common electrode line.

5. The array substrate according to claim 1, characterized in that: The array substrate further includes a second active layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are connected to the second active layer.

6. The array substrate according to claim 5, characterized in that: The array substrate further includes a pixel electrode and a data line. The source electrode is electrically connected to the data line, and the drain electrode is electrically connected to the pixel electrode.

7. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 6.

8. A display device, characterized in that: Comprising the display panel as claimed in claim 7.

9. A process for preparing an array substrate, used for preparing the array substrate according to any one of claims 1 to 6, characterized in that: The following steps are involved: The common electrode and the gate insulating layer are sequentially formed on a base substrate; forming an active layer on the gate insulating layer, retaining the active layer in the via region through exposure and development processes, and forming the first active layer; forming a bonding metal line with two ends respectively located above the two first active layers; A passivation layer is formed to cover the bonding metal line and the first active layer, and the first via hole is formed in the via hole region.

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