Flexible power sequencing for dual-power memory

Abstract

A dual-power domain SRAM is disclosed in which the dual power domains can be powered up or down in any desired order. For example, the (CX) power domain can be powered up first, followed by the memory (MX) power domain. Conversely, the MX power domain can be powered up before the CX domain.

Description

[0001] Priority claim under 35 U.S.C. § 119

[0002] This patent application claims priority to non-provisional application No. 16 / 164,108, filed on October 18, 2018, entitled “FLEXIBLE POWER SEQUENCING FOR DUAL-POWER MEMORY,” which is assigned to the present assignee and is hereby expressly incorporated herein by reference. Technical Field

[0003] The present application relates to dual power memories, and more particularly to flexible power sequencing of dual power memories. Background Art

[0004] The dual power supply memory has two power domains: a memory power domain that is powered by a memory power supply voltage, and a core power domain that is powered by a core power supply voltage. If the dual power memory is embedded in a system on a chip (SoC), the core power supply voltage can also be shared by the processor cores within the SoC. Typically, in addition to the bit cells, the memory also requires various peripheral digital circuits such as an address decoder, a clock, and a write driver. Therefore, the memory power domain includes not only the bit cells, but also a portion of the peripheral digital circuits. The core power domain includes the rest of the peripheral digital circuits (which can also be represented as peripheral logic) for the dual power memory.

[0005] Including two separate power domains in a dual-power memory increases efficiency by supporting both a retention sleep mode and a non-retention sleep mode. In retention sleep mode, the peripheral logic in both power domains is disconnected, but the bit cells are still powered so that they can retain their stored data. In non-retention sleep mode, even the bit cells are powered off so that no stored data is retained. Retention sleep mode advantageously conserves power by cutting off leakage losses in the peripheral logic during quiescent periods for the dual-power memory while still retaining stored data.

[0006] While dual power memory is thus advantageously low power, the separate power domains require fixed sequencing during power up and power down. For example, the memory power domain may always be powered up first (and therefore powered down last). Figure 1An example conventional dual-power memory 100 with such fixed power-on sequencing is shown in FIG. The memory includes a memory power (MX) domain 105 powered by a memory power supply voltage VDDMX and a core power (CX) domain 110 powered by a core power supply voltage VDDCX. MX power domain 105 includes a plurality of bit cells 115 and MX peripheral logic 120, while CX power domain 110 includes CX peripheral logic 160. When MX power domain 105 is powered on, an MX clamp signal is asserted, which is used to isolate MX peripheral devices 120 from the memory power supply voltage VDDMX by turning off a header switch, such as a p-type metal oxide semiconductor (PMOS) transistor P1. Once dual-power memory 100 is fully powered on and in normal operating mode, it can exit normal operation by entering a sleep retention mode in response to assertion of a sleep retention signal in CX power domain 110. In sleep retention mode, header switch transistor P1 is turned off to isolate MX peripheral logic 120. Similarly, during the sleep retention mode, the CX peripheral logic 160 is also isolated from the core power supply voltage VDDCX by turning off the header switch (such as PMOS transistor P3).

[0007] To enable header switch transistors P1 and P3 to turn off in response to assertion of either the MX clamp signal or the sleep hold signal, the sleep hold signal is level-shifted by level shifter (LS) 135 and mixed with the MX clamp signal in MX domain NOR gate 125. Therefore, when either the MX clamp signal or the sleep hold signal is asserted, the output of NOR gate 125 goes low. The output of NOR gate 125 is level-shifted by level shifter 135 in the CX power domain 150 and then inverted by inverter 150 to drive header switch transistor P3. Consequently, header switch transistor P3 turns off in response to assertion of either the MX clamp signal or the sleep hold signal. The output of NOR gate 125 is also inverted by MX domain inverter 130 to drive the gate of header switch transistor P1. Therefore, when either the MX clamp signal or the sleep hold signal is asserted, MX peripheral logic 120 is isolated from the memory power supply voltage.

[0008] Assertion of the sleep non-retentive signal in the CX power domain 110 controls whether the sleep non-retentive mode is active. The sleep non-retentive signal is level-shifted by level shifter 130 to drive the gate of the PMOS header switch transistor P2, disconnecting the bit cell 115 from the memory power supply voltage VDDMX. However, during the assertion of the MX clamp signal, it is desirable that the current state of the header switch transistor P2 be maintained, so that the level shifter 130 also functions as a latch. To prevent the sleep non-retentive signal from affecting the state of the latch, assertion of the MX clamp signal is used to isolate the sleep non-retentive signal from the level shifter / latch 130 through logic circuit 130.

[0009] As long as the MX power domain 105 is powered on before the CX power domain 110, the dual-power memory 100 will operate properly. However, it is difficult for all designs to always meet this strict power-on sequencing. Therefore, for some embodiments, it is possible that the CX power domain 110 is the first power domain to be powered on. However, since the MX power domain 105 is not powered on during the power-up of the CX power domain 110, the output of the NOR gate 125 is unknown, making the output of the level shifter 145 also unknown. Therefore, it is possible that the head switch transistor P3 is turned on when the CX power domain 110 is powered on. However, it is noted that the CX peripheral logic domain 160 will include many level shifters (not shown) to level shift the various signals that the CX peripheral logic domain 160 receives from the MX peripheral logic 120. Since the inputs to these level shifters are unknown, the output signals of these level shifters are also unknown, so that a substantial portion of these level shifter output signals may be charged up to the core power supply voltage VDDCX and thereby turn on the internal CX domain switch (not shown), resulting in substantial power consumption during startup of the dual power memory 100.

[0010] Therefore, there is a need in the art for a dual power memory with flexible power-on sequencing with reduced power consumption. Summary of the Invention

[0011] A dual-power SRAM includes a memory (MX) power domain and a core (CX) power domain. The MX power domain is powered by the memory power supply voltage, while the CX power domain is powered by the core power supply voltage. These dual power domains can be powered on or off in any desired order. To provide this advantageous power sequencing, the dual-power memory includes a sequencing controller that asserts an MX clamp signal when the MX power domain is powered on (or off). Similarly, the sequencing controller asserts a CX clamp signal when the CX power domain is powered on (or off). The dual-power supply memory includes a logic circuit device that is configured to respond to the assertion of either the MX clamp signal or the CX clamp signal by isolating peripheral logic in the MX domain and peripheral logic in the CX domain from their respective power supply rails.

[0012] These and other advantageous features will be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram of a conventional dual-power memory.

[0014] Figure 2 is a diagram of a dual power memory with flexible power-on and power-off sequences according to one aspect of the present disclosure.

[0015] Figure 3 yes Figure 2 FIG. 1 is a diagram of a first level shifter and latch in a dual power memory, and associated logic.

[0016] Figure 4 yes Figure 2 FIG. 1 is a diagram of a second level shifter in a dual power memory and associated logic.

[0017] Figure 5 yes Figure 3 Circuit diagram of the level shifter and latch.

[0018] Figure 6 is a flow chart of power-on sequencing for dual-power memory according to one aspect of the present disclosure.

[0019] Embodiments of the present disclosure and their advantages will be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0020] A dual power supply memory is disclosed in which power domains can be powered up or down in any order desired. Figure 2An example dual-power memory 200 configured for such flexible power sequencing is shown in FIG. Dual-power memory 200 includes a memory (MX) power domain 205 and a core (CX) power domain 210. A memory power supply voltage VDDMX supplies power to MX power domain 205, while a core power supply voltage VDDCX supplies power to CX power domain 210. Dual-power memory 200 shares many features with the previously described dual-power memory 100. For example, MX power domain 105 includes a plurality of bit cells 115 and also includes MX peripheral logic 120, while CX power domain 110 includes CX peripheral logic 160. Furthermore, MX peripheral logic 120 is connected to the MX power rail for memory power supply voltage VDDMX via a PMOS header switch transistor P1 (it should be understood that the header switch transistor disclosed herein may include multiple header switch transistors arranged in parallel). Similarly, CX peripheral logic 160 is connected to the CX power rail for core power supply voltage VDDCX through PMOS header switch transistor P3, while bit cell 115 is coupled to the MX power rail through PMOS header switch transistor P2.

[0021] The power sequencing controller 201 controls the power-on and power-off sequencing of the MX power domain 205 and the CX power domain 210, allowing either power domain to be sequenced on or off before the other in any order desired by a particular implementation. Specifically, the controller 201 asserts the MX clamp signal when the MX power domain 205 is powered on or off. Similarly, the controller 201 asserts the CX clamp signal when the CX power domain 210 is powered on or off. These signals are referred to as "clamp" signals because the dual-power memory is configured to respond to the assertion of these clamp signals by turning off header switch transistors P1 and P3, isolating the MX peripheral logic 120 and the CX peripheral logic 160 from their respective power rails. As discussed with respect to the dual-power memory 100, these peripheral logic circuits include various peripheral components required for the operation of the dual-power memory 200, such as row and column address decoders, clocks, write drivers, and sense amplifiers. In an embodiment of a static random access memory (SRAM), each bit cell 115 includes a pair of cross-coupled inverters. In the following discussion, it will be assumed that the dual power memory 200 is a dual power SRAM, but it should be understood that the techniques and circuits disclosed herein can be applied to any suitable type of memory, such as dynamic random access memory (DRAM).

[0022] To conserve power, the dual power memory 200 is configured to implement a sleep mode with retention and also a sleep mode with no retention. During the sleep mode with retention, the head switch transistors P1 and P3 are turned off to isolate the MX peripheral logic 120 and the CX peripheral logic 160 from their power rails. However, the head switch transistors P1 and P3 should also be turned off in response to the assertion of the MX clamp signal or the assertion of the CX clamp signal. As used herein, a signal is said to be "asserted" when it is charged to the power supply voltage for its power domain. Since the MX clamp signal is an MX power domain signal, the MX clamp signal is considered to be asserted by being charged to the memory power supply voltage VDDX. Similarly, since the CX clamp signal is a CX power domain signal, the CX clamp signal is considered to be asserted by being charged to the core power supply voltage VDDCX.

[0023] To configure dual-power memory 200 so that header switch transistors P1 and P3 are switched during sleep mode with retention and when either the MX or CX clamp signals are asserted, dual-power memory 200 includes logic circuitry 215 that asserts a logic output signal in response to assertion of either the sleep retention signal or the CX clamp signal. The sleep retention signal is a CX power domain signal that is asserted during sleep retention mode. As discussed with respect to dual-power memory 100, bit cells 115 retain their contents during sleep retention mode. However, during sleep retention mode, MX peripheral logic circuitry 120 and CX peripheral logic circuitry 160 are disconnected because these circuits are isolated from their respective power rails by the disconnection of header switch transistors P1 and P3. In this way, by cutting off leakage from MX peripheral logic circuitry 120 and CX peripheral logic circuitry 160, the dual-power memory conserves power, saving power during sleep retention mode.

[0024] The logic output signal from logic circuit 215 (if asserted) is level-shifted from the core power supply voltage VDDCX to the memory power supply voltage VDDMX by MX-to-CX level shifter (LS) 230 in MX power domain 205. Note that level shifter 230 can be a differential level shifter that level-shifts the input signal and its complement. For this differential level shifting, an embodiment of logic circuit 215 is further described herein, which generates the corresponding output signal and its complement. Since MX power domain 205 can be powered before CX power domain 210, the input to level shifter 230 is unknown in this case. Therefore, level shifter 230 is connected to the MX power rail via a PMOS header switch transistor P4. The MX clamp signal drives the gate of header switch transistor P4, causing it to turn off in response to assertion of the MX clamp signal. Therefore, when the MX clamp signal is asserted, level shifter 230 is disconnected from the memory power supply voltage VDDMX. The NOR gate 125 processes the level-shifted output signal from the level shifter 230 using the MX clamp signal. In response to assertion of any input signal to the NOR gate 125, the output of the NOR gate 125 is discharged to ground. Therefore, in response to assertion of the sleep hold signal, assertion of the MX clamp signal, or assertion of the CX clamp signal, the output of the NOR gate 125 will be discharged to ground.

[0025] The output of NOR gate 125 is level-shifted by MX-to-CX level shifter 225. The level-shifted output signal from level shifter 225 is then inverted by inverter 150 to drive the gate of header switch transistor P3. It will be appreciated that in differential embodiments, level shifter 225 can be configured to respond to both true and false input signals. In such embodiments, level shifter 225 processes the output of NOR gate 125 and the complement of the output of NOR gate 125 to produce its level-shifted output signal. Note that CX power domain 210 can be powered on before MX power domain 205. In this case, the output of NOR gate 125 would be unknown. Therefore, level shifter 225 is connected to the CX power rail via PMOS header switch transistor P5. The CX clamp signal drives the gate of header switch transistor P5, causing header switch transistor P5 to be turned off when the CX clamp signal is asserted. To ensure that header switch transistor P3 is turned off when the CX clamp signal is asserted, the output of level shifter 225 is coupled to ground via an n-type metal oxide semiconductor (NMOS) switch or grounding transistor M7. The CX clamp signal drives the gate of switch transistor M7 so that the input to inverter 150 is grounded when the CX clamp signal is asserted. In this way, header switch transistor P3 is ensured to be turned off when the CX clamp signal is asserted. In one embodiment, logic circuit 215, level shifter 230, NOR gate 125, and level shifter 225 are considered to form a component for turning off the first header switch (transistor P1) and the second header switch (transistor P2) in response to assertion of the CX clamp signal or the MX clamp signal, and turning on the first and second header switches in response to deassertion of the MX clamp signal and the CX clamp signal.

[0026] During sleep mode without retention, the head switch transistor P2 is turned off to isolate the bit cell 115 from the MX power rail. When sleep mode without retention is active, the CX domain control signal, designated as the sleep non-hold signal, is asserted. However, during assertion of the MX clamp signal or the CX clamp signal, any current state (open or closed) of the head switch transistor P2 should be maintained so that the head switch transistor P2 does not respond to any changes in the sleep non-hold signal while either of the clamp signals is asserted. To control the head switch transistor P2, the logic circuit 220 processes the sleep non-hold signal and the CX clamp signal to drive the CX-to-MX level shifter and the latch 240, which is also responsive to the MX clamp signal. In some embodiments, as Figure 3As shown in FIG, the CX-to-MX level shifter and latch 240 can respond to both a true input signal (in) and a false or complementary input signal (inb). CX-domain NOR gate 300 and CX-domain NOR gate 305 form logic circuit 220. The CX clamp signal is received as an input signal to both NOR gates 300 and 305. NOR gate 305 also receives the sleep non-holding signal, while NOR gate 300 receives the complement of the sleep non-holding signal as converted by inverter 310. The output of NOR gate 300 forms the in input signal for the CX-to-MX level shifter and latch 240, while the output of NOR gate 305 forms the inb input signal.

[0027] As will be further described herein, if the in and inb input signals are complementary to each other and both clamp signals are deasserted (discharged to ground), the latching function in the CX-to-MX level shifter and latch 240 is configured to be transparent. In the transparent state, the input signal to the CX-to-MX level shifter and latch 240 flows through to form the level-shifted output of the CX-to-MX level shifter and latch 240. In the closed state, the CX-to-MX level shifter and latch 240 does not respond to the input signal, but instead maintains its output signal in whatever state it was in before entering the closed state. If both the CX clamp signal and the MX clamp signal are deasserted (discharged to ground) and the sleep non-hold signal is asserted, the in input signal will be asserted and the inb input signal will be discharged. Thus, the latching function will be transparent, causing the output signal of the CX-to-MX level shifter and latch 240 to be asserted, thereby turning off the header switch transistor P3. If either of the clamp signals is then asserted, the latch function closes to maintain the header switching transistor off. Conversely, if both clamp signals are deasserted, and the sleep non-retentive signal is also deasserted, the inb input signal will be asserted, while the in input signal will be deasserted. The latch function is transparent again, allowing the low state for the in input signal to flow through to turn on the header transistor P3. If either of the clamp signals is then asserted, the latch function closes to latch and maintain the deasserted state of its output signal.

[0028] exist Figure 42 shows in greater detail an embodiment in which the CX-to-MX level shifter 230 processes both a true (in) input signal and a complementary (inb) input signal. NOR gate 400 generates the in input signal, while NOR gate 405 generates the inb input signal. If the sleep hold signal is asserted when the CX clamp signal is deasserted, NOR gate 400 will process two binary zero input signals, causing the in input signal to be asserted. The assertion of the sleep hold signal causes the inb input signal to be deasserted. Assuming the MX clamp signal is also deasserted, the output of the CX-to-MX level shifter 230 will therefore be asserted high, causing both header switch transistors P1 and P3 to be turned off during the sleep hold mode. Conversely, if the sleep hold signal is deasserted when the CX clamp signal is deasserted, the inb input signal will be asserted, while the in input signal will be deasserted. Assuming that the MX clamp signal is also de-asserted to keep the header switch transistor P4 turned on to supply power to the CX-to-MX level shifter 230, the output of the CX-to-MX level shifter 230 is de-asserted. Then, the two header switch transistors P1 and P3 will then be maintained turned on.

[0029] Figure 5 This is shown in more detail in Figure 3 The CX-to-MX level shifter and latch 240 is implemented in a 1.5-μm CMOS process. The in input signal drives the gate of NMOS transistor M1, which has a source connected to ground, while the inb input signal drives the gate of NMOS transistor M2, which also has a source connected to ground. If both the in and inb input signals are deasserted, the latching function for the CX-to-MX level shifter and latch 240 is disabled because no input signal can affect the state of the latch. In the off state, the latch is implemented by an inverter (formed by NMOS transistor M5 and PMOS transistor P6) cross-coupled with another inverter (formed by NMOS transistor M6 and PMOS transistor P9). The source of transistor M5 is connected to ground, while the drain of transistor M5 is connected to the drain of transistor P6. The source of transistor P6 is coupled to the MX power rail via a pair of PMOS transistors P7 and P8 arranged in parallel. The inb input signal drives the gate of transistor P7, while the complement of the MX clamp signal (MX clamp bar) drives the gate of transistor P8. Therefore, if the inb input signal or the MX clamp bar signal is deasserted, the inverter formed by transistors P6 and M5 will be supplied with power. The drains of transistors P6 and M5 form the output node for carrying the output signal from the CX-to-MX level shifter and latch 240.

[0030] To create cross-coupling between the inverters for the latch, the drains of transistors P6 and M5 are connected to the gates of transistors P9 and M6. The source of transistor P9 is coupled to the MX power rail via a pair of PMOS transistors P10 and P11 arranged in parallel. The MX clamp bar signal drives the gate of transistor P10, while the in input signal drives the gate of transistor P11. Therefore, if either the MX clamp bar signal or the in input signal is deasserted, power is supplied to the inverter formed by transistors P9 and M6. The drains of transistors P9 and M6 are connected to the gates of transistors P6 and M5, completing the cross-coupling of the inverters.

[0031] If the MX clamp signal is asserted, the latching function for the CX-to-MX level shifter and latch 240 should be disabled. In this case, to prevent the MX level shifter and latch 240 from responding to the in and inb input signals, the drain of transistor M1 is coupled to the gates of transistors P6 and M5 via NMOS transistor M3. Similarly, the drain of transistor M2 is coupled to the gates of transistors P9 and M6 via NMOS transistor M4. The MX clamp bar signal drives the gates of transistors M3 and M4, preventing the in and inb input signals from affecting the state of the output signal when the MX clamp signal is asserted. Deasserting the MX clamp bar signal turns on both transistors P11 and P8, powering both inverters. In this way, through the cross-coupling of the inverters, the output signal is latched in whatever state it was in before the MX clamp signal was asserted. If the MX clamp signal is de-asserted, both transistors M3 and M4 will be turned on, allowing the MX level shifter and latch 240 to respond to the in and inb input signals. The latch formed by the cross-coupled inverters will be transparent because one of the inverters is powered off depending on the binary state of the in and inb input signals.

[0032] Now about Figure 6A method for operating a dual-power memory with a flexible power-on sequence is discussed with reference to a flowchart of FIG. The method includes an act 600 of asserting a core domain clamp signal during a power-on period for a core power supply domain, where power is supplied by a core power supply voltage in the dual-power memory. The method includes an act 600 of asserting a core domain clamp signal during a power-on period for the core power supply domain, where power is supplied by a core power supply voltage in the dual-power memory. Assertion of the CX clamp signal, as discussed with respect to dual-power memory 200, is an example of act 600. The method also includes an act 605 of asserting a memory domain clamp signal during a power-on period for a memory power supply domain, where power is supplied by a memory power supply voltage in the dual-power memory. Assertion of the MX clamp signal, as discussed with respect to dual-power memory 200, is an example of act 605. Note that there is no implied order for actions 600 and 605; either action can occur before the other. The method also includes an action 610 of isolating peripheral logic in the memory power supply domain from the memory domain voltage rail for the memory power supply voltage in response to assertion of the core domain clamp signal or in response to assertion of the memory domain clamp signal. Turning off header switch transistor P1, as discussed with respect to dual power memory 200, is an example of action 610. Finally, the method includes an action 615 of isolating peripheral logic in the logic power supply domain from the logic domain voltage rail for the logic power supply voltage in response to assertion of the core domain clamp signal or in response to assertion of the memory domain clamp signal. Turning off transistor P3 is an example of action 615. Regardless of which power domain is powered up first, deassertion of the memory domain clamp signal and the core domain clamp signal occurs after completion of the power up sequence.

[0033] It should be understood that many modifications, substitutions, and changes may be made to the materials, devices, configurations, and methods of use of the apparatus of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are merely examples thereof, but rather should be fully commensurate with the scope of the appended claims and their functional equivalents.

Claims

1. A dual power supply memory, comprising: a memory power domain comprising a memory power rail for a memory power supply voltage, a memory peripheral logic circuit device, a first header switch, and a first level shifter, the memory peripheral logic circuit device being coupled to the memory power supply voltage via the first header switch; a core power domain comprising a core power rail for a core power supply voltage, a core peripheral logic circuit device, a second header switch, and a second level shifter, the core peripheral logic circuit device being coupled to the core power rail via the second header switch; as well as a controller configured to assert a memory domain clamp signal during a power-on period for the memory power domain and to assert a core domain clamp signal during a power-on period for the core power domain, wherein the dual power supply memory is configured to turn off the first head switch and the second head switch in response to assertion of the memory domain clamp signal or assertion of the core domain clamp signal, The first level shifter is configured to level-shift the core domain clamp signal into a first level-shifted output signal for influencing the turn-off of the first head switch, and the second level shifter is configured to level-shift the first logic output signal into a second level-shifted output signal for influencing the turn-off of the second head switch.

2. The dual power supply memory according to claim 1 , further comprising: a first logic gate in the memory power domain, configured to process the first level-shifted output signal and the memory domain clamp signal into the first logic output signal; as well as An inverter in the core power domain is configured to convert the second level-shifted output signal into a first inverted signal, wherein the second head switch is a first p-type metal oxide semiconductor (PMOS) transistor having a gate configured to receive the first inverted signal.

3. The dual power supply memory according to claim 2, further comprising: An inverter in the memory power domain is configured to convert the first logic output signal into a second inverted signal, wherein the first head switch is a second PMOS transistor having a gate configured to receive the second inverted signal.

4. The dual power supply memory according to claim 2, further comprising: A third header switch is configured to couple the first level shifter to the memory power rail, wherein the third header switch is configured to turn off in response to the assertion of the memory domain clamp signal.

5. The dual power supply memory of claim 2 , further comprising a grounding switch connected between ground and an output node for the second level shifter, wherein the grounding switch is configured to be turned on in response to the assertion of the core domain clamp signal.

6. The dual power supply memory according to claim 2, further comprising: A sleep retention logic circuit in the core power domain is configured to process the core domain clamp signal using a sleep retention signal, wherein the first level shifter is configured to level shift an output signal from the sleep retention logic circuit to generate the first level-shifted output signal. 7 . The dual power supply memory according to claim 6 , wherein the sleep retention logic circuit comprises a second logic gate and a third logic gate.

8. The dual power supply memory according to claim 7 , wherein the second logic gate is a NOR gate configured to process the core domain clamp signal and an inverted version of the sleep hold signal, and wherein the third logic gate is a NAND gate configured to process the sleep hold signal and the core domain clamp signal.

9. The dual power supply memory according to claim 2, further comprising: a plurality of bit cells in the memory power domain; a third header switch configured to couple the plurality of bit cells to the memory power rail; as well as A third level shifter is configured to level-shift a sleep non-retention signal from the core power domain into a third level-shifted output signal, wherein the third head switch is configured to turn off in response to assertion of the third level-shifted output signal.

10. The dual power supply memory of claim 9, wherein the third level shifter further comprises a latch configured to latch the third level-shifted output signal in response to the assertion of the core domain clamp signal or the memory domain clamp signal.

11. The dual power supply memory according to claim 9, further comprising: The non-retentive logic circuit is configured to process the core domain clamp signal and the sleep non-retentive signal to form a second logic output signal, wherein the third level shifter is configured to level shift the second logic output signal to form the third level-shifted output signal. 12 . The dual power supply memory according to claim 11 , wherein the non-retentive logic circuit comprises a second logic gate and a third logic gate.

13. The dual power supply memory according to claim 12 , wherein the second logic gate is a first NOR gate configured to process the core domain clamp signal and an inverted version of the sleep non-retention signal, and wherein the third logic gate is a second NOR gate configured to process the core domain clamp signal and the sleep non-retention signal.

14. The dual power supply memory of claim 1, wherein the dual power supply memory comprises a dual power supply static random access memory (SRAM).

15. A method for dual power supply memory, comprising: asserting a core domain clamp signal during a power-on period for a core power supply domain, the power-on period for the core power supply domain being supplied power by a core power supply voltage in the dual power supply memory; asserting a memory domain clamp signal during a power-on period for a memory power supply domain, the power-on period for the memory power supply domain being supplied power by a memory power supply voltage in the dual power supply memory; responsive to the assertion of the core domain clamp signal, or responsive to the assertion of the memory domain clamp signal, isolating peripheral logic in the memory power supply domain from a memory domain voltage rail for the memory power supply voltage; as well as responsive to the assertion of the core domain clamp signal, or responsive to the assertion of the memory domain clamp signal, isolating peripheral logic in the core power supply domain from a core domain voltage rail for the core power supply voltage, The memory power supply domain includes a first head switch and a first level shifter, and the core power supply domain includes a second head switch and a second level shifter. The first level shifter is configured to level-shift the core domain clamp signal into a first level-shifted output signal for influencing the turn-off of the first head switch; and the second level shifter is configured to level-shift the first logic output signal into a second level-shifted output signal for influencing the turn-off of the second head switch.

16. The method for dual power supply memory according to claim 15, further comprising: responsive to assertion of a sleep hold signal, isolating the peripheral logic in the memory power supply domain from the memory domain voltage rail; as well as In response to the assertion of the sleep hold signal, the peripheral logic in the core power supply domain is isolated from the core domain voltage rail.

17. A dual power supply memory, comprising: a memory power domain comprising a memory power rail for a memory power supply voltage, a memory peripheral logic circuit device, a first header switch, and a first level shifter, the memory peripheral logic circuit device being coupled to the memory power supply voltage via the first header switch; a core power domain comprising a core power rail for a core power supply voltage, a core peripheral logic circuit device, a second header switch, and a second level shifter, the core peripheral logic circuit device being coupled to the core power rail via the second header switch; a controller configured to assert a memory domain clamp signal during a power-on period for the memory power domain and to assert a core domain clamp signal during a power-on period for the core power domain; as well as means for: turning off the first and second headswitch in response to the assertion of the core domain clamp signal or the memory domain clamp signal, and turning on the first and second headswitch in response to deassertion of the core domain clamp signal and the memory domain clamp signal, The first level shifter is configured to level-shift the core domain clamp signal into a first level-shifted output signal for influencing the turn-off of the first head switch, and the second level shifter is configured to level-shift the first logic output signal into a second level-shifted output signal for influencing the turn-off of the second head switch.

18. The dual power supply memory according to claim 17, further comprising: Means for turning off the first and second headswitch in response to assertion of a sleep hold signal from the core power domain.

19. The dual power supply memory according to claim 17, further comprising: a plurality of bit cells in the memory power domain; a third header switch configured to couple the plurality of bit cells to the memory power rail; as well as A component for: level-shifting a sleep non-retention signal from the core power domain to a switch control signal for the third head switch in response to de-assertion of the memory domain clamp signal and the core domain clamp signal, and latching the switch control signal in response to assertion of the memory domain clamp signal or assertion of the core domain clamp signal.

20. The dual power supply memory of claim 17, wherein the dual power supply memory comprises a dual power supply SRAM.

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