Light emitting device, method for manufacturing the same, and display device including the same

Abstract

A light emitting device according to an embodiment of the present invention includes: a substrate; a first electrode and a second electrode disposed on different layers on the substrate; a first insulating layer disposed between the first electrode and the second electrode; and at least one light emitting diode electrically connected between the first electrode and the second electrode.

Description

Technical Field

[0001] Various embodiments of the present disclosure are directed to a light emitting device, a method of manufacturing the light emitting device, and a display apparatus having the light emitting device. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting diode using a material having a reliable inorganic crystal structure and manufacturing a light-emitting device using the light-emitting diode has been developed. For example, a technology for manufacturing an ultra-small light-emitting diode having a small size ranging from a nanometer level to a micrometer level and forming a light source of a light-emitting device using the ultra-small light-emitting diode has been developed. Such a light-emitting device can be provided in various electronic devices such as display devices and lighting devices. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure are directed to a light emitting device including a light emitting diode, a method of manufacturing the light emitting device, and a display apparatus including the light emitting device.

[0005] Technical Solution

[0006] The light emitting device according to an embodiment of the present disclosure includes: a substrate; a first electrode and a second electrode, which are arranged on different layers above the substrate; a first insulating layer, which is placed between the first electrode and the second electrode; and at least one light emitting diode, which is electrically connected between the first electrode and the second electrode.

[0007] In an embodiment, the first electrode and the second electrode may overlap each other in at least one region and be spaced apart from each other with a first insulating layer interposed therebetween.

[0008] In an embodiment, the at least one light emitting diode may include a first end and a second end disposed adjacent to the first electrode and the second electrode and positioned at opposite ends in a length direction of the at least one light emitting diode. The first end may be disposed at one end of the at least one light emitting diode and configured to face the first electrode and the second electrode, and the second end may be disposed at opposite ends of the at least one light emitting diode.

[0009] In an embodiment, the light-emitting device may further include: a first contact electrode, disposed on the first end of the at least one light-emitting diode and a region of the first electrode and the second electrode, and configured to electrically connect the first end to the first electrode; and a second contact electrode, disposed on the second end of the at least one light-emitting diode, and configured to electrically connect the second end to the second electrode.

[0010] In an embodiment, the light emitting device may further include: a first partition wall disposed between the substrate and the first electrode and the second electrode, and positioned adjacent to the first end of the at least one light emitting diode; and a second partition wall disposed between the substrate and the second contact electrode, and positioned adjacent to the second end of the at least one light emitting diode.

[0011] In an embodiment, the first electrode may be disposed on the first insulating layer. The second electrode may be disposed between the substrate and the first insulating layer to overlap with the first electrode.

[0012] In an embodiment, in a region where the first electrode and the second electrode overlap each other, the second electrode may have a width greater than that of the first electrode.

[0013] In an embodiment, a first end of the at least one light emitting diode may be disposed to face the first electrode. At least one region of the at least one light emitting diode may overlap the second electrode.

[0014] In an embodiment, the light emitting device may further include at least one partition wall disposed between the substrate and the second electrode and positioned adjacent to either end of the at least one light emitting diode.

[0015] In an embodiment, the number of the first electrode and the second electrode may be different from each other. The second electrode may include: a first sub-electrode overlapping the first electrode; and at least one second sub-electrode disposed to be spaced apart from the first electrode and the first sub-electrode by a predetermined distance in a plan view.

[0016] In an embodiment, the at least one light emitting diode may include a rod-type light emitting diode positioned in a horizontal direction between the first electrode and the second electrode in a plan view.

[0017] In an embodiment, the first electrode and the second electrode may be disposed to be spaced apart from each other by a predetermined distance in a plan view so as not to overlap each other.

[0018] In an embodiment, the first electrode and the second electrode may have a stripe shape extending in the same direction and be disposed in parallel with each other at a constant interval.

[0019] In an embodiment, the second electrode may include a bent portion on a side edge region thereof adjacent to the first electrode. The first electrode and the second electrode may be arranged at positions spaced apart from each other by a first distance in the first region, and at positions spaced apart from each other by a second distance greater than the first distance in the second region adjacent to the first region.

[0020] In an embodiment, the first region and the second region may be sequentially arranged in an extension direction of each of the first electrode and the second electrode.

[0021] In an embodiment, the at least one light emitting diode may be disposed in the first region.

[0022] According to an embodiment of the present disclosure, the method for manufacturing a light-emitting device includes the following steps: forming a lower electrode on a substrate; forming a first insulating layer on the substrate to at least cover the lower electrode; forming an upper electrode on the first insulating layer; supplying at least one light-emitting diode on the substrate including the lower electrode and the upper electrode, and aligning the at least one light-emitting diode so that one end of the at least one light-emitting diode is adjacent to the upper electrode; and electrically connecting the at least one light-emitting diode between the lower electrode and the upper electrode.

[0023] In an embodiment, the step of electrically connecting the at least one light emitting diode between the lower electrode and the upper electrode may include forming a first contact electrode and a second contact electrode, the first contact electrode and the second contact electrode connecting opposite ends of the at least one light emitting diode to the upper electrode and the lower electrode, respectively.

[0024] In an embodiment, the method may further include forming at least one partition wall on the substrate before the step of forming the lower electrode.

[0025] A display device according to an embodiment of the present disclosure includes: a substrate including a display area; and a pixel arranged in the display area. The pixel includes: a first electrode and a second electrode arranged on different layers on the substrate; a first insulating layer disposed between the first electrode and the second electrode; and at least one light emitting diode electrically connected between the first electrode and the second electrode.

[0026] Beneficial Effects

[0027] In the light emitting device, the method of manufacturing the light emitting device, and the display device including the light emitting device according to the embodiment of the present disclosure, the light emitting diode may be effectively arranged between the first electrode and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0031] Figure 4is a plan view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 5a to Figure 5c Each is a circuit diagram showing a light emitting device according to an embodiment of the present disclosure, for example, showing different embodiments of active pixels including the light emitting device.

[0033] Figure 6 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel formed by the light emitting device.

[0034] Figure 7 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Figure 6 The line II' corresponds to an embodiment of a cross section.

[0035] Figure 8 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an example of a pixel formed by the light emitting device.

[0036] Figure 9a and Figure 9b is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Figure 8 The line II-II' corresponds to different embodiments of the cross section.

[0037] Fig.10 is a flowchart showing a method for manufacturing a light emitting device according to an embodiment of the present disclosure, for example, Figures 8 to 9b Embodiments of the light emitting device of the embodiments of the method.

[0038] Fig.11a 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel including the light emitting device.

[0039] Fig.11b It shows that according to Fig.11a A plan view showing the relative arrangement relationship of the first electrode, the second electrode and the light emitting diode of the embodiment.

[0040] Fig.12a and Figure 12b Each is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Fig.11a The line III-III' corresponds to different embodiments of the cross section.

[0041] Fig.13a 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel including the light emitting device.

[0042] Fig.13b It shows that according to Fig.13a A plan view showing the relative arrangement relationship of the first electrode, the second electrode and the light emitting diode of the embodiment.

[0043] Fig.14 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Fig.13a An embodiment of a cross section corresponding to line IV-IV'.

[0044] Fig.15 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel including the light emitting device.

[0045] Fig.16 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Fig.15 An embodiment of a cross section corresponding to line V-V'.

[0046] Fig.17a 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel including the light emitting device.

[0047] Fig.17b It shows that according to Fig.17a A plan view showing the relative arrangement relationship of the first electrode, the second electrode and the light emitting diode of the embodiment.

[0048] Fig.18a 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel including the light emitting device.

[0049] Fig.18b It shows that according to Fig.18a A plan view showing the relative arrangement relationship of the first electrode, the second electrode and the light emitting diode of the embodiment.

[0050] Fig.19a 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel including the light emitting device.

[0051] Fig.19b It shows that according to Fig.19a A plan view showing the relative arrangement relationship of the first electrode, the second electrode and the light emitting diode of the embodiment. DETAILED DESCRIPTION

[0052] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, as the embodiments of the present disclosure may be variously modified in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0053] Some elements in the drawings that are not directly related to the features of the present disclosure may be omitted to clearly explain the present disclosure. In addition, the sizes, proportions, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that throughout the drawings, the same reference numerals are used to represent the same or similar elements, and repeated descriptions will be omitted.

[0054] It should be understood that, although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, it is explained that there are stated features, wholes, steps, operations, elements, components and / or combinations thereof, but it is not excluded that there are or add one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when the first component or part is arranged on the second component or part, the first component or part can not only be directly on the second component or part, but also the third component or part can be placed between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions according to the viewing angle or direction.

[0055] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings to describe the present disclosure in detail so that a person skilled in the art with ordinary knowledge in the technical field to which the present disclosure belongs can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0056] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting diode LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting diode LD is illustrated, but the type and / or shape of the light emitting diode LD according to the present disclosure is not limited thereto.

[0057] Reference Figure 1a and Figure 1b The light emitting diode LD according to an embodiment of the present disclosure may include a first conductive type semiconductor layer 11 (or referred to as a "first semiconductor layer"), a second conductive type semiconductor layer 13 (or referred to as a "second semiconductor layer"), and an active layer 12 disposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting diode LD may be composed of a stacked body formed by sequentially stacking the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13.

[0058] In an embodiment, the light emitting diode LD may be provided in the form of a rod extending in one direction. If the direction along which the light emitting diode LD extends is defined as a length direction (or longitudinal direction), the light emitting diode LD may have a first end and a second end relative to the length direction.

[0059] In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a first end of the light emitting diode LD, and the other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a second end of the light emitting diode LD.

[0060] In an embodiment, the light emitting diode LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type" includes rod-like shapes and strip-like shapes such as cylindrical shapes and prismatic shapes extending in the length direction (i.e., to have an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting diode LD may be greater than its diameter D (or the width of its cross section).

[0061] In an embodiment, the light emitting diode LD may have a small size corresponding to a range from nanometer to micrometer, for example, a diameter D and / or a length L in a range from nanometer to micrometer. However, in the present disclosure, the size of the light emitting diode LD is not limited thereto. For example, the size of the light emitting diode LD may be changed in various ways according to design conditions of various devices (for example, display devices), each of which uses a light emitting device using the light emitting diode LD as a light source.

[0062] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a first conductive dopant such as Si, Ge, or Sn. However, the material used to form the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0063] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a capping layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the capping layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0064] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light emitting diode LD, the light emitting diode LD emits light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting diode LD can be controlled based on the aforementioned principle, the light emitting diode LD can be used as a light source for various light emitting devices and pixels of a display device.

[0065] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0066] In an embodiment, the light emitting diode LD may further include an insulating film INF disposed on the surface of the light emitting diode LD. In an embodiment, the insulating film INF may be formed on the surface of the light emitting diode LD to surround at least the outer circumferential surface of the active layer 12. In addition, the insulating film INF may also surround the region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may enable the opposite ends of the light emitting diode LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting diode LD relative to the length direction, for example, the two base sides (top surface and bottom surface) of the cylinder may be exposed instead of covering the two base sides.

[0067] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0068] In an embodiment, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF, the light emitting diode LD may further include other additional components. For example, the light emitting diode LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer and / or at least one electrode layer disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0069] For example, Figure 2a and Figure 2b As shown in , the light emitting diode LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. In an embodiment, as shown in Figure 3a and Figure 3b As shown in , the light emitting diode LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0070] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO, and oxides or alloys thereof may be used alone or in combination with each other. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, light generated from the light emitting diode LD may be emitted from the light emitting diode LD through the electrode layers 14 and 15.

[0071] In an embodiment, the insulating film INF may at least partially surround the outer circumferential surface of the electrode layers 14 and 15, or may not surround the outer circumferential surface. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to enable the opposite ends of the light emitting diode LD having different polarities to be exposed, for example, to expose at least one region of each of the electrode layers 14 and 15. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0072] If the insulating film INF is provided on the surface of the light emitting diode LD, in particular, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, at least one of the contact electrodes connected to the opposite ends of the light emitting diode LD). Therefore, the electrical stability of the light emitting diode LD can be ensured.

[0073] In addition, due to the insulating film INF formed on the surface of the light emitting diode LD, the occurrence of defects on the surface of the light emitting diode LD can be minimized, so that the life and efficiency of the light emitting diode LD can be improved. In addition, if the insulating film INF is formed on each light emitting diode LD, even in the case where a plurality of light emitting diodes LD are arranged adjacent to each other, the light emitting diode LD can be prevented from being unexpectedly short-circuited.

[0074] In the embodiments of the present disclosure, the light emitting diodes LD may be manufactured by a surface treatment process. For example, the light emitting diodes LD may be surface treated (e.g., surface treated by a coating process) so that when a plurality of light emitting diodes LD are mixed with a fluid solution and then supplied to each light emitting region (e.g., the light emitting region of each pixel), the light emitting diodes LD may be evenly distributed rather than unevenly aggregated in the solution.

[0075] The light-emitting device including the above-mentioned light-emitting diode LD can be used in various devices including a display device that requires a light source. For example, at least one ultra-small light-emitting diode LD (for example, a plurality of ultra-small light-emitting diodes LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel. In addition, the application field of the light-emitting diode LD according to the present disclosure is not limited to display devices. For example, the light-emitting diode LD can also be used in various devices such as lighting devices that require a light source.

[0076] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (particularly, a display panel PNL provided in the display device) is shown as a reference. Figures 1a to 3b The light emitting diode LD is described as an example of a device of a light source. For example, each pixel PXL of the display panel PNL may include a light emitting device. The light emitting device may include at least one light emitting diode LD.

[0077] For illustrative purposes, Figure 4 The structure of the display panel PNL according to the embodiment is simply shown concentrated on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may also be provided in the display panel PNL.

[0078] Reference Figure 4, the display panel PNL according to an embodiment of the present disclosure may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. In detail, the display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the substrate SUB.

[0079] In an embodiment, the display area DA may be disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed in the peripheral area of ​​the display panel PNL in such a manner as to surround (or enclose) the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0080] The substrate SUB may form a base of the display panel PNL. In an embodiment, the substrate SUB may be a rigid or flexible substrate, and its material or properties are not particularly limited. For example, the substrate SUB may be a rigid substrate made of glass or tempered glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. For example, the substrate SUB may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0081] One area on the substrate SUB is defined as a display area DA in which the pixels PXL are disposed, and another area thereof is defined as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0082] In an embodiment, the pixels PXL may be distributed and arranged in the display area DA. In an embodiment, the pixels PXL may be arranged in the display area DA in a stripe shape. However, the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the display area DA in various known shapes.

[0083] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or power (eg, a first power and a second power), for example, according to Figures 1a to 3bThe light emitting diode LD of any one of the embodiments of the present invention. For example, each pixel PXL may include at least one light emitting diode LD having a small size ranging from nanometer level to micrometer level. For example, each pixel PXL may include a plurality of rod-type light emitting diodes connected in parallel between pixel electrodes and / or power lines. A plurality of rod-type light emitting diodes may form a light emitting device of each pixel PXL (e.g., a light source or light source unit of each pixel PXL).

[0084] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving method of the pixel PXL applicable to the display device according to the present disclosure are not particularly limited. For example, each pixel PXL may have the same structure as that of a pixel of various known passive or active light-emitting display devices.

[0085] Figure 5a to Figure 5c 1 is a circuit diagram showing a light emitting device according to an embodiment of the present disclosure, for example, showing different embodiments of an active pixel PXL including a light emitting device. In the embodiment, Figure 5a to Figure 5c Each pixel PXL shown in FIG. 1 may be set to Figure 4 The pixels PXL may have substantially the same or similar structures.

[0086] Reference Figure 5a The pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal and a pixel circuit PXC configured to drive the light source unit LSU. The light source unit LSU may form a light emitting device according to an embodiment of the present disclosure.

[0087] In an embodiment, the light source unit LSU may include a plurality of light emitting diodes LD between a first power source VDD and a second power source VSS. In an embodiment, the light emitting diodes LD may be connected in parallel with each other, but the present disclosure is not limited thereto. For example, in an embodiment, the plurality of light emitting diodes LD may be connected between the first power source VDD and the second power source VSS in a series / parallel combination structure.

[0088] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting diode LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting diode LD or more at least during the light emitting period of the pixel PXL.

[0089] although Figure 5aAn embodiment is shown in which the light emitting diodes LD of the light source unit LSU forming each pixel PXL are connected in parallel to each other in the same direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, in an embodiment, some of the light emitting diodes LD may be connected to each other in a first direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, and the other light emitting diodes LD may be connected to each other in a second direction (e.g., in the reverse direction). Alternatively, in an embodiment, at least one pixel PXL may include only a single light emitting diode LD.

[0090] In an embodiment, a first end of the light emitting diode LD forming each light source unit LSU may be commonly connected to a corresponding pixel circuit PXC through a first electrode (or referred to as a "first pixel electrode") of the light source unit LSU, and may be commonly connected to a first power source VDD through the pixel circuit PXC and a first power line PL1. A second end of the light emitting diode LD may be commonly connected to a second power source VSS through a second electrode (or referred to as a "second pixel electrode") of the light source unit LSU and a second power line PL2.

[0091] Each light source unit LSU may emit light having brightness corresponding to a driving current supplied thereto through a corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0092] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (where i is a natural number) and the j-th column (where j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0093] The first transistor (driving transistor) T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0094] The second transistor (switching transistor) T2 may be connected between the data line Dj and the first node N1. A gate electrode of the second transistor T2 is connected to the scan line Si.

[0095] When a scan signal of a gate-on voltage (e.g., a low voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj. During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is stored in the storage capacitor Cst.

[0096] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to a data signal supplied to the first node N1 during each frame period, and maintain the charged voltage until a data signal of a subsequent frame is supplied thereto.

[0097] Despite Figure 5a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, either of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0098] For example, Figure 5b As shown in FIG. 1 , both the first transistor T1 and the second transistor T2 can be formed by N-type transistors. In addition to the feature that the connection positions of some circuit elements vary according to the type of transistor, Figure 5b The construction and operation of the pixel PXL shown in Figure 5a The configuration and operation of the pixel PXL are basically similar. Therefore, the description of Figure 5b A detailed description of the pixel PXL.

[0099] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving methods. For example, the pixel circuit PXC may be formed with Figure 5c The embodiment shown in FIG. 1 is constructed in the same manner.

[0100] Reference Figure 5c, the pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal row, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged in the i-th row of the display area DA can also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0101] The first transistor T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0102] The second transistor T2 is connected between the data line Dj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. The second transistor T2 can be turned on when a scan signal of a gate-on voltage is supplied from the scan line Si to electrically connect the data line Dj to the one electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj can be transmitted to the first transistor T1.

[0103] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. The third transistor T3 can be turned on when a scan signal of a gate-on voltage is supplied from the scan line Si to electrically connect the first transistor T1 in the form of a diode.

[0104] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. The fourth transistor T4 may be turned on when a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1, so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be equal to or less than the minimum voltage of the data signal.

[0105] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 can be turned off when the emission control signal of the gate cut-off voltage (for example, a high voltage) is supplied to the emission control line Ei, and can be turned on in other cases.

[0106] The sixth transistor T6 is connected between the first transistor T1 and the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 can be turned off when the emission control signal of the gate-off voltage is supplied to the emission control line Ei, and can be turned on in other cases.

[0107] The seventh transistor T7 is connected between the first electrode of the light source unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. The seventh transistor T7 can be turned on when a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU.

[0108] The storage capacitor Cst is connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0109] Despite Figure 5c , the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0110] The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 5a to Figure 5c , and each pixel PXL may have various known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a known pixel circuit that may have various structures and / or be operated by various driving methods. In an embodiment of the present disclosure, each pixel PXL may be constructed in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first pixel electrode and the second pixel electrode of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0111] Figure 61 is a plan view showing a light emitting device according to an embodiment of the present disclosure (eg, showing an example of a pixel PXL including a light emitting device). In the embodiment, Figure 6 A light emitting device (e.g., a pixel PXL of a passive light emitting display device) is shown, which includes a first power line PL1 and a second power line PL2 (or a signal line such as a scan line and a data line) or is directly connected to the first power line PL1 and the second power line PL2. However, the light emitting device according to the present disclosure is not limited to Figure 6 For example, in an embodiment of the present disclosure, the light emitting device may be connected via at least one circuit element (e.g., Figure 5a to Figure 5c The pixel circuit PXC), connection lines, signal lines, etc. are connected to the first power line PL1 and / or the second power line PL2.

[0112] Reference Figure 6 According to an embodiment of the present disclosure, the pixel PXL may include a first electrode ELT1, a second electrode ELT2, and at least one light emitting diode LD electrically connected between the first electrode ELT1 and the second electrode ELT2. For example, the pixel PXL may include a plurality of light emitting diodes LD connected in series and / or in parallel to each other between the first electrode ELT1 and the second electrode ELT2.

[0113] In addition, the pixel PXL may further include a first contact electrode CNE1 and a second contact electrode CNE2, the first contact electrode CNE1 being configured to electrically connect the first end EP1 of the light emitting diode LD to the first electrode ELT1, and the second contact electrode CNE2 being configured to electrically connect the second end EP2 of the light emitting diode LD to the second electrode ELT2. The light emitting diode LD may be electrically connected between the first electrode ELT1 and the second electrode ELT2 through the first contact electrode CNE1 and the second contact electrode CNE2.

[0114] In addition, the pixel PXL may further include a first connection electrode CNL1 and a second connection electrode CNL2, the first connection electrode CNL1 being configured to connect the first electrode ELT1 to the first power line PL1, and the second connection electrode CNL2 being configured to connect the second electrode ELT2 to the second power line PL2. In an embodiment, the first connection electrode CNL1 and the second connection electrode CNL2 may be connected to the first electrode ELT1 and the second electrode ELT2, respectively and integrally, or respectively electrically connected to the first electrode ELT1 and the second electrode ELT2 via at least one contact hole, etc. In the case where the first connection electrode CNL1 and the second connection electrode CNL2 are connected to the first electrode ELT1 and the second electrode ELT2, respectively and integrally, each of the first connection electrode CNL1 and the second connection electrode CNL2 may be considered as a region of the corresponding electrode of the first electrode ELT1 and the second electrode ELT2. In the description of the embodiment of the present disclosure, the first connection electrode CNL1 and the second connection electrode CNL2 and the first electrode ELT1 and the second electrode ELT2 will be described separately from each other to more clearly describe the relative arrangement relationship of the first electrode ELT1 and the second electrode ELT2, etc.

[0115] In an embodiment, the first electrode ELT1 and the second electrode ELT2, the light emitting diode LD, and / or the first contact electrode CNE1 and the second contact electrode CNE2 may form a light emitting device according to an embodiment of the present disclosure. For example, the first electrode ELT1 and the second electrode ELT2, the light emitting diode LD, and / or the first contact electrode CNE1 and the second contact electrode CNE2 may form a light source unit (for example, Figure 5a to Figure 5c of LSU).

[0116] In an embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 may be arranged to overlap each other and be separated from each other with substantially the same width. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged at positions spaced apart from each other on different layers on a substrate as a base of the pixel PXL (or light-emitting device), and at least one insulating layer is placed between the first electrode ELT1 and the second electrode ELT2. For example, the relative arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways according to the embodiment. In an embodiment, the first electrode ELT1 and the second electrode ELT2 may have substantially the same width at least in the overlapping region of the first electrode ELT1 and the second electrode ELT2. However, the present disclosure is not limited thereto. For example, the relative size (e.g., width) of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0117] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may be any pixel electrode, for example, one of an anode electrode and a cathode electrode. For example, if the first electrode ELT1 may be an anode electrode, the second electrode ELT2 may be a cathode electrode.

[0118] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer or multi-layer structure. For example, each of the first electrodes ELT1 may have a multi-layer structure including a first reflective electrode and a first conductive cover layer. Each of the second electrodes ELT2 may have a multi-layer structure including a second reflective electrode and a second conductive cover layer. The constituent material and / or cross-sectional structure of each of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways according to the embodiment without being particularly limited.

[0119] In an embodiment, the first electrode ELT1 may be connected to a first power line (eg, Figure 5a to Figure 5c PL1, or a predetermined signal line such as a scan line, a data line, or a control line). In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions. For example, in the case where the first connection electrode CNL1 extends in a first direction DR1 (for example, in a horizontal direction), the first electrode ELT1 may extend in a second direction DR2 (for example, in a vertical direction) intersecting the first direction DR1.

[0120] In an embodiment, the first electrode ELT1 may be integrally connected to the first connection electrode CNL1. For example, the first electrode ELT1 may be bifurcated from the first connection electrode CNL1 in at least one manner. However, the present disclosure is not limited thereto. For example, in an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be separately formed and electrically connected to each other through at least one contact hole, a via hole, etc.

[0121] In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may be integrally connected to the first power line PL1 (or the first signal line). In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may be formed separately from the first power line PL1 and electrically connected to the first power line PL1 via at least one contact hole and / or at least one circuit element. Therefore, the first power supply voltage (or the first signal such as a scan signal, a data signal or a control signal) supplied to the first power line PL1 (or the first signal line) may be transmitted to the first electrode ELT1.

[0122] In an embodiment, the second electrode ELT2 may be connected to the second power line PL2 (or a predetermined second signal line such as a scan line, a data line, or a control line) through the second connection electrode CNL2. In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions. For example, in the case where the second connection electrode CNL2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 intersecting the first direction DR1.

[0123] In an embodiment, the second electrode ELT2 may be integrally connected to the second connection electrode CNL2. For example, the second electrode ELT2 may be bifurcated from the second connection electrode CNL2 in at least one manner. However, the present disclosure is not limited thereto. For example, in an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be separately formed and electrically connected to each other through at least one contact hole, a via, etc.

[0124] In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may be connected to the second power line (eg, Figures 5a to 5c PL2, or the second signal line) is integrally connected. In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may be formed separately from the second power line PL2 and electrically connected to the second power line PL2 via at least one contact hole and / or at least one circuit element. Therefore, the second power supply voltage (or the second signal such as a scan signal, a data signal or a control signal) supplied to the second power line PL2 (or the second signal line) may be transmitted to the second electrode ELT2.

[0125] In an embodiment, a first power source (eg, Figure 5a to Figure 5c VDD) and a second power supply (e.g., Figure 5a to Figure 5c The first power supply VDD and the second power supply VSS may have different potentials. For example, the potential difference between the first power supply VDD and the second power supply VSS may be equal to or greater than the threshold voltage of the light emitting diode LD. In an embodiment, the first power supply VDD and the second power supply VSS may have a potential that enables at least one light emitting diode LD to be connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction. In other words, the voltage between the first power supply VDD and the second power supply VSS may have a value that enables at least one light emitting diode LD included in the pixel PXL (or the light emitting device) to emit light.

[0126] In an embodiment, each light emitting diode LD may be a rod-type light emitting diode disposed adjacent to the first electrode ELT1 and the second electrode ELT2 and including a first end EP1 and a second end EP2 disposed at opposite ends thereof with respect to the length direction. For example, each light emitting diode LD may be an ultra-small rod-type light emitting diode having a diameter D and / or a length L ranging from nanometer level to micrometer level, such as Figures 1a to 3b However, the shape and / or size of the light emitting diode LD may be changed in various ways according to the design conditions of each light emitting device (eg, pixel PXL), etc.

[0127] In an embodiment, the first end EP1 of the at least one light emitting diode LD may be disposed at one end facing a region of the first electrode ELT1 and the second electrode ELT2 (e.g., a region where the first electrode ELT1 and the second electrode ELT2 overlap), and the second end EP2 of the light emitting diode LD may be disposed at an end opposite to the first end EP1. For example, the at least one light emitting diode LD may be horizontally positioned in a direction (e.g., a first direction DR1) intersecting an extending direction (e.g., a second direction DR2) of the first electrode ELT1 and the second electrode ELT2. The first end EP1 of the light emitting diode LD may be adjacent to the first electrode ELT1 and the second electrode ELT2.

[0128] although Figure 6 The light emitting diodes LD are shown to be uniformly positioned in any direction (eg, in the first direction DR1), but the present disclosure is not limited thereto. For example, at least one of the light emitting diodes LD may be positioned in a diagonal direction inclined with respect to the first direction DR1 and the second direction DR2.

[0129] In an embodiment, a plurality of light emitting diodes LD may be connected in parallel between the first electrode ELT1 and the second electrode ELT2. For example, a first end EP1 of the light emitting diode LD may be directly or indirectly connected to the first electrode ELT1. A second end EP2 of the light emitting diode LD may be directly or indirectly connected to the second electrode ELT2.

[0130] For example, in an embodiment of the present disclosure, the first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1 via the first contact electrode CNE1. The second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2 via the second contact electrode CNE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of each light emitting diode LD may be in direct contact with the first electrode ELT1 and / or the second electrode ELT2, and electrically connected to the first electrode ELT1 and / or the second electrode ELT2.

[0131] In an embodiment, the light emitting diode LD may be prepared in a diffused form in a predetermined solution and then supplied to a predetermined emission area (e.g., the emission area of ​​each pixel PXL) defined in the light emitting device by an inkjet printing method or the like. For example, the light emitting diode LD may be mixed with a volatile solvent and supplied to each emission area. Here, if a predetermined first alignment voltage and a second alignment voltage are applied to the first electrode ELT1 and the second electrode ELT2 by the first power line PL1 and the second power line PL2, respectively, an electric field may be formed between the first electrode ELT1 and the second electrode ELT2. Thus, the light emitting diode LD is aligned. After the light emitting diode LD has been aligned, the solvent may be removed by a volatilization method or other methods. In this way, the light emitting diode LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, after the light emitting diode LD has been arranged, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed on the opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting diode LD, respectively. Therefore, the light emitting diode LD may be more reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0132] In an embodiment, the first contact electrode CNE1 may be disposed on the first end EP1 of the light emitting diode LD and a region of the first electrode ELT1 and the second electrode ELT2 (e.g., a region where the first electrode ELT1 and the second electrode ELT2 overlap), so that the first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1. The second contact electrode CNE2 may be disposed on the second end EP2 of the light emitting diode LD and electrically connected to the second electrode ELT2 through at least one contact hole CH0 and / or the second connection electrode CNL2. The second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2 through the second contact electrode CNE2.

[0133] When the voltage (or first signal) of the first power source VDD is applied to the first end EP1 of the light emitting diode LD via the first power line PL1, the first electrode ELT1, etc., and the voltage (or second signal) of the second power source VSS is applied to the second end EP2 of the light emitting diode LD via the second power line PL2, the second electrode ELT2, etc., at least one light emitting diode LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction may emit light. Thus, the pixel PXL may emit light.

[0134] Figure 7 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Figure 6 In the embodiment, Figure 7The light emitting device may correspond to the passive pixel PXL, but the light emitting device according to the present disclosure is not limited to the pixel PXL.

[0135] Reference Figure 6 and Figure 7 , the pixel PXL (or the light emitting device) according to the embodiment of the present disclosure may include a substrate SUB, a buffer layer BFL continuously disposed on one surface of the substrate SUB, a second electrode ELT2, a second connection electrode CNL2, a first insulating layer INS1, a first electrode ELT1, a first connection electrode CNL1, at least one light emitting diode LD (for example, a plurality of light emitting diodes LD), a first contact electrode CNE1, a second insulating layer INS2, a second contact electrode CNE2, and an encapsulation layer ENC. For example, in the embodiment of the present disclosure, based on one surface of the substrate SUB, the buffer layer BFL may be disposed on a first layer, the second electrode ELT2 and the second connection electrode CNL2 may be disposed on a second layer, the first insulating layer INS1 may be disposed on a third layer, the first electrode ELT1 and the first connection electrode CNL1 may be disposed on a fourth layer, the light emitting diode LD may be disposed on a fifth layer, the first contact electrode CNE1 may be disposed on a sixth layer, the second insulating layer INS2 may be disposed on a seventh layer, the second contact electrode CNE2 may be disposed on an eighth layer, and the encapsulation layer ENC may be disposed on a ninth layer. Here, the above-defined corresponding positions of the components on the layer are based on the relative arrangement relationship between the components disposed on the substrate SUB and / or the order of forming or supplying the components, and may not be based on the distance, height, etc. from the substrate SUB.

[0136] In addition, in some embodiments, at least one of the aforementioned components may be omitted, or the position of the at least one component may be changed. For example, the positions of the first electrode ELT1 and the first connection electrode CNL1 disposed on the layer may be switched with the positions of the second electrode ELT2 and the second connection electrode CNL2. For example, in an embodiment of the present disclosure, the first electrode ELT1 and the first connection electrode CNL1 may be disposed on the second layer of the substrate SUB, and the second electrode ELT2 and the second connection electrode CNL2 may be disposed on the fourth layer of the substrate SUB. Similarly, the positions of the first contact electrode CNE1 and the second contact electrode CNE2 on the layer may be switched with each other. In addition, in an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be selectively omitted. Figure 7 At least one of the components shown in FIG. 1 , or other additional components may be provided in each pixel PXL.

[0137] The substrate SUB may form a display panel (eg, Figure 4The substrate SUB may be a substrate of a PNL and may be a rigid substrate or a flexible substrate. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. In other words, in the present disclosure, the material or properties of the substrate SUB are not particularly limited. The buffer layer BFL may be disposed on one surface of the substrate SUB.

[0138] The buffer layer BFL may prevent impurities from diffusing into electrodes, wires, and / or circuit elements disposed on the buffer layer BFL. In an embodiment, the buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, the corresponding layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted. The buffer layer BFL may be selectively formed on one surface of the substrate SUB.

[0139] The second electrode ELT2 and the second connection electrode CNL2 may be disposed on one surface of the substrate SUB on which the buffer layer BFL is formed. In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions. In addition, the second electrode ELT2 and the second connection electrode CNL2 may be connected to each other integrally or non-integrally.

[0140] In the embodiment, the second electrode ELT2 and the second connection electrode CNL2 may include various conductive materials. For example, the second electrode ELT2 and the second connection electrode CNL2 may have at least one reflective electrode layer, but the present disclosure is not limited thereto.

[0141] For example, the second electrode ELT2 and / or the second connection electrode CNL2 may include a conductive material having a predetermined reflectivity. For example, the second electrode ELT2 and / or the second connection electrode CNL2 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or an alloy thereof), a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO)) and a conductive polymer such as PEDOT, but the present disclosure is not limited thereto. In other words, the constituent materials of the second electrode ELT2 and the second connection electrode CNL2 are not particularly limited, and the second electrode ELT2 and the second connection electrode CNL2 may have various known electrode materials.

[0142] In addition, each of the second electrode ELT2 and the second connection electrode CNL2 may be formed of a single layer or multiple layers, and its cross-sectional structure (e.g., stacked structure) is not particularly limited. For example, the second electrode ELT2 may have a multilayer structure including at least one reflective electrode layer and at least one conductive cap layer. In addition, the second electrode ELT2 may also selectively include at least one transparent electrode layer. In an embodiment, the second connection electrode CNL2 may have a cross-sectional structure that is the same as that of the second electrode ELT2, but the present disclosure is not limited thereto.

[0143] In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may include at least one reflective electrode layer, at least one transparent electrode layer disposed above the reflective electrode layer and / or below the reflective electrode layer, and at least one conductive cover layer configured to cover the upper portion of the reflective electrode layer and / or the transparent electrode layer. In an embodiment, the reflective electrode layer may be formed of various conductive materials (e.g., Ag) having reflectivity, and its constituent materials are not particularly limited. In the case where the second electrode ELT2 and / or the second connection electrode CNL2 include a reflective electrode layer, light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting diodes LD may travel in the direction along which the image is displayed (e.g., in the front direction).

[0144] In addition, if the second electrode ELT2 and / or the second connection electrode CNL2 has a multilayer structure including at least one transparent electrode layer disposed above and / or below the reflective electrode layer, the voltage drop due to signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting diode LD. In an embodiment, the transparent electrode layer can be formed of various transparent conductive materials including ITO, and its constituent materials are not particularly limited.

[0145] In addition, if the second electrode ELT2 and / or the second connection electrode CNL2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the second electrode ELT2 and / or the second connection electrode CNL2, etc. can be prevented from being damaged due to defects caused during the process of manufacturing the pixel PXL. However, the conductive cover layer may be selectively included in the second electrode ELT2 and / or the second connection electrode CNL2, and the conductive cover layer may be omitted in some embodiments. The conductive cover layer may be considered as a component of the second electrode ELT2 and / or the second connection electrode CNL2, or as a separate component disposed on the second electrode ELT2 and / or the second connection electrode CNL2.

[0146] The first insulating layer INS1 may be disposed on the substrate SUB on which the second electrode ELT2 and the second connection electrode CNL2 are formed. For example, the first insulating layer INS1 may be disposed on the substrate SUB to cover the second electrode ELT2 and the second connection electrode CNL2.

[0147] The first insulating layer INS1 may have a single-layer or multi-layer structure including at least one organic layer and / or inorganic layer, and may include various known insulating materials. For example, the first insulating layer INS1 may include SiN x At least one inorganic layer is formed, but the present disclosure is not limited thereto.

[0148] In an embodiment, the first insulating layer INS1 may include a contact hole CH0 exposing a region of the second connection electrode CNL2. For example, the first insulating layer INS1 may include at least one contact hole CH0 in a region where the second connection electrode CNL2 and the second contact electrode CNE2 overlap.

[0149] The first electrode ELT1 and the first connection electrode CNL1 may be disposed on a substrate SUB on which a first insulating layer INS1 is formed. In an embodiment, the first electrode ELT1 may be disposed to overlap with the second electrode ELT2, and the first insulating layer INS1 is disposed between the first electrode ELT1 and the second electrode ELT2. In other words, regions of the first electrode ELT1 and the second electrode ELT2 may overlap and be spaced apart from each other, and at least the first insulating layer INS1 is disposed between the first electrode ELT1 and the second electrode ELT2.

[0150] In the embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions. In addition, the first electrode ELT1 and the first connection electrode CNL1 may be integrally or non-integrally connected to each other.

[0151] In the embodiment, the first electrode ELT1 and the first connection electrode CNL1 may include various conductive materials. For example, the first electrode ELT1 and the first connection electrode CNL1 may include at least one reflective electrode layer, but the present disclosure is not limited thereto.

[0152] For example, the first electrode ELT1 and / or the first connection electrode CNL1 may include a conductive material having a predetermined reflectivity. For example, the first electrode ELT1 and / or the first connection electrode CNL1 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or an alloy thereof), a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO)) and a conductive polymer such as PEDOT, but the present disclosure is not limited thereto. In other words, the constituent materials of the first electrode ELT1 and the first connection electrode CNL1 are not particularly limited, and the first electrode ELT1 and the first connection electrode CNL1 may have various known electrode materials. In addition, the first electrode ELT1 and / or the first connection electrode CNL1 may include the same conductive material as the conductive material of the second electrode ELT2 and / or the second connection electrode CNL2, or may include a conductive material different from the conductive material of the second electrode ELT2 and / or the second connection electrode CNL2.

[0153] In addition, each of the first electrode ELT1 and the first connection electrode CNL1 may be formed of a single layer or multiple layers, and its cross-sectional structure (e.g., stacked structure) is not particularly limited. For example, the first electrode ELT1 may have a multilayer structure including at least one reflective electrode layer and at least one conductive cap layer. In addition, the first electrode ELT1 may also selectively include at least one transparent electrode layer. In an embodiment, the first connection electrode CNL1 may have a cross-sectional structure that is the same as that of the first electrode ELT1, but the present disclosure is not limited thereto.

[0154] In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may include at least one reflective electrode layer, at least one transparent electrode layer disposed above the reflective electrode layer and / or below the reflective electrode layer, and at least one conductive cover layer configured to cover the upper portion of the reflective electrode layer and / or the transparent electrode layer. In an embodiment, the reflective electrode layer may be formed of various conductive materials (e.g., Ag) having reflectivity, and its constituent materials are not particularly limited. In the case where the first electrode ELT1 and / or the first connection electrode CNL1 include a reflective electrode layer, light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting diodes LD may travel in a direction along which an image is displayed (e.g., in a front direction).

[0155] In addition, if the first electrode ELT1 and / or the first connection electrode CNL1 has a multilayer structure including at least one transparent electrode layer disposed above and / or below the reflective electrode layer, the voltage drop due to signal delay can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting diode LD. In an embodiment, the transparent electrode layer can be formed of various transparent conductive materials including ITO, and its constituent materials are not particularly limited.

[0156] In addition, if the first electrode ELT1 and / or the first connection electrode CNL1 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, it is possible to prevent the reflective electrode layer of the first electrode ELT1 and / or the first connection electrode CNL1 from being damaged due to defects caused during the process of manufacturing the pixel PXL. However, the conductive cover layer may be selectively included in the first electrode ELT1 and / or the first connection electrode CNL1, and the conductive cover layer may be omitted in some embodiments. The conductive cover layer may be considered as a component of the first electrode ELT1 and / or the first connection electrode CNL1, or as a separate component disposed on the first electrode ELT1 and / or the first connection electrode CNL1.

[0157] At least one light emitting diode LD may be disposed on the substrate SUB on which the first electrode ELT1 and the first connection electrode CNL1 are formed. For example, a plurality of light emitting diodes LD may be disposed in each pixel region in which each pixel PXL is formed.

[0158] In an embodiment, the first end EP1 of each of the light emitting diodes LD may be disposed adjacent to the first electrode ELT1 and the second electrode ELT2. For example, the first end EP1 of each of the light emitting diodes LD may be disposed adjacent to one edge (e.g., the left edge or the right edge) of the first electrode ELT1. The second end EP2 of each of the light emitting diodes LD may be disposed on a side opposite to the first end EP1.

[0159] The first contact electrode CNE1 may be disposed on a substrate SUB on which the light emitting diode LD is disposed. In an embodiment, the first contact electrode CNE1 may be disposed to cover a region of the first electrode ELT1 and the second electrode ELT2 and the first end EP1 of the light emitting diode LD. In some embodiments, the first contact electrode CNE1 may be directly formed on the first electrode ELT1 so that the first contact electrode CNE1 contacts the first electrode ELT1 and the first end EP1 of the light emitting diode LD, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one insulating layer may be disposed between the first electrode ELT1 and the first contact electrode CNE1. The first electrode ELT1 and the first contact electrode CNE1 may be connected to each other through a contact hole (or opening) formed in the insulating layer, etc. The first contact electrode CNE1 may stably support the first end EP1 of the light emitting diode LD and electrically connect the first end EP1 to the first electrode ELT1.

[0160] In an embodiment, the first contact electrode CNE1 may be substantially transparent or translucent. For example, the first contact electrode CNE1 may be formed of a transparent conductive material including ITO or IZO, and may also be made of various known transparent conductive materials. Thus, light generated from each light emitting diode LD may be emitted from the light emitting diode LD through the first contact electrode CNE1.

[0161] The second insulating layer INS2 may be disposed on the substrate SUB on which the first contact electrode CNE1 is formed. For example, the second insulating layer INS2 may be disposed on the first contact electrode CNE1 to at least cover the first contact electrode CNE1. One end of the second insulating layer INS2 may be placed between the first contact electrode CNE1 and the second contact electrode CNE2. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 are reliably separated from each other, so that the electrical stability between the first contact electrode CNE1 and the second contact electrode CNE2 can be ensured. In other words, a short circuit defect between the first contact electrode CNE1 and the second contact electrode CNE2 can be prevented by the second insulating layer INS2.

[0162] In an embodiment, the second insulating layer INS2 may have a single-layer or multi-layer structure including at least one organic layer and / or at least one inorganic layer, and include various known insulating materials. For example, the second insulating layer INS2 may include SiN x At least one inorganic layer is formed, but the present disclosure is not limited thereto. In addition, the second insulating layer INS2 may include the same insulating material as that of the first insulating layer INS1, or include an insulating material different from that of the first insulating layer INS1.

[0163] The second contact electrode CNE2 may be disposed on the substrate SUB on which the second insulating layer INS2 is formed. In an embodiment, the second contact electrode CNE2 may be disposed to cover the second end EP2 of the light emitting diode LD and a region of the second connection electrode CNL2.

[0164] For example, the second contact electrode CNE2 may be disposed on the second end EP2 of the light emitting diode LD so that the second contact electrode CNE2 directly contacts the second end EP2. The second contact electrode CNE2 may be disposed to overlap a region of the second connection electrode CNL2 and thus be electrically connected to the second connection electrode CNL2 and the second electrode ELT2 through at least one contact hole CH0 passing through the first insulating layer INS1. The second contact electrode CNE2 may stably support the second end EP2 of the light emitting diode LD and electrically connect the second end EP2 to the second electrode ELT2.

[0165] In an embodiment, the second contact electrode CNE2 may be substantially transparent or translucent. For example, the second contact electrode CNE2 may be formed of a transparent conductive material including ITO or IZO, and may also be made of various known transparent conductive materials. Thus, light generated from each light emitting diode LD may be emitted from the light emitting diode LD through the second contact electrode CNE2. In addition, the second contact electrode CNE2 may include a conductive material that is the same as that of the first contact electrode CNE1, or include a conductive material that is different from that of the first contact electrode CNE1.

[0166] At least one insulating layer may be disposed on the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. For example, one surface of the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed may be covered with at least one insulating layer. In an embodiment, the at least one insulating layer may include an encapsulation layer ENC (or an overcoat).

[0167] The encapsulation layer ENC may be formed of a single layer or multiple layers. For example, the encapsulation layer ENC may be a thin film encapsulation layer including a plurality of inorganic insulating layers stacked on top of each other and at least one organic insulating layer disposed between the plurality of inorganic insulating layers. However, the constituent material and / or cross-sectional structure of the encapsulation layer ENC are not particularly limited and may be changed in various ways. In an embodiment, the encapsulation layer ENC may be formed to cover at least the display area (e.g., Figure 4 In the embodiment, not only the encapsulation layer ENC but also at least one passivation layer, an optical layer, etc. may be selectively disposed on one surface of the substrate SUB on which the light emitting diode LD, etc. is disposed.

[0168] exist Figure 6 and Figure 7 In the above-mentioned embodiments, the first electrode ELT1 and the second electrode ELT2 are arranged to overlap each other on different layers above the substrate SUB. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged on different layers separated from each other, and the first insulating layer INS1 is placed between the first electrode ELT1 and the second electrode ELT2. In this way, if the first electrode ELT1 and the second electrode ELT2 are separately arranged on different layers, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 can be effectively prevented from occurring in the step of manufacturing the pixel PXL (or the light emitting device).

[0169] In addition, as described in the aforementioned embodiment, if the first electrode ELT1 and the second electrode ELT2 are separately disposed on different layers, the distance between the first electrode ELT1 and the second electrode ELT2, which can be set in consideration of a process margin, etc., can be further reduced compared to the distance between the first electrode ELT1 and the second electrode ELT2 of the pixel of other embodiments (or the light-emitting device of other embodiments) in which the first electrode ELT1 and the second electrode ELT2 are formed on the same layer. For example, in the case of using an embodiment of the present disclosure, the distance between the first electrode ELT1 and the second electrode ELT2 can be reduced to less than 2.5 μm. If the distance between the first electrode ELT1 and the second electrode ELT2 is reduced, the magnitude of the electric field formed between the first electrode ELT1 and the second electrode ELT2 can be further increased even when the voltage applied to the first electrode ELT1 and the second electrode ELT2 is the same as that of the existing case. In addition, the magnitude of the electric field formed between the first electrode ELT1 and the second electrode ELT2 can be easily controlled by adjusting the thickness of the first insulating layer INS1. Therefore, the light-emitting diode LD can be effectively aligned between the first electrode ELT1 and the second electrode ELT2, and the quality of the alignment can be improved. In other words, according to the aforementioned embodiment, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 may be effectively prevented or mitigated, and at least one light emitting diode LD may be effectively and stably arranged between the first electrode ELT1 and the second electrode ELT2.

[0170] In addition, the electric field formed between the first electrode ELT1 and the second electrode ELT2 may have the greatest intensity in the edge region of the first electrode ELT1 and the second electrode ELT2 (e.g., in a plan view, the opposite edges of the first electrode ELT1 and the second electrode ELT2), so that the light emitting diode LD may be effectively arranged on the opposite sides of the first electrode ELT1 and the second electrode ELT2. According to the aforementioned embodiment, even if a size deviation (e.g., a width deviation) of the first electrode ELT1 and the second electrode ELT2 occurs due to a process error or the like, a biased alignment phenomenon in which the light emitting diode LD is biased toward only one electrode may be prevented.

[0171] Figure 8 1 is a plan view illustrating a light emitting device according to an embodiment of the present disclosure (eg, illustrating an example of a pixel PXL including the light emitting device). Figure 9a and Figure 9b Each is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Figure 8 The line II-II' corresponds to different embodiments of the cross section. For example, Figure 9a and Figure 9b Different embodiments are shown in relation to the shape of the partition wall PW. Figures 8 to 9b In the embodiment of Figure 6 to Figure 7 The components of the embodiments are identical or similar to each other, and their detailed description will be omitted.

[0172] Reference Figures 8 to 9b , the pixel PXL (or the light emitting device) may further include at least one partition wall PW. For example, the pixel PXL may include a first partition wall PW1 (or referred to as a "first wall" or a "first bank") disposed under the first electrode ELT1 and the second electrode ELT2 and at least one second partition wall PW2 (or referred to as a "second wall" or a "second bank") disposed under each second contact electrode CNE2. In addition, the pixel PXL may further selectively include a reflective layer REF on each second partition wall PW2.

[0173] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be disposed on the buffer layer BFL at positions spaced apart from each other. In the case where the buffer layer BFL is omitted, etc., the first partition wall PW1 and the second partition wall PW2 may be directly formed on one surface of the substrate SUB. However, the present disclosure is not limited thereto, and the positions of the first partition wall PW1 and the second partition wall PW2 disposed on the layer may be changed in various ways.

[0174] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be disposed on the same layer on the substrate SUB at positions spaced apart from each other by a predetermined distance (or predetermined interval). In addition, the first partition wall PW1 and the second partition wall PW2 may have substantially the same structure, shape and / or height, but the present disclosure is not limited thereto.

[0175] In an embodiment, the first partition wall PW1 may be disposed between the substrate SUB and the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first partition wall PW1 may be disposed between the second electrode ELT2 and the substrate SUB on which the buffer layer BFL is formed. The first partition wall PW1 may be disposed adjacent to the first end EP1 of at least one light emitting diode LD. For example, one side surface of the first partition wall PW1 may be positioned adjacent to the first end EP1 of at least one light emitting diode LD and disposed to face the first end EP1.

[0176] In an embodiment, the second partition wall PW2 may be disposed between the substrate SUB and the second contact electrode CNE2. For example, the second partition wall PW2 may be disposed between the first insulating layer INS1 and the substrate SUB on which the buffer layer BFL is formed. The reflective layer REF may be selectively disposed on the second partition wall PW2. The second partition wall PW2 may be disposed adjacent to the second end EP2 of at least one light emitting diode LD. For example, one side surface of the second partition wall PW2 may be positioned adjacent to the second end EP2 of at least one light emitting diode LD and disposed to face the second end EP2. In addition, at least one reflective layer REF may also be disposed between the second partition wall PW2 and the second contact electrode CNE2. In an embodiment, in the process step of forming the second electrode ELT2, the reflective layer REF may be simultaneously formed of the same material as the material of the second electrode ELT2 (particularly, the reflective electrode layer of the second electrode ELT2), but the present disclosure is not limited thereto.

[0177] The partition walls PW may have various shapes. For example, each partition wall PW may have a trapezoidal cross-section whose width decreases upward, such as Figure 9a In this case, each partition wall PW may have an inclined surface on at least one side surface. In an embodiment, as shown in Figure 9b As shown in , each partition wall PW may have a semicircular or semi-elliptical cross-section whose width gradually decreases upward. In this case, each partition wall PW may have a curved surface on at least one side surface. In other words, in the present disclosure, the shape of the partition wall PW is not particularly limited and may be changed in various ways. In an embodiment, at least one of the partition walls PW (e.g., the first partition wall PW1 and / or the second partition wall PW2) may be omitted, or its position may be changed.

[0178] In an embodiment, each partition wall PW may include an insulating material including an inorganic material or an organic material. Further, each partition wall PW may be formed of a single layer or multiple layers. In other words, in the present disclosure, the constituent material and / or the stacked structure of the partition wall PW are not particularly limited and may be changed in various ways.

[0179] In an embodiment of the present disclosure, each partition wall PW may also serve as a reflective component. For example, each partition wall PW may be used together with a reflective layer REF and / or a first electrode ELT1 and a second electrode ELT2 provided on the partition wall PW as a reflective component for improving the efficiency of light emitted from each light-emitting diode LD.

[0180] The first electrode ELT1, the second electrode ELT2, etc. may be continuously provided on the first partition wall PW1. The reflective layer REF, etc. may be provided on the second partition wall PW2. In an embodiment, the first electrode ELT1, the second electrode ELT2, and the reflective layer REF respectively provided on the first partition wall PW1 and the second partition wall PW2 may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2. For example, the first electrode ELT1, the second electrode ELT2, and the reflective layer REF may have shapes corresponding to the corresponding partition wall PW and may protrude in the height direction of the substrate SUB.

[0181] If, as described above, the first electrode ELT1, the second electrode ELT2, and the reflective layer REF have shapes corresponding to the corresponding partition wall PW, the light emitted from the first end EP1 and the second end EP2 of the light-emitting diode LD may be reflected by the first electrode ELT1, the second electrode ELT2, the reflective layer REF, etc., and thus may travel more effectively in the front direction of the light-emitting device. Thereby, the efficiency of the light emitted from the light-emitting diode LD can be improved.

[0182] Fig.10 is a flowchart showing a method of manufacturing a light-emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a method of manufacturing a light-emitting device according to an embodiment of Figures 8 to 9b of the present disclosure. Hereinafter, a method of manufacturing a light-emitting device (for example, a pixel PXL including a light-emitting device) according to an embodiment of the present disclosure will be described with reference to Figures 8 to 10 A method of manufacturing a light-emitting device (for example, including a pixel PXL of a light-emitting device) according to an embodiment of the present disclosure will be described.

[0183] <ST100: Step of forming a partition wall>

[0184] First, at least one partition wall PW is formed on a surface of the substrate SUB or on a buffer layer BFL provided on a surface of the substrate SUB. For example, a first partition wall PW1 and a second partition wall PW2 may be formed at positions spaced apart from each other on each emission region defined on the substrate SUB (e.g., the emission region of each pixel PXL).

[0185] Although embodiments in which the partition wall PW is directly formed on the substrate SUB or the buffer layer BFL are disclosed in Figures 8 to 10 , the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, a circuit element layer (not shown) may be formed on the substrate SUB or the buffer layer BFL, and the first partition wall PW1 and the second partition wall PW2, the first electrode ELT1 and the second electrode ELT2, the light-emitting diode LD, and / or the first contact electrode CNE1 and the second contact electrode CNE2 may be formed on the circuit element layer. In this case, the process of forming the circuit element layer may be performed before forming the partition wall PW. Additionally, in the case of omitting the partition wall PW as described in the embodiments of Figure 6 and Figure 7 , the step of forming the partition wall may be omitted.

[0186] <ST200: Step of forming a lower electrode>

[0187] Subsequently, a lower electrode is formed on the substrate SUB on which the buffer layer BFL and / or the partition wall PW is formed. For example, the second electrode ELT2 and the second connection electrode CNL2 may be formed on the substrate SUB. Further, in an embodiment, a reflective layer REF or the like may also be formed together with the second electrode ELT2 and the second connection electrode CNL2.

[0188] <ST300: Step of forming a first insulating layer>

[0189] Subsequently, a first insulating layer INS1 is formed on the substrate SUB on which the second electrode ELT2 and the second connection electrode CNL2 are formed. For example, the first insulating layer INS1 may be formed on the substrate SUB to cover at least the second electrode ELT2.

[0190] <ST400: Step of forming an upper electrode>

[0191] Thereafter, an upper electrode is formed on the substrate SUB on which the first insulating layer INS1 is formed. For example, the first electrode ELT1 and the first connection electrode CNL1 may be formed on the substrate SUB. In an embodiment, the first electrode ELT1 may be formed on the first insulating layer INS1 such that the first electrode ELT1 overlaps with the second electrode ELT2, but the present disclosure is not limited thereto.

[0192] <ST500: Step of Supplying and Aligning Light-Emitting Diodes>

[0193] Subsequently, at least one light-emitting diode LD is supplied onto a substrate SUB on which a first electrode ELT1 and a first connection electrode CNL1 are formed, and the light-emitting diode LD is aligned such that one end of the light-emitting diode LD is adjacent to the upper electrode (e.g., the first electrode ELT1). For example, a plurality of light-emitting diodes LD can be supplied onto the substrate SUB by an inkjet printing method or the like, and a predetermined alignment voltage is applied to the first electrode ELT1 and the second electrode ELT2, whereby the light-emitting diode LD can be aligned.

[0194] <ST600: Step of Forming a First Contact Electrode and a Second Contact Electrode>

[0195] Thereafter, the light-emitting diode LD is electrically connected between the lower electrode (e.g., the second electrode ELT2) and the upper electrode (e.g., the first electrode ELT1) by forming a first contact electrode CNE1 and a second contact electrode CNE2 on the substrate SUB on which the light-emitting diode LD is aligned. For example, the light-emitting diode LD can be electrically connected between the first electrode ELT1 and the second electrode ELT2 by forming the first contact electrode CNE1 and forming the second contact electrode CNE2. The first contact electrode CNE1 is configured to electrically connect the first end EP1 of the light-emitting diode LD to the first electrode ELT1, and the second contact electrode CNE2 is configured to electrically connect the second end EP2 of the light-emitting diode LD to the second electrode ELT2.

[0196] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on different layers above the substrate SUB. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed continuously. For example, after forming the first contact electrode CNE1 on the first electrode ELT1, a second insulating layer INS2 can be formed to cover the first contact electrode CNE1. Thereafter, the second contact electrode CNE2 can be formed on the second insulating layer INS2.

[0197] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the same layer of the substrate SUB at positions spaced apart from each other. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed simultaneously.

[0198] <ST700: Step of Forming a Encapsulation Layer>

[0199] Thereafter, an encapsulation layer ENC is formed on the substrate SUB on which the first and second contact electrodes CNE1 and CNE2 are formed, thereby reliably protecting the display element layer including the first and second electrodes ELT1 and ELT2, the light emitting diode LD, the first and second contact electrodes CNE1 and CNE2, and the like.

[0200] Fig.11a 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an embodiment of a pixel PXL including the light emitting device. Fig.11b It shows that according to Fig.11a FIG. 1 is a plan view showing a relative arrangement relationship between the first electrode ELT1 and the second electrode ELT2 and the light emitting diode LD of the embodiment. Fig.12a and Figure 12b Each is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Fig.11a The line III-III' corresponds to different embodiments of the cross section. Figures 11a to 12b In the description of the embodiments, the same reference numerals will be used to denote components similar or equivalent to those of the previous embodiments, and their detailed description will be omitted.

[0201] In an embodiment, Figures 11a to 12b The light emitting device (for example, a pixel PXL of an active light emitting display device) is shown, in which the first electrode ELT1 and / or the second electrode ELT2 are connected to the first power line PL1 and the second power line PL2 respectively through at least one contact hole, or the first electrode ELT1 and / or the second electrode ELT2 are connected to the first power line PL1 and the second power line PL2 via at least one circuit element (for example, included in Figure 5a to Figure 5c At least one transistor in the pixel circuit PXC) is connected to the first power line PL1 or the second power line PL2.

[0202] In an embodiment, Fig.11a The light source unit LSU shown in FIG. 1 may have the same configuration as that according to the above-described embodiments (eg, Figure 8 The configuration of the light emitting device (or pixel PXL) of the embodiment shown in FIG. 1 is substantially similar or identical to that of the embodiment shown in FIG. 1 . Fig.12a and Figure 12b The display element layer LDL shown in FIG. Figure 9a and Figure 9b The cross-section of the light emitting device (or pixel PXL) of the embodiment shown in FIG. 1 is substantially similar or identical to the cross-section of the light emitting device (or pixel PXL) of the embodiment shown in FIG. Figures 11a to 12b In the following description of the embodiments of the present invention, the same reference numerals are used to indicate not only Figures 8 to 9b Components that are equivalent to or similar to the components of the embodiments, and represent components that are identical to or similar to at least one of the above-described embodiments, and a detailed description thereof will be omitted.

[0203] Will refer to Figures 11a to 12b and Figures 4 to 10 The present embodiment is described together. Each pixel PXL may include a display element layer LDL, the display element layer LDL includes a first electrode ELT1 and a second electrode ELT2 disposed on different layers on a substrate SUB and at least one light emitting diode LD electrically connected between the first electrode ELT1 and the second electrode ELT2, and each pixel PXL may also include a circuit element layer PCL disposed under the display element layer LDL. For example, the circuit element layer PCL may be disposed between the substrate SUB and the display element layer LDL.

[0204] In an embodiment, the circuit element layer PCL may include a plurality of circuit elements disposed in the display area DA. For example, the circuit element layer PCL may include a plurality of circuit elements disposed in corresponding pixel regions to form corresponding pixel circuits PXC. In other words, in an embodiment, the circuit element layer PCL may be a pixel circuit layer.

[0205] For example, the circuit element layer PCL may include a plurality of transistors (eg, Figure 5a and Figure 5b a first transistor T1 and a second transistor T2) and at least one capacitor (eg, Figure 5a and Figure 5b In addition, the circuit element layer PCL may further include at least one scan line Si, a data line Dj, a first power line PL1 and / or a second power line PL2.

[0206] In an embodiment, a plurality of transistors (e.g., a first transistor T1 and a second transistor T2) provided in each pixel circuit PXC may have substantially the same or similar cross-sectional structures. However, the present disclosure is not limited thereto. In an embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0207] In addition, the circuit element layer PCL may include a plurality of insulating layers. For example, the circuit element layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV that are sequentially stacked on one surface of the substrate SUB.

[0208] In an embodiment, the buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, the corresponding layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0209] In an embodiment, each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Fig.12a and Figure 12b An embodiment in which each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor forming each pixel circuit PXC may be formed integrally with the corresponding semiconductor layer SCL.

[0210] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the substrate SUB on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region contacting the first transistor electrode ET1, a second region contacting the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0211] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0212] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0213] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode ET1 and the second transistor electrode ET2 and the semiconductor layer SCL and the gate electrode GE. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to the first region and the second region of the semiconductor layer SCL respectively through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0214] In an embodiment, at least one transistor (eg, Figure 5a and Figure 5b Any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 of the passivation layer may be electrically connected to the first electrode ELT1 of the light source unit LSU disposed on the passivation layer PSV through the first contact hole CH1 passing through the passivation layer PSV.

[0215] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be provided on a layer equivalent to a layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, a second power line PL2 for supplying a second power source VSS may be provided on the same layer as a layer of a gate electrode GE of the first transistor T1 and the second transistor T2, and may be electrically connected to a second connection electrode CNL2 and a second electrode ELT2 of a light source unit LSU provided on the passivation layer PSV through a bridge pattern BRP provided on the same layer as a layer of the first transistor electrode ET1 and the second transistor electrode ET2 and through at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2 may be changed in various ways.

[0216] The display element layer LDL is a layer in which the light source unit LSU of each pixel PXL is disposed, and may be, for example, Figures 8 to 9b The light emitting device of the pixel PXL described is constructed in a substantially same or similar manner. For example, the display element layer LDL may include a first electrode ELT1 and a second electrode ELT2 arranged to overlap each other in each pixel region above the circuit element layer PCL, and at least one light emitting diode LD electrically connected between the first electrode ELT1 and the second electrode ELT2. For example, the display element layer LDL may include a plurality of light emitting diodes LD, which are arranged above the circuit element layer PCL in each pixel region and constitute each light source unit LSU. In addition, the display element layer LDL may further include, for example, at least one insulating layer (or insulating pattern) and / or electrode. For example, the display element layer LDL may also include reference Figures 6 to 9b The described embodiment includes at least one of the first and second partition walls PW1 and PW2 , the first and second insulating layers INS1 and INS2 , the first and second contact electrodes CNE1 and CNE2 , and the encapsulation layer ENC.

[0217] In the above-mentioned embodiment, the light source unit LSU of each pixel PXL may be formed of a light emitting device including at least one light emitting diode LD and first and second electrodes ELT1 and ELT2 electrically connected to opposite ends of the light emitting diode LD. Since the light emitting device according to the embodiment of the present disclosure has been described above, a detailed description of each light source unit LSU corresponding to the light emitting device and a display element layer LDL for configuring the light source unit LSU will be omitted.

[0218] In an embodiment, at least one first circuit element and / or at least one line disposed on the circuit element layer PCL may overlap with the first electrode ELT1 and / or the second electrode ELT2 of the display element layer LDL. For example, the first transistor T1 may overlap with the first electrode ELT1 or a region of the first connection electrode CNL1, and thus be electrically connected to the first electrode ELT1 through the first contact hole CH1. Alternatively, in an embodiment, in the case where the first electrode ELT1 is directly connected to the first power line PL1, a region of the first power line PL1 may overlap with the first electrode ELT1 and be electrically connected to the first electrode ELT1 through at least one contact hole.

[0219] In an embodiment, the second power line PL2 may overlap with a region of the second electrode ELT2 or the second connection electrode CNL2, and thus be electrically connected to the second electrode ELT2 through the second contact hole CH2. In an embodiment, the second electrode ELT2 may be connected to the second power line PL2 via at least one second circuit element. In this case, the second circuit element may overlap with a region of the second electrode ELT2 or the second connection electrode CNL2, and thus be electrically connected to the second electrode ELT2 through at least one contact hole.

[0220] In this way, at least the circuit elements and / or lines arranged on the circuit element layer PCL can overlap with at least one electrode and / or light emitting diode LD of the display element layer LDL. If the circuit element layer PCL and the display element layer LDL are arranged to overlap each other, the pixel area with limited area can be used more effectively.

[0221] Fig.13a 1 is a plan view illustrating a light emitting device according to an embodiment of the present disclosure (eg, illustrating an example of a pixel PXL including the light emitting device). Fig.13b It shows that according to Fig.13a FIG. 1 is a plan view showing a relative arrangement relationship between the first electrode ELT1 and the second electrode ELT2 and the light emitting diode LD of the embodiment. Fig.14 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Fig.13a The line IV-IV' corresponds to the cross section of the embodiment. Figures 13a to 14In the description of the embodiments, the same reference numerals will be used to denote components similar or equivalent to those of the previous embodiments, and their detailed description will be omitted.

[0222] Reference Figures 13a to 14 , the first electrode ELT1 and the second electrode ELT2 may have different widths. For example, in a region where at least the first electrode ELT1 and the second electrode ELT2 overlap each other, the second electrode ELT2 may have a width greater than that of the first electrode ELT1 and may be disposed below the first electrode ELT1.

[0223] In an embodiment, the second electrode ELT2 may have a width w2 long enough to overlap with the first electrode ELT1, a plurality of light emitting diodes LD, and a first partition wall PW1 and a second partition wall PW2, wherein the plurality of light emitting diodes LD are disposed adjacent to the first electrode ELT1 so that their respective first ends EP1 face the first electrode ELT1, and the first partition wall PW1 and the second partition wall PW2 are disposed adjacent to the first end EP1 and the second end EP2 of the light emitting diode LD, respectively. However, the present disclosure is not limited thereto, and for example, the width w2 or shape of the second electrode ELT2 may be changed in various ways. For example, in an embodiment, the second electrode ELT2 may have a width w2 greater than the width w1 of the first electrode ELT1, and may be disposed below the first electrode ELT1, and the second electrode ELT2 may have an appropriate width to overlap only with some corresponding portions of the light emitting diode LD disposed on at least one side of the first electrode ELT1. In this case, the second electrode ELT2, together with the first electrode ELT1, may overlap with only one region of each of the light emitting diodes LD, and may not overlap with at least one partition wall (for example, each second partition wall PW2).

[0224] The light emitting diode LD can be set at a self-aligned position by an electric field formed between the first electrode ELT1 and the second electrode ELT2 by a predetermined alignment voltage applied to the first electrode ELT1 and the second electrode ELT2 during the alignment process. The magnitude of the electric field can be changed according to the size of the first electrode ELT1 and the second electrode ELT2 (e.g., the width w1 and w2 or the surface area of ​​the first electrode ELT1 and the second electrode ELT2) and the relative position (e.g., the distance d1 between the corresponding edges of the first electrode ELT1 and the second electrode ELT2, such as the left end or the right end). Therefore, the position where the light emitting diode LD is arranged can be controlled by adjusting the size and position of the first electrode ELT1 and / or the second electrode ELT2.

[0225] Each partition wall PW may be disposed adjacent to either end of each of the light emitting diodes LD. For example, the first partition wall PW1 may be disposed adjacent to the first end EP1 of at least one light emitting diode LD, and the second partition wall PW2 may be disposed adjacent to the second end EP2 of at least one light emitting diode LD. In an embodiment, each partition wall PW may have a cross-section whose width decreases upward, for example, a trapezoidal cross-section, but the present disclosure is not limited thereto. For example, in an embodiment, each partition wall PW may have a cross-section including a curved surface, such as a semicircular or semi-elliptical cross-section, such as Figure 9b and Figure 12b As described in the embodiments shown in FIG.

[0226] In an embodiment, in the case where the second electrode ELT2 has a width w2 long enough to overlap the first partition wall PW1 and the second partition wall PW2, the first partition wall PW1 and the second partition wall PW2 may be disposed below the second electrode ELT2. For example, the first partition wall PW1 and the second partition wall PW2 may be disposed between the second electrode ELT2 and the substrate SUB (or a surface of the substrate SUB on which the buffer layer BFL and / or the circuit element layer PCL are formed). In other words, in an embodiment, the first partition wall PW1 and the second partition wall PW2 may be covered with the second electrode ELT2. In this case, even if not used Figure 9a and Figure 9b The separate reflective layer REF disclosed in the embodiment of the present invention can also more efficiently transmit light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting diodes LD in the front direction. Therefore, the optical efficiency of the light emitting device (or the pixel PXL including the light emitting device) can be improved.

[0227] In an embodiment, in the case where at least one partition wall PW does not overlap the first electrode ELT1 and / or the second electrode ELT2, a separate reflective layer may be disposed on the partition wall PW, for example, Figure 9a and Figure 9b The reflective layer REF disclosed in the embodiment of the present invention. Optionally, in the embodiment, the partition wall PW itself may include a reflective material. Therefore, the optical efficiency of the light emitting device can be improved.

[0228] As described in the aforementioned embodiments, for example, the size and relative position of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways. Adjustment of the size and / or relative position of the first electrode ELT1 and / or the second electrode ELT2 makes it easy to control the magnitude of the electric field formed between the first electrode ELT1 and the second electrode ELT2 during the alignment process of the light emitting diode LD, and makes it easy to control the alignment position of the light emitting diode LD.

[0229] Fig.151 is a plan view illustrating a light emitting device according to an embodiment of the present disclosure (eg, illustrating an example of a pixel PXL including the light emitting device). Fig.16 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, for example, Fig.15 The line V-V' corresponds to the cross section of the embodiment. Fig.15 and Fig.16 In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (for example, Figures 13a to 14 ) are similar or equivalent to the components of the embodiment, and their detailed description will be omitted.

[0230] Reference Fig.15 and Fig.16 , can be omitted Figures 13a to 14 In this case, the first electrode ELT1 or / and the second electrode ELT2 may have a substantially planar shape.

[0231] In an embodiment, the emission area of ​​each pixel PXL (for example, the area in which the light emitting diode LD is supplied and aligned between the first electrode ELT1 and the second electrode ELT2) may be surrounded (or enclosed) by a bank layer, a dam structure, etc., not shown. The bank layer, the dam structure, etc. may include a reflective layer on its surface. Optionally, in an embodiment, a separate light guide structure, a separate reflective structure, etc. may be provided around the light emitting diode LD. According to an embodiment, even in the absence of a first partition wall PW1 and / or a second partition wall PW2, the optical efficiency of the light emitting device may be improved.

[0232] In an embodiment, the light emitting device may further include at least one insulating layer disposed directly on the first electrode ELT1. For example, the light emitting device may further include a third insulating layer INS3 disposed directly on the first electrode ELT1 to cover at least one region of the first electrode ELT1. The light emitting diode LD may be supplied and aligned on a substrate SUB having the third insulating layer INS3 formed thereon. Since the third insulating layer INS3 is formed, the first electrode ELT1 may be prevented from being damaged during a subsequent process after the first electrode ELT1 has been formed.

[0233] The third insulating layer INS3 may partially form an opening on a region of the first electrode ELT1. The first contact electrode CNE1 may be formed to cover an upper portion of at least one region of the first electrode ELT1 including a region where the third insulating layer INS3 forms an opening. Therefore, the first electrode ELT1 may be electrically connected to the first contact electrode CNE1.

[0234] Fig.17a1 is a plan view illustrating a light emitting device according to an embodiment of the present disclosure (eg, illustrating an example of a pixel PXL including the light emitting device). Fig.17b It shows that according to Fig.17a A plan view of the relative arrangement relationship between the first electrode ELT1, the second electrode ELT2 and the light emitting diode LD of the embodiment of FIG. Fig.17a and Fig.17b In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (e.g., Figures 11a to 12b ) are similar or identical components to the components of the embodiment, and their detailed description will be omitted.

[0235] Reference Fig.17a and Fig.17b , the numbers of the first electrodes ELT1 and the second electrodes ELT2 may be different from each other. For example, the number of the second electrodes ELT2 provided in each emission region may be greater than the number of the first electrodes ELT1.

[0236] In an embodiment, some of the second electrodes ELT2 may overlap with the first electrode ELT1, and other second electrodes ELT2 may not overlap with the first electrode ELT1. For example, the second electrode ELT2 may include at least one first sub-electrode ELT2_1 overlapping with each first electrode ELT1 and at least one second sub-electrode ELT2_2 disposed at a position spaced apart from the first electrode ELT1 and the first sub-electrode ELT2_1. For example, the light emitting device may include one first electrode ELT1 and one first sub-electrode ELT2_1 and two second sub-electrodes ELT2_2, the first electrode ELT1 and the first sub-electrode ELT2_1 being disposed to overlap each other in the corresponding emission region, and the two second sub-electrodes ELT2_2 being disposed on opposite sides of the first sub-electrode ELT2_1 at a position spaced apart from the first sub-electrode ELT2_1. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, a plurality of second electrodes ELT2 may be disposed in each emission region, and all second electrodes ELT2 may be disposed not to overlap with the first electrode ELT1.

[0237] In an embodiment, in a plan view, each second sub-electrode ELT2_2 may be disposed at a position spaced apart from the first electrode ELT1 and the first sub-electrode ELT2_1 by a predetermined distance (or interval) d2. In an embodiment, when it is assumed that a plurality of second sub-electrodes ELT2_2 (for example, two second sub-electrodes ELT2_2) are disposed on opposite sides of the first sub-electrode ELT2_1, the plurality of second sub-electrodes ELT2_2 may be disposed at positions spaced apart from the first sub-electrode ELT2_1 by the same or different distances d2. However, the present disclosure is not limited thereto.

[0238] In an embodiment, each light emitting diode LD may be positioned in a horizontal direction between the first electrode ELT1 and the second sub-electrode ELT2_2 in a plan view. For example, each light emitting diode LD may be a rod-type light emitting diode having a first end EP1 and a second end EP2 at respective opposite ends thereof in a length direction. The first end EP1 and the second end EP2 may be disposed toward the first electrode ELT1 and the second sub-electrode ELT2_2, respectively.

[0239] In the aforementioned embodiments, the number and relative positions of the first electrode ELT1 and the second electrode ELT2 (for example, the distance d2 between the first electrode ELT1 and the second sub-electrode ELT2_2 adjacent thereto) can be changed in various ways. Adjustment of the number and / or relative positions of the first electrode ELT1 and / or the second electrode ELT2 makes it easy to control the size of the electric field formed between the first electrode ELT1 and the second electrode ELT2 during the alignment process of the light emitting diode LD, and makes it easy to control the alignment position of the light emitting diode LD.

[0240] Fig.18a 1 is a plan view illustrating a light emitting device according to an embodiment of the present disclosure (eg, illustrating an example of a pixel PXL including the light emitting device). Fig.18b It shows that according to Fig.18a A plan view of the relative arrangement relationship between the first electrode ELT1, the second electrode ELT2 and the light emitting diode LD of the embodiment of FIG. Fig.18a and Fig.18b In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (e.g., Figures 11a to 12b ) are similar or equivalent to the components of the embodiment, and their detailed description will be omitted.

[0241] Reference Fig.18a and Fig.18b , the plurality of first electrodes ELT1 and second electrodes ELT2 may be alternately disposed so as not to overlap each other. For example, the first electrodes ELT1 and the second electrodes ELT2 may be spaced apart from each other by a predetermined distance d3 so as not to overlap each other in a plan view.

[0242] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed in a predetermined emission region at positions spaced apart from each other by a predetermined distance d3 in the first direction DR1. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed in the form of strips extending in the same direction (e.g., in the second direction DR2) and disposed parallel to each other at uniform intervals.

[0243] In the aforementioned embodiment, the first electrode ELT1 and the second electrode ELT2 may be arranged on different layers in the same manner as in the aforementioned embodiment, and at least the first insulating layer INS1 is placed between the first electrode ELT1 and the second electrode ELT2. Therefore, the probability of a short-circuit defect of the first electrode ELT1 and the second electrode ELT2 may be reduced, so that the distance between the first electrode ELT1 and the second electrode ELT2 may also be reduced. For example, the thickness of the first insulating layer INS1 and / or the distance d3 between the first electrode ELT1 and the second electrode ELT2 may be reduced. Therefore, during the process of aligning the light emitting diode LD, the magnitude of the electric field between the first electrode ELT1 and the second electrode ELT2 may be increased, so that the light emitting diode LD may be effectively aligned. In addition, since the positions of the first electrode ELT1 and the second electrode ELT2, the thickness of the first insulating layer INS1 and / or the distance d3 between the first electrode ELT1 and the second electrode ELT2 may be adjusted, not only the magnitude of the electric field formed between the first electrode ELT1 and the second electrode ELT2 during the process of aligning the light emitting diode LD may be easily controlled, but also the alignment position of the light emitting diode LD may be controlled. In other words, according to the aforementioned embodiments, the light emitting diode LD can be easily disposed at a desired position.

[0244] Fig.19a 1 is a plan view illustrating a light emitting device according to an embodiment of the present disclosure (eg, illustrating an example of a pixel PXL including the light emitting device). Fig.19b It shows that according to Fig.19a A plan view of the relative arrangement relationship between the first electrode ELT1, the second electrode ELT2 and the light emitting diode LD of the embodiment of FIG. Fig.19a and Fig.19b In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (e.g., Fig.18a and Fig.18b ) are similar or equivalent to the components of the embodiment, and their detailed description will be omitted.

[0245] Reference Fig.19a and Fig.19b , the second electrode ELT2 may be a curved portion that is angled or bent into a curved shape in an area adjacent to the first electrode ELT1 (for example, in a left edge area adjacent to the first electrode ELT1). In this case, in each emission area, the distance (or interval) between the first electrode ELT1 and the second electrode ELT2 may vary according to the area.

[0246] For example, each emission region in which at least one pair of first electrodes ELT1 and second electrodes ELT2 are provided may include at least one first region ZONE1 and at least one second region ZONE2 sequentially arranged in an extension direction (e.g., second direction DR2) of each of the first electrodes ELT1 and second electrodes ELT2. For example, each emission region may include a plurality of first regions ZONE1 and a plurality of second regions ZONE2 alternately arranged in the second direction DR2.

[0247] In an embodiment, in a plan view, the first electrode ELT1 and the second electrode ELT2 may be disposed in the first zone ZONE1 at positions spaced apart from each other by a first distance ds1, and may be disposed in the second zone ZONE2 adjacent to the first zone ZONE1 at positions spaced apart from each other by a second distance ds2 greater than the first distance ds1. In this case, when a predetermined alignment voltage is applied to the first electrode ELT1 and the second electrode ELT2 during a process of aligning the light emitting diode LD, the electric field between the first electrode ELT1 and the second electrode ELT2 formed in the first zone ZONE1 may be stronger than the electric field between the first electrode ELT1 and the second electrode ELT2 formed in the second zone ZONE2. Therefore, the light emitting diodes LD may be densely disposed in the first zone ZONE1. For example, in the case of ensuring that the first zone ZONE1 is large enough to arrange the light emitting diodes LD supplied to each emission zone, all effective light emitting diodes LD that contribute to actual emission (e.g., light emitting diodes LD that are effectively connected between the first electrode ELT1 and the second electrode ELT2) may be disposed in the first zone ZONE1.

[0248] In the aforementioned embodiment, the distance between the first electrode ELT1 and the second electrode ELT2 in the plan view may be changed according to the region or section. In addition, the first electrode ELT1 and / or the second electrode ELT2 may have a shape corresponding thereto. According to the aforementioned embodiment, since the shape of the first electrode ELT1 and / or the second electrode ELT2 and / or the distance between the first electrode ELT1 and the second electrode ELT2 is set to be changed according to the region, it is not only possible to easily control the size of the electric field between the first electrode ELT1 and the second electrode ELT2 in each region during the process of aligning the light emitting diode LD, but also possible to easily set the light emitting diode LD at a desired position.

[0249] The light-emitting device (e.g., a pixel PXL formed by or including the light-emitting device) according to various embodiments of the present disclosure, a method for manufacturing the light-emitting device, and a display device including the light-emitting device may include a stacked electrode structure. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed on different layers on the substrate SUB and separated from each other, and at least the first insulating layer INS1 is disposed between the first electrode ELT1 and the second electrode ELT2.

[0250] In this way, if the first electrode ELT1 and the second electrode ELT2 are separately disposed on different layers, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 can be effectively prevented from occurring during the process of manufacturing the pixel PXL. In addition, the process margin between the first electrode ELT1 and the second electrode ELT2 can be reduced so that the first electrode ELT1 and the second electrode ELT2 can be disposed closer to each other. According to the above-mentioned embodiment, during the process of aligning the light emitting diode LD, the electric field formed between the first electrode ELT1 and the second electrode ELT2 can be increased so that the light emitting diode LD can be effectively and stably aligned between the first electrode ELT1 and the second electrode ELT2. In addition, since the sizes of the first electrode ELT1 and the second electrode ELT2, the relative arrangement relationship between the first electrode ELT1 and the second electrode ELT2, and / or the thickness of the first insulating layer INS1 can be adjusted, the size of the electric field formed between the first electrode ELT1 and the second electrode ELT2 and the alignment position of the light emitting diode LD can be easily controlled during the process of aligning the light emitting diode LD.

[0251] Although the scope of the present disclosure is described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and modifications may be made here without departing from the scope of the present disclosure defined by the claims.

[0252] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A light emitting device, comprising: substrate; A first electrode and a second electrode are disposed on different layers above the substrate; A first insulating layer is disposed between the first electrode and the second electrode; as well as at least one light emitting diode electrically connected between the first electrode and the second electrode, wherein the first electrode and the second electrode overlap each other in at least one region, and the first electrode and the second electrode are spaced apart from each other by the first insulating layer disposed between the first electrode and the second electrode, wherein the at least one light emitting diode comprises a first end and a second end which are arranged adjacent to the first electrode and the second electrode and are positioned at opposite ends in a length direction of the at least one light emitting diode, and The first end is disposed on one end of the at least one light emitting diode and is configured to face the first electrode and the second electrode, and the second end is disposed on an opposite end of the at least one light emitting diode.

2. The light emitting device according to claim 1, further comprising: a first contact electrode disposed on a first end of the at least one light emitting diode and a region of the first electrode and the second electrode and configured to electrically connect the first end to the first electrode; as well as The second contact electrode is disposed on the second end of the at least one light emitting diode and is configured to electrically connect the second end to the second electrode.

3. The light emitting device according to claim 2, further comprising: a first partition wall disposed between the substrate and the first and second electrodes and positioned adjacent to the first end of the at least one light emitting diode; as well as A second partition wall is disposed between the substrate and the second contact electrode and is positioned adjacent to the second end of the at least one light emitting diode.

4. The light emitting device according to claim 1, in, The first electrode is disposed on the first insulating layer, and Wherein, the second electrode is arranged between the substrate and the first insulating layer to overlap with the first electrode.

5. The light emitting device according to claim 4, wherein: In a region where the first electrode and the second electrode overlap each other, the second electrode has a width greater than that of the first electrode.

6. The light emitting device according to claim 5, in, The first end of the at least one light emitting diode is arranged to face the first electrode, and Wherein, at least one region of the at least one light emitting diode overlaps with the second electrode. 7 . The light emitting device according to claim 4 , further comprising at least one partition wall disposed between the substrate and the second electrode and positioned adjacent to either end of the at least one light emitting diode.

8. The light emitting device according to claim 1, in, The numbers of the first electrodes and the second electrodes are different from each other, and Wherein, the second electrode comprises: a first sub-electrode, overlapping the first electrode; and At least one second sub-electrode is disposed to be spaced apart from the first electrode and the first sub-electrode by a predetermined distance in a plan view.

9. The light emitting device according to claim 8, wherein: The at least one light emitting diode includes a rod-type light emitting diode positioned in a horizontal direction between the first electrode and the second electrode in a plan view.

10. A light emitting device, comprising: substrate; a first electrode and a second electrode, which are disposed on different layers above the substrate and are disposed to be spaced apart from each other by a predetermined distance in a plan view so as not to overlap each other; A first insulating layer is disposed between the first electrode and the second electrode; at least one light emitting diode electrically connected between the first electrode and the second electrode; a first contact electrode disposed on the first electrode and the first end of the at least one light emitting diode and configured to electrically connect the first end to the first electrode; as well as A second contact electrode is disposed on the second electrode and the second end of the at least one light emitting diode and is configured to electrically connect the second end to the second electrode.

11. The light emitting device according to claim 10, wherein: The first electrode and the second electrode have a stripe shape extending in the same direction, and are disposed in parallel with each other at a constant interval.

12. The light emitting device according to claim 10, in, The second electrode includes a bent portion on an edge region of one side adjacent to the first electrode, and The first electrode and the second electrode are disposed at positions spaced apart from each other by a first distance in the first region, and are disposed at positions spaced apart from each other by a second distance greater than the first distance in a second region adjacent to the first region.

13. The light emitting device according to claim 12, wherein: The first region and the second region are sequentially arranged in an extending direction of each of the first electrode and the second electrode.

14. The light emitting device according to claim 12, wherein: The at least one light emitting diode is disposed in the first region.

15. A method for manufacturing a light emitting device, the method comprising the following steps: forming a lower electrode on the substrate; forming a first insulating layer on the substrate to at least cover the lower electrode; forming an upper electrode on the first insulating layer; supplying at least one light emitting diode on the substrate including the lower electrode and the upper electrode, and aligning the at least one light emitting diode to be horizontally oriented in a direction intersecting with an extending direction of the lower electrode and the upper electrode so that one of opposite ends of the at least one light emitting diode in a length direction is adjacent to the upper electrode and the lower electrode; as well as The at least one light emitting diode is electrically connected between the lower electrode and the upper electrode.

16. The method according to claim 15, wherein: The step of electrically connecting the at least one light emitting diode between the lower electrode and the upper electrode includes forming a first contact electrode and a second contact electrode connecting opposite ends of the at least one light emitting diode to the upper electrode and the lower electrode, respectively. 17 . The method according to claim 15 , further comprising forming at least one partition wall on the substrate before the step of forming the lower electrode.

18. A display device, comprising: a substrate including a display area; as well as pixels, arranged in the display area, Wherein, the pixels include: A first electrode and a second electrode are disposed on different layers on the substrate; A first insulating layer disposed between the first electrode and the second electrode; and at least one light emitting diode electrically connected between the first electrode and the second electrode, wherein the first electrode and the second electrode overlap each other in at least one region, and the first electrode and the second electrode are spaced apart from each other by the first insulating layer disposed between the first electrode and the second electrode, wherein the at least one light emitting diode comprises a first end and a second end which are arranged adjacent to the first electrode and the second electrode and are positioned at opposite ends in a length direction of the at least one light emitting diode, and The first end is disposed on one end of the at least one light emitting diode and is configured to face the first electrode and the second electrode, and the second end is disposed on an opposite end of the at least one light emitting diode.

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