A scan chain construction method, device, equipment and storage medium

Abstract

The application provides a scan chain construction method, device and equipment and a storage medium. The method comprises the following steps: selecting any register as a starting register of a scan chain; determining a next-level register of the starting register based on a matching degree of each candidate register and the starting register, wherein the matching degree is determined based on physical position information of the register and path delay information based on clock tree synthesis (CTS); taking the next-level register as a new starting register, and performing the operation of determining the next-level register of the starting register based on the matching degree of each candidate register and the starting register until the next-level register is the last register in the chip; and constructing the scan chain of all registers according to the relationship between the starting register and the next-level register.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuits, specifically to a scan chain construction method, apparatus, device, and storage medium. Background Technology

[0002] As digital chip designs become increasingly large-scale, a certain defect rate exists during the manufacturing process. Design for Testability (DFT) is an important safeguard for screening out defective chips after chip production, and scan testing is one of the most important testing methods in DFT.

[0003] In SCAN testing, a chain formed by connecting registers in the chip using different strategies is called a scan chain. Common scan chain construction methods include clock domain-based chaining, power region-based chaining, and logic hierarchy-based chaining. In specific implementations, one or a combination of these methods can be used.

[0004] However, existing scan chain construction methods do not consider the impact of CTS in the physical implementation on the scan chain, resulting in poor results for the scan chain. For example, if the results are not ideal after CTS, it will cause poor setup / holding timing on the scan chain path, resulting in additional increase in area and power consumption. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for constructing scan chains.

[0006] This application provides a method for constructing a scan chain, characterized by comprising:

[0007] Choose any register as the starting register of the scan chain;

[0008] The next-level register of the starting register is determined based on the matching degree between each candidate register and the starting register; wherein the matching degree is determined by the physical location information and timing information of the register;

[0009] The next-level register is used as the new starting register, and the operation of determining the next-level register of the starting register based on the matching degree between each candidate register and the starting register is performed until the next-level register is the last register in the chip;

[0010] Construct a scan chain that includes all registers based on the relationship between the start register and the next level register.

[0011] This application provides a scanning chain construction apparatus, characterized in that it includes:

[0012] The selection module is configured to select any register as the starting register of the scan chain;

[0013] The next-level register determination module is configured to determine the next-level register of the starting register based on the matching degree between each candidate register and the starting register; wherein the matching degree is determined by the physical location information and timing information of the register;

[0014] The new start register determination module is configured to use the next-level register as the new start register and perform the operation of determining the next-level register of the start register based on the matching degree between each candidate register and the start register, until the next-level register is the last register in the chip;

[0015] The scan chain building module is configured to build a scan chain of all registers according to the relationship between the start register and the next level register.

[0016] This application provides a device, characterized in that it includes:

[0017] One or more processors;

[0018] Memory, used to store one or more programs;

[0019] When the one or more programs are executed by the one or more processors, the one or more processors implement any of the methods in the embodiments of this application.

[0020] This application provides a storage medium storing a computer program, which, when executed by a processor, implements any of the methods described in this application.

[0021] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0022] Figure 1 This is a flowchart of the scan chain construction method provided in the embodiments of this application;

[0023] Figure 2 This is a schematic diagram of the CTS result scanning chain construction method provided in the embodiments of this application;

[0024] Figure 3 This is a SCAN chain flowchart based on the chip physical design CTS results provided in an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the scanning chain construction device provided in the embodiments of this application;

[0026] Figure 5 This is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0028] The basic principle of SCAN testing is to connect all the flip-flops in the chip into a scan chain, then feed them into the chip byte by byte using a pre-designed scan mode. Data capture is then enabled, and the Q output of each flip-flop is fed into the combinational circuit it drives. The data input of the next stage flip-flop in the scan chain captures the output of this combinational circuit. If a fault exists in the circuit, the next stage flip-flop can capture an incorrect value. The captured output data of each stage of the combinational circuit is then shifted out of the scan chain, resulting in a set of result vectors at the scan chain output. This set of result vectors is compared with the pre-calculated expected result, and the comparison result is used to determine whether there is a manufacturing error in the chip.

[0029] In SCAN testing, a chain formed by connecting registers in the chip using different strategies is called a scan chain. Common scan chain construction methods include clock domain-based chaining, power region-based chaining, and logic hierarchy-based chaining. In specific implementations, one or a combination of these methods can be used.

[0030] However, the above scan chain construction method does not take into account the impact of physical design on the SCAN chain. Because the location information of the SCAN register is unknown, the registers of the two levels before and after the SCAN chain may be far apart on the layout. A lot of wiring resources and buffers are needed to solve the problem of long-distance signal transmission, which increases the area and power consumption.

[0031] To address the impact of register location information in advance during SCAN chaining, DCG SCAN, a graphical design editor (DCG) approach, is introduced. This approach involves virtual placement before SCAN chaining, and the physical location information between SCAN registers is considered in advance based on the virtual placement results. This information is then used as input to optimize the SCAN chaining, preventing the physical layout of registers at different levels from becoming too far apart after SCAN chaining, which could lead to routing issues.

[0032] The above chaining method does not consider the impact of CTS in the physical implementation. In particular, the clock tree now adopts clock concurrent optimization (CCOPT) and can theoretically make full use of the clock delay difference between registers. However, if this factor is not taken into account when chaining via SCAN, it may cause mutual interference: that is, SCAN chaining will lead to unsatisfactory CCOPT results, or SCAN chaining after CCOPT will have many hold violations. Even if the physical positions are adjacent, the clock tree results may have a large clock offset, requiring a large number of additional buffers or caches to solve timing problems, which will cause additional increase in area and power consumption. In addition, the virtual routing method still has some consistency differences with the actual routing method in the physical design, which will cause SCAN chaining to not obtain the optimal results when analyzing position information.

[0033] SCAN chains are an essential DFT design circuit in current chips. However, SCAN chains inevitably increase the difficulty of wiring, power consumption, and area. The scan chain construction method based on physical flow provided in this application solves the problem of minimizing the negative impact of scan chain construction on the wiring, area, and power consumption of the design.

[0034] Figure 1 This is a flowchart of a scan chain construction method provided in an embodiment of this application. This method is applicable to SCAN chain scenarios based on physical implementation processes. This method can be executed by the scan chain construction device provided in this application, which can be implemented in software and / or hardware.

[0035] like Figure 1 As shown, the scan chain construction method provided in this application embodiment mainly includes steps S11, S12, S13 and S14.

[0036] S11. Select any register as the starting register of the scan chain.

[0037] S12. Determine the next-level register of the starting register based on the matching degree between each candidate register and the starting register; wherein, the matching degree is determined by the physical location information and timing information of the register.

[0038] S13. Use the next-level register as the new starting register, and perform the operation of determining the next-level register of the starting register based on the matching degree between each candidate register and the starting register, until the next-level register is the last register in the chip.

[0039] S14. Construct a scan chain for all registers according to the relationship between the start register and the next level register.

[0040] In one exemplary implementation, selecting any register as the starting register of the scan chain includes: selecting the register with the smallest clock delay as the starting register of the scan chain.

[0041] In one exemplary implementation, determining the next-level register of the starting register based on the matching degree between each candidate register and the starting register includes: determining an analysis region based on the starting register and a preset length; determining the matching degree between each candidate register in the analysis region and the starting register; and determining the candidate register corresponding to the minimum matching degree as the next-level register of the starting register.

[0042] In one exemplary implementation, determining the analysis region based on the starting register and the preset length includes: defining a circular region centered on the starting register and with a preset length as the radius as the analysis region.

[0043] In an exemplary implementation, determining the matching degree between each candidate register and the starting register in the analysis region includes: for each candidate register, determining the distance and clock delay information between the candidate register and the starting register, as well as the hold time and delay time of the candidate register; and calculating the matching degree between the candidate register and the starting register based on the distance, clock delay information, hold time, and delay time.

[0044] In one exemplary implementation, the clock delay information of the candidate register is the difference between the clock length of the starting register and the clock length of the candidate register, and the clock delay information of the candidate register is determined by the path delay information of the clock tree.

[0045] In one exemplary implementation, before selecting any register as the starting register of the scan chain, the method further includes: synthesizing the clock tree based on the synthesized netlist without a scan chain.

[0046] The technical solution provided in this application can identify the physical location information of each SCAN register, especially the clock tree information, during SCAN chaining. Based on this, the optimal selection of the scan chain structure can be performed, which can significantly reduce the winding difficulty, power consumption and area caused by SCAN logic.

[0047] In an application example, a schematic diagram is provided illustrating a method for constructing a scan chain based on CTS results.

[0048] Figure 2 This is a schematic diagram of the CTS result scanning chain construction method provided in the embodiments of this application, as shown below. Figure 2 As shown,

[0049] SCAN register 1 is selected as the starting register of the scan chain. That is, this register is the starting register. The circle area with the starting register as the center and M as the radius is the analysis area of ​​the candidate registers. SCAN register 2 and SCAN register 3, which are located in this circle area, are the candidate next-level candidate registers of SCAN register 1. SCAN register 4 is not considered as the next-level candidate register of SCAN register 1 because it exceeds the analysis area.

[0050] Calculate the matching degree between SCAN register 2, SCAN register 3, and SCAN register 1. The matching degree is represented by Match_value. The smaller the Match_value, the higher the matching degree. The expression for Match_value is as follows:

[0051] Match_value=(V_distance-V_skew+V_hold-V_delay)

[0052] in,

[0053] V_distance is the distance between the candidate register and the start register, representing the influence of the distance between the start register and the candidate register. It is related to the process and is proportional to the distance.

[0054] V_skew is the clock delay difference between the candidate register and the start register;

[0055] V_hold represents the hold time in the candidate register timing library;

[0056] V_delay represents the delay time in the timing library of the start register, that is, the delay from the clock end to the data end.

[0057] Wherein, V_distance = K * (distance between the start register and the candidate register), where K is the path delay per unit distance of the wire net, which is an estimated value determined by the manufacturing process. The more advanced the manufacturing process, the smaller the value of K.

[0058] V_hold and V_delay can be obtained by looking up the timing library corresponding to the register.

[0059] V_skew = Start register clock length - (Candidate register clock length).

[0060] After completing the calculations, the Match_values ​​obtained from SCAN register 2 and SCAN register 3 are compared, and the smaller one is selected as the next-level candidate register for SCAN register 1. The next-level candidate register is then used as the new starting register to begin a new round of analysis. This process is repeated to gradually complete the order determination of the entire scan chain.

[0061] In one application example, the clock delay difference V_skew between the candidate register and the start register is determined by the CTS result. In the prior art, a scan chain candidate is typically performed before the CTS test; therefore, this application provides a SCAN chaining process based on the results of the chip physical design CTS.

[0062] SCAN chaining is not performed during the netlist generation stage before physical implementation. SCAN chaining analysis is performed after the floor-plan, place, and CTS steps are completed in the physical design to obtain the SCAN chaining order information. Based on this information, the netlist is then chained together, and then the physical design process such as post-routing continues.

[0063] Figure 3 This is a flowchart of the SCAN chain based on the chip physical design CTS results provided in an embodiment of this application, such as... Figure 3 As shown, the main part of this process belongs to the physical implementation. The SCAN chain process based on the chip physical design CTS results includes steps one to seven.

[0064] Step 1: floor_plan, this step mainly involves placing the logic such as IP, memory, and IO;

[0065] Step 2: Pre-scan place. This step mainly involves placing the registers, combinational logic, and other stand cells into appropriate positions.

[0066] Step 3: Pre_scan CTS. The main purpose of this step is to synthesize the clock tree based on the unlinked synthesis netlist.

[0067] Step 4: SCAN Chaining. The main purpose of this step is to chain the SCAN registers into a SCAN chain based on the results of CTS analysis.

[0068] Step 5: Placement. This step is mainly based on the netlist after the SCAN chain and places the stand cells such as registers and combinational logic in appropriate positions.

[0069] Step Six: CTS, this step will synthesize the clock tree based on the netlist after the SCAN chain;

[0070] Step 7: Routing, this step implements physical routing;

[0071] There are other physical design processes following Routing, but they are not the focus of this application and are therefore omitted.

[0072] Figure 4 This is a schematic diagram of the scan chain construction device provided in the embodiments of this application. This device can be applied to the case of SCAN chaining based on a physical implementation process. The scan chain construction device can be implemented by software and / or hardware.

[0073] like Figure 4 As shown, the scan chain construction device provided in this application embodiment mainly includes a selection module 41, a next-level register determination module 42, a new starting register determination module 43, and a scan chain construction module 44.

[0074] Select module 41 is configured to select any register as the starting register of the scan chain;

[0075] The next-level register determination module 42 is configured to determine the next-level register of the starting register based on the matching degree between each candidate register and the starting register; wherein the matching degree is determined by the physical location information and timing information of the register;

[0076] The new start register determination module 43 is configured to use the next-level register as the new start register and perform the operation of determining the next-level register of the start register based on the matching degree between each candidate register and the start register, until the next-level register is the last register in the chip;

[0077] Scan chain building module 44 is configured to build a scan chain of all registers according to the relationship between the start register and the next level register.

[0078] In one exemplary implementation, the selection module 41 is configured to select the register with the smallest clock delay as the starting register of the scan chain.

[0079] In one exemplary embodiment, the next-level register determination module 42 includes an analysis region determination unit, a matching degree determination unit, and a next-level register determination unit, wherein...

[0080] The analysis region determination unit is configured to determine the analysis region based on the start register and a preset length.

[0081] The matching degree determination unit is configured to determine the matching degree between each candidate register and the starting register in the analysis region.

[0082] The next-level register determination unit is configured to determine the next-level register of the candidate register corresponding to the minimum matching degree as the starting register.

[0083] In one exemplary embodiment, the analysis region determination unit is configured to determine a circular region centered on the start register and with a preset length as the radius as the analysis region.

[0084] In one exemplary implementation, the analysis region determination unit is configured to determine, for each candidate register, the distance and clock delay information between the candidate register and the starting register, as well as the hold time and delay time of the candidate register; and calculate the matching degree between the candidate register and the starting register based on the distance, clock delay difference, hold time and hold time.

[0085] In one exemplary implementation, the clock delay information of the candidate register is the difference between the clock length of the starting register and the clock length of the candidate register, and the clock delay information of the candidate register is determined by the path delay information of the clock tree.

[0086] In one exemplary embodiment, the apparatus further includes a clock tree synthesis module configured to synthesize the clock tree based on a synthesis netlist without a built scan chain.

[0087] The technical solution provided in this application can identify the physical location information of each SCAN register, especially the clock tree information, during SCAN chaining. Based on this, the optimal selection of the scan chain structure can be performed, which can significantly reduce the winding difficulty, power consumption and area caused by SCAN logic.

[0088] In one exemplary embodiment, this application also provides a device. Figure 5 This is a schematic diagram of the structure of a device provided in an embodiment of this application, such as... Figure 5 As shown, the device includes a processor 50, a memory 51, an input device 52, and an output device 53; the number of processors 50 in the device can be one or more. Figure 5 Taking a processor 50 as an example; the processor 50, memory 51, input device 52, and output device 53 in the device can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0089] The memory 51, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the scan chain construction method in the embodiments of this application (e.g., the selection module 41, the next-level register determination module 42, the new start register determination module 43, and the scan chain construction module 44 in the scan chain construction device). The processor 50 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 51, thereby implementing the scan chain construction method described above.

[0090] The memory 51 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory 51 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory, or other non-volatile solid-state storage device. In some instances, the memory 51 may further include memory remotely located relative to the processor 50, which can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0091] Input device 52 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the device. Output device 53 may include display devices such as a display screen.

[0092] In one exemplary embodiment, this application also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a scan chain construction method, the method comprising:

[0093] Choose any register as the starting register of the scan chain;

[0094] The next-level register of the starting register is determined based on the matching degree between each candidate register and the starting register; wherein the matching degree is determined by the physical location information and timing information of the register;

[0095] The next-level register is used as the new starting register, and the operation of determining the next-level register of the starting register based on the matching degree between each candidate register and the starting register is performed until the next-level register is the last register in the chip;

[0096] Construct a scan chain that includes all registers based on the relationship between the start register and the next level register.

[0097] Of course, the computer-executable instructions provided in the embodiments of this application are not limited to the method operations described above, but can also execute related operations in the scan chain construction method provided in any embodiment of this application.

[0098] Based on the above description of the implementation methods, those skilled in the art can clearly understand that this application can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0099] It is worth noting that in the embodiments of the above-mentioned scanning chain construction device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of this application.

[0100] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0101] Those skilled in the art will understand that the term user terminal encompasses any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicle-mounted mobile stations.

[0102] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0103] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0104] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored in memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Multifunction Discs, DVDs, or CDs), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (FGPAs), and processors based on multi-core processor architectures.

[0105] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. A scan chain construction method, characterized by, The method comprises the following steps: selecting any register as a starting register of a scan chain; determining an analysis region based on the starting register and a preset length; for each candidate register, respectively determining a distance between the candidate register and the starting register, clock skew information between the candidate register and the starting register, a hold time of the candidate register, and a delay time of the candidate register; wherein the clock skew information is a difference between a clock length of the starting register and a clock length of the candidate register; calculating a matching degree of the candidate register and the starting register according to the distance, the clock skew information, the hold time, and the delay time; determining a next-level register of the starting register as a candidate register corresponding to a minimum matching degree; taking the next-level register as a new starting register, and performing an operation of determining a next-level register of the starting register based on a matching degree of each candidate register and the starting register until the next-level register is a last register in the chip; constructing a scan chain of all registers according to a relationship between the starting register and the next-level register; wherein a calculation formula of the matching degree is as follows: Match_value = (V_distance - V_skew + V_hold - V_delay) wherein Match_value is the matching degree of the candidate register and the starting register, V_distance is the distance between the candidate register and the starting register, V_skew is the clock skew information between the candidate register and the starting register, V_hold is the hold time in a timing library of the candidate register, and V_delay is the delay time in a timing library of the starting register.

2. The method of claim 1, wherein, The selecting any register as the starting register of the scan chain comprises: selecting a register with a minimum clock delay as the starting register of the scan chain.

3. The method of claim 1, wherein, The determining the analysis region based on the starting register and the preset length comprises: determining a circle region with the starting register as a center and a preset length as a radius as the analysis region.

4. The method of claim 1, wherein, The clock skew information of the candidate register is determined by path delay information of a clock tree.

5. The method of claim 1, wherein, Before the selecting any register as the starting register of the scan chain, the method further comprises: performing synthesis of a clock tree based on a comprehensive netlist of which a scan chain is not constructed.

6. A scan chain construction apparatus characterized by comprising: The method comprises the following steps: a selecting module configured to select any register as a starting register of a scan chain; a next-level register determining module configured to determine an analysis region based on the starting register and a preset length; for each candidate register, respectively determine a distance between the candidate register and the starting register, clock skew information between the candidate register and the starting register, a hold time of the candidate register, and a delay time of the candidate register; wherein the clock skew information is a difference between a clock length of the starting register and a clock length of the candidate register; calculate a matching degree of the candidate register and the starting register according to the distance, the clock skew information, the hold time, and the delay time; and determine a next-level register of the starting register as a candidate register corresponding to a minimum matching degree. The new start register determining module is configured to determine the next level register of the start register as a new start register, and perform an operation of determining the next level register of the start register based on a matching degree between each candidate register and the start register until the next level register is the last register in the chip. The scan chain constructing module is configured to construct a scan chain of all registers according to the relationship between the start register and the next level register. The calculation formula of the matching degree is as follows: Match_value=(V_distance-V_skew+V_hold-V_delay) Wherein, Match_value is the matching degree between the candidate register and the start register, V_distance is the distance between the candidate register and the start register, V_skew is the clock delay information between the candidate register and the start register, V_hold is the hold time in the timing library of the candidate register, and V_delay is the delay time in the timing library of the start register.

7. A computer device, comprising: The method comprises the following steps: One or more processors; Memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method of any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method of any one of claims 1-5.

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