Display substrate, display module and display device

Abstract

The present invention provides a display substrate, a display module and a display device, wherein the display substrate has a display area and a test pad area arranged on one side of the display area, and the display substrate comprises: a substrate; at least one pad arranged on the substrate, the pad being located in the test pad area; a first spacing layer arranged on a side of the pad away from the substrate; a plurality of support portions and at least one test signal line located in the test pad area, the support portions and the test signal line being arranged on a side of the first spacing layer away from the substrate, one end of each test signal line being connected to a pad, and the other end being used to be connected to an array test device; wherein at least two of the plurality of support portions are arranged along a first direction, the first direction intersecting with a direction pointing from the display area to the test pad area, each support portion having a support end away from the substrate, the support end protruding from a surface of the test signal line on a side away from the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a display module and a display device. Background Art

[0002] With the development of liquid crystal display technology, narrow-frame or borderless liquid crystal display devices have become the mainstream trend of high-quality display devices. In common narrow-frame or borderless liquid crystal display devices, in order to eliminate the alignment deviation between the color filter substrate and the array substrate, a color filter film is generally made on the array substrate, that is, the COA (Color Filter on Array) technology is used to form a COA substrate. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate, a display module and a display device.

[0004] In order to achieve the above object, the present invention provides a display substrate, wherein the display substrate has a display area and a test pad area arranged on one side of the display area, wherein the display substrate comprises:

[0005] substrate;

[0006] At least one pad is disposed on the substrate, the pad being located in the test pad area;

[0007] A first spacer layer disposed on a side of the pad away from the substrate;

[0008] A plurality of support parts and at least one test signal line located in the test pad area, wherein the support parts and the test signal line are arranged on a side of the first spacing layer away from the substrate, one end of each of the test signal lines is connected to one of the pads, and the other end is used to connect to an array test device;

[0009] Among them, at least two of the multiple supporting parts are arranged along a first direction, which intersects with the direction from the display area to the test pad area, and each of the supporting parts has a supporting end away from the substrate, and the supporting end protrudes from the surface of the test signal line on the side away from the substrate.

[0010] Optionally, at least one first spacer portion is provided on the substrate, and the first spacer portion is located in the test pad area;

[0011] The first spacer layer covers the first spacer portion, and a portion of the first spacer layer opposite to the first spacer portion protrudes in a direction away from the substrate to form the support portion.

[0012] Optionally, a thin film transistor is further disposed on the substrate, and the first spacer portion is disposed in the same layer as an active layer of the thin film transistor.

[0013] Optionally, the first spacer portion includes a plurality of sub-spacer portions that are spaced apart from each other, and the plurality of sub-spacer portions of the same first spacer portion are arranged in a direction from the display area to the test pad area.

[0014] Optionally, the display substrate further comprises: a first electrode, a second electrode and a second spacer layer located in the display area, the first electrode being arranged between the second spacer layer and the substrate, and the second electrode being arranged on a side of the second spacer layer away from the substrate;

[0015] The first spacing layer and the second spacing layer are arranged in the same layer, and the test signal line and the second electrode are arranged in the same layer.

[0016] Optionally, the display substrate further comprises a second spacer portion arranged in the display area, the second spacer portion is located at a side of the second spacing layer away from the substrate, and the support portion and the second spacer portion are arranged in the same layer.

[0017] Optionally, at least a portion of each of the test signal lines is covered by the supporting portion.

[0018] Optionally, the display substrate further comprises a color filter and a thin film transistor located in the display area, the color filter is arranged on a side of the thin film transistor away from the substrate, and the first electrode is arranged on a side of the color filter away from the substrate.

[0019] Optionally, the test signal line is located at a side of the pad away from the display area, and the test signal line extends in a direction from the display area to the test pad area;

[0020] The support portion is in a strip shape, and the extending direction of the support portion is the same as the extending direction of the test signal line; and / or,

[0021] The supporting part is block-shaped.

[0022] Optionally, the display substrate comprises a plurality of the test signal lines, the plurality of the test signal lines are arranged along the first direction, and at least one support portion is disposed on both sides of each of the test signal lines along the first direction.

[0023] Optionally, at least one supporting portion is disposed between any two adjacent test signal lines.

[0024] Optionally, a thin film transistor is also disposed on the substrate.

[0025] The pad includes a first body portion, and the first body portion is arranged at the same layer as the gate of the thin film transistor; and / or,

[0026] The pad includes a second body portion, and the second body portion is arranged in the same layer as the source and drain of the thin film transistor.

[0027] Optionally, the substrate further includes: a first connecting line, one end of the first connecting line is connected to the pad, and the other end of the first connecting line is used to connect to the driving chip.

[0028] Optionally, the substrate includes a plurality of the pads, the plurality of pads include at least one first pad and at least one second pad, and a distance from the first pad to the display area is smaller than a distance from the second pad to the display area;

[0029] In a direction from the display area to the test pad area, each of the first pads overlaps with at least one of the second pads.

[0030] Optionally, the display substrate further comprises: a plurality of columns of sub-pixels and a plurality of data lines located in the display area, the sub-pixels in the same column are connected to the same data line, and each of the sub-pixels is connected to the pad via the data line.

[0031] The present invention also provides a display module, which includes: a frame and the above-mentioned display substrate;

[0032] The frame is supported on the supporting end of the supporting portion, and the orthographic projection of the frame on the display substrate surrounds the display area.

[0033] The present invention further provides a display device, which includes the above-mentioned display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0035] Figure 1a is a plan view showing a substrate in an example;

[0036] Figure 1b for Figure 1a Sectional view along section line BB';

[0037] Figure 1c This is a schematic diagram of an example in which a display substrate and a frame are assembled;

[0038] Figure 2 A schematic plan view of a display substrate provided by an embodiment of the present invention;

[0039] Figure 3a for Figure 2 A cross-sectional view along the section line CC';

[0040] Figure 3b A schematic diagram of an assembly of a display substrate and a frame provided by an embodiment of the present invention;

[0041] Figure 4 A cross-sectional view of a sub-pixel provided by an embodiment of the present invention;

[0042] Figure 5a One of the specific structural schematic diagrams of the test pad area provided by the embodiment of the present invention;

[0043] Figure 5b for Figure 5a Sectional view along section line DD';

[0044] Figure 6a A second schematic diagram of a specific structure of a test pad area provided in an embodiment of the present invention;

[0045] Figure 6b for Figure 6a Sectional view along section line EE';

[0046] Figure 7a A third schematic diagram of the specific structure of the test pad area provided in an embodiment of the present invention;

[0047] Figure 7b for Figure 7a Sectional view along section line FF'. DETAILED DESCRIPTION

[0048] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in the present invention do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0050] Figure 1a FIG. 1 is a plan view showing a substrate in an example. Figure 1a As shown, the COA display substrate has a display area AA and a test pad area ET arranged on one side of the display area AA. A plurality of scan lines GL and a plurality of data lines DL are arranged in the display area AA; the plurality of scan lines GL and the plurality of data lines DL are arranged crosswise to define a plurality of sub-pixels. Exemplarily, every three adjacent sub-pixels along the row direction form a pixel unit, and three adjacent sub-pixels (for example, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B) are used to display different colors. Among them, the sub-pixels in the same row are provided with a scan signal by the same scan line GL, and the sub-pixels in the same column are provided with a data voltage signal by the same data line DL.

[0051] A test signal line TL and a pad Pad are provided in the test pad area ET, and the test signal line TL is connected to the signal line in the display area AA through the pad Pad. For example, the test signal line TL is connected to the data line DL in the display area AA through the pad Pad. Specifically, the pad Pad is connected to the data line DL through a connecting line drawn from the display area AA. When performing an array test, the array test device is connected to the test signal line TL, so that a test signal can be provided to the data line DL in the display area AA through the test signal line TL and the pad Pad to test whether each sub-pixel in the display area AA has a defect.

[0052] Figure 1b for Figure 1a The cross-sectional view along the section line BB' is as follows: Figure 1b As shown, the display substrate comprises: a base substrate 1, a functional film layer 2 arranged on the base substrate 1, and a test signal line TL arranged on a side of the functional film layer 2 away from the base substrate 1. Figure 1c FIG. 1 is a schematic diagram showing the assembly of a display substrate and a frame in an example. Figure 1c As shown, when the frame 3 is assembled with the display substrate, the frame 3 will be directly pressed onto the test signal line TL, and metal parts are provided on the frame 3, which will cause the metal parts on the frame 3 to contact with the test signal line TL, thereby causing a short circuit between different test signal lines TL, and further causing a short circuit between different data lines in the display area AA, resulting in poor display.

[0053] In view of this, an embodiment of the present invention provides a display substrate. Figure 2 A schematic plan view of a display substrate provided by an embodiment of the present invention, such as Figure 2As shown, the display substrate has: a display area AA and a test pad area ET, and the test pad area ET is located on one side of the display area AA. The portion of the display substrate located in the display area AA includes: elements for displaying images, such as thin film transistors, scan lines GL, data lines DL, common electrodes, pixel electrodes, and the like. Figure 3a for Figure 2 Cross-sectional view along section line CC', combined Figure 2 and Figure 3a As shown, the display substrate includes: a substrate 1, a first connecting line CL1 (which will be described in detail below and will not be repeated here) and at least one pad Pad arranged on the substrate 1, a first spacing layer 2 arranged on the side of the pad Pad away from the substrate 1, and a plurality of support portions S and at least one test signal line TL arranged on the side of the first spacing layer 2 away from the substrate 1. Among them, the pad Pad, the plurality of support portions S and the at least one test signal line TL are all located in the test pad area ET, and the pad Pad can be arranged in the same layer as the first connecting line CL1. One end of each test signal line TL is connected to a pad Pad, and the other end is used to connect to the array test device. At least two of the plurality of support portions S are arranged along a first direction, and the first direction intersects with the direction from the display area AA to the test pad area ET. Each support portion 3 has a support end S1 away from the substrate 1, and the support end S1 protrudes from the surface of the side of the test signal line TL away from the substrate 1.

[0054] In the embodiment of the present invention, the pad Pad may be connected to the display signal line in the display area AA, for example, the pad Pad may be connected to the data line DL in the display area AA, and specifically, the pad Pad may be connected to the data line DL via a connecting line. The test signal line TL may be arranged in the same layer as the driving electrode in the display area AA, for example Figure 4 The second electrode 46 will be described in detail below and will not be described here. Figure 3b The schematic diagram of the assembly of the display substrate and the frame provided by the embodiment of the present invention is as follows: Figure 3b As shown, since the supporting end S1 of the supporting portion S is higher than the test signal line TL, after the frame 3 is assembled with the display substrate, the supporting portion S can play a supporting role, thereby separating the test signal line TL from the frame 3, thereby preventing the test signal line TL from contacting the metal parts on the frame 3, avoiding the problem of short circuit of the test signal line TL caused by this, and thus improving the yield of the display product.

[0055] The specific structure of the display substrate of the embodiment of the present invention is described in detail below. Specifically, Figure 2As shown, the display substrate includes multiple rows of scan lines GL and multiple columns of data lines DL located in the display area AA, and the multiple rows of scan lines GL and the multiple columns of data lines DL cross to define multiple sub-pixels. Exemplarily, every three adjacent sub-pixels along the row direction form a pixel unit, and the colors of the multiple sub-pixels in the same pixel unit are different. For example, the same pixel unit includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Among them, the sub-pixels located in the same row are provided with scan signals by the same scan line GL, and the sub-pixels located in the same column are provided with data voltage signals by the same data line DL. The scan line GL is connected to the gate drive circuit, and the data line DL can be connected to the pad Pad through a connecting line.

[0056] In an embodiment of the present invention, the display substrate may be a COA display substrate. Figure 4 A cross-sectional view of a sub-pixel provided in an embodiment of the present invention, such as Figure 4 As shown, each sub-pixel includes: a thin film transistor T arranged on a substrate 1, a first passivation layer 41 covering the thin film transistor T, and a color filter film 42, a second passivation layer 43, a first electrode 44, a second spacer layer 45 and a second electrode 46 arranged in sequence in a direction away from the thin film transistor T.

[0057] In an embodiment of the present invention, the material of the first passivation layer 41 (the second passivation layer 43) may include a silicon compound, for example, silicon oxide, silicon nitride, or silicon oxynitride. Optionally, the thickness of the second passivation layer 43 may be set between 0.5 μm and 3 μm, for example, 1.3 μm to 2 μm. The color filter film 42 may be a red filter film, a green filter film, or a blue filter film. The thickness of the color filter film 42 may be set between 1 μm and 4 μm, for example, 2.7 μm.

[0058] One of the first electrode 44 and the second electrode 46 is a pixel electrode, and the other is a common electrode. Optionally, in an embodiment of the present invention, the first electrode 44 is a common electrode, and the second electrode 46 is a pixel electrode. The first electrode 44 and the second electrode 46 can be made of a light-transmitting material, such as indium tin oxide (ITO). Optionally, the second electrode 46 is a slit electrode, and the first electrode 44 is a plate electrode, so that the first electrode 44 and the second electrode 46 can form an electric field. When the display substrate is used in a display panel, the display substrate is arranged opposite to the box substrate, and a liquid crystal layer is arranged between the display substrate and the box substrate. The electric field formed between the first electrode 44 and the second electrode 46 can deflect the liquid crystal in the liquid crystal layer, thereby adjusting the transmittance of the liquid crystal layer. Optionally, the thickness of the first electrode 44 (the second electrode 46) can be set between 0.01μm and 0.2μm, for example, 0.08μm.

[0059] In some specific embodiments, the first spacer layer 2 and the second spacer layer 45 are arranged in the same layer, and the test signal line TL and the second electrode 46 are arranged in the same layer. It should be noted that "arranged in the same layer" in the embodiments of the present invention means that the two structures are formed by the same material layer through a patterning process, so the two are in the same layer in terms of the stacking relationship; but this does not mean that the distances between the two and the substrate must be the same.

[0060] The material of the second spacer layer 45 includes an insulating material, and the second spacer layer 45 is used to maintain electrical insulation between the first electrode 44 and the second electrode 46. The material of the second spacer layer 45 may include a silicon compound, a metal oxide. For example, the material of the second spacer layer 45 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second spacer layer 45 can be formed as a single layer or a multilayer. Optionally, the thickness of the second spacer layer 45 can be set between 0.1 μm and 1 μm, for example, 0.6 μm.

[0061] In the embodiment of the present invention, the thin film transistor T may be a top gate structure or a bottom gate structure, which is not limited here. Taking the bottom gate structure as an example, the thin film transistor T includes: a gate Gate, a gate insulating layer GI, an active layer ACT, and a source-drain metal layer SD arranged in sequence in a direction away from the substrate 1. Among them, the substrate 1 may be a glass substrate. The source-drain metal layer SD includes a source electrode and a drain electrode, and the source electrode and the drain electrode are spaced apart from each other. The active layer ACT includes a source connection portion connected to the source electrode, a drain connection portion connected to the drain electrode, and a channel portion arranged between the source connection portion and the drain connection portion. The first passivation layer 41 covers the active layer ACT and the source-drain metal layer SD. The second electrode 46 can be connected to the drain of the thin film transistor T through a via hole penetrating the second spacer layer 45, the second passivation layer 43, the color filter film 42 and the first passivation layer 41.

[0062] The material of the gate Gate may include metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the gate Gate may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate Gate may have a single layer or multiple layers. Optionally, the thickness of the gate Gate may be set between 0.1 μm and 1 μm, for example, 0.3 μm.

[0063] The material of the gate insulating layer GI may include silicon compounds and metal oxides. For example, the material of the gate insulating layer GI includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. In addition, the gate insulating layer GI may be a single layer or a multilayer.

[0064] The material of the active layer ACT may include, for example, inorganic semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, oxide semiconductor materials. Both the source connection portion and the drain connection portion may be doped with impurities (e.g., N-type impurities or P-type impurities) with a higher impurity concentration than that of the channel portion. The channel portion is directly opposite to the gate Gate of the thin film transistor T. When the voltage signal loaded by the gate Gate reaches a certain value, a carrier path is formed in the channel portion, thereby turning on the source and drain of the thin film transistor T. Optionally, the thickness of the active layer ACT may be set between 0.05 μm and 0.5 μm, for example, 0.2 μm.

[0065] The material of the source-drain metal layer SD may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The source-drain metal layer SD may be a single layer or multiple layers of metal, for example, Mo / Al / Mo or Ti / Al / Ti. Optionally, the thickness of the source-drain metal layer SD may be set between 0.2 μm and 0.4 μm, for example, 0.3 μm.

[0066] In some specific embodiments, each sub-pixel further includes: a black matrix B, and the black matrix B is located above the thin film transistor T. The black matrix B may be located above or below the first electrode 44. Optionally, in the embodiment of the present invention, the black matrix B is located above the first electrode 44. The color of the black matrix B may be black, so that the light absorption performance of the black matrix B can be enhanced, the reflection of the black matrix B to the external ambient light can be reduced, and the display contrast can be improved.

[0067] In some specific embodiments, the display substrate further includes a second spacer portion PS disposed in the display area AA, the second spacer portion PS being located on a side of the second spacing layer 45 away from the substrate 1 , and the second spacer portion PS being used to maintain the box thickness of the display panel after the display substrate is aligned with the box-aligning substrate.

[0068] In some specific embodiments, the support portion S can be prepared by using a process of a certain film layer in the display area AA, thereby solving the problem of contact between the test signal line TL and the metal parts on the frame 3 while avoiding adding new processes, thereby reducing production costs.

[0069] Figure 5a One of the specific structural schematic diagrams of the test pad area provided by the embodiment of the present invention, Figure 5b for Figure 5a The cross-sectional view along the section line DD', combined with Figure 2 , Figure 4 , Figure 5a and 5b As shown, in some specific embodiments, at least one first spacer portion 13 is provided on the substrate 1, the first spacer portion 13 is located in the test pad area ET, the first spacer layer 2 covers the first spacer portion 13, and the portion of the first spacer layer 2 opposite to the first spacer portion 13 protrudes in a direction away from the substrate 1 to form a support portion S.

[0070] In some specific embodiments, the first spacer 13 can be provided in the same layer as a thick and patterned film layer in the display area AA. Specifically, the first spacer 13 is provided in the same layer as the active layer ACT of the thin film transistor T in the display area AA, and the thickness of the first spacer 13 can be the same as the thickness of the active layer ACT. In this way, the first spacer 13 can be prepared in the test pad area ET while the active layer ACT is prepared in the display area AA by simply adjusting the pattern of the mask plate used to prepare the active layer ACT, and then the support portion S can be obtained without adding a new preparation process.

[0071] In the embodiment of the present invention, since the thickness of the active layer ACT can be set at about 0.2um, and the test signal line TL is set at the same layer as the second electrode 46, and its thickness is generally set at about 0.08um, the thickness of the active layer ACT is significantly greater than the thickness of the test signal line TL. Therefore, after the first spacer layer 2 covers the first spacer portion 13, the thickness of its protruding portion (i.e., the supporting portion) is significantly greater than the thickness of the test signal line TL. In this way, it is only necessary to set the supporting portion S at a suitable position so that the supporting end S1 of the supporting portion S can be protruded from the surface of the test signal line TL away from the substrate. For example, the height difference between the area where the first spacer layer 2 is provided with the supporting portion S and the area where the test signal line TL is provided on the first spacer layer 2 is smaller than the thickness difference between the first spacer portion 13 and the test signal line TL.

[0072] Of course, the first spacer portion 13 may also be disposed in the same layer as other thick and patterned film layers in the display area AA. For example, the first spacer portion 13 is disposed in the same layer as the second passivation layer 43 provided with vias.

[0073] In some specific embodiments, the cross-sectional area of ​​the support portion S gradually increases along a direction approaching the substrate 1 , so that the support portion S can have better stability.

[0074] In some specific embodiments, the test signal line TL is located on the side of the pad Pad away from the display area AA, and the test signal line TL extends in a direction from the display area AA to the test pad area ET. The support portion S is strip-shaped, and the extension direction of the support portion S is the same as the extension direction of the test signal line TL; and / or, the support portion S is block-shaped, for example, the positive projection of the block-shaped support portion S on the substrate 1 is a polygon or a circle. Optionally, the embodiment of the present invention adopts a strip-shaped support portion S.

[0075] In some specific embodiments, there are multiple test signal lines TL, and the multiple test signal lines TL are arranged along the first direction. In the embodiment of the present invention, there is no limitation on the specific number of the support parts S, which can be determined according to actual needs. For example, a support part S can be provided for every N test signal lines TL, where N is a positive integer.

[0076] In some specific embodiments, at least one support portion S is disposed on both sides of each test signal line TL along the first direction C. In this way, no matter which test signal line TL is, support portions S are disposed on both sides thereof, which is beneficial to improving the stability of the support.

[0077] In some specific embodiments, at least one supporting portion S is disposed between any two adjacent test signal lines TL, so as to further improve the supporting stability of the supporting portion S.

[0078] In some specific embodiments, each test signal line TL corresponds to two support parts S. The two support parts S corresponding to each test signal line TL form a groove with the first spacing layer 2. The test signal line TL is located at the bottom of the groove. Different test signal lines TL correspond to different support parts S.

[0079] The pad Pad in the embodiment of the present invention is described below. In some specific embodiments, the pad Pad includes a first body portion, and the first body portion is arranged in the same layer as the gate Gate of the thin film transistor T. In the test pad area ET, the test signal line TL can be connected to the pad Pad through a first via hole penetrating the first spacer layer 2.

[0080] In some other specific embodiments, the pad Pad includes a second body portion, and the second body portion is disposed in the same layer as the source and drain of the thin film transistor T. In the embodiment of the present invention, the pad Pad and the corresponding test signal line TL may also be connected through a via penetrating the film layer therebetween.

[0081] In other specific embodiments, the pad Pad can be a double-layer pad, that is, the pad Pad includes a first main body portion and a second main body portion, the first main body portion is arranged on the same layer as the gate Gate of the thin film transistor T, and the second main body portion is arranged on the same layer as the source and drain metal layer SD of the thin film transistor T. In an embodiment of the present invention, the test signal line TL can be connected to the first main body portion or to the second main body portion, which can be determined according to actual needs and is not limited here.

[0082] In some specific embodiments, the display substrate further includes a first connection line CL1 and an insulating layer 12 disposed in the test pad area ET. The first connection line CL1 is disposed on the substrate 1, one end of the first connection line CL1 is connected to the pad Pad, the other end of the first connection line CL1 is used to connect to the driving chip (IC), and the first connection line CL1 is disposed in the same layer as the gate of the thin film transistor T. The insulating layer 12 and the gate insulating layer GI in the display area AA may be disposed in the same layer.

[0083] In the embodiment of the present invention, the first connection line CL1 is connected to the driver chip, and the driver chip can provide a driving signal to the display signal line in the display area AA through the first connection line CL1 and the pad Pad. For example, the display signal line can be the data line DL mentioned above, or other signal lines, such as the first power line VDD, the second power line VS, or the reference signal line Vint.

[0084] In the embodiment of the present invention, the test pad area ET is divided into a first sub-area ET1 close to the display area AA and a second sub-area ET2 located on a side of the first sub-area away from the display area AA. In the first sub-area ET1, the first connection line CL1 extends along the arrangement direction of the display area AA and the test pad area ET, and the orthographic projections of the test signal line TL and the support portion S on the first spacing layer 2 are both located within the orthographic projection range of the first connection line CL1 on the first spacing layer 2. In the second sub-area ET2, the extension direction of the first connection line CL1 turns to extend along the first direction.

[0085] In the embodiment of the present invention, the first spacer 13 is disposed in the same layer as the active layer ACT, and its material is a semiconductor material. Therefore, the first spacer 13 may interfere with the signal on the first connection line CL1 nearby. To solve this problem, the first spacer 13 can be arranged to be spaced into a plurality of sub-spacers 13a. Specifically, in some specific embodiments, the first spacer 13 includes a plurality of sub-spacers 13a spaced apart, and the plurality of sub-spacers 13a of the same first spacer 13 are arranged in a direction from the display area AA to the test pad area ET.

[0086] like Figure 3a As shown, in the second sub-area ET2, the first spacer portion 13 extends in a direction from the display area AA to the test pad area ET, and the extension direction of the first spacer portion 13 intersects with the extension direction of the plurality of first connection lines CL1. In the embodiment of the present invention, the first spacer portion 13 can be disconnected at the junction of different first connection lines CL1, thereby forming a plurality of sub-spacer portions 13a, thereby reducing the interference of the first spacer portion 13 on the first connection line CL1.

[0087] In some specific embodiments, the display substrate includes a plurality of pads Pad, the plurality of pads Pad include at least one first pad and at least one second pad, and the distance from the first pad to the display area AA is less than the distance from the second pad to the display area AA. In the direction from the display area AA to the test pad area ET, each first pad Pad overlaps with at least one second pad Pad. By adopting the above arrangement, more pads Pad can be arranged in a smaller lateral size, thereby improving space utilization.

[0088] In some specific embodiments, the portion of the substrate 1 located in the display area AA includes multiple columns of sub-pixels and multiple data lines DL, the sub-pixels in the same column are connected to the same data line DL, and each sub-pixel is connected to the pad Pad through the data line DL connected thereto.

[0089] In an embodiment of the present invention, the sub-pixel is connected to the pad Pad via the data line DL. Specifically, the pad Pad is connected to the data line DL in the display area AA via the second connection line CL2 extending from the display area AA. Each pad Pad is connected to at least one data line DL. A gating module (e.g., a thin film transistor) may be provided on the second connection line CL2, and the gating module is configured to control the pad Pad to be turned on or off with the corresponding data line DL according to the received control signal, so that the pad Pad can transmit electrical signals to the plurality of data lines DL in a predetermined order.

[0090] In some specific embodiments, the second connection line CL2 can be led out from the side of the display area AA close to the test pad area ET, or can be led out from the side of the display area AA away from the test pad area ET; when the second connection line CL2 is led out from the side of the display area AA away from the test pad area ET, the second connection line CL2 can extend to the test pad area ET through the frame area located on the left and right sides of the display area AA.

[0091] Figure 6a The second specific structural diagram of the test pad area provided by the embodiment of the present invention is as follows: Figure 6b for Figure 6a The cross-sectional view along the section line EE', combined with Figure 2 , Figure 4 , Figure 6a and Figure 6b As shown, in some other specific embodiments, the support portion S is disposed in the same layer as the second spacer portion PS in the display area AA, and the thickness thereof may be the same as that of the second spacer portion PS.

[0092] In the embodiment of the present invention, the second spacer PS is used to play a supporting role after the display substrate and the box-matching substrate are matched, so as to maintain the distance between the display substrate and the box-matching substrate. The thickness of the second spacer PS can be set between 2μm and 5μm, for example, 3.5μm. Since the thickness of the support portion S set on the same layer as the second spacer PS is the same as that of the second spacer PS, the thickness of the support portion S is much greater than the thickness of the test signal line TL. Therefore, the area where the support portion S is set on the first spacer layer 2 and the area where the test signal line TL is set on the first spacer layer 2 do not need to be at the same height. Therefore, the setting of the support portion S is compared with Figure 5a and Figure 5b The embodiment shown in FIG. 1 is more flexible.

[0093] Figure 7a The third schematic diagram of the specific structure of the test pad area provided by the embodiment of the present invention is as follows: Figure 7b for Figure 7a Sectional view along section line FF', combined with Figure 7a and Figure 7bAs shown, in some specific embodiments, the support portion S is disposed in the same layer as the second spacer portion PS in the display area AA, and at least a portion of each test signal line TL is covered by the support portion S, so that the test signal line TL can be separated from the outside world to prevent the test signal line from being interfered by the outside world. Figure 7a and Figure 7b Although only the support portion S covering the test signal line TL is shown in the figure, it can be understood that, in addition to the support portion S covering the test signal line TL, a support portion S can also be provided between two adjacent test signal lines TL in the embodiment of the present invention.

[0094] It should be noted that Figure 6a to Figure 6b The illustrated embodiments and Figure 7a and Figure 7b The embodiment shown, compared to Figure 5a and Figure 5b For the embodiment shown, except for the different arrangement of the support portion S, the arrangement of the other components can be the same, so it will not be repeated here. Figures 5a to 7b The display substrate provided by the illustrated embodiments does not require changing the number of manufacturing processes of the existing display substrate, thereby reducing production costs.

[0095] The embodiment of the present invention further provides a display module, comprising: a frame and the above-mentioned display substrate. The frame is supported on the supporting end of the supporting part, and the orthographic projection of the frame on the display substrate surrounds the display area.

[0096] In an embodiment of the present invention, as shown in the figure, the frame is supported by the support part, so that the frame is separated from the test signal line on the display substrate, preventing the metal parts on the frame from contacting the test signal line and avoiding the problem of short circuit of the test signal line caused by this.

[0097] The display module also includes a pair of cell substrates arranged opposite to the array substrate, and a liquid crystal layer located between the pair of cell substrates. The second spacer portion arranged on the second spacing layer is supported between the display substrate and the pair of cell substrates to maintain the cell thickness of the liquid crystal layer.

[0098] The present invention also provides a display device, which can be any product or component with display function, such as a vehicle-mounted display device, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc. The display device includes the above-mentioned display module.

[0099] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a display area and a test pad area arranged on one side of the display area, characterized in that: The display substrate comprises: substrate; At least one pad and a first connecting line are arranged on the substrate, the pad and the first connecting line are both located in the test pad area; one end of the first connecting line is connected to the pad; the pad and the first connecting line are arranged in the same layer; A first spacer layer disposed on a side of the pad away from the substrate; A plurality of support parts and at least one test signal line located in the test pad area, wherein the support parts and the test signal line are arranged on a side of the first spacing layer away from the substrate, one end of each of the test signal lines is connected to one of the pads, and the other end is used to connect to an array test device; At least two of the plurality of support portions are arranged along a first direction, the first direction intersects with a direction from the display area to the test pad area, and each of the support portions has a support end away from the substrate, and the support end protrudes from a surface of a side of the test signal line away from the substrate; At least one first spacer portion is disposed on the substrate, and the first spacer portion is located in the test pad area; the first spacer layer covers the first spacer portion, and a portion of the first spacer layer opposite to the first spacer portion protrudes in a direction away from the substrate to form the support portion; The display substrate further comprises a second spacer layer and a second spacer portion arranged in the display area: the first spacer layer and the second spacer layer are arranged in the same layer; the second spacer portion is located on a side of the second spacer layer away from the substrate, and the support portion and the second spacer portion are arranged in the same layer.

2. The display substrate according to claim 1, characterized in that: A thin film transistor is also arranged on the substrate, and the first spacer portion is arranged in the same layer as the active layer of the thin film transistor.

3. The display substrate according to claim 1, characterized in that: The first spacer portion includes a plurality of sub-spacer portions that are spaced apart from each other, and the plurality of sub-spacer portions of the same first spacer portion are arranged in a direction from the display area to the test pad area.

4. The display substrate according to claim 1, characterized in that: The display substrate further comprises: a first electrode and a second electrode arranged in the display area, wherein the first electrode is arranged between the second spacing layer and the substrate, and the second electrode is arranged on a side of the second spacing layer away from the substrate; The test signal line is arranged in the same layer as the second electrode.

5. The display substrate according to claim 4, characterized in that: At least a portion of each of the test signal lines is covered by the supporting portion.

6. The display substrate according to claim 4, characterized in that: The display substrate further comprises a color filter film and a thin film transistor arranged in the display area, the color filter film is arranged on a side of the thin film transistor away from the substrate, and the first electrode is arranged on a side of the color filter film away from the substrate.

7. The display substrate according to claim 1, characterized in that: The test signal line is located at a side of the pad away from the display area, and the test signal line extends in a direction from the display area to the test pad area; The support portion is in a strip shape, and an extending direction of the support portion is the same as an extending direction of the test signal line; and / or, The supporting part is block-shaped.

8. The display substrate according to claim 7, characterized in that: The display substrate comprises a plurality of the test signal lines, the plurality of the test signal lines are arranged along the first direction, and at least one support portion is disposed on both sides of each of the test signal lines along the first direction.

9. The display substrate according to claim 8, characterized in that: At least one supporting portion is disposed between any two adjacent test signal lines.

10. The display substrate according to claim 1, characterized in that: A thin film transistor is also arranged on the substrate. The pad includes a first body portion, and the first body portion is arranged at the same layer as the gate of the thin film transistor; and / or, The pad includes a second body portion, and the second body portion is arranged in the same layer as the source and drain of the thin film transistor.

11. The display substrate according to any one of claims 1 to 9, characterized in that: The other end of the first connecting line is used to connect to the driving chip.

12. The display substrate according to any one of claims 1 to 9, characterized in that: The substrate comprises a plurality of pads, the plurality of pads comprises at least one first pad and at least one second pad, and a distance from the first pad to the display area is smaller than a distance from the second pad to the display area; In a direction from the display area to the test pad area, each of the first pads overlaps with at least one of the second pads.

13. The display substrate according to any one of claims 1 to 9, characterized in that: The display substrate further includes: a plurality of columns of sub-pixels and a plurality of data lines located in the display area, the sub-pixels in the same column are connected to the same data line, and each of the sub-pixels is connected to the pad through the data line.

14. A display module, characterized in that: include: A frame and a display substrate as claimed in any one of claims 1 to 13; The frame is supported on the supporting end of the supporting portion, and the orthographic projection of the frame on the display substrate surrounds the display area.

15. A display device, characterized in that: Comprising the display module as claimed in claim 14.

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