Implementation method and system of a RISC-V instruction set remainder instruction

Abstract

The present application relates to the technical field of microprocessor, and particularly relates to a RISC-V instruction set remainder instruction implementation method and system, the present application is to CPU out-of-order execution, instruction from the instruction fetch unit enters the instruction decoding unit, and instruction decoding is carried out; the instruction after decoding is carried out in the renaming unit and the renaming of the destination register is carried out, and the remainder instruction is optimized; if the remainder instruction does not satisfy the optimization condition, the instruction after renaming enters the reservation station, and then enters the execution unit for execution; the instruction after execution is submitted through the reordering cache, and the division instruction code cache resource allocated in the renaming stage is released. The present application realizes the function of the remainder instruction by increasing the remainder instruction acceleration unit in the renaming stage, when the division and remainder instruction pairing appears, the destination register of the remainder instruction is mapped to the physical register of the division instruction write remainder, the remainder generated by the division instruction is taken, and the remainder instruction execution efficiency is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microprocessors, in particular to a RISC-V instruction set remainder instruction implementation method and system. BACKGROUND

[0002] Microprocessors have undergone vigorous development in architecture along with semiconductor technology over the past 50 years. From single-core to physical multi-core and logical multi-core; from sequential execution to out-of-order execution; from single issue to multi-issue; especially in the server field, the performance of the processor is constantly pursued. With the increasing requirements of data centers and scientific computing, the performance requirements of division and remainder instructions are also increasing, and the proportion of division and remainder instructions in instructions is gradually increasing. The execution period of division and remainder instructions is relatively long, and the execution period is related to data, and the execution period is variable. These factors have a great impact on CPU performance. SUMMARY

[0003] In view of the defects of the prior art, the present application discloses a RISC-V instruction set remainder instruction implementation method and system, which is used to solve the problem that the remainder instruction cannot use the execution result of the division instruction, and each remainder instruction needs to be executed in the execution unit to obtain the remainder. The long execution period of the remainder instruction causes low efficiency.

[0004] The present application is implemented by the following technical solutions:

[0005] In a first aspect, the present application discloses a RISC-V instruction set remainder instruction implementation method, comprising the following steps:

[0006] S1, the CPU executes out of order, and the instruction enters the instruction decoding unit from the instruction fetching unit, and the instruction decoding is performed;

[0007] S2, the instruction after decoding is subjected to register renaming in the renaming unit, and the remainder instruction is optimized;

[0008] S3, if the remainder instruction does not meet the optimization condition, the instruction after renaming enters the reservation station and then enters the execution unit for execution;

[0009] S4, the instruction after execution is submitted through the reordering buffer, and the division instruction encoding buffer resource allocated in the renaming stage is released.

[0010] Further, in the method, when the division and remainder instruction pair appears, the remainder instruction is mapped to the physical register where the division instruction writes the remainder, and the remainder generated by the division instruction is taken.

[0011] Further, in the method, when the remainder instruction appears in the renaming stage, the remainder instruction acceleration unit is searched for the division instruction code cache, if the code of the division instruction matches the code of the remainder instruction successfully, the remainder instruction can be optimized;

[0012] If the code of the division instruction does not match the code of the remainder instruction successfully, the remainder instruction needs to be executed in the execution unit to calculate the remainder.

[0013] Further, in the method, the rule for judging that the remainder instruction does not match successfully is that when the continuous division instructions of different types, the continuous remainder instructions of different types, or the division instruction and the remainder instruction do not match;

[0014] When the division instruction and the remainder instruction are judged to not match, the field of whether the pair is matched in the remainder instruction acceleration unit is set to 0.

[0015] Further, in the method, when the division instruction is written into the division instruction code cache, it is necessary to judge whether there is a free entry, and the information of the division instruction is written into the corresponding entry; when the identifier rem_val of the remainder instruction is valid, it indicates that the current instruction is a remainder instruction, and if the valid bit valid is valid, the remainder instruction matches successfully.

[0016] Further, in the method, the division instruction applies the physical registers div_phy_quo and div_phy_rem in the renaming stage, which are used to store the quotient and the remainder of the division instruction respectively, wherein the div_phy_quo of the division instruction is updated to the destination register renaming mapping table RAT of the division instruction, and the div_phy_rem is stored in the write remainder destination register PHY_REG of the division instruction code cache.

[0017] Further, in the method, when the division instruction enters the renaming stage, when there is no paired remainder instruction, the division instruction writes the division instruction information into the division instruction code cache according to the code; when the division instruction writes the cache, the free position in the cache is found first, and then the code DIV_N_OP of the division instruction, the physical register address div_phy_rem for saving the result of the paired remainder instruction, and the reordering ROB_ID of the division instruction are written into the cache, at this time, the valid bit valid of the division instruction code cache is set to 1.

[0018] When the remainder instruction enters the renaming stage, the remainder instruction code REM_N_OP and the division instruction code DIV_N_OP are matched, and the pairing rule of the division instruction DIV and the remainder instruction REM is checked; if the remainder instruction comparison hits, the mapping relationship of the destination register rem_rd is mapped to rem_phy_reg, and is updated to the destination register renaming mapping table RAT, the remainder instruction execution is completed, the instruction execution completion indication in the reordering buffer is updated, and the division instruction code cache resource is released.

[0019] Further, in the method, when a refresh, a reset, or a subsequent new division instruction or remainder instruction occurs, the physical register applied by the division instruction is released, and the division instruction code cache is released.

[0020] When the division instruction is submitted in the ROB, the ROB_ID of the division instruction is obtained according to the submission pointer cm_ptr, and the ROB_ID is used to search the division instruction code cache; if the division instruction code cache is not released due to an abnormal refresh or a branch instruction prediction error refresh, the position is released in the case of pairing with the remainder instruction;

[0021] When there is an instruction paired with the division instruction being submitted, the paired remainder instruction releases the physical register div_phy_quo; when there is no remainder instruction paired with the division instruction being submitted, the division instruction releases the physical register div_phy_quo and the physical register div_phy_rem.

[0022] Further, in the method, when a remainder instruction is in the renaming stage and the division instruction code cache does not have a matched division instruction, the remainder instruction needs to be sent to the instruction execution unit, the instruction calculates the remainder, and the remainder destination register is updated.

[0023] In a second aspect, the application discloses an implementation system of a remainder instruction of a RISC-V instruction set, which is used to execute the implementation method of the remainder instruction of the RISC-V instruction set, and includes a register, an execution unit, a division unit, an instruction decoding unit and an instruction fetching unit.

[0024] The application has the following beneficial effects:

[0025] In the renaming stage, the application realizes the function of the remainder instruction by adding a remainder instruction acceleration unit; when the division and remainder instruction pairing occurs, the remainder instruction does not need to be sent to the subsequent division execution unit, but is mapped to the physical register of the division instruction writing remainder through the destination register of the remainder instruction, and the remainder generated by the division instruction is taken, so that the execution efficiency of the remainder instruction is high. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0027] Figure 1 is a remainder instruction implementation architecture diagram;

[0028] Figure 2 is a remainder instruction acceleration processing unit diagram;

[0029] Figure 3 is a division instruction execution diagram;

[0030] Figure 4 is a division and remainder instruction adjacent diagram;

[0031] Figure 5 is a division and remainder instruction paired non-adjacent diagram;

[0032] Figure 6 is a division instruction and remainder instruction paired different beat diagram;

[0033] Figure 7 is a division instruction and remainder instruction paired check diagram. DETAILED DESCRIPTION

[0034] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of protection of the present application.

[0035] Embodiment 1

[0036] The present embodiment discloses a new method for implementing a remainder instruction. The method implements the function of the remainder instruction through adding a remainder instruction acceleration unit in the renaming stage, as shown in Figure 1 When the division and remainder instruction pair appears, the remainder instruction does not need to be transmitted to the subsequent division execution unit, but is mapped to the physical register where the remainder of the division instruction is written through the destination register of the remainder instruction, and the remainder generated by the division instruction is taken.

[0037] The embodiment takes specific RISC V instructions as an example for detailed description. In the out-of-order CPU, instructions enter the instruction decoding unit from the instruction fetch unit, and instruction decoding is performed. After decoding, the instructions perform destination register renaming in the renaming unit, and the remainder instruction is optimized in the renaming stage. If the remainder instruction does not meet the optimization condition, the instruction after renaming enters the reservation station, and then enters the execution unit for execution.

[0038] The embodiment mainly focuses on division instructions and remainder instructions. The executed instructions are submitted through the reordering cache, and resources such as division instruction encoding cache allocated in the renaming stage are released, as shown in Figure 1

[0039] The embodiment solves the problem that the remainder instruction cannot use the execution result of the division instruction, and each remainder instruction needs to be executed in the execution unit to obtain the remainder. The long execution period of the remainder instruction causes low efficiency.

[0040] Embodiment 2

[0041] The embodiment generates a new operation code N_OP for the division instruction and the remainder instruction in the instruction decoding stage. For convenience of description, the N_OP encoding of the division and remainder instructions is shown in Table 1.

[0042] Table 1 Division and Remainder Instruction Encoding

[0043]

[0044] In the embodiment, the instructions in Table 1 are mainly taken as examples for description. The division instruction and the remainder instruction can be combined in pairs as follows: 000 and 100, 001 and 101, 010 and 110, and 011 and 111. The encoding of the division instruction in N_OP is called DIV_N_OP, and the encoding of the remainder instruction in N_OP is called REM_N_OP.

[0045] In the embodiment, when the remainder instruction appears in the renaming stage, the division instruction encoding cache in the remainder instruction acceleration unit is searched. If DIV_N_OP and REM_N_OP match successfully, the remainder instruction can be optimized. If DIV_N_OP and REM_N_OP do not match successfully, the remainder instruction needs to be executed in the execution unit to calculate the remainder. The rule for judging that the remainder instruction does not match successfully is that the same type of division instruction is continuous, the same type of remainder instruction is continuous, or the division instruction and the remainder instruction do not match. When the division instruction and the remainder instruction are judged to be unmatched, the pairing field in the remainder instruction acceleration unit is set to 0.

[0046] ​In this embodiment, the division instruction applies for two physical registers div_phy_quo and div_phy_rem in the renaming stage. The two physical registers store the quotient and the remainder of the division instruction respectively. The div_phy_quo of the division instruction is updated to the RAT of the destination register of the division instruction. The div_phy_rem is stored to the PHY_REG of the write remainder destination register of the encoding cache of the division instruction. The new encoding N_OP of the division instruction mapped in Table 1 is written to the DIV_N_OP of the encoding cache of the division instruction. The ROB ID of the division instruction is also written to the ROB_ID field of the encoding cache of the division instruction. When the information of the division instruction is written, the valid is set to be valid, as shown in Figure 2

[0047] In this embodiment, the encoding cache of the division instruction in the remainder instruction acceleration unit stores the division instruction and the related information which need to be paired. When the division instruction is written to the encoding cache of the division instruction, it is needed to determine whether there is a free entry, and write the information of the division instruction to the corresponding entry. When the identifier rem_val of the remainder instruction is valid, it means that the current instruction is the remainder instruction. The encoding REM_N_OP of the remainder instruction matches the encoding DIV_N_OP of the division instruction in the encoding cache of the division instruction. Meanwhile, if the valid bit valid is valid, the remainder instruction is matched successfully, that is, div_rem_hit is 1. The destination register rem_rd of the remainder instruction is mapped to the physical register rem_phy_reg.

[0048] In this embodiment, when the division instruction enters the execution unit of the division, the quotient and the remainder are obtained at the same time. In addition to Forwarding the quotient and the remainder to the early wake-up logic, the quotient and the remainder are also written to the physical register file. The addresses of the writing are div_phy_quo and div_phy_rem respectively. When there is a dependent relationship between the reservation station and the division instruction, by comparing the div_phy_quo and the div_phy_rem, if the physical register addresses match, the data is obtained in advance, and is transmitted to the execution unit for execution in advance.

[0049] Embodiment 3

[0050] This embodiment discloses several cases of the implementation of the division instruction and the remainder instruction. In the first case, the division instruction and the remainder instruction are paired and appear in the same pipeline:

[0051] When the division and the remainder instructions in the pipeline are paired and there is no other instruction between the division and the remainder instructions, the remainder instruction in the paired instruction does not need to be executed, that is, the remainder instruction does not need to be sent to the subsequent pipeline, and the function of the remainder instruction is completely implemented by the paired division instruction, that is, as shown in Figure 4 ​. The adjacent division instruction and the remainder instruction are paired.

[0052] If the paired division instruction and the remainder instruction exist in the pipeline, but there are other instructions between the division instruction and the remainder instruction, the remainder instruction in the paired instruction does not need to be executed, i.e., the remainder instruction does not need to be sent to the subsequent pipeline, and the function of the remainder instruction is completely implemented by the paired division instruction, i.e., as Figure 5 . The paired but non-adjacent division instruction and the remainder instruction.

[0053] The second case is that the division instruction and the remainder instruction are paired, but not in the same beat pipeline:

[0054] When the division instruction enters the renaming stage, if there is no paired remainder instruction in the beat, the division instruction writes the division instruction information into the division instruction encoding cache according to the encoding in Table 1. When the division instruction writes the cache, an idle position is first found in the cache, and then the encoding DIV_N_OP of the division instruction, the physical register address div_phy_rem for saving the result of the paired remainder instruction, and the ROB_ID of the division instruction are written into the cache. The valid bit of the division instruction encoding cache is set to 1.

[0055] When the remainder instruction enters the renaming stage, the remainder instruction encoding REM_N_OP and the division instruction encoding DIV_N_OP are matched and checked. According to the pairing rule of the division instruction DIV and the remainder instruction REM in Table 1, the check is performed. If the remainder instruction is a hit, i.e., div_rem_hit is 1, it means that the remainder required by the remainder instruction can be obtained by the previous division instruction, and the remainder is saved in rem_phy_reg. Therefore, the remainder instruction only needs to map the destination register rem_rd to rem_phy_reg, and update the destination register renaming mapping table RAT. The remainder instruction is executed and does not need to enter the subsequent execution unit for execution. Only the instruction execution completion indication in the reordering buffer is updated, and the division instruction encoding cache resource is released, i.e., valid is set to 0, as shown in Figure 2 . The remainder instruction releases the physical register when it is submitted in the reordering buffer.

[0056] The third case is that the division instruction and the remainder instruction are not paired.

[0057] The division instruction itself cannot determine whether it can be paired with the subsequent remainder instruction, so the division instruction applies for a physical register for the remainder in the renaming stage. When a flush, reset, or subsequent new division instruction or remainder instruction occurs, the physical register applied by the division instruction is released, and the division instruction encoding cache is also released.

[0058] When the division instruction is committed in the ROB, the ROB_ID of the division instruction is obtained according to the commit pointer cm_ptr, and the ROB_ID is used to retrieve the division instruction encoding cache, as shown in Figure 7 . If the division instruction encoding cache is not released due to exception flushing or branch instruction prediction error flushing, the location is the release condition when the remainder instruction is paired. When there is an instruction paired with the division instruction being committed, the division instruction only needs to release the physical register div_phy_quo. The paired remainder instruction will release the physical register div_phy_quo. When there is no remainder instruction paired with the division instruction being committed, the division instruction needs to release the physical register div_phy_quo and the physical register div_phy_rem at the same time.

[0059] The fourth case is that the division instruction and the remainder instruction are not paired, and there is only one remainder instruction:

[0060] When a remainder instruction is in the renaming stage and there is no division instruction matched in the division instruction encoding cache, the remainder instruction needs to be sent to the instruction execution unit, the instruction calculates the remainder, and updates the remainder register. The processing flow of the remainder instruction and other instructions in this case is exactly the same.

[0061] In order to further illustrate the principle, it is assumed that the bandwidth of the CPU is one instruction per clock cycle, and the following table of RISC V instruction sequences is used as an example for illustration.

[0062] Table 1 RISC V instruction sequence

[0063]

[0064]

[0065] Table 2 Write sequence 1 divw division instruction

[0066]

[0067] The divw instruction of sequence number 1 applies for two physical registers div_phy_quo_1 and div_phy_rem_1 when it is renamed. The ROB ID assigned to the divw instruction of sequence number 1 is rob_id_1. The information is written into the division instruction encoding buffer. At the same time, it is marked that the divw instruction has a pair remu instruction, i.e. the pair field is set to 1. Between the instruction of sequence number 1 and the instruction of sequence number 6, there is no remu instruction which is the pair of the divw instruction. When the divw instruction of sequence number 1 is submitted in the ROB, the physical registers div_phy_quo_1 and div_phy_rem_1 are released. The divu instruction of sequence number 6 applies for two physical registers div_phy_quo_2 and div_phy_rem_2 when it is renamed. The ROB ID assigned to the divu instruction of sequence number 6 is rob_id_2. The information is written into the division instruction encoding buffer. At the same time, it is marked that the divw instruction of sequence number 1 has no pair remu instruction, i.e. the pair field is set to 0. The pair field of the divu instruction of sequence number 6 is set to 1.

[0068] Table 3 writes the divu instruction of sequence number 6

[0069]

[0070] The remu instruction of sequence number 9 is found that there is a pair divu instruction in the division instruction encoding buffer when it is renamed, i.e. the divu instruction of sequence number 6. At this time, the remu instruction of sequence number 9 is decoded as a MOV instruction, i.e. the physical register div_phy_rem_2 assigned by the pair divu instruction is mapped to the destination register of the remu instruction of sequence number 9. The remu instruction of sequence number 9 does not need to be sent to the division execution unit for execution. The resource of the divu instruction of sequence number 6 in the division instruction encoding buffer is released.

[0071] Table 4 releases the divu instruction of sequence number 6

[0072]

[0073] The remu instruction of sequence number 16 is found that there is no pair divu instruction in the division instruction encoding buffer when it is renamed. At this time, the instruction needs to be sent to the division execution unit to calculate the remainder.

[0074] The serial number 22 divuw division instruction applies for two physical registers div_phy_quo_3 and div_phy_rem_3 during the renaming. The serial number 22 divuw instruction assigns a ROB_ID as rob_id_3. And writes the information into the division instruction encoding cache. At the same time, it is defaulted that the division instruction has a remainder instruction paired, that is, the pairing field is set to 1.

[0075] Table 5 writes the serial number 22 divuw division instruction

[0076]

[0077] The serial number 25 remu remainder instruction finds that the paired division instruction does not exist in the division instruction encoding cache during the renaming. At this time, the instruction needs to be sent to the division execution unit to calculate the remainder. At the same time, the pairing of the serial number 22 divuw instruction is marked as 0, that is, the instruction does not have a paired remainder instruction.

[0078] Table 6 releases the serial number 22 divuw division instruction

[0079]

[0080] Embodiment 4

[0081] The embodiment discloses an implementation system of a remainder instruction of a RISC-V instruction set, and the system is used for implementing an implementation method of the remainder instruction of the RISC-V instruction set, and includes a register, an execution unit, a division unit, an instruction decoding unit and an instruction fetching unit.

[0082] The application implements the function of the remainder instruction by adding a remainder instruction acceleration unit in the renaming stage. When the division and remainder instruction pairing appears, the remainder instruction does not need to be sent to the subsequent division execution unit, but is mapped to the physical register where the division instruction writes the remainder through the destination register of the remainder instruction, and the remainder generated by the division instruction is taken, so that the remainder instruction has high execution efficiency.

[0083] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing a RISC-V instruction set remainder instruction, the method comprising: The method comprises the following steps: S1, CPU out-of-order execution, instructions from the instruction fetch unit into the instruction decoding unit, instruction decoding; S2, the decoded instructions in the renaming unit for the purpose of the register renaming, while the optimization of the remainder instruction; S3, if the remainder instruction does not meet the optimization condition, the instruction after renaming enters the reservation station, and then enters the execution unit for execution; S4, the executed instructions are submitted through the reordering buffer, and the division instruction encoding cache resources allocated in the renaming stage are released; In the method, when the division and remainder instruction pair appears, the remainder instruction is mapped to the physical register where the remainder of the division instruction is written, and the remainder generated by the division instruction is taken; In the method, when the division instruction enters the renaming stage, if there is no paired remainder instruction, the division instruction writes the division instruction information into the division instruction encoding cache according to the encoding. When the division instruction writes the cache, the idle position in the cache is found first, and then the encoding DIV_N_OP of the division instruction, the physical register address div_phy_rem for saving the result of the paired remainder instruction, and the reordering ROB_ID of the division instruction are written into the cache. At this time, the valid bit valid of the division instruction encoding cache is set to 1; When the remainder instruction enters the renaming stage, the remainder instruction encoding REM_N_OP and the division instruction encoding DIV_N_OP are matched and checked according to the pairing rules of the division instruction DIV and the remainder instruction REM. If the remainder instruction hits, the mapping relationship of the destination register rem_rd is mapped to rem_phy_reg, and is updated to the destination register renaming mapping table RAT. The remainder instruction is executed, the instruction execution completion indication in the reordering buffer is updated, and the division instruction encoding cache resources are released.

2. The method of claim 1, wherein the RISC-V instruction set remainder instruction is implemented as: In the method, when the remainder instruction appears in the renaming stage, the division instruction encoding cache in the remainder instruction acceleration unit is searched. If the encoding of the division instruction and the encoding of the remainder instruction match successfully, the remainder instruction can be optimized; If the encoding of the division instruction and the encoding of the remainder instruction do not match successfully, the remainder instruction needs to be executed in the execution unit to calculate the remainder.

3. The method of claim 2, wherein the RISC-V instruction set remainder instruction is implemented as: In the method, the rule for judging whether the remainder instruction matches successfully is that when the continuous division instructions of different types, the continuous remainder instructions of different types, or the division instruction and the remainder instruction do not match, the pairing field in the remainder instruction acceleration unit is set to 0.

4. The method of claim 1, wherein the RISC-V instruction set remainder instruction is implemented as: In the method, when the division instruction is written into the division instruction encoding cache, it is necessary to judge whether there is an idle entry, and the information of the division instruction is written into the corresponding entry. When the identifier rem_val of the remainder instruction is valid, it indicates that the current instruction is a remainder instruction. If the valid bit valid is valid, the remainder instruction matches successfully.

5. The method of claim 1, wherein the RISC-V instruction set remainder instruction is implemented as: In the method, the division instruction applies for the physical registers div_phy_quo and div_phy_rem in the renaming stage, for storing quotient and remainder of the division instruction respectively, wherein the div_phy_quo of the division instruction is updated to the RAT of the destination register of the division instruction, and the div_phy_rem is stored to the PHY_REG of the write remainder of the encoding buffer of the division instruction.

6. The method of claim 1, wherein the RISC-V instruction set remainder instruction is implemented as: In the method, when a refresh, reset or a new division instruction or remainder instruction occurs subsequently, the physical registers applied for by the division instruction are released, and the encoding buffer of the division instruction is released. When the division instruction is submitted in the ROB, the ROB_ID of the division instruction is obtained according to the submission pointer cm_ptr, and the ROB_ID is used to search the encoding buffer of the division instruction, if the encoding buffer of the division instruction is not released due to abnormal refresh or branch instruction prediction error refresh, then the position of the encoding buffer of the division instruction is released when the remainder instruction is paired; When there is an instruction paired with the division instruction being submitted, the paired remainder instruction releases the physical register div_phy_quo, and when there is no remainder instruction paired with the division instruction being submitted, the division instruction releases the physical register div_phy_quo and the physical register div_phy_rem simultaneously.

7. The method of claim 1, wherein the RISC-V instruction set remainder instruction is implemented as: In the method, when a remainder instruction does not have a division instruction matched in the encoding buffer of the division instruction in the renaming stage, the remainder instruction needs to be sent to the instruction execution unit, the instruction calculates the remainder, and the remainder is updated to the register of the remainder.

8. A system for implementing a RISC-V instruction set remainder instruction, the system configured to perform the method for implementing a RISC-V instruction set remainder instruction according to any one of claims 1-7, wherein The method comprises a register, an execution unit, a division unit, an instruction decoding unit and an instruction fetching unit.

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