Three-dimensional integrated circuit and manufacturing method thereof

Abstract

The present invention relates to a three-dimensional integrated circuit and a manufacturing method thereof. The three-dimensional integrated circuit includes: a memory wafer, a plurality of first power supply lines are provided on a metal layer of the memory wafer, and the plurality of first power supply lines are used to supply power to circuits on the memory wafer; a logic wafer, a plurality of second power supply lines are provided on a metal layer of the logic wafer, and the plurality of second power supply lines are used to supply power to circuits on the memory wafer; wherein each of the plurality of first power supply lines is connected in parallel with a corresponding second power supply line among the plurality of second power supply lines.

Description

Technical Field

[0001] The present invention relates to the field of memories. Specifically, the present invention relates to three-dimensional integrated circuits and manufacturing methods thereof. Background Art

[0002] The process of dynamic random access memory (DRAM) generally provides three metal layers, which greatly limits the power supply routing in high-speed and high-capacity designs. When operating at high speed, the internal circuits of DRAM consume a large amount of current. The limited power supply routing causes excessive voltage drops on the internal power supply lines, deteriorating the timing circuit functions and performance parameters.

[0003] Figure 1 FIG. shows a schematic diagram of the power supply routing of a metal layer in a prior art DRAM wafer. As Figure 1 shown, the DRAM wafer has multiple power pads to introduce external power, and multiple power supply lines with different widths arranged horizontally and vertically are disposed on the metal layer of the DRAM wafer. Figure 1 The power supply lines within the dashed box in FIG. supply power to hundreds of parallel high-frequency signal circuits, and these power supply lines are set as wide conductors. However, due to the wiring limitation of only three metal layers in DRAM, the power supply lines within the dashed box are often insufficient (limited in width), resulting in a large voltage drop between the voltages on these power supply lines and the power supply voltage introduced by the power pads, affecting the timing functions and performance of the circuit.

[0004] Therefore, it is urgent to solve the above technical problems in the prior art. Summary of the Invention

[0005] The present invention relates to three-dimensional integrated circuits, manufacturing methods thereof, and corresponding electronic devices. In the three-dimensional integrated circuit, the power network on the logic process chip is used to improve the voltage drop of the power network on the memory array chip, solving the technical problem of insufficient power supply routing of the memory array chip in the prior art, enabling the circuits within the memory array to operate at a higher frequency and parallelly operate more modules, thereby having better performance.

[0006] According to a first aspect of the present invention, there is provided a three-dimensional integrated circuit, the three-dimensional integrated circuit comprising:

[0007] A memory wafer, wherein a plurality of first power supply lines are provided on the metal layer of the memory wafer, and the plurality of first power supply lines are used to supply power to the circuits on the memory wafer;

[0008] A logic wafer, wherein a plurality of second power supply lines are provided on the metal layer of the logic wafer, and the plurality of second power supply lines are used to supply power to the circuits on the memory wafer;

[0009] Each of the plurality of first power supply lines is connected in parallel with a corresponding one of the plurality of second power supply lines.

[0010] According to a second aspect of the present invention, there is provided an electronic device, wherein the electronic device includes a three-dimensional integrated circuit according to the first aspect described above.

[0011] According to a third aspect of the present invention, there is provided a method of manufacturing a three-dimensional integrated circuit, the method comprising:

[0012] Obtaining a memory wafer, wherein a metal layer of the memory wafer is provided with a plurality of first power supply lines for supplying power to circuits on the memory wafer;

[0013] Obtaining a logic wafer, wherein a metal layer of the logic wafer is provided with a plurality of second power supply lines for supplying power to circuits on the memory wafer; and

[0014] Connecting each of the plurality of first power supply lines in parallel with a corresponding one of the plurality of second power supply lines.

[0015] According to a fourth aspect of the present invention, there is provided an electronic device, wherein the electronic device includes a three-dimensional integrated circuit manufactured by the method according to the third aspect described above. Description of the Drawings

[0016] To better understand the present invention and to show how it may be implemented, reference will now be made to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a power supply wiring of a metal layer of a DRAM wafer in the prior art is shown;

[0018] Figure 2 An example schematic diagram of a power supply network of a three-dimensional integrated circuit according to an embodiment of the present invention is illustrated; and

[0019] Figure 3 An example flowchart of a method of manufacturing a three-dimensional integrated circuit according to an embodiment of the present invention is illustrated. Detailed Description

[0020] The following description sets forth example embodiments in accordance with the present disclosure. Other example embodiments and implementations will be apparent to those of ordinary skill in the art. Additionally, those of ordinary skill in the art will recognize that various equivalent techniques may be applied in lieu of or in combination with the embodiments discussed below, and all such equivalents should be considered to be covered by the present disclosure.

[0021] According to a first aspect of the present invention, there is provided a three-dimensional integrated circuit, comprising:

[0022] A memory die, wherein a metal layer of the memory die is provided with a plurality of first power supply lines for supplying power to circuits on the memory die;

[0023] A logic die, wherein a metal layer of the logic die is provided with a plurality of second power supply lines for supplying power to circuits on the memory die;

[0024] Wherein each of the plurality of first power supply lines is connected in parallel with a corresponding one of the plurality of second power supply lines.

[0025] According to a specific embodiment of the first aspect of the present invention, wherein the first power supply lines of the top metal layer of the memory die and the second power supply lines of the top metal layer of the logic die are hybrid bonded at a plurality of corresponding positions.

[0026] According to a specific embodiment of the first aspect of the present invention, wherein the memory die is a dynamic random access memory die.

[0027] According to an embodiment of the first aspect of the present invention, wherein the logic die is provided with power pins, and the power pins are connected to the second power supply lines of the metal layer of the logic die.

[0028] According to an embodiment of the first aspect of the present invention, wherein at least one of the plurality of first power supply lines is disposed in the top metal layer of the memory and corresponds in position to the second power supply lines that are adjacent to the power pins.

[0029] According to an embodiment of the first aspect of the present invention, wherein the positions of the hybrid bonding include the positions where the second power supply lines adjacent to the power pins are adjacent to the power pins.

[0030] According to a preferred embodiment of the first aspect of the present invention, wherein the first power supply lines of the memory die have an equivalent width of not less than 10 μm. In an embodiment of the present invention, "equivalent width" refers to the width of a power supply line composed of a single wire or the total width of a power supply line composed of a plurality of wires connected in parallel.

[0031] According to an embodiment of the first aspect of the present invention, wherein at least one of the plurality of first power supply lines of the memory die is composed of a plurality of wires connected in parallel. In one embodiment of the present invention, at least one of the plurality of first power supply lines is composed of 4-5 wires with a width of 2.5 μm connected in parallel.

[0032] According to a preferred embodiment of the first aspect of the present invention, the equivalent widths of the plurality of first power supply lines of the memory chip are not greater than the equivalent widths of the corresponding second power supply lines. More preferably, the equivalent widths of the plurality of first power supply lines of the memory chip are the same as the equivalent widths of the corresponding second power supply lines.

[0033] According to an embodiment of the first aspect of the present invention, at least one of the plurality of first power supply lines is disposed at a position where the voltage drop exceeds 10%, preferably 5%, of the power supply voltage when only the internal power supply lines of the memory chip are used as the power supply lines of the memory chip.

[0034] According to a second aspect of the present invention, there is provided an electronic device, wherein the electronic device includes a three-dimensional integrated circuit according to the above first aspect.

[0035] According to a third aspect of the present invention, there is provided a method of manufacturing a three-dimensional integrated circuit, wherein the method includes:

[0036] Obtaining a memory chip, wherein a metal layer of the memory chip is provided with a plurality of first power supply lines for supplying power to circuits on the memory chip;

[0037] Obtaining a logic chip, wherein a metal layer of the logic chip is provided with a plurality of second power supply lines for supplying power to circuits on the memory chip; and

[0038] Connecting each of the plurality of first power supply lines in parallel with a corresponding one of the plurality of second power supply lines.

[0039] According to a specific embodiment of the third aspect of the present invention, the top metal layer of the memory chip is bonded to the top metal layer of the logic chip face to face by hybrid bonding the first power supply lines of the top metal layer of the memory chip and the second power supply lines of the top metal layer of the logic chip at a plurality of corresponding positions to form the three-dimensional integrated circuit.

[0040] According to an embodiment of the third aspect of the present invention, the memory chip is a dynamic random access memory chip.

[0041] According to an embodiment of the third aspect of the present invention, a power supply pin is provided on the logic chip, and the power supply pin is connected to the second power supply line of the metal layer of the logic chip.

[0042] According to an embodiment of the third aspect of the present invention, at least one of the plurality of first power supply lines is disposed in the top metal layer of the memory and corresponds in position to the second power supply line adjacent to the power supply pin.

[0043] According to an embodiment of the third aspect of the present invention, wherein the position of the hybrid bonding includes a position where a second power supply line adjacent to the power supply pins is adjacent to the power supply pins.

[0044] According to an embodiment of the third aspect of the present invention, wherein the first power supply line of the memory chip has an equivalent width of not less than 10 μm.

[0045] According to an embodiment of the third aspect of the present invention, wherein at least one of the plurality of first power supply lines of the memory chip is composed of a plurality of parallel wires.

[0046] According to a preferred embodiment of the third aspect of the present invention, wherein the equivalent widths of the plurality of first power supply lines of the memory chip are not greater than the equivalent widths of the corresponding second power supply lines. More preferably, the equivalent widths of the plurality of first power supply lines of the memory chip are the same as the equivalent widths of the corresponding second power supply lines.

[0047] According to an embodiment of the third aspect of the present invention, wherein at least one of the plurality of first power supply lines is disposed at a position where the voltage drop exceeds 10%, preferably 5%, of the power supply voltage when only the internal power supply line of the memory chip is used as the power supply line of the memory chip.

[0048] According to a fourth aspect of the present invention, there is provided an electronic device, wherein the electronic device includes a three-dimensional integrated circuit manufactured by the method according to the above-mentioned third aspect.

[0049] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0050] Figure 2 A schematic diagram of a power supply network of a three-dimensional integrated circuit according to an embodiment of the present invention is illustrated. Figure 2 The three-dimensional integrated circuit shown therein includes a memory chip 210 (such as a DRAM chip) and a logic chip 220.

[0051] Herein, the logic chip refers to a chip that implements a logic function, and the memory chip is a chip that implements a storage function.

[0052] In addition, to avoid obscuring the gist of the present invention, Figure 2 only the top metal layer of the memory chip 210 and the top metal layer of the logic chip 220 are shown therein, and those skilled in the art should be aware that the memory chip 210 and the logic chip 220 may include multiple metal layers and also include Figure 2 some components not shown therein.

[0053] In Figure 2Among them, the top metal layer of the memory chip 210 includes a plurality of power supply lines arranged horizontally and vertically, and the power supply lines in the area where the dashed box 214 is located are connected to a large number (such as hundreds of parallel signals) of high-frequency (e.g., 300 - 400 MHz) circuits. As in Figure 1 When only the internal power supply lines of the memory chip are used as the power supply lines of the memory chip as shown, the voltage drop of the two vertical power supply lines within the dashed box 214 exceeds 5%, and even 10%, of the power supply voltage compared to the power supply voltage. Therefore, the two vertical power supply lines within the dashed box 214 are set as wider conductors, thereby reducing the resistance of the power supply lines to reduce the voltage drop. In an embodiment of the present invention, the equivalent width of a single wide power supply line is set to be not less than 10 μm. It should be understood that such a wide power supply line can be composed of multiple parallel wires, for example, 3 - 5 parallel 2.5 - 5 μm wires form a single wide power supply line with a total width of not less than 10 μm.

[0054] In Figure 2 In the illustrated embodiment, the top metal layer of the logic chip 220 has the same wide power supply lines as the wide power supply lines of the top metal layer of the memory chip 210. Here, this means that when the top metal layer of the logic chip 220 is flipped and buckled together with the top metal layer of the memory chip 210, some of the wide power supply lines on the top metal layer of the logic chip 220 completely coincide with the wide power supply lines on the top metal layer of the memory chip 210, that is, they are equal in size and corresponding in position. It should be understood that in some embodiments, at least one wide power supply line on the top metal layer of the logic chip 220 is wider than the corresponding wide power supply line on the top metal layer of the memory chip 210. It should be understood that since the logic chip 220 can have 5 - 6 layers of metal wiring, in addition to the wide power supply lines that are the same as those of the top metal layer of the memory chip 210, the top metal layer of the logic chip 220 can also be provided with a plurality of horizontal and vertical wide power supply lines.

[0055] In Figure 2In this case, both the memory chip 210 and the logic chip 220 are provided with hybrid bonding (HB) connection points 212 and 222 at corresponding multiple positions of the wide power supply lines. When the top metal layers of the memory chip 210 and the logic chip 220 are buckled together face to face, the metal layers of the two chips are vertically connected together through the metal vias of the HB connection points. This connects the power supply lines of the top metal layer of the memory chip 210 to the power supply lines of the top metal layer of the logic chip 220, reducing the impedance of the wide power supply line of the top metal layer of the memory chip 210 and improving the voltage drop at this position of the memory chip 210. In addition, it should also be understood that both the memory chip 210 and the logic chip 220 have multiple layers of metal wirings. Among them, the non-top metal layer of the memory chip 210 may also include a power supply line, and this power supply line can be connected in parallel with the top metal layer of the memory chip 210 through a via, and then connected in parallel with the power supply line of the top metal layer of the logic chip 220 through hybrid bonding. Similarly, the power supply line of the non-top metal layer of the logic chip 220 can also be connected in parallel with the power supply line of the top metal layer of the logic chip 220 through a via, and then connected in parallel with the top metal layer of the memory chip 210 through hybrid bonding.

[0056] Different from Figure 1 as shown in Figure 2 In this case, the memory chip 210 does not have power pins provided, while the logic chip 220 is provided with multiple power pins 221, and the power pins 221 are connected to the adjacent power supply lines 223. Since the power supply is introduced into the logic chip 220 through the power supply line 223, the power supply line 223 adjacent to all the multiple power pins 221 is set as a wide wire. In order to optimally introduce the power supply into the memory chip 210, hybrid bonding connection points are provided at the positions where the power supply lines 213 and 223 are adjacent to the multiple power pins 221, so that the power is connected from the pins 221 to the position with a larger voltage drop of the memory chip 210 through the wide wire.

[0057] Figure 3 Illustrates a flowchart of an embodiment of a method for manufacturing a three-dimensional integrated circuit according to the present invention.

[0058] Step 301: Obtain the memory chip 210, and multiple power supply lines for powering the circuits on the memory chip are provided on the metal layer of the memory chip 210.

[0059] Step 302: Obtain the logic chip 220, and multiple power supply lines for powering the circuits on the memory chip are provided on the metal layer of the logic chip 220.

[0060] Step 303: Connect each of the plurality of power supply lines of the memory chip 210 in parallel with a corresponding one of the plurality of power supply lines of the logic chip 220. It should be understood that the parallel connection is achieved by the hybrid bonding described above.

[0061] It should be noted that the above embodiments illustrate rather than limit the present invention, and those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The phrase "comprising" or "including" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may implement the functions of a plurality of units recited in the claims. Any reference signs or labels in the claims should not be construed as limiting their scope.

Claims

1. A three-dimensional integrated circuit, comprising: A memory die, wherein a metal layer of the memory die is provided with a plurality of first power supply lines for supplying power to circuits on the memory die; A logic die, wherein a metal layer of the logic die is provided with a plurality of second power supply lines for supplying power to circuits on the memory die; Wherein each of the plurality of first power supply lines is connected in parallel with a corresponding one of the plurality of second power supply lines.

2. The three-dimensional integrated circuit according to claim 1, wherein The first power supply lines of the top metal layer of the memory die and the second power supply lines of the top metal layer of the logic die are hybrid bonded at a plurality of corresponding positions.

3. The three-dimensional integrated circuit according to claim 1 or 2, characterized in that, The memory die is a dynamic random access memory die.

4. The three-dimensional integrated circuit according to claim 1 or 2, characterized in that, The logic die is provided with power pins connected to the second power supply lines of the metal layer of the logic die.

5. The three-dimensional integrated circuit according to claim 4, wherein At least one of the plurality of first power supply lines is disposed in the top metal layer of the memory and corresponds in position to a second power supply line adjacent to both of the power pins.

6. The three-dimensional integrated circuit according to claim 2, wherein, The positions of the hybrid bonding include positions where the second power supply lines adjacent to both of the power pins are adjacent to the power pins.

7. The three-dimensional integrated circuit according to claim 1 or 2, characterized in that, The first power supply lines of the memory die have an equivalent width of not less than 10 μm.

8. The three-dimensional integrated circuit according to claim 1 or 2, characterized in that, At least one of the plurality of first power supply lines of the memory die is composed of a plurality of parallel wires.

9. The three-dimensional integrated circuit according to claim 1 or 2, characterized in that, The equivalent widths of the plurality of first power supply lines of the memory die are not greater than the equivalent widths of the corresponding second power supply lines.

10. The three-dimensional integrated circuit according to claim 9, wherein The equivalent widths of the plurality of first power supply lines of the memory die are the same as the equivalent widths of the corresponding second power supply lines.

11. The three-dimensional integrated circuit according to claim 1 or 2, characterized in that, At least one of the plurality of first power supply lines is disposed at a position where the voltage drop exceeds 10% of the power supply voltage when only the internal power supply lines of the memory die are used as the power supply lines of the memory die.

12. The three-dimensional integrated circuit according to claim 11, wherein At least one of the plurality of first power supply lines is disposed at a position where the voltage drop exceeds 5% of the power supply voltage when only the internal power supply lines of the memory die are used as the power supply lines of the memory die.

13. An electronic device, characterized in that, The electronic device includes the three-dimensional integrated circuit according to any one of claims 1-12.

14. A method for manufacturing a three-dimensional integrated circuit, characterized in that, The method includes: Obtaining a memory die, wherein a metal layer of the memory die is provided with a plurality of first power supply lines for supplying power to circuits on the memory die; Obtaining a logic die, wherein a metal layer of the logic die is provided with a plurality of second power supply lines for supplying power to circuits on the memory die; and Connecting each of the plurality of first power supply lines in parallel with a corresponding one of the plurality of second power supply lines.

15. The method according to claim 14, wherein By hybrid bonding the first power supply lines of the top metal layer of the memory die and the second power supply lines of the top metal layer of the logic die at a plurality of corresponding positions, the top metal layer of the memory die and the top metal layer of the logic die are joined face to face to form the three-dimensional integrated circuit.

16. The method according to claim 14 or 15, characterized in that The memory die is a dynamic random access memory die.

17. The method according to claim 14 or 15, characterized in that, A power pin is provided on the logic chip, and the power pin is connected to a second power supply line of the metal layer of the logic chip.

18. The method according to claim 17, wherein At least one of the plurality of first power supply lines is provided in the top metal layer of the memory and is positioned corresponding to a second power supply line that is adjacent to all of the power pins.

19. The method according to claim 15, characterized in that The position of the hybrid bonding includes a position where the second power supply line adjacent to all of the power pins is adjacent to the power pins.

20. The method according to claim 14 or 15, characterized in that, The first power supply line of the memory chip has an equivalent width of not less than 10 μm.

21. The method according to claim 14 or 15, characterized in that, At least one of the plurality of first power supply lines of the memory chip is composed of a plurality of parallel wires.

22. The method according to claim 14 or 15, characterized in that, The equivalent widths of the plurality of first power supply lines of the memory chip are not greater than the equivalent width of the corresponding second power supply line.

23. The method according to claim 22, wherein The equivalent widths of the plurality of first power supply lines of the memory chip are the same as the equivalent width of the corresponding second power supply line.

24. The method according to claim 14 or 15, characterized in that At least one of the plurality of first power supply lines is provided at a position where the voltage drop exceeds 10% of the power supply voltage when only the internal power supply line of the memory chip is used as the power supply line of the memory chip.

25. The method according to claim 24, wherein At least one of the plurality of first power supply lines is provided at a position where the voltage drop exceeds 5% of the power supply voltage when only the internal power supply line of the memory chip is used as the power supply line of the memory chip.

26. An electronic device, characterized in that, The electronic device includes a three-dimensional integrated circuit manufactured by the method according to any one of claims 14-25.

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