Display device

Abstract

Embodiments of the present disclosure relate to a display device, in which a planarization layer on a thin film transistor disposed in a display panel is removed to form an opening in the planarization layer, and a top gate electrode is disposed in the opening of the planarization layer, so that the driving performance of the thin film transistor is enhanced while reducing the size of the thin film transistor disposed in the display panel. In addition, the top gate electrode is implemented using an electrode layer located on an upper layer of the planarization layer, and a thin film transistor including a dual gate electrode is easily implemented without additional processing.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0159571, filed on December 4, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device. Background Art

[0004] The development of the information society has led to an increase in demand for display devices that display images and the use of various types of display devices (for example, liquid crystal display devices, organic light emitting display devices, etc.).

[0005] The display device may include a display panel having a plurality of sub-pixels and various signal lines and various driving circuits that provide signals or voltages for driving the sub-pixels. In some cases, the driving circuits may be disposed on the display panel.

[0006] The driving circuit or sub-pixel disposed in the display panel may include various circuit elements, such as thin film transistors, and the size of the thin film transistors may be increased according to the required performance.

[0007] If the size of the thin film transistor disposed in the display panel increases, the frame area of ​​the display panel can be increased, and the aperture ratio in the active area of ​​the display panel can be reduced. Therefore, a method of realizing a thin film transistor with high performance while reducing the area in which the thin film transistor is disposed is needed. Summary of the invention

[0008] Embodiments of the present disclosure provide methods for enhancing driving performance of a thin film transistor disposed on a display panel without increasing the size of the thin film transistor.

[0009] Embodiments of the present disclosure provide a method for enhancing driving performance of a thin film transistor disposed on a display panel without an additional process for enhancing the performance of the thin film transistor.

[0010] According to various embodiments of the present disclosure, a display device includes: a substrate including an active area in which a plurality of sub-pixels are disposed and an inactive area positioned outside the active area; a plurality of thin film transistors disposed on the substrate; and a planarization layer disposed in at least a portion of the inactive area and the active area on the substrate; wherein at least one of the plurality of thin film transistors includes: a first gate electrode on the substrate; a semiconductor layer on the first gate electrode; and a second gate electrode on the semiconductor layer.

[0011] Here, the planarization layer is located in a layer between a layer provided with a second gate electrode and a layer provided with a semiconductor layer, and the planarization layer is provided on at least a portion of a region other than a region where a channel region of the semiconductor layer overlaps with the second gate electrode. And a portion of the second gate electrode may be located on the planarization layer.

[0012] The second gate electrode may be electrically connected to the first gate electrode through a contact hole included in the planarization layer in a region other than a region where the semiconductor layer is disposed.

[0013] Alternatively, the second gate electrode is insulated from the first gate electrode, and the second gate electrode is supplied with the same signal as that supplied to the first gate electrode.

[0014] According to various embodiments of the present disclosure, a display device includes: a plurality of first gate lines; a plurality of semiconductor layers, the plurality of semiconductor layers being located on the first gate lines and overlapping with a portion of the first gate lines; a planarization layer, which is located on the semiconductor layer and is disposed on an area other than at least a portion of an area where the semiconductor layer is disposed; and a plurality of second gate lines, the plurality of second gate lines being located on the semiconductor layer and the planarization layer and overlapping with at least a portion of an area where the first gate lines and the semiconductor layer overlap.

[0015] According to various embodiments of the present disclosure, a display device includes: a substrate; a plurality of thin film transistors disposed on the substrate; a planarization layer disposed on the thin film transistors and including at least one opening located in a region overlapping with the thin film transistors; and a plurality of auxiliary electrode patterns disposed in the openings included in the planarization layer and on portions of a region on the planarization layer.

[0016] According to various embodiments of the present disclosure, a planarization layer disposed on a channel region of a thin film transistor including a bottom gate electrode is removed, and a top gate electrode is disposed on that region, thereby realizing a thin film transistor with high performance while reducing an area in which the thin film transistor is disposed.

[0017] Furthermore, a top gate electrode of the thin film transistor is implemented using one of the electrode layers located on the planarization layer, and therefore, the driving performance of the thin film transistor can be enhanced without adding a separate process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a view schematically showing a configuration of a display device according to various embodiments of the present disclosure;

[0020] Figure 2 is a view showing an example of a structure in which a thin film transistor according to various embodiments of the present disclosure is provided in a display panel;

[0021] Figure 3 and Figure 4 is a view showing an example of a structure connecting a bottom gate electrode and a top gate electrode of a thin film transistor according to various embodiments of the present disclosure;

[0022] Figure 5 is a view showing another example of a structure in which a thin film transistor according to various embodiments of the present disclosure is provided in a display panel;

[0023] Figure 6 , Figure 7 and Figure 8 is a view showing an example in which a thin film transistor according to various embodiments of the present disclosure is implemented in an inactive area of ​​a display panel;

[0024] Fig. 9 is a view showing an example in which a thin film transistor according to various embodiments of the present disclosure is implemented in an active area of ​​a display panel;

[0025] Fig.10 is along Fig. 9 A cross-sectional view taken along lines I-I' and J-J';

[0026] Fig.11 is a view showing another example in which a thin film transistor according to various embodiments of the present disclosure is implemented in an active area of ​​a display panel;

[0027] Fig.12 is along Fig.11 A cross-sectional view taken along line K-K'; and

[0028] Fig.13 is a view showing another example in which a thin film transistor according to various embodiments of the present disclosure is implemented in an active area of ​​a display panel. DETAILED DESCRIPTION

[0029] In the following description of the examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, wherein specific examples or embodiments that can be implemented are shown by way of illustration, and wherein, even when reference numerals and symbols are shown in drawings that are different from each other, the same reference numerals and symbols may be used to represent the same or similar parts. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that the description may make the subject matter in some embodiments of the present disclosure unclear, the detailed description of the known functions and parts incorporated herein will be omitted. The terms used herein, for example, "including", "having", "containing", "constituting", "made up of" and "formed of" are generally intended to allow the addition of other parts, unless the term is used together with the term "only". As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0030] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding elements from other elements.

[0031] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be interpreted that the first element may not only be “directly connected or coupled to” the second element or “directly contact or overlaps” the second element, but also a third element may be “inserted” between the first and second elements, or the first and second elements may be “connected or coupled to” each other, “contacts or overlaps” each other, etc. via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to” each other, “contacts or overlaps” each other, etc.

[0032] When time-related terms such as "after", "subsequent to", "next", "before", etc. are used to describe the processing or operation of an element or configuration, or the process or steps in an operation, process, or manufacturing method, these terms may be used to describe non-continuous or non-sequential processing or operations, unless the terms "directly" or "immediately" are used together.

[0033] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no relevant description is specified. In addition, the term "may" fully includes all meanings of the term "can".

[0034] Figure 1 1 is a view schematically illustrating a configuration of a display device 100 according to various embodiments of the present disclosure.

[0035] Reference Figure 1 The display device 100 may include a display panel 110 including an active area AA and a non-active area NA, a gate driving circuit 120 , a data driving circuit 130 , and a controller 140 for driving the display panel 110 .

[0036] The display panel 110 may include a plurality of gate lines GL, a plurality of data lines DL, and sub-pixels SP at intersections of the gate lines GL and the data lines DL.

[0037] The gate driving circuit 120 may be controlled by the controller 140 to continuously output scanning signals to a plurality of gate lines GL disposed in the display panel 110 , thereby controlling a driving timing of the sub-pixels SP.

[0038] The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs). The gate driving circuit 120 may be positioned on only one side of the display panel 110 or on each of two opposing sides, depending on the driving scheme.

[0039] Each gate driver integrated circuit (GDIC) may be connected to a bonding pad of the display panel 110 through a tape automated packaging (TAB) scheme or a chip on glass (COG) scheme, or may be directly disposed on the display panel 110 by being implemented as a GIP (gate in panel) type, and in some cases, may be integrated and disposed on the display panel 110. In addition, each gate driver integrated circuit (GDIC) may be implemented through a chip on film (COF) scheme in which each gate driver integrated circuit (GDIC) is mounted on a film connected to the display panel 110.

[0040] The data driving circuit 130 receives image data from the controller 140 and converts the image data into analog data voltages. The data driving circuit 130 outputs data voltages to each data line DL according to the timing of applying a scan signal through the gate line GL, thereby allowing each subpixel SP to represent brightness according to the image data.

[0041] The data driving circuit 130 may include one or more source driver integrated circuits (SDICs).

[0042] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0043] Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 through a tape automated packaging (TAB) scheme or a chip on glass (COG) scheme, or may be directly disposed on the display panel 110, and in some cases, may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented through a chip on film (COF) scheme, in which case each source driver integrated circuit (SDIC) may be mounted on a film connected to the display panel 110 and electrically connected to the display panel 110 through wiring on the film.

[0044] The controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130 , and controls operations of the gate driving circuit 120 and the data driving circuit 130 .

[0045] The controller 140 is mounted on a printed circuit board, a flexible printed circuit, or the like, and is electrically connected to the gate driving circuit 120 and the data driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0046] The controller 140 enables the gate driving circuit 120 to output a scanning signal according to a timing for implementing each frame, converts image data received from the outside to meet a data signal format used by the data driving circuit 130 , and outputs the resulting image data to the data driving circuit 130 .

[0047] The controller 140 receives various timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal IDE, and a clock signal, as well as image data from the outside (eg, a host system).

[0048] The controller 140 may generate diverse control signals using timing signals received from the outside, and output the control signals to the gate driving circuit 120 and the data driving circuit 130 .

[0049] As an example, in order to control the gate driving circuit 120 , the controller 140 outputs various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE.

[0050] The gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits (GDICs) constituting the gate driving circuit 120. The gate shift clock GSC is a clock signal generally input to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. The gate output enable signal GOE indicates timing information about one or more gate driver integrated circuits (GDICs).

[0051] In order to control the data driving circuit 130 , the controller 140 outputs various data control signals DCS including, for example, a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE.

[0052] The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the data driving circuit 130. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0053] The display device 100 may further include a power management integrated circuit that supplies various voltages or currents to, for example, the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 , or controls various voltages or currents to be supplied.

[0054] Each sub-pixel SP may be a region defined by the intersection of the gate line GL and the data line DL, and liquid crystal or a light emitting element may be disposed in the sub-pixel SP according to the type of the display device 100 .

[0055] For example, when the display device 100 is a liquid crystal display device, the display device 100 includes a light source device such as a backlight unit that provides light to the display panel 110, and liquid crystals are arranged in the sub-pixels SP. The display device 100 controls the arrangement of the liquid crystals by an electric field formed when a data voltage is supplied to each sub-pixel SP, and the display device 100 can display an image by representing brightness according to video data.

[0056] For another example, when the display device 100 is an organic light emitting display device, an organic light emitting diode (OLED) and various circuit elements may be disposed on a plurality of sub-pixels SP. The display device 100 controls current supplied to the organic light emitting diode (OLED) disposed in the sub-pixels SP, and each sub-pixel SP may represent brightness corresponding to video data.

[0057] Alternatively, the light emitting element provided in the sub-pixel SP may be a light emitting diode (LED) or a micro light emitting diode (μLED).

[0058] The sub-pixels or the driving circuit may include a plurality of thin film transistors for driving the sub-pixels SP, etc. Also, if the size of the thin film transistor is increased to enhance the driving performance of the thin film transistor, the aperture ratio of the sub-pixel SP may be reduced or the area of ​​the non-active region NA may be increased.

[0059] According to various embodiments of the present disclosure, a method is provided to enhance the driving performance of a thin film transistor while reducing the size of the thin film transistor without additional processing.

[0060] Figure 2 1 is a view showing an example of a structure in which a thin film transistor according to various embodiments of the present disclosure is provided in the display panel 110 .

[0061] Reference Figure 2 , the thin film transistor may be a thin film transistor disposed on the active area AA or the non-active area NA.

[0062] For example, the thin film transistor according to various embodiments of the present disclosure may include the first gate electrode GE1 as a bottom gate electrode and the second gate electrode GE2 as a top gate electrode.

[0063] Here, the second gate electrode GE2 may be implemented using an electrode layer disposed on a planarization layer PAC, which is disposed after the semiconductor layer ACT of the thin film transistor and the like are disposed.

[0064] Specifically, the first gate electrode GE1 may be disposed on the substrate SUB, and the first gate insulating layer GI1 may be disposed on the first gate electrode GE1. In some cases, the first gate insulating layer GI1 may include two or more layers, for example, may be SiN x 、SiO 2 Equi-stacked structure.

[0065] The semiconductor layer ACT may be disposed on the first gate insulating layer GI1 , and the source electrode SE and the drain electrode DE may be disposed on the semiconductor layer ACT.

[0066] The second gate insulating layer GI2 may be disposed on the source electrode SE and the drain electrode DE. Similar to the first gate insulating layer GI1, in some cases, the second gate insulating layer GI2 may include two or more layers, which may be SiN x 、SiO 2 Equi-stacked structure.

[0067] A planarization layer PAC may be disposed on the second gate insulating layer GI2 .

[0068] The planarization layer PAC may include at least one opening OA in a region corresponding to the thin film transistor.

[0069] For example, the opening OA included in the planarization layer PAC may be located in a region overlapping with the semiconductor layer ACT of the thin film transistor or in a region including a region overlapping with the semiconductor layer ACT. Alternatively, the opening OA of the planarization layer PAC may be located in a region overlapping with the channel region of the semiconductor layer ACT of the thin film transistor.

[0070] Here, for example, the channel region of the semiconductor layer ACT may mean a region where the semiconductor layer ACT overlaps the first gate electrode GE1 .

[0071] Since the opening OA of the planarization layer PAC is located in the region corresponding to the thin film transistor, the planarization layer PAC may be removed in the region corresponding to the thin film transistor. Therefore, a portion of the second gate electrode GE2 disposed under the planarization layer PAC may be exposed by the opening OA of the planarization layer PAC.

[0072] And the second gate electrode GE2 may be disposed on the second gate insulating layer GI2 in the opening OA of the planarization layer PAC.

[0073] The second gate electrode GE2 may be provided using an electrode layer provided on an upper layer of the planarization layer PAC.

[0074] For example, the second gate electrode GE2 may be provided using the same material as the common electrode COM or the pixel electrode PXL provided on the upper layer of the planarization layer PAC. That is, the second gate electrode GE2 may be provided on the same layer as the pixel electrode PXL or the common electrode COM.

[0075] Therefore, the second gate electrode GE2 may be disposed on the semiconductor layer ACT without adding a separate process or electrode layer.

[0076] The second gate electrode GE2 may overlap the semiconductor layer ACT. Alternatively, the second gate electrode GE2 may overlap a region where the first gate electrode GE1 overlaps the semiconductor layer ACT.

[0077] And a portion of the second gate electrode GE2 may be disposed on a partial region on the planarization layer PAC.

[0078] Since the second gate electrode GE2 is disposed on the second gate insulating layer GI2 in the opening OA and overlaps the semiconductor layer ACT, the second gate electrode GE2 may constitute a double gate electrode with the first gate electrode GE1 disposed under the semiconductor layer ACT.

[0079] That is, since the planarization layer PAC disposed on the semiconductor layer ACT is removed, a channel can be formed in the semiconductor layer ACT by an electric field formed by the second gate electrode GE2, which is implemented using an electrode layer located on the planarization layer PAC. Therefore, since a channel can be formed by the first gate electrode GE1 and the second gate electrode GE2, the mobility of the thin film transistor can be increased. And according to the increase in mobility, the current flowing through the semiconductor layer ACT can be increased.

[0080] Therefore, by increasing the current characteristics of the thin film transistor while reducing the size of the thin film transistor, the driving performance of the thin film transistor can be enhanced.

[0081] In addition, since the second gate electrode GE2 is disposed to overlap with the peripheral region including the semiconductor layer ACT, the second gate electrode GE2 can provide an element protection function like a shield against static electricity introduced from the outside.

[0082] This may mean that an auxiliary electrode pattern for element protection or the like is provided in the opening OA and the peripheral region of the planarization layer PAC by using the electrode layer on the upper layer of the planarization layer PAC, and part of the auxiliary electrode pattern performs the function of a top gate electrode.

[0083] As described above, according to various embodiments of the present disclosure, by forming an opening OA in the planarization layer PAC and realizing the second gate electrode GE2 by using an electrode layer set on the upper layer of the planarization layer PAC, the driving performance of the thin film transistor set in the display panel 110 can be enhanced without additional processing.

[0084] Here, the second gate electrode GE2 may be provided to be insulated from the first gate electrode GE1 , and the same signal as the signal supplied to the first gate electrode GE1 may be supplied to the second gate electrode GE2 .

[0085] Alternatively, the second gate electrode GE2 may be electrically connected to the corresponding first gate electrode GE1.

[0086] Figure 3 and Figure 4 is a view illustrating an example of a structure connecting a bottom gate electrode and a top gate electrode of a thin film transistor according to various embodiments of the present disclosure.

[0087] Figure 3 An example of implementing the second gate electrode GE2 by using the common electrode COM positioned on the upper layer of the planarization layer PAC is shown, and Figure 4 An example is shown in which the second gate electrode GE2 is realized by using the pixel electrode PXL positioned on the upper layer of the planarization layer PAC.

[0088] and Figure 3 and Figure 4 An example is shown in which the pixel electrode PXL is disposed on an upper layer than the common electrode COM, but in some cases, the common electrode COM may be disposed on an upper layer than the pixel electrode PXL, or the pixel electrode PXL and the common electrode COM may be disposed on the same layer.

[0089] Reference Figure 3 , the first gate electrode GE1 is disposed under the semiconductor layer ACT, and the opening OA of the planarization layer PAC may be positioned in a region including a region overlapping the semiconductor layer ACT or a channel region of the semiconductor layer ACT.

[0090] And the second gate electrode GE2 may be disposed on the same layer as the common electrode COM disposed on the planarization layer PAC.

[0091] That is, in the process of providing the common electrode COM, the second gate electrode GE2 may be implemented by providing an auxiliary electrode pattern made of the same material as the common electrode COM and separated from the common electrode COM in the opening OA of the planarization layer PAC.

[0092] A protection layer PAS may be disposed on the second gate electrode GE2 for insulating the common electrode COM from the pixel electrode PXL.

[0093] The second gate electrode GE2 is disposed to overlap the region where the semiconductor layer ACT is disposed and the peripheral region of the region, and is electrically connected to the first gate electrode GE1 positioned under the planarization layer PAC through a contact hole CH_g positioned in a region other than the region where the semiconductor layer ACT is disposed.

[0094] That is, the planarization layer PAC may have a structure in which it is removed in a region of the semiconductor layer ACT where the thin film transistor is provided and in a region where the first gate electrode GE1 and the second gate electrode GE2 are connected.

[0095] Here, in the process of setting the planarization layer PAC, the planarization layer PAC may not be set at the position of the contact hole CH_g. Alternatively, in the process of forming the contact hole CH_g in the gate insulating layer or the like set below the planarization layer PAC, the planarization layer PAC may be removed in a state where the planarization layer PAC is set at the position of the contact hole CH_g.

[0096] In this manner, the first gate electrode GE1 and the second gate electrode GE2 are easily electrically connected through the contact hole CH_g to form a dual gate electrode.

[0097] In addition, the second gate electrode GE2 may be implemented by using the pixel electrode PXL located on the uppermost layer among the electrode layers positioned on the planarization layer PAC.

[0098] Reference Figure 4 , the first gate electrode GE1 may be disposed on the substrate SUB, and the semiconductor layer ACT may be disposed on the first gate electrode GE1. A planarization layer PAC including an opening OA at a position corresponding to the semiconductor layer ACT may be disposed on the semiconductor layer ACT.

[0099] The protection layer PAS may be disposed in the planarization layer PAC and the opening OA of the planarization layer PAC for insulation between the common electrode COM and the pixel electrode PXL.

[0100] And the second gate electrode GE2 made of the same material as the pixel electrode PXL may be disposed on the protection layer PAS.

[0101] The second gate electrode GE2 may be disposed on the protective layer PAS positioned in the opening OA of the planarization layer PAC. In addition, the second gate electrode GE2 may be disposed on the protective layer PAS positioned on the planarization layer PAC. And the second gate electrode GE2 may be electrically connected to the first gate electrode GE1 positioned below the planarization layer PAC through the contact hole CH_g.

[0102] Since the second gate electrode GE2 is provided by using an electrode layer located on the uppermost layer among electrode layers located on the upper layer of the planarization layer PAC, the contact hole CH_g may be formed after providing the insulating layer and the electrode layer located below the uppermost layer.

[0103] Therefore, the contact hole CH_g for connection between the first gate electrode GE1 and the second gate electrode GE2 may be easily formed.

[0104] In this manner, since a portion of the planarization layer PAC positioned on the semiconductor layer ACT is removed and the second gate electrode GE2 is provided by using an electrode layer positioned on the planarization layer PAC, the driving performance of the thin film transistor can be enhanced while reducing the size of the thin film transistor.

[0105] Also, since the size of the thin film transistor disposed in the display panel 110 is reduced, the non-active area NA where the thin film transistor is disposed may be reduced, or the aperture ratio in the active area AA may be increased.

[0106] In addition, according to various embodiments of the present disclosure, since the semiconductor layer ACT of the thin film transistor is provided as a double layer having different composition ratios of materials included in the semiconductor layer ACT, the driving performance of the thin film transistor can be enhanced while reducing the size of the thin film transistor.

[0107] Figure 5 is a view illustrating another example of a structure in which a thin film transistor is provided in the display panel 110 according to various embodiments of the present disclosure.

[0108] Reference Figure 5 , the first gate electrode GE1 may be disposed on the substrate SUB, and the semiconductor layer ACT may be positioned on the first gate electrode GE1.

[0109] The planarization layer PAC positioned on the semiconductor layer ACT may be a structure removed in a region corresponding to the semiconductor layer ACT, and the second gate electrode GE2 implemented by using an electrode layer positioned on an upper layer of the planarization layer PAC may be disposed in a region where the planarization layer PAC is removed and in a peripheral region of the region.

[0110] Here, for example, the semiconductor layer ACT may be an oxide semiconductor.

[0111] And the semiconductor layer ACT includes a first oxide semiconductor layer ACT1 positioned on the first gate insulating layer GI1 and a second oxide semiconductor layer ACT2 positioned on the first oxide semiconductor layer ACT1 .

[0112] A composition ratio of a material included in the first oxide semiconductor layer ACT1 may be different from a composition ratio of a material included in the second oxide semiconductor layer ACT2 .

[0113] For example, the first oxide semiconductor layer ACT1 and the second oxide semiconductor layer ACT2 include indium, gallium, and zinc.

[0114] The composition ratio of indium, gallium, and zinc included in the first oxide semiconductor layer ACT1 may be 1:1:1. And the content of gallium included in the second oxide semiconductor layer ACT2 may be higher than the contents of indium and zinc included in the second oxide semiconductor layer ACT2.

[0115] That is, the first oxide semiconductor layer ACT1 may be formed by including indium, gallium, and zinc in the same ratio, and the second oxide semiconductor layer ACT2 may be formed by including relatively more gallium.

[0116] Here, the resistivity of the second oxide semiconductor layer ACT2 having a non-uniform composition ratio of indium, gallium, and zinc may be high. When the second oxide semiconductor layer ACT2 having a high resistivity is provided on the first oxide semiconductor layer ACT1, even if the channel length is short, the change in the threshold voltage of the thin film transistor may be small.

[0117] Therefore, it is possible to maintain uniformity of driving characteristics of the thin film transistor while reducing the size of the thin film transistor provided in the display panel 110 .

[0118] Since the current characteristics of the thin film transistor are improved by setting the second gate electrode GE2 in the opening OA of the planarization layer PAC, and the uniformity of the driving characteristics of the thin film transistor is maintained even if the size of the thin film transistor is reduced, the driving performance of the thin film transistor can be enhanced while minimizing the size of the thin film transistor set in the display panel 110.

[0119] Furthermore, since the area where the thin film transistor is set is reduced and the performance of the thin film transistor is enhanced, the area where the driving circuit is set in the non-active area NA of the display panel 110 can be reduced, or the aperture ratio of the sub-pixel SP set in the active area AA can be increased.

[0120] Figure 6 , Figure 7 and Figure 8 1 is a view illustrating an example in which a thin film transistor according to various embodiments of the present disclosure is implemented in a non-active area NA of a display panel 110 .

[0121] Reference Figure 6 , the gate driving circuit 120 included in the display device 100 may be disposed as a GIP type on the non-active area NA of the display panel 110. And for example, the gate driving circuit 120 may include: a pull-up transistor Tup configured to control the supply of a gate high voltage VGH to the gate line GL; and a pull-down transistor Tdown configured to control the supply of a gate low voltage VGL to the gate line GL.

[0122] The pull-up transistor Tup may be controlled by a voltage level of the Q node, and the pull-down transistor Tdown may be controlled by a voltage level of the QB node.

[0123] In addition, the gate driving circuit 120 may include a plurality of thin film transistors to control the voltage level of the Q node and the voltage level of the QB node.

[0124] Like the thin film transistors according to various embodiments of the above disclosure, the thin film transistor included in the gate driving circuit 120 may include a first gate electrode GE1 disposed under the semiconductor layer ACT and a second gate electrode GE2 positioned on the semiconductor layer ACT and disposed in the opening OA of the planarization layer PAC.

[0125] And the second gate electrode GE2 may be electrically connected to the first gate electrode GE1 to form a double gate electrode.

[0126] Therefore, since the size of the thin film transistor included in the gate driving circuit 120 is reduced, the area required to provide the gate driving circuit 120 is reduced and the non-active area NA can be reduced.

[0127] In addition, a portion of the second gate electrode GE2 may be disposed on a peripheral region of the opening OA.

[0128] Therefore, the thin film transistor disposed in the outer region of the display panel 110 , which is susceptible to external static electricity or the like, may be protected by the second gate electrode GE2 .

[0129] In this way, according to various embodiments of the present disclosure, since the size of the thin film transistors provided in the display panel 110 is reduced, the increase of the non-active area NA can be minimized when the driving circuit is provided on the non-active area NA of the display panel 110.

[0130] Alternatively, since the size of the thin film transistor can be reduced, when the multiplexing circuit or the demultiplexing circuit is provided in the non-active area NA, the number of wirings provided on the display panel 110 can be reduced.

[0131] Reference Figure 7 and Figure 8 , a demultiplexing circuit including a plurality of thin film transistors may be disposed on the non-active area NA.

[0132] The thin film transistor included in the demultiplexing circuit may be electrically connected between the data line DL and the link line LL. And the link line LL may be a signal wiring electrically connected to the data driving circuit 130. The link line LL may output signals out1, out2, out3, ... from the data driving circuit 130, respectively.

[0133] Here, each of a plurality of thin film transistors included in the demultiplexing circuit may be electrically connected to one data line DL, and two or more thin film transistors may be electrically connected to the same link line LL.

[0134] For example, as Figure 7 In the example shown in FIG. 1 , three thin film transistors may be electrically connected to one link line LL, and each of the three thin film transistors may be controlled by a multiplexed signal.

[0135] Therefore, one link line LL, that is, one channel included in the data driving circuit 130 can drive three data lines DL.

[0136] For example, refer to Figure 7 and Figure 8, during a period in which the thin film transistor controlled by the first multiplexing signal Mux1 is turned on, a data voltage D1 (R) for driving the red sub-pixel SP may be supplied to the data line DL.

[0137] And during the period in which the thin film transistor controlled by the second multiplexing signal Mux2 is turned on, the data voltage D2(G) for driving the green sub-pixel SP may be provided to the data line DL, and during the period in which the thin film transistor controlled by the third multiplexing signal Mux3 is turned on, the data voltage D3(B) for driving the blue sub-pixel SP may be provided to the data line. The total period in which the thin film transistor controlled by the multiplexing signals Mux1, Mux2, and Mux3 is turned on may be represented by 1H.

[0138] Since the thin film transistor included in the demultiplexing circuit includes a dual gate electrode, the current supply performance of the thin film transistor is enhanced, and even if the period for supplying the data voltage to each of the data lines DL is shortened by the demultiplexing circuit, the data voltage can be sufficiently supplied to each of the sub-pixels SP.

[0139] Therefore, the number of channels included in the data driving circuit 130 and the number of link lines LL electrically connected to the data driving circuit 130 and disposed on the non-active area NA may be reduced while maintaining the performance of supplying the data voltage to the sub-pixel SP.

[0140] In addition, the thin film transistor according to various embodiments of the present disclosure may be included in the sub-pixel SP disposed on the active area AA of the display panel 110 .

[0141] Fig. 9 is a view showing an example in which a thin film transistor according to various embodiments of the present disclosure is implemented in the active area AA of the display panel 110. And, Fig.10 is along Fig. 9 sectional views taken along lines II' and JJ' are shown in FIG.

[0142] Reference Fig. 9 and Fig.10 , the sub-pixel SP disposed on the active area AA may include a gate line GL disposed in one direction and a data line DL disposed in a direction intersecting the gate line GL. And the sub-pixel SP may separately include a common electrode COM disposed on two or more sub-pixels SP and a pixel electrode PXL disposed on each sub-pixel SP.

[0143] Fig. 9 and Fig.10 The example shown in exemplifies an example of a structure in which the pixel electrode PXL is provided on an upper layer than the common electrode COM.

[0144] Here, the sub-pixel SP may include a thin film transistor electrically connected between the data line DL and the pixel electrode PXL.

[0145] For example, part of the gate line GL may constitute the first gate electrode GE1 of the thin film transistor, and part of the data line DL may constitute the source electrode SE or drain electrode DE of the thin film transistor. And the drain electrode DE or source electrode SE disposed on the same layer as the data line DL may be electrically connected to the pixel electrode PXL through the contact hole CH_g.

[0146] In addition, the thin film transistor may include a second gate electrode GE2 disposed on the same layer as the pixel electrode PXL and made of the same material as the pixel electrode PXL.

[0147] For example, the second gate electrode GE2 may be disposed in a region including a region overlapping with a channel region of a thin film transistor or a region of the semiconductor layer ACT, and may be disposed in a region other than a region where the pixel electrode PXL is disposed. And the second gate electrode GE2 may be disposed in a specific pattern shape on the gate line GL including the first gate electrode GE1.

[0148] Here, the planarization layer PAC may be positioned on a layer between a layer where the semiconductor layer ACT where the thin film transistor is disposed and a layer where the pixel electrode PXL is disposed, and the planarization layer PAC may include an opening OA positioned in a region corresponding to the semiconductor layer ACT.

[0149] Therefore, the second gate electrode GE2 may be disposed in the opening OA of the planarization layer PAC. In addition, the second gate electrode GE2 may be disposed on a peripheral region of the opening OA.

[0150] And the second gate electrode GE2 may be electrically connected to the gate line GL located under the planarization layer PAC through a contact hole CH_g formed in the planarization layer PAC.

[0151] By using the same material as the pixel electrode PXL, the second gate electrode GE2 may be disposed in a region of the sub-pixel SP where the pixel electrode PXL is not disposed. And since the planarization layer PAC is not disposed under the second gate electrode GE2, a thin film transistor including dual gate electrodes may be easily implemented.

[0152] Therefore, since the size of the thin film transistor is reduced while the driving performance of the thin film transistor disposed in the sub-pixel SP is enhanced, the aperture ratio of the sub-pixel SP may be improved according to the reduction of the area in which the thin film transistor is disposed.

[0153] Furthermore, since the second gate electrode GE2 is formed by using an electrode layer positioned on an upper layer of the planarization layer PAC like the pixel electrode PXL or the common electrode COM without adding a separate process, a thin film transistor with enhanced driving performance may be easily implemented.

[0154] Furthermore, in some cases, the second gate electrode GE2 may be implemented in a shape corresponding to the gate line GL including the first gate electrode GE1 .

[0155] Fig.11 is a view showing another example in which a thin film transistor according to various embodiments of the present disclosure is implemented in the active area AA of the display panel 110 . Fig.12 is along Fig.11 A cross-sectional view taken along line K-K' shown in FIG.

[0156] Reference Fig.11 and Fig.12 The data line DL may be disposed in the sub-pixel SP along one direction, and the first gate line GL1 may be disposed in a direction intersecting the data line DL.

[0157] The first gate line GL1 may be disposed on the substrate SUB and positioned under the semiconductor layer ACT.

[0158] And a portion of the first gate line GL1 may overlap the semiconductor layer ACT to form a first gate electrode GE1.

[0159] The planarization layer PAC may be positioned on the semiconductor layer ACT, and the planarization layer PAC may include an opening OA positioned in a region corresponding to the semiconductor layer ACT.

[0160] The planarization layer PAC may be disposed in a region other than a region corresponding to the semiconductor layer ACT, and the common electrode COM, the protection layer PAS, and the pixel electrode PXL may be sequentially disposed on the planarization layer PAC.

[0161] Here, the second gate line GL2 may be disposed in a region other than a region where the pixel electrode PXL is disposed on the planarization layer PAC.

[0162] The second gate line GL2 may be disposed on the same layer as the pixel electrode PXL and made of the same material as the pixel electrode PXL.

[0163] And the second gate line GL2 may be disposed to correspond to the first gate line GL1 positioned under the semiconductor layer ACT.

[0164] Since the second gate line GL2 is disposed to correspond to the first gate line GL1, the second gate line GL2 may be disposed in the opening OA of the planarization layer PAC in the region where the semiconductor layer ACT is located, and a portion where the second gate line GL2 overlaps the semiconductor layer ACT may constitute a second gate electrode GE2.

[0165] The second gate line GL2 may be a structure not connected to the first gate line GL1 in the active area AA, and the same signal as the signal provided to the first gate line GL1 may be provided to the second gate line GL2. Here, the first gate line GL1 and the second gate line GL2 may be provided with signals through separate signal wirings.

[0166] Therefore, a thin film transistor including a dual gate electrode may be implemented without forming a hole for electrical connection between the first gate line GL1 and the second gate line GL2 in the sub-pixel SP.

[0167] Alternatively, the first gate line GL1 and the second gate line GL2 are separated in the active area AA and may be electrically connected through a hole formed in the planarization layer PAC in the non-active area NA.

[0168] Even in this case, since there is no need to form a hole in each sub-pixel SP, a thin film transistor including a dual gate electrode can be easily implemented while reducing the number of holes for electrical connection between the first gate electrode GE1 and the second gate electrode GE2 .

[0169] In addition, the thin film transistor according to various embodiments of the present disclosure may be applied regardless of the type of the display device 100. That is, the various embodiments of the present disclosure may be applied to all display devices 100 having the following structure: the thin film transistor is provided on the substrate SUB in the display panel 110, the insulating layer like the planarization layer PAC is provided on the thin film transistor, and the electrode layer exists on the insulating layer.

[0170] Fig.13 is a view showing another example in which a thin film transistor according to various embodiments of the present disclosure is implemented in the active area AA of the display panel 110 , and shows an example in which the display device 100 is an organic light emitting display device.

[0171] And in a structure in which a sub-pixel SP provided in a display panel 110 of an organic light emitting display device includes a light emitting area EA and a non-light emitting area NEA, Fig.13 A cross-sectional view taken along line LL′ as a portion of the light emitting area EA and the non-light emitting area NEA is shown.

[0172] Reference Fig.13The first gate electrode GE1 may be disposed on the substrate SUB, the first gate insulating layer GI1 may be disposed on the first gate electrode GE1, and the semiconductor layer ACT, the source electrode SE and the drain electrode DE may be disposed on the first gate insulating layer GI1, and the second gate insulating layer GI2 may be disposed thereon.

[0173] The planarization layer PAC may be disposed on the second gate insulating layer GI2. The planarization layer PAC may include an opening OA in a region corresponding to the semiconductor layer ACT. In addition, the planarization layer PAC may include a contact hole CH_p for electrical connection between the pixel electrode PXL positioned on the planarization layer PAC and the thin film transistor.

[0174] The second gate electrode GE2 may be disposed in the opening OA of the planarization layer PAC. In addition, a portion of the second gate electrode GE2 may be disposed on a partial region on the planarization layer PAC.

[0175] The second gate electrode GE2 may be made of the same material as the pixel electrode PXL and positioned on the same layer as the pixel electrode PXL.

[0176] That is, by placing the same material as the pixel electrode PXL in the opening OA of the planarization layer PAC in a structure in which the planarization layer PAC is removed in a region corresponding to the semiconductor layer ACT, a thin film transistor including a dual gate electrode may be implemented.

[0177] Therefore, a structure in which the thin film transistor disposed in the active area AA includes a dual gate electrode may be easily realized without adding a process or a separate electrode layer.

[0178] As an example, the thin film transistor is a driving transistor provided in the sub-pixel SP, but in some cases, it may be a switching transistor instead of the driving transistor.

[0179] The second gate electrode GE2 may be connected to the first gate electrode GE1 through a contact hole CH_g included in the planarization layer PAC.

[0180] The bank BANK may be disposed on the opening OA of the planarization layer PAC and the contact holes CH_p and CH_g, and the light emitting layer EL may be disposed in a region where the bank BANK is not disposed.

[0181] The common electrode COM may be disposed on the light emitting layer EL. The common electrode COM may be made of, for example, a transparent conductive material, and is completely disposed on the active area AA including the sub-pixel SP.

[0182] An encapsulation ENCAP including a first protective layer PAS1, a second protective layer PCL, and a third protective layer PAS2 may be disposed on the common electrode COM. For example, the first protective layer PAS1 and the third protective layer PAS2 may be inorganic encapsulation layers, and the second protective layer PCL may be an organic encapsulation layer.

[0183] That is, when the display device 100 is an organic light emitting display device, since the common electrode COM may be completely disposed on the active area AA, the second gate electrode GE2 is disposed on a layer where the pixel electrode PXL is disposed, and a thin film transistor including dual gate electrodes may be implemented.

[0184] In this way, according to various embodiments of the present disclosure, since the planarization layer PAC located on the area corresponding to the thin film transistor in the display panel 110 is removed and the second gate electrode GE2 is placed, the driving performance of the thin film transistor can be improved while reducing the size of the thin film transistor set in the display panel 110.

[0185] In addition, since the second gate electrode GE2 is implemented by using an electrode layer disposed on an upper layer of the planarization layer PAC, a thin film transistor including a dual gate electrode may be easily implemented without adding a separate process.

[0186] In addition, since part of the second gate electrode GE2 is disposed on a partial region of the planarization layer PAC, the second gate electrode GE2 can provide a function of protecting the thin film transistor from static electricity or the like caused from the outside.

[0187] The above description has been presented to enable any person skilled in the art to make and use the technical ideas of the present invention, and the above description has been provided in the context of specific applications and their requirements. Various modifications, additions and substitutions of the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and the accompanying drawings provide examples of the technical ideas of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present invention. Therefore, the scope of the present invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the present invention should be interpreted based on the attached claims, and all technical ideas within the scope of their equivalents should be interpreted as included within the scope of the present invention.

Claims

1. A display device, comprising: A substrate including an active area provided with a plurality of sub-pixels and an inactive area positioned outside the active area; a plurality of thin film transistors disposed on the substrate; a planarization layer disposed in at least a portion of the inactive region and the active region on the substrate; as well as a protective layer disposed on the planarization layer, Wherein, at least one of the plurality of thin film transistors comprises: a first gate electrode on the substrate; a semiconductor layer on the first gate electrode; A source electrode and a drain electrode disposed on the semiconductor layer; and a second gate electrode, the source electrode and the drain electrode on the semiconductor layer, Wherein, the planarization layer is located in a layer between a layer provided with the second gate electrode and a layer provided with the semiconductor layer; wherein the planarization layer is disposed on at least a portion of a region other than a region where a channel region of the semiconductor layer and the second gate electrode overlap with each other, and the planarization layer includes at least one opening region, and the at least one opening region is located on a region including a region where the second gate electrode and the channel region of the semiconductor layer overlap with each other; wherein the second gate electrode is arranged to cover the semiconductor layer, the source electrode and the drain electrode, and extends along the inclined surface and the top surface of the planarization layer; wherein the protective layer is disposed on the at least one opening region of the planarization layer, the inclined surface, and the top surface and between the second gate electrode and the planarization layer; and The top surface of the planarization layer and a portion of the second gate electrode are located outside a region overlapping with the source electrode and the drain electrode.

2. The display device according to claim 1, wherein: The second gate electrode is electrically connected to the first gate electrode through a contact hole included in the planarization layer in a region other than a region where the semiconductor layer is provided.

3. The display device according to claim 1, wherein: The second gate electrode is insulated from the first gate electrode, and the second gate electrode is supplied with the same signal as that supplied to the first gate electrode.

4. The display device according to claim 1, wherein: The second gate electrode is located in the same layer as a layer in which at least one of a pixel electrode and a common electrode provided in the sub-pixel is provided.

5. The display device according to claim 4, wherein: The second gate electrode is located in the same layer as an electrode located on a higher layer among the pixel electrode and the common electrode.

6. The display device according to claim 4, wherein: The second gate electrode is located in the same layer as the pixel electrode, and the common electrode is located on the pixel electrode and is disposed over the entire area of ​​the sub-pixel.

7. The display device according to claim 1, further comprising: a first gate insulating layer, located between the first gate electrode and the semiconductor layer; as well as A second gate insulating layer is located between the semiconductor layer and the second gate electrode and below the planarization layer.

8. The display device according to claim 7, wherein: The planarization layer exposes a portion of the second gate insulating layer.

9. The display device according to claim 1, wherein: The semiconductor layer is an oxide semiconductor layer.

10. The display device according to claim 9, wherein: The semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer provided on the first oxide semiconductor layer, and Here, a composition ratio of a material included in the first oxide semiconductor layer is different from a composition ratio of a material included in the second oxide semiconductor layer.

11. The display device according to claim 10, wherein: One of the first oxide semiconductor layer and the second oxide semiconductor layer has indium, gallium, and zinc at a content ratio of 1:1:1, and the other has a gallium content higher than a content of indium and a content of zinc.

12. The display device according to claim 1, wherein: A thin film transistor including the second gate electrode is disposed on the inactive region and is electrically connected to a gate line disposed on the active region.

13. The display device according to claim 1, wherein: A thin film transistor including the second gate electrode is disposed on the inactive region and is electrically connected between a link line disposed on the inactive region and a data line disposed on the active region, and A first thin film transistor electrically connected to the first data line and a second thin film transistor electrically connected to the second data line are electrically connected to the same link line.

14. The display device according to claim 1, wherein: A thin film transistor including the second gate electrode is disposed on the active region and is electrically connected to a pixel electrode disposed in the sub-pixel.

15. A display device, comprising: a plurality of first gate lines; a plurality of semiconductor layers, the plurality of semiconductor layers being located on the first gate line and overlapping a portion of the first gate line; a planarization layer located on the semiconductor layer and provided on a region other than at least a portion of a region where the semiconductor layer is provided; a protective layer disposed on the planarization layer; and a plurality of second gate lines, the plurality of second gate lines being located on the semiconductor layer and the planarization layer and overlapping at least a portion of a region where the first gate line and the semiconductor layer overlap each other, The planarization layer includes at least one opening region, and the at least one opening region is located on a region including a region where the semiconductor layer is disposed. Wherein, the second gate line is arranged to correspond to the first gate line; wherein the protection layer is disposed on the at least one opening region, the inclined surface and the top surface of the planarization layer and between the second gate line and the planarization layer; The top surface of the planarization layer and a portion of the second gate line are located outside a region overlapping with a source region and a drain region of the semiconductor layer.

16. The display device according to claim 15, wherein: The second gate line is separated from the first gate line in the active area.

17. The display device according to claim 16, wherein: Each of the plurality of second gate lines corresponds to each of the plurality of first gate lines and is electrically connected to the corresponding first gate line in the inactive region.

18. A display device comprising: substrate; a plurality of thin film transistors disposed on the substrate; a planarization layer disposed on the thin film transistor and comprising at least one opening region located in a region overlapping the thin film transistor; a protective layer, disposed on the planarization layer; as well as a plurality of auxiliary electrode patterns disposed in the opening region included in the planarization layer and disposed on a portion of a region on the planarization layer, wherein the plurality of auxiliary electrode patterns are arranged to cover the thin film transistor and extend along the inclined surface and the top surface of the planarization layer; wherein the protective layer is disposed on the at least one opening region of the planarization layer, the inclined surface, and the top surface and between the auxiliary electrode pattern and the planarization layer; and The top surface of the planarization layer and a portion of the auxiliary electrode pattern are located outside a region overlapping with a source electrode and a drain electrode of the thin film transistor.

19. The display device according to claim 18, wherein: The auxiliary electrode pattern is electrically connected to a gate electrode of the thin film transistor.

20. The display device according to claim 18, further comprising at least one insulating layer between the thin film transistor and the planarization layer, and in, A portion of at least one insulating layer is exposed through the opening region of the planarization layer.

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