Lower plasma removal zone ring for bevel etcher

Abstract

A substrate processing system for processing a substrate includes an upper plasma exclusion region ring disposed above the substrate during plasma processing of a beveled edge of the substrate. An upper electrode is disposed above the substrate during the plasma processing. A lower plasma exclusion region ring is at least partially disposed below the substrate during the plasma processing. A lower electrode is at least partially disposed below the substrate during the plasma processing. The lower plasma exclusion region ring includes an annular body having: a lower portion at least partially disposed below the substrate; and an upwardly projecting flange extending upward from the lower portion of the annular body at a location spaced apart from a radially outer edge of the substrate. The upwardly projecting flange includes a uppermost surface extending vertically to either a middle portion of the substrate or above the middle portion of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 747,226, filed October 18, 2018. The entire disclosure of the above-cited application is incorporated herein by reference. Technical Field

[0003] This disclosure relates to substrate processing systems, and more specifically to a lower plasma exclusion region ring for a bevel etcher. Background Technology

[0004] The background description provided herein is for the purpose of presenting the general context of this disclosure. The work of the currently designated inventors, within the scope described in this background section and in the various aspects of the specification that could not be identified as prior art at the time of filing, neither expressly nor impliedly acknowledges that it is prior art to this disclosure.

[0005] Substrate processing systems can be used to perform etching, deposition, cleaning, and / or other processing of substrates such as semiconductor wafers. During processing, the substrate is positioned on a substrate support (such as a base, electrostatic chuck (ESC), etc.) within the processing chamber of the substrate processing system. A process gas mixture is introduced into the processing chamber to process the substrate. The process gas mixture may contain precursors for deposition or etching gases for etching. Plasma can be ignited to enhance the chemical reactions within the processing chamber. RF bias can be supplied to the substrate support to control ion energy.

[0006] During substrate processing, multiple film layers are deposited onto the substrate. After deposition, plasma can be used to etch portions of the pre-deposited film on the substrate. In some cases, the etching plasma density may be lower near the substrate edges. As a result, buildup of film or byproduct layers may occur on the top and bottom surfaces of the substrate's beveled edges.

[0007] Over time, the bond between one or more byproduct layers and the substrate may weaken, and the byproduct layers may detach or peel off. For example, the resulting particles may fall off during substrate transport and potentially contaminate other substrates, leading to defects. Substrate processing systems used for etching or cleaning beveled edges are used to remove byproduct layers. Summary of the Invention

[0008] A substrate processing system for processing a substrate includes an upper plasma exclusion region ring disposed above the substrate during plasma processing of a beveled edge of the substrate. An upper electrode is disposed above the substrate during the plasma processing. A lower plasma exclusion region ring is at least partially disposed below the substrate during the plasma processing. A lower electrode is at least partially disposed below the substrate during the plasma processing. The lower plasma exclusion region ring includes an annular body having: a lower portion at least partially disposed below the substrate; and an upwardly projecting flange extending upward from the lower portion of the annular body at a location spaced apart from a radially outer edge of the substrate. The upwardly projecting flange includes a uppermost surface extending vertically to either a middle portion of the substrate or above the middle portion of the substrate.

[0009] Among other features, the lower electrode is at least partially located below the lower plasma exclusion region ring. The lower plasma exclusion region ring includes a plurality of annular steps disposed on its substrate-facing surface. The uppermost surface of the upwardly projecting flange is flat.

[0010] Among other features, the arcuate surface extends downward from the radially inner edge of the uppermost surface to a position adjacent to the apex of the substrate. The arcuate surface extends downward from the radially inner edge of the uppermost surface to the lower portion of the annular body.

[0011] Among other features, the gap is defined in a horizontal plane between the apex of the substrate and the radially inner surface of the upwardly projecting flange. The gap has a width in the range of 0.1 mm to 1 mm. The width is in the range of 0.1 mm to 0.5 mm.

[0012] Among other features, the uppermost surface lies in a plane parallel to the plane containing the upper surface of the substrate. The thickness of the substrate is in the range of 50 micrometers to 2 mm. The lower plasma exclusion zone (PEZ) ring is made of a material selected from the group consisting of alumina and yttrium oxide.

[0013] Among other features, the substrate is attached to a carrier substrate. The upwardly projecting flange of the lower plasma exclusion region ring defines an upper pocket positioned radially inward from the uppermost surface and a lower pocket positioned radially inward from the upper pocket.

[0014] Among other features, an annular ridge located between the upper pocket and the lower pocket is configured at or above the apex of the radial outer edge of the substrate.

[0015] A lower plasma exclusion region ring for a bevel etcher includes an annular body defining: a first annular step located below and radially inward of a substrate's radially outer edge; and a second annular step extending upward and radially outward from the first annular step. The transition between the first and second annular steps is located radially inward of the substrate's radially outer edge. An upwardly projecting flange extends upward from the upper surface of the second annular step at the substrate's radially outer side. The uppermost surface of the upwardly projecting flange extends upward from the upper surface of the second annular step to a position vertically adjacent to at least one of: a middle portion of the substrate; and above the middle portion of the substrate.

[0016] Among other features, the uppermost surface of the upwardly projecting flange lies in a plane parallel to the plane containing the upper surface of the substrate. An arcuate surface extends downward and inward from the radial inner edge of the upwardly projecting flange to a position adjacent to the vertex of the substrate.

[0017] Among other features, the arcuate surface extends downward and inward from the radial inner edge of the upwardly projecting flange to the upper surface of the second annular step.

[0018] Among other features, the gap is defined in a horizontal plane between the apex of the substrate and the radially inner surface of the upwardly projecting flange. The gap has a width ranging from 0.1 mm to 1 mm. The width ranges from 0.1 mm to 0.5 mm. The thickness of the substrate ranges from 50 micrometers to 2 mm. The annular body is made of a material selected from the group consisting of alumina and yttrium oxide.

[0019] A lower plasma exclusion region ring for a bevel etcher includes an annular body defining: a first annular step configured to support a lower electrode of the bevel etcher; a second annular step extending upward and radially outward from the first annular step and configured to support a substrate; and a third annular step extending upward and radially outward from the second annular step. The radially inner surface of the third annular step defines: a first pocket; a second pocket located radially inward and below the first pocket; and an annular ridge located between the first pocket and the second pocket.

[0020] Among other features, the second pocket is configured to support the substrate, and the annular ridge is positioned at or above the apex of the radial outer edge of the substrate. The uppermost surface of the third annular step lies in a plane parallel to the plane containing the upper surface of the substrate. A gap is defined in a horizontal plane between the apex of the substrate and the annular ridge. The gap has a width in the range of 0.1 mm to 1 mm. The width is in the range of 0.1 mm to 0.5 mm. The thickness of the substrate is in the range of 50 micrometers to 2 mm. The annular body is made of a material selected from the group consisting of alumina and yttrium oxide.

[0021] The further scope of the applicability of this disclosure will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are for illustrative purposes only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0022] This disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0023] Figure 1 A side cross-sectional view of an example portion of a substrate processing system;

[0024] Figure 2 An enlarged side cross-sectional view of an example of a beveled etcher with upper and lower plasma exclusion zone rings;

[0025] Figure 3 A side cross-sectional view of an example of a substrate, lower plate, and lower plasma exclusion region ring according to this disclosure;

[0026] Figure 4 and Figure 5 A side cross-sectional view of other examples of a substrate, lower plate, and lower plasma exclusion region ring according to this disclosure;

[0027] Figure 6 and Figure 7 A side cross-sectional view of an additional example of a substrate, lower plate, and lower plasma exclusion region ring according to this disclosure;

[0028] In the accompanying drawings, reference numerals may be used repeatedly to identify similar and / or identical elements. Detailed Implementation

[0029] As described above, substrate processing systems used for etching the beveled edges of a substrate are typically designed to etch the radial outer edge of the substrate (but not the radial interior). In other words, the substrate processing system etches the upper surface of the substrate near the radial outer edge, the beveled edge of the substrate, and the lower surface of the substrate near the radial outer edge. The bevel etcher typically removes byproduct layers or other films from these surfaces. The radial interior of the substrate is left unetched.

[0030] In some applications, it is desirable to perform substrate etching above the apex of the bevel edge, but not below it. In other applications, the substrate comprises a first substrate attached to an underlying carrier substrate. Etching of the first substrate is intended to trim the first substrate while limiting etching of the carrier substrate.

[0031] The following description shows a conventional bevel etcher used for etching or cleaning the beveled edges of a substrate. Figure 1 ).exist Figure 2 The image shows an alternative configuration of the electrodes and the lower plasma exclusion zone ring for the bevel etcher. Figure 3 In the middle, the lower plasma exclusion zone (PEZ) ring is modified and configured very close to the bottom surface of the substrate (near the radial outer edge of the substrate) to reduce etching of the bottom surface of the substrate.

[0032] exist Figure 4 and Figure 5 According to this disclosure, the lower PEZ ring extends upward near the radial outer edge of the substrate to the apex of the substrate or above the apex (typically located in the middle portion of the substrate in the vertical direction) or on the upper surface of the substrate. Figure 6 and Figure 7 The additional changes to the PEZ ring are explained below.

[0033] Now for reference Figure 1 This image shows a substrate processing system 100 for cleaning the beveled edges of a substrate 118. The substrate processing system 100 includes a chamber wall 102 having a gate 142 through which the substrate 118 is loaded / unloaded. An upper electrode assembly 104 is attached to a support 108. The substrate processing system 100 includes a lower electrode assembly 106. An actuator (not shown) is attached to the support 108 for moving the upper electrode assembly 104 up and down (in the direction of the double arrows) to adjust the gap between the upper electrode assembly 104 and the substrate 118.

[0034] The metal bellows 148 creates a vacuum seal between the chamber wall 102 and the support 108 while allowing the support 108 to move vertically relative to the chamber wall 102. The support 108 has a central gas feed section (channel) 112 and an edge gas feed section (channel) 120. One or both of the gas feed sections 112 and 120 can deliver a plasma gas mixture to clean the bevel edge and / or deposit a thin film on the bevel edge.

[0035] During operation, plasma is formed around the beveled edge of the substrate 118, and this plasma is generally annular. To prevent the plasma from reaching the central portion of the substrate 118, the space between the upper dielectric plate 116 on the upper electrode assembly 104 and the substrate 118 is small, and the process gas is fed from the central feed section (e.g., through the stepped conduit 114). The gas then passes through the gap between the upper electrode assembly 104 and the substrate 118 in the radial direction of the substrate.

[0036] In some examples, purge gas is injected through a central gas feeder 112, while process gas is injected through an edge gas feeder 120. Plasma / process gas is evacuated from chamber space 151 to bottom space 140 via multiple orifices (outlets) 141. In some examples, a vacuum pump 143 may be used to evacuate bottom space 140 during cleaning or deposition operations.

[0037] The upper electrode assembly 104 includes an upper dielectric plate 116 and an upper metal component 110. The upper metal component 110 is fixed to a support member 108 by a suitable fastening mechanism and grounded via the support member 108. The upper metal component 110 has one or more edge gas passages or through-holes 122a, 122b and an edge gas filling section 124a. The edge gas passages or through-holes 122a, 122b are coupled to an edge gas feed section 120 for fluid communication during operation. The upper dielectric plate 116 is attached to the upper metal component 110.

[0038] The lower electrode assembly 106 includes a power supply electrode 126 having an upper portion 126a and a lower portion 126b. A pin actuation unit 132 and a lifting pin 130 move the substrate 118 vertically. A bottom dielectric ring 138 includes an upper portion 138a and a lower portion 138b. In some examples, the chuck includes an electrostatic chuck or a vacuum chuck. Hereafter, the term power supply electrode refers to one or both of the upper and lower portions 126a, 126b. Similarly, the term bottom dielectric ring 138 refers to one or both of the upper and lower portions 138a, 138b. The power supply electrode 126 is coupled to one or both radio frequency (RF) power sources 170 and 171 to receive RF power during operation.

[0039] The lifting pin 130 moves vertically within the cylindrical bore or path 131 and is moved between upper and lower portions by a pin actuation unit 132 located in the power supply electrode 126. The pin actuation unit 132 includes a housing surrounding each lifting pin to maintain a vacuum-sealed environment around the pin. The pin actuation unit 132 includes any suitable lifting pin mechanism, such as a robotic arm 133 (e.g., a horizontal arm having segments extending into each housing and attached to each pin) and an arm actuation device (not shown) and has a pin guide assembly 133a.

[0040] The substrate 118 is mounted on the lower electrode or on a lower configurable plasma exclusion zone (PEZ) ring 160. The term PEZ refers to the radial distance from the center of the substrate to the outer edge of the region (where plasma will be used to clean the bevel). In one embodiment, a closed vacuum region recess (vacuum region) 119 can be formed on the top surface of the power supply electrode 126, the bottom surface of the substrate 118, and the inner periphery of the lower configurable PEZ ring 160, which is in fluid communication with a vacuum source such as a vacuum pump 136. Cylindrical holes or paths for the lifting pins 130 are also shared as gas passages through which the vacuum pump 136 empties the vacuum region 119 during operation. The power supply electrode 126 includes an inflation section 134 to reduce transient pressure fluctuations in the vacuum region 119. In the case of multiple lifting pins, the inflation section 134 provides a uniform suction rate to the cylindrical holes.

[0041] During operation, substrate warpage can be reduced by utilizing the pressure difference between the top and bottom surfaces of substrate 118. The pressure in vacuum region 119 is maintained at a vacuum level during operation by a vacuum pump 136 coupled to the gas filling section 134. By adjusting the gap between the upper dielectric plate 116 and the top surface of substrate 118, the gas pressure in the gap can be varied without changing the overall flow rate of the process gas. Therefore, by controlling the gas pressure in the gap, the pressure difference between the top and bottom surfaces of substrate 118 can be varied, thereby controlling the bending force applied to substrate 118.

[0042] In some examples, the lower portion 138b of the bottom dielectric ring has a step 152 formed on the inner periphery of its upper surface to engage with a recess on the lower edge of the power supply electrode 126. In some examples, the lower portion 138b has a step 150 formed on its outer periphery to engage with a stepped surface on the upper portion 138a of the bottom dielectric ring (referred to as the focusing ring). Steps 150 and 152 align the bottom dielectric ring 138 with the power supply electrode 126. Step 150 also forms a tortuous gap along its surface to eliminate direct line of sight between the power supply electrode 126 and the chamber wall 102, thereby reducing the possibility of secondary plasma ignition between the power supply electrode 126 and the chamber wall 102.

[0043] Controller 190 controls the operation of substrate processing system 100. The controller communicates with gas delivery system 192 to deliver gas to substrate processing system 100 at appropriate times during processing. Controller 190 communicates with an RF sensor (not shown) that senses RF voltage or RF voltage, current, and phase angle. The RF sensor is mounted between an RF matching network (not shown here) and the processing chamber. Controller 190 communicates with and controls vacuum pumps 136 and 143 to control pressure within the substrate processing system. Controller 190 communicates with and controls a robotic arm 133. Controller 190 communicates with and controls RF power sources 170 and 171.

[0044] Now for reference Figure 2 This illustrates another configuration of the components of the bevel etcher 200. The bevel etcher 200 includes corresponding upper PEZ ring 202 and lower PEZ ring 204. The upper PEZ ring 202 and lower PEZ ring 204 have annular bodies and are located very close to the substrate 205, above and below the radial outer edge of the substrate 205, respectively. The radial outer ends of the substrate 205 extend beyond the radial outer surfaces of the upper PEZ ring 202 and lower PEZ ring 204 into the plasma processing region 207. As a result, the upper and lower surfaces of the substrate 205 at the radial outer edges are directly exposed to the plasma during bevel etching.

[0045] The upper electrode 206 and lower electrode 208 are positioned adjacent to the upper PEZ ring 202 and lower PEZ ring 204, respectively, and are located radially outward from the upper PEZ ring 202 and lower PEZ ring 204. RF power is applied across the upper electrode 202 and lower electrode 204 while plasma gas is supplied to generate plasma. The lower isolation ring 210 is located below the lower PEZ ring 204 and lower electrode 208. The dielectric plate 212 is positioned radially inward from the upper PEZ ring 202 above the substrate 205. A cooling plate 224 is positioned above the upper PEZ ring 202, upper electrode 206, and dielectric plate 212. The lower electrode plate 220 is positioned below the substrate 205.

[0046] exist Figure 3In the middle, the lower PEZ ring 260 has an annular body. The lower PEZ ring 260 is disposed below the substrate 270 and extends horizontally beyond the apex 274 (or radial outer edge) of the substrate 270. The lower PEZ ring 260 is disposed below the substrate 270 and is located between the lower electrode plate 264 and the lower electrode 266. The lower PEZ ring 260 is annular and includes one or more steps generally shown at 272. The bottom surface of the substrate 270 is placed on the uppermost of a plurality of steps 272 near the apex 274 of the substrate 270. In other words, the bottom surface near the apex 274 of the substrate 270 is not as... Figure 1 and Figure 2 The cantilever shape is shown. As can be seen, ions 278 generated by plasma 228 are incident on the vertex 274 of substrate 270. Although less etching occurs on the bottom surface of substrate 270, vertex 274 and other portions near the radial outer surface of substrate 270 are still etched.

[0047] Now refer to Figure 4 and Figure 5 The diagram shows a lower plasma exclusion zone (PEZ) ring 310. The lower PEZ ring 310 is disposed between a lower electrode plate 264 and another electrode 266. The lower PEZ ring 310 is annular and defines a pocket 312 for receiving a substrate 270. The pocket 312 has a vertical pocket depth greater than or equal to half the thickness of the substrate 270 and a diameter larger than the diameter of the substrate 270. The lower PEZ ring 310 includes a lower portion 314 having one or more steps 322. A portion of the bottom surface of the substrate 270 is located on the uppermost of a plurality of steps 322 near the radially outer edge of the substrate 270. A first step of the plurality of steps 322 includes a first laterally extending upper surface extending radially outward from a first radially inner annular ridge 323. A second step of the plurality of steps 322 includes a second laterally extending upper surface extending radially outward from a second radially inner annular ridge 325. The upper (or uppermost) surface 318 of the upwardly projecting annular flange 320 extends radially outward from the third radially inner annular ridge 327.

[0048] The lower PEZ ring 310 also includes an upwardly projecting annular flange 320 extending upward from the lower portion 314. In some examples, the upwardly projecting annular flange 320 extends vertically to a plane located at or above the middle portion of the substrate 270 in the vertical direction. In some examples, the upwardly projecting annular flange 320 extends to a plane located at or above the upper surface of the substrate in the vertical direction.

[0049] In some examples, the gap (defined in the horizontal direction) between the vertex 274 of the substrate 270 and the adjacent surface 321 of the upwardly projecting annular flange 320 is in the range of 0.1 to 1 mm. In some examples, the gap between the vertex 274 of the substrate 270 and the adjacent surface 321 of the upwardly projecting annular flange 320 is in the range of 0.1 to 0.5 mm.

[0050] The concave bend 316 may be located at the lower radial outer edge adjacent to the substrate 270, below the apex 274. The arcuate bend 316 is a transition surface from the second (or upper) step 322 to the adjacent surface 321, extending vertically from the second step 322 to the upper surface 318. The upper surface 318 of the upwardly projecting annular flange 320 may be located at a distance d1 above the plane defined by the lower surface of the substrate 270, where d1 >= d2 / 2, and d2 is equal to the thickness of the substrate. In other examples, d1 >= d2. In some examples, the substrate thickness d2 is in the range of 50 micrometers to 2 mm. In other examples, the substrate thickness d2 is in the range of 50 micrometers to 1.25 mm. In some examples, the lower PEZ ring 310 is made of alumina (Al2O3) or yttrium oxide (Y2O3).

[0051] Substrate 270 can have different constructions. In some examples, substrate 270 includes, for example: Figure 2-4 The single substrate shown. Alternatively, substrate 270 includes a first substrate 350 bonded to or otherwise attached to carrier substrate 352, such as Figure 5 As shown.

[0052] like Figure 4 As can be seen, the ions 278 generated by plasma 228 are partially blocked by the upwardly projecting annular flange, causing the ions to be incident on the beveled edge 274 of the substrate 270 in the region above the vertex 274. As a result, a selected region from the vertex 274 to the upper surface near the radial outer surface of the substrate 270 is etched, while the lower region is not etched.

[0053] like Figure 5 As can be seen, the ions 278 generated by plasma 228 are partially blocked by the upwardly projecting annular flange, causing the ions to incident on the first substrate 350 rather than on the carrier substrate 352. As a result, a selected area near the radially outer end of the first substrate 350 is etched or trimmed, while the carrier substrate 352 is not. As can be understood, the height of the upwardly projecting flange 320 can be varied to provide different etching effects.

[0054] Now refer to Figure 6The diagram at 610 shows an alternative configuration of the lower PEZ ring. The lower PEZ ring 610 includes a first step 614, a second step 616, and a third step 618, with increasing heights. The first step 614, second step 616, and third step 618 are configured on the substrate-facing side of the lower PEZ ring 610. In some examples, the uppermost surface 620 of step 618 is generally flat and lies in a plane parallel to the plane of the upper surface of the substrate 630. In some examples, the plane containing the uppermost surface 620 lies at or above the plane containing the upper surface of the substrate 630.

[0055] The radially inward portion of the uppermost surface 620 transitions to an arcuate surface 634, which slopes downward toward the second step 616. In some examples, the arcuate surface 634 helps to center the substrate 630 during placement.

[0056] Now refer to Figure 7 The diagram at 710 shows an alternative configuration of the lower PEZ ring. The lower PEZ ring 710 includes a first annular step 714, a second annular step 716, and a third annular step 718 of increasing height. The first annular step 714, the second annular step 716, and the third annular step 718 have respective laterally extending surfaces 715, 717, and 720 and are configured on the substrate-facing side of the lower PEZ ring 710. In some examples, the laterally extending surface 720 is the uppermost surface 720 of the third annular step 718 and is generally flat, lying in a plane parallel to the plane of the upper surface of the substrate 630. In some examples, during placement, the plane containing the uppermost surface 620 lies at or above the plane containing the upper surface of the substrate 630.

[0057] The radially inner surface of the third annular step 718 of the lower PEZ ring 710 defines a first pocket 733, a second pocket 735, and an annular ridge 736, transitioning downward toward the second annular step 716. The first pocket 733 has an arcuate surface 734 that is concave and transitions at a cliff (referred to as a ridge) 736 near the apex 274 of the ramp edge. In some examples, the arcuate surface 734 helps to center the substrate 630. The second pocket 735 has a surface 738 that transitions directly downward, downward and outward, or downward and inward to the first step 714.

[0058] The lower PEZ ring 710 defines first and second (or upper and lower) pockets 733 and 735. The lower pocket 735 has a depth greater than or equal to half the thickness of the substrate 630. The diameter of the lower pocket 735 is greater than the diameter of the substrate 630. The inner diameter of the upper pocket 733 is greater than the diameter of the lower pocket 735, and its outer diameter is greater than its inner diameter. An arcuate surface 734 extends from the outer diameter of the upper pocket 733 to the inner diameter of the upper pocket 733.

[0059] The foregoing description is merely illustrative in nature and is in no way intended to limit this disclosure, its application, or its use. The broad teachings of this disclosure can be implemented in various forms. Therefore, while this disclosure includes specific examples, its true scope should not be so limited, as other modifications will become apparent upon examination of the drawings, specification, and appended claims. It should be understood that one or more steps in the method may be performed in different orders (or simultaneously) without altering the principles of this disclosure. Furthermore, while each embodiment is described above as having certain features, any one or more of those features described relative to any embodiment of this disclosure may be implemented in and / or combined with features of any other embodiment, even if such combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and substitution of one or more embodiments for each other remains within the scope of this disclosure.

[0060] Various terms are used to describe spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), including “connection,” “joint,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “set.” Unless the relationship between the first and second elements is explicitly described as “direct,” the relationship described in the above disclosure can be a direct relationship, where no other intermediate element exists between the first and second elements, but it can also be an indirect relationship, where one or more intermediate elements exist between the first and second elements (spatially or functionally). As used herein, the phrase “at least one of A, B, and C” should be interpreted as meaning the use of a non-exclusive logical OR (A or B or C) logic and should not be interpreted as meaning “at least one of A, at least one of B, and at least one of C.”

[0061] In some implementations, the controller is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing apparatus, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronics may be referred to as a “controller”, which can control various components or sub-components of one or more systems. Depending on the processing requirements and / or system type, the controller may be programmed to control any process disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer tools and other transfer tools, and / or loading locks connected to or interfaced with a specific system.

[0062] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. Integrated circuits can include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions can be instructions sent to the controller in the form of various individual settings (or program files), which define operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silica, surfaces, circuits, and / or the die of the wafer.

[0063] In some implementations, the controller may be part of or coupled to a computer integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or be all or part of a fab host system, allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool, to which the controller is configured to interface with or control the tool. Therefore, as described above, a controller can be distributed, for example, by comprising one or more discrete controllers networked together and operating toward a common purpose (such as the process and control described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a room that communicate with one or more integrated circuits remotely (e.g., at the platform level or as part of a remote computer), which together control the process on the room.

[0064] Example systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, rotary rinsing chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfering edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0065] As described above, depending on one or more processing steps to be performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a host computer, another controller, or tools used in the transport of materials to and from the tool location and / or loading port in the semiconductor manufacturing plant.

Claims

1. A substrate processing system for processing a substrate, comprising: an upper plasma exclusion zone ring configured above the substrate during plasma processing of a bevel edge of the substrate; an upper electrode configured above the substrate during the plasma processing; a lower plasma exclusion zone ring configured at least partially below the substrate during the plasma processing; a lower electrode configured at least partially below the substrate during the plasma processing, wherein the lower plasma exclusion zone ring comprises a ring body having: a lower portion, wherein the lower portion includes a first annular step including a first laterally extending upper surface and a second annular step including a second laterally extending upper surface and extending upwardly and radially outwardly from the first annular step; and a upwardly projecting ledge extending upwardly from the second annular step of the lower portion of the ring body at a location spaced apart from a radially outer edge of the substrate, wherein the upwardly projecting ledge comprises: a side surface extending vertically and adjacent to the radially outer edge of the substrate to limit an amount of ions impinging a lower portion of the radially outer edge of the substrate, and an uppermost surface extending laterally toward a middle portion of the radially outer edge of the substrate.

2. The substrate processing system of claim 1, wherein the lower electrode is at least partially located below the lower plasma exclusion zone ring.

3. The substrate processing system of claim 1, wherein the uppermost surface of the upwardly projecting ledge is planar.

4. The substrate processing system of claim 3, wherein an arcuate surface extends downwardly from a radially inner edge of the uppermost surface to the lower portion of the ring body.

5. The substrate processing system of claim 1, wherein a gap is defined in a horizontal plane between an apex of the radially outer edge of the substrate and the side surface of the upwardly projecting ledge, and wherein the gap has a width in a range of 0.1 mm to 1 mm.

6. The substrate processing system of claim 5, wherein the width is in a range of 0.1 mm to 0.5 mm.

7. The substrate processing system of claim 1, wherein the uppermost surface is located in a plane parallel to a plane comprising an upper surface of the substrate.

8. The substrate processing system of claim 1, wherein a thickness of the substrate is in a range of 50 microns to 2 mm.

9. The substrate processing system of claim 1, wherein the lower plasma exclusion zone (PEZ) ring is made of a material selected from the group consisting of aluminum oxide and yttrium oxide.

10. The substrate processing system of claim 1, wherein the substrate is attached to a carrier substrate. a height of the upwardly projecting ledge measured from the second laterally extending upper surface of the lower portion to the uppermost surface is equal to one-half of a thickness of the substrate.

11. The substrate processing system of claim 1, wherein, a height of the upwardly projecting ledge measured from the second laterally extending upper surface of the lower portion to the uppermost surface is in a range of 25 microns to 1 mm.

12. The substrate processing system of claim 1, wherein, ​ 13. The substrate processing system of claim 1, wherein, The height at which the uppermost surface of the upwardly projecting ledge lies is equal to a height at one-half the distance between the height of the top surface of the substrate and the height of the bottom surface of the substrate.

14. The substrate processing system of claim 1, further comprising the substrate.

15. The substrate processing system of claim 4, wherein the arcuate surface is concave.

16. The substrate processing system of claim 1, wherein the uppermost surface of the lower portion supports the substrate.

17. The substrate processing system of claim 1, wherein the lower portion of the lower plasma exclusion zone ring extends adjacent to the lower electrode that supports the substrate.

18. A lower plasma exclusion zone ring for a bevel etcher, comprising: a ring-shaped body defining: a first ring-shaped step including a first laterally extending upper surface and located below and radially inward of a radially outer edge of a substrate; and a second ring-shaped step including a second laterally extending upper surface and extending upwardly and radially outwardly from the first ring-shaped step, wherein a transition between the first ring-shaped step and the second ring-shaped step is located radially inward of the radially outer edge of the substrate; and an upwardly projecting ledge extending upwardly from the second laterally extending upper surface of the second ring-shaped step at a radially outer side of the substrate and not below the second laterally extending upper surface, wherein an upwardly extending surface of the upwardly projecting ledge extends upwardly from the second laterally extending upper surface of the second ring-shaped step to an intermediate portion horizontally adjacent to the radially outer edge of the substrate; and the upwardly extending surface extends from the second laterally extending upper surface to an uppermost surface of the upwardly projecting ledge and not below the second laterally extending upper surface.

19. The lower plasma exclusion zone ring of claim 18, wherein the uppermost surface of the upwardly projecting ledge lies in a plane parallel to a plane containing an upper surface of the substrate.

20. The lower plasma exclusion zone ring of claim 18, wherein an arcuate surface extends downwardly and inwardly from a radially inner edge of the upwardly projecting ledge to the second laterally extending upper surface of the second ring-shaped step.

21. The lower plasma exclusion zone ring of claim 18, wherein a gap is defined in a horizontal plane between an apex of the radially outer edge of the substrate and a radially inner surface of the upwardly projecting ledge, and wherein the gap has a width in a range of 0.1 mm to 1 mm.

22. The lower plasma exclusion zone ring of claim 21, wherein the width is in a range of 0.1 mm to 0.5 mm.

23. The lower plasma exclusion zone ring of claim 18, wherein a thickness of the substrate is in a range of 50 microns to 2 mm.

24. The lower plasma exclusion zone ring of claim 18, wherein the ring-shaped body is made of a material selected from the group consisting of aluminum oxide and yttrium oxide.

25. The lower plasma exclusion zone ring of claim 18, wherein the upwardly extending surface extends upwardly from the second laterally extending upper surface of the second annular step to a location vertically adjacent to a location above an apex of the radially outer edge of the substrate.

26. The lower plasma exclusion zone ring of claim 18, wherein, the upwardly extending surface of the upwardly projecting flange extends downwardly and radially inwardly to a transition surface of the second laterally extending upper surface of the second annular step.

27. The lower plasma exclusion zone ring of claim 18, further comprising a transition surface extending downwardly and radially inwardly from the upwardly extending surface of the upwardly projecting flange to the second laterally extending upper surface of the second annular step.

28. The lower plasma exclusion zone ring of claim 18, wherein, a portion of the upwardly extending surface of the upwardly projecting flange transitions upwardly and outwardly between the second laterally extending upper surface of the second annular step and the uppermost surface of the upwardly projecting flange.

29. The lower plasma exclusion zone ring of claim 18, wherein the upwardly extending surface of the upwardly projecting flange is arcuate.

30. The lower plasma exclusion zone ring of claim 18, further comprising a transition surface extending downwardly and radially inwardly from the upwardly extending surface of the upwardly projecting flange toward the medial portion of the radially outer edge of the substrate.

31. The lower plasma exclusion zone ring of claim 18, wherein, the upwardly projecting flange height measured from the second laterally extending upper surface to the uppermost surface of the upwardly projecting flange is equal to one-half of a thickness of the substrate.

32. The lower plasma exclusion zone ring of claim 18, wherein, the upwardly projecting flange height measured from the second laterally extending upper surface to the uppermost surface of the upwardly projecting flange is 25 microns to 1 mm.

33. The lower plasma exclusion zone ring of claim 18, wherein: the first laterally extending upper surface comprises a first radially inner annular ridge; the second laterally extending upper surface comprises a second radially inner annular ridge; and the uppermost surface of the upwardly projecting flange comprises a third radially inner annular ridge.

34. The lower plasma exclusion zone ring of claim 18, wherein the second laterally extending upper surface supports the substrate.

35. The lower plasma exclusion zone ring of claim 18, wherein the lower plasma exclusion zone ring excludes and controls at least one of a plasma profile at the radially outer edge of the substrate.

36. A lower plasma exclusion zone ring for a bevel etcher, comprising: an annular body defining: a first annular step comprising a first laterally extending surface; a second annular step comprising a second laterally extending surface and extending upwardly and radially outwardly from the first annular step and configured to support a substrate; and a third annular step comprising a third laterally extending surface and extending upwardly and radially outwardly from the second annular step; wherein a radially inner surface of the third annular step between the second laterally extending surface and the third laterally extending surface defines: a first pocket; ​ a second pocket located radially inward of the first pocket and below the first pocket; and an annular ridge located between the first pocket and the second pocket.

37. The lower plasma exclusion zone ring of claim 36, wherein the second pocket is configured to support the substrate, and the annular ridge is positioned at or above an apex of a radially outer edge of the substrate.

38. The lower plasma exclusion zone ring of claim 36, wherein an uppermost surface of the third annular step is located in a plane parallel to a plane containing an upper surface of the substrate.

39. The lower plasma exclusion zone ring of claim 36, wherein a gap is defined in a horizontal plane between the apex of the radially outer edge of the substrate and the annular ridge, and wherein the gap has a width in a range of 0.1 mm to 1 mm.

40. The lower plasma exclusion zone ring of claim 39, wherein the width is in a range of 0.1 mm to 0.5 mm.

41. The lower plasma exclusion zone ring of claim 36, wherein a thickness of the substrate is in a range of 50 microns to 2 mm.

42. The lower plasma exclusion zone ring of claim 36, wherein the annular body is made of a material selected from the group consisting of aluminum oxide and yttrium oxide.

43. The lower plasma exclusion zone ring of claim 36, wherein the annular ridge located between the first pocket and the second pocket is configured at or above an apex of a radially outer edge of the substrate.

44. The lower plasma exclusion zone ring of claim 36, wherein the first annular step is configured to support a lower electrode of the bevel etcher.

45. The lower plasma exclusion zone ring of claim 36, wherein the annular ridge extends laterally around the substrate.

46. The lower plasma exclusion zone ring of claim 36, wherein the annular ridge extends laterally around the substrate adjacent to an apex of a radially outer edge of the substrate.

47. The lower plasma exclusion zone ring of claim 36, wherein: the first laterally extending surface comprises a first radially inner annular ridge; the second laterally extending surface comprises a second radially inner annular ridge; an uppermost surface of the third annular step comprises a third radially inner annular ridge; and the first pocket and the second pocket are disposed between the second radially inner annular ridge and the third radially inner annular ridge.

48. A substrate processing system, comprising: the lower plasma exclusion zone ring of claim 18; and the substrate.

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