Storage device with fault detection function and control system including the same

Abstract

A storage device having a failure detection function for improving functional safety and a control system including the same are provided. The storage device includes a first memory cell array configured to store input data and output the input data as output data, and a second memory cell array configured to store bit values of row addresses and column addresses of the first memory cell array in which the input data is stored, and output the bit values of the row addresses and the column addresses as internal row addresses and internal column addresses. A row / column address designating a read operation can be compared with the internal row / column addresses, and an address comparison signal as a comparison result can be output. The address comparison signal can provide a failure detection function for a data error of an automotive electronic system.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0161671, filed on December 6, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a storage device, and more specifically, to a storage device capable of improving functional safety by performing fault detection functions used by automotive electronic systems, and a control system including the storage device. Background Technology

[0004] Unlike devices used in general electronic products, malfunctions in automotive electronic equipment (e.g., electronic control units) can pose a fatal risk to vehicle safety in some situations. As the number of electronic components in automobiles increases, functional safety becomes a critical factor for automotive electronic equipment. Functional safety means the absence of unreasonable risk, i.e., a reasonable level of risk. Reasonable risk refers to controlling the probability of failure to a reasonable level based on the electronic equipment's rating. Automotive Safety Integrity Levels (ASILs) can be assigned to individual electronic devices in a vehicle to provide a standard for risk management. ASIL ratings are classified in ascending order from ASIL-A to ASIL-D according to the standards required for risk management. An ASIL-D rating represents the highest integrity requirement and applies to safety-related processing tasks. ASIL-D electronic equipment needs to identify safety-related failures at the arithmetic, logic, and memory levels.

[0005] Inputs read from various sensors installed in a vehicle are transmitted to an electronic control unit (ECU) to control the vehicle's operation. To facilitate vehicle control, the ECU may include a processor and storage devices for storing operating parameters, user inputs, sensor data, and / or instruction data such as those executable by the processor. Because the key functional parameters of the storage device are tested at the chip level of the integrated circuit (IC) before it is installed in the vehicle, the opportunity to test its proper functioning and / or for malfunctions after installation is limited. Therefore, a method is needed to detect faults in storage devices included in electronic devices requiring high safety levels—such as ASIL-D ratings. Summary of the Invention

[0006] This disclosure provides a storage device with fault detection function for improving functional safety, a method of operating the storage device, and a control system including the storage device.

[0007] A storage device according to an example embodiment of the present disclosure includes: a first storage cell array including a plurality of first storage cells located at corresponding intersections of a plurality of first bit lines and word lines, each word line being connected to a corresponding cell row in a plurality of storage cell rows; a second storage cell array located adjacent to the first storage cell array and including a plurality of second storage cells located at corresponding intersections of a plurality of second bit lines extending from the first storage cell array and the word lines; and a control logic block configured to control write operations and read operations of the first and second storage cell arrays, and to receive address signals, including row address signals for addressing word lines and column address signals for addressing a plurality of first bit lines. When a write operation is performed, the bit values ​​of the row address signal and the column address signal are stored in multiple second storage cells of the second storage cell array corresponding to the row address signal and the column address signal. When a read operation is performed, the bit values ​​of the row address signal and the column address signal stored in the multiple second storage cells of the second storage cell array corresponding to the row address signal and the column address signal are output as internal row address signal and internal column address signal. A first comparator is configured to receive the row address signal and the column address signal of the specified read operation, compare the row address signal with the internal row address signal, compare the column address signal with the internal column address signal, and output an address comparison signal as a comparison result.

[0008] A method for operating a storage device according to an example embodiment of the present disclosure, used to provide fault detection of a storage device including a first storage cell array and a second storage cell array, the method comprising: receiving row address signals and column address signals of a write operation of a specified storage device; storing input data in a first storage cell of the first storage cell array corresponding to the row address signals and column address signals; storing bit values ​​of the row address signals and column address signals in a second storage cell of the second storage cell array corresponding to the row address signals and column address signals; receiving row address signals and column address signals of a read operation of a specified storage device; outputting the bit values ​​of the row address signals and column address signals stored in the second storage cell of the second storage cell array corresponding to the row address signals and column address signals as internal row address signals and internal column address signals; comparing the row address signals with the internal row address signals, and comparing the column address signals with the internal column address signals; and outputting an address comparison signal indicating address matching or address mismatch as a comparison result.

[0009] A control system for controlling the operation of an electronic system according to an example embodiment of the present disclosure includes: a storage device configured to store input data related to the operation of the electronic system; and a processor communicatively connected to the storage device and configured to detect data errors or faults in the storage device. The storage device includes: a first storage cell array, including a first storage cell for storing input data; a second storage cell array, including a second storage cell for storing copies of row address signals and column address signals, the row address signals and column address signals being used to address the first storage cell storing the input data; a control logic block configured to control write and read operations of the storage device, storing the bit values ​​of the row address signals and column address signals when performing a write operation, and outputting the bit values ​​of the row address signals and column address signals stored in the second storage cell of the second storage cell array as internal row address signals and internal column address signals when performing a read operation; and a first comparator configured to receive the row address signals and column address signals of a specified read operation, compare the row address signals with the internal row address signals, compare the column address signals with the internal column address signals, output an address comparison signal as the comparison result, and provide the address comparison signal to the processor, wherein the processor is further configured to detect data errors in the storage device through the address comparison signal. Attached Figure Description

[0010] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 These are diagrams illustrating an automotive electronic system according to an exemplary embodiment of the present disclosure;

[0012] Figure 2 This is a block diagram describing a storage device according to an exemplary embodiment of the present disclosure;

[0013] Figure 3 It is a description Figure 2 Circuit diagrams of the memory cells in the first and second cell arrays;

[0014] Figure 4A and Figure 4B This describes an example embodiment. Figure 2 A diagram showing a portion of an exemplary structure of the first and second storage units;

[0015] Figures 5 to 7 This describes an example embodiment. Figure 2 Timing diagram of the operation of the storage device;

[0016] Figure 8A , Figure 8B and Figure 9A diagram illustrating a storage device according to an example embodiment of the present disclosure; and

[0017] Figure 10 and Figure 11 This describes an example embodiment. Figure 8A The timing diagram of the operation of the storage device. Detailed Implementation

[0018] Figure 1 This is a diagram illustrating an automotive electronic system according to an example embodiment of the present disclosure.

[0019] Reference Figure 1 The automotive electronic system 100 may consist of multiple functional elements included in the vehicle, and includes a control system 110 and multiple electronic devices 120. The control system 110 can connect to and communicate with the electronic devices 120 via an in-vehicle network. The in-vehicle network may be a Controller Area Network (CAN), a FlexRay-based network, a Media Oriented System Transport (MOST)-based network, etc. In some embodiments, the control system 110 can connect to and communicate with the electronic devices 120 via an external communication network. The external communication network may include a Personal Area Network (PAN) such as a Bluetooth network, a Local Area Network (LAN) such as an 802.11x WiFi network, and / or a Wide Area Network (WAN) such as a fourth-generation (4G) network or a Long Term Evolution (LTE) cellular network.

[0020] In some examples, the terms “coupled” and “connected” may be used together with their derivatives and described. However, these terms are not necessarily intended to be synonyms. For example, a description using the terms “connected” and / or “coupled” may indicate a state in which two or more elements are physically or electrically in contact with each other. Furthermore, the term “in coupling” means a state in which two or more elements cooperate or interact with each other but are not in contact with each other.

[0021] Control system 110 can control the operation of automotive electronic system 100. Control system 110 may include processor 112 and storage device 114 connected to and communicating with processor 112. Control system 110 can control the operation of automotive electronic system 100 based on user instructions and can receive user instructions as user input via steering wheel, brake pedal, and / or buttons. Control system 110 can autonomously control the operation of at least one part of automotive electronic system 100, either according to user instructions or without receiving user instructions. For example, when operating an advanced driver assistance system (ADAS), control system 110 can determine operating parameters from storage device 114, such as distance to surrounding objects, vehicle direction, and / or vehicle speed, and autonomously instruct the vehicle to apply brakes when a collision with a surrounding object is anticipated. Furthermore, when operating an autonomous driving system, control system 110 can determine operating parameters from storage device 114, such as the vehicle's current position, target destination, route from the current position to the target destination, and / or operational constraints based on the route, and control the vehicle to travel from the current position to the target destination. The Automotive Safety Integrity Level (ASIL) rating of the automotive electronic system 100 can be ASIL-D, which corresponds to a high rating.

[0022] Processor 112 can perform operations for controlling the overall operation of automotive electronic system 100. Processor 112 can execute tasks or processes based on at least a portion of operating parameters of automotive electronic system 100, sensor data, and / or data stored in storage device 114. When running a specific task or process, processor 112 may need to access data in storage device 114; that is, processor 112 may need to store data in or output data from storage device 114. Processor 112 and storage device 114 may have a common time base, such that time-driven storage and output of data are performed corresponding to the execution time of the task or process. The common time base can be implemented, for example, through a common clock or a suitable synchronization mechanism.

[0023] Processor 112 can access data in storage device 114. Storage device 114 can store and / or output data received from electronic device 120, such as user input data, sensor data, control commands, data to be processed by processor 112, and / or instructions executable by processor 112. Storage device 114 may include volatile memory (e.g., static random access memory (SRAM) or dynamic random access memory (DRAM)) and / or non-volatile memory (e.g., flash memory, resistive RAM (RRAM), magnetic RAM (MRAM), or phase-change RAM (PRAM)). Hereinafter, storage device 114 is described as SRAM; however, the technical concepts of this disclosure are not limited to SRAM.

[0024] Electronic device 120 may include multiple functional elements connected to control system 110. More specifically, electronic device 120 may include brake controller 121, steering controller 122, powertrain controller 123, lighting controller 124, image sensor 125, engine controller 126, battery controller 127, wiper controller 128, safety controller 129, and display controller 130.

[0025] The brake controller 121 may include multiple sensors for reading the state of the brake. The brake controller 121 may transmit the sensor readings to the control system 110. The brake controller 121 may receive control commands from the control system 110. The brake controller 121 may control the brake according to the control commands.

[0026] The steering controller 122 may include multiple sensors for reading the state of the steering unit. The steering controller 122 may transmit the sensor readings to the control system 110. The steering controller 122 may receive control commands from the control system 110. The steering controller 122 may control the steering unit according to the control commands.

[0027] Similarly, the powertrain controller 123 can transmit readouts from multiple sensors regarding the powertrain to the control system 110. The powertrain controller 123 can control the powertrain according to control commands from the control system 110.

[0028] The lamp controller 124 can transmit the readings of multiple lamps from multiple sensors to the control system 110. The lamp controller 124 can control the lamps according to the control commands from the control system 110.

[0029] The image sensor 125 can encode the scene in the field of view into image data and transmit the image data to the control system 110.

[0030] The engine controller 126 can transmit engine-related readouts from multiple sensors to the control system 110. The engine controller 126 can control the engine according to control commands from the control system 110.

[0031] The battery controller 127 can transmit information about the battery status to the control system 110. The battery controller 127 can control the battery settings according to control commands from the control system 110.

[0032] The wiper controller 128 can transmit readouts from multiple sensors regarding the external environment (e.g., whether it is raining) to the control system 110. The wiper controller 128 can control the wipers according to control commands from the control system 110.

[0033] The safety controller 129 can transmit readouts from multiple sensors regarding safety equipment (such as seat belts, airbags, electronically controlled suspension (ECS), etc.) to the control system 110. Furthermore, the safety controller 129 can send readouts regarding the external environment (e.g., tilting, falling, collision, etc.) to the control system 110. The safety controller 129 can control the safety equipment according to control commands received from the control system 110.

[0034] The display controller 130 can transmit readouts about the external environment (e.g., lighting intensity, movement speed, etc.). The display controller 130 can adjust the lighting intensity of the display or limit the content to be displayed based on control commands from the control system 110.

[0035] The control system 110 and electronic device 120 can be implemented as hardware circuits including semiconductors, such as custom very large scale interface (VLSI) circuits, gate arrays, logic chips, transistors, or other discrete components. The control system 110 and electronic device 120 can also be implemented as programmable hardware devices, such as programmable gate arrays, programmable gate logic, programmable gate devices, etc. Furthermore, the control system 110 and electronic device 120 can be implemented as software configured with executable code, objects, processes, or functions.

[0036] The control system 110 can autonomously control at least one operation of the vehicle based on data retrieved from the storage device 114. Errors or malfunctions in the storage device 114 may affect the operational reliability of the control system 110 and even the vehicle's electronic system 100.

[0037] Therefore, this invention provides a technique for improving the functional safety of automotive electronic systems 100 by detecting or identifying faults based on the error detection function of storage device 114 in control system 110. To easily reduce the impact of memory errors (or data errors), control system 110 can use the address comparison signal ACMP and / or data comparison signal DCMP provided by storage device 114 to determine error parameters, such as the location of memory errors (or data errors), before performing operations based on data from storage device 114, and provides a fault detection function. The fault detection function can use a high safety level to meet ASIL-D requirements.

[0038] According to embodiments of the present invention, the functional elements of the electronic device 120 may include devices similar to processor 112 and storage device 114, which operate on the control system 110 to provide the functions of processor 112 and storage device 114. For example, the processor and local storage device may be separately included in brake controller 121, steering controller 122, powertrain controller 123, lamp controller 124, image sensor 125, engine controller 126, battery controller 127, wiper controller 128, safety controller 129, and / or display controller 130. The local storage device included in each functional element of the electronic device 120 can be accessed by the corresponding processor and stores and / or outputs user input data for the corresponding functional element, sensor data as sensor readout results, and / or control commands from the control system 110. The local storage device included in each functional element of the electronic device 120 may also use address comparison signals and / or data comparison signals provided by the local storage device to determine error parameters, such as the location of memory errors, and provide fault detection functionality.

[0039] Figure 2 This is a block diagram describing a storage device 114 according to an example embodiment of the present disclosure.

[0040] Reference Figure 1 and Figure 2 The storage device 114 may include a first storage cell array 211, a second storage cell array 212, an address decoder and word line driver 220, a control logic block 230, a first input / output (I / O) circuit 241, a second input / output circuit 242, and a comparator 251.

[0041] Each of the first memory cell array 211 and the second memory cell array 212 may include a plurality of memory cells MC provided as a two-dimensional matrix, in which a plurality of rows and a plurality of columns are arranged. The first memory cell array 211 and the second memory cell array 212 may include a plurality of word lines WL and a plurality of bit lines BLF and BLS connected to the corresponding memory cell MC. The memory cells MC of the first memory cell array 211 and the second memory cell array 212 may be memory cells of the same type and may be a plurality of rewritable SRAM cells. For example, the memory cell MC may be a plurality of six-transistor SRAM cells.

[0042] Multiple word lines (WL) can be provided to each row of memory cells in the first memory cell array 211. Multiple bit lines (BLF) can be provided to each column of memory cells in the first memory cell array 211. Each bit line (BLF) can be implemented as a pair of bit lines including a bit line (BL) and a complementary bit line ( / BL).

[0043] The second memory cell array 212 may be adjacent to the first memory cell array 211 in the column direction. The memory cell rows of the second memory cell array 212 may be connected to word lines WL that are connected to the corresponding memory cell rows of the first memory cell array 211. Word lines WL may be connected to the memory cell rows of both the first and second memory cell arrays 211. For example, word lines WL may extend to both the first and second memory cell arrays 211 and 212. Bit lines BLS may be provided to each memory cell column of the second memory cell array 212, and each bit line BLS may be implemented as a pair of bit lines including a bit line BL and a complementary bit line / BL.

[0044] The address decoder and word line driver 220 can drive word lines WL connected to the rows of memory cells in the first memory cell array 211 and the second memory cell array 212, respectively. The address decoder and word line driver 220 can operate synchronously with a clock signal CK. The clock signal CK can be generated by the processor 112 (see...). Figure 1 The address decoder and word line driver 220 can receive the row address signal ADDR[X] in response to the clock signal CK, decode the row address signal ADDR[X], and enable the word lines WL of the memory cell rows of the first memory cell array 211 and the second memory cell array 212 according to the decoded row address signal ADDR[X]. For example, the word line WL corresponding to the row address signal ADDR[X] among the multiple word lines WL of the first memory cell array 211 and the second memory cell array 212 can be activated.

[0045] Control logic block 230 can operate synchronously with clock signal CK. Control logic block 230 can respond to clock signal CK from processor 112 (see...). Figure 1 The control logic block 230 receives address signals ADDR[X:Y] and / or control signals CTRL. Address signals ADDR[X:Y] may include row address signals ADDR[X] and column address signals ADDR[Y], and control signals CTRL may include write enable signals WE. Address signals ADDR[X:Y] may be provided to the second input / output circuit 242 and comparator 251. The control logic block 230 may output various internal control signals based on address signals ADDR[X:Y] and control signals CTRL to perform write and / or read operations on the first memory cell array 211 and the second memory cell array 212.

[0046] When the write enable signal WE is activated, the control logic block 230 can perform write operations on the first memory cell array 211 and the second memory cell array 212, and when the write enable signal WE is deactivated, the control logic block 230 can perform read operations on the first memory cell array 211 and the second memory cell array 212. The control logic block 230 can provide the row address signal ADDR[X] in the address signal ADDR[X:Y] to the address decoder and word line driver 220, and provide the column address signal ADDR[Y] to the first input / output circuit 241. When performing a read operation on the first memory cell array 211 and the second memory cell array 212, the control logic block 230 can provide the comparator 251 with the address signal ADDR[X:Y] specifying the read operation.

[0047] The first input / output circuit 241 may include a column decoder for decoding the column address signal ADDR[Y] and a column selection circuit for selecting the bit line BLF of the first memory cell array 211 based on the decoded column address signal. The bit line corresponding to the column address signal ADDR[Y] among the multiple bit lines BLF of the first memory cell array 211 can be selected. (For reference...) Figure 2 It is readily understood that the first input / output circuit 241 is described as including a column decoder and column selection circuitry of the first memory cell array 211. However, the column decoder and column selection circuitry of the first memory cell array 211 can be separated from the first input / output circuit 241.

[0048] The first input / output circuit 241 and the second input / output circuit 242 can be provided as data input / output circuits for the first memory cell array 211 and the second memory cell array 212, respectively. The first input / output circuit 241 and the second input / output circuit 242 can operate as write drivers or sense amplifiers according to the control of the control logic block 230. The first input / output circuit 241 and the second input / output circuit 242 can operate as write drivers when performing a write operation and as sense amplifiers when performing a read operation.

[0049] When a write operation is performed, the first input / output circuit 241 can receive the input data DIN to be written to the first memory cell array 211 according to the control of the control logic block 230, and write the input data DIN to the memory cell MC selected from the first memory cell array 211. The input data DIN can be written to the memory cell MC of the first memory cell array 211, and the memory cell MC is connected to the word line WL corresponding to the row address signal ADDR[X] activated and the bit line BLF corresponding to the column address signal ADDR[Y] selected.

[0050] When a write operation is performed, the second input / output circuit 242 receives the address signal ADDR[X:Y] according to the control of the control logic block 230, and writes a copy of the address signal ADDR[X:Y] to the memory cell MC selected from the second memory cell array 212, where MC corresponds to the column address signal ADDR[Y]. The copy of the address signal ADDR[X:Y] can be the bit values ​​of the row address signal ADDR[X] and column address signal ADDR[Y] of the memory cell MC in the first memory cell array 211 to which the input data DIN is written. For example, when the row address signal ADDR[X] is "0" and the column address signal ADDR[Y] is "1", the copy of the row address signal ADDR[X] and column address signal ADDR[Y] is "01". The copy of the address signal ADDR[X:Y] can be written to the memory cell MC in the second memory cell array 212 connected to the word line WL corresponding to the row address signal ADDR[X] activation via the bit line BLS. For example, the memory cell MC of the second memory cell array 212 corresponding to the row address signal ADDR[X] can store copies of the row address signal ADDR[X] and the column address signal ADDR[Y], and write the input data DIN into the first memory cell array 211 through the row address signal ADDR[X] and the column address signal ADDR[Y].

[0051] In some embodiments, the number of memory cells MC connected to the second memory cell array 212, which corresponds to the word line WL—and the row address signal ADDR[X]—can be equal to 32 (= 2). 5 The number of bits in the address array 212 (e.g., the number of column address ADDR[Y] is 5) is multiplied by the number of bits in the address signal ADDR[X:Y]. The number of bits in the address signal ADDR[X:Y] is the sum of the number of bits in the row address signal ADDR[X] and the number of bits in the column address signal ADDR[Y]. Furthermore, the number of bit lines (BLS) in the second memory cell array 212 can also be equal to the number of bits in the address signal ADDR[X:Y].

[0052] The first input / output circuit 241 and the second input / output circuit 242 can read data from the memory cell MC selected from the first memory cell array 211 and the second memory cell array 212 according to the control of the control logic block 230. The read data can be stored in latches included in the first input / output circuit 241 and the second input / output circuit 242.

[0053] When a read operation is performed, the first input / output circuit 241 can read the data in the memory cell MC of the first memory cell array 211 and store the read data in a latch. The memory cell MC is connected to the word line WL activated by the row address signal ADDR[X] and the bit line BLF selected by the column address signal ADDR[Y]. The first input / output circuit 241 can output the data stored in the latch as output data DOUT according to the control of the control logic block 230. For example, the input data DIN written to the memory cell MC of the first memory cell array 211 can be output as output data DOUT. The memory cell MC is connected to the word line WL activated by the row address signal ADDR[X] and the bit line BLF selected by the column address signal ADDR[Y].

[0054] When a read operation is performed, the second input / output circuit 242 can read the data in the memory cell MC of the second memory cell array 212 and store the data in a latch of the second input / output circuit 242. The memory cell MC is connected to the word line WL corresponding to the row address signal ADDR[X] activated. The second input / output circuit 242 can output the data stored in the latch as an internal address signal iADDR[X:Y] according to the control of the control logic block 230. For example, a copy of the address signal ADDR[X:Y] written to the memory cell MC of the second memory cell array 212 can be output as the internal address signal iADDR[X:Y], the memory cell MC being connected to the word line WL corresponding to the row address signal ADDR[X]. The internal address signal iADDR[X:Y] can be provided to the comparator 251.

[0055] When a read operation is performed, comparator 251 can latch the address signal ADDR[X:Y] received by storage device 114 and compare the latched address signal ADDR[X:Y] with the internal address signal iADDR[X:Y] output from the second input / output circuit 242. Comparator 251 can compare the address signal ADDR[X:Y] of the specified read operation with the internal address signal iADDR[X:Y] read from the second memory cell array 212 at timings corresponding to the read operation of address signal ADDR[X:Y] to determine whether address signal ADDR[X:Y] matches internal address signal iADDR[X:Y]. Comparator 251 can compare each bit of address signal ADDR[X:Y] with the corresponding bit of the row address signal ADDR[X] of internal address signal iADDR[X:Y], and compare each bit of address signal ADDR[X:Y] with the corresponding bit of the column address signal ADDR[Y] of internal address signal iADDR[X:Y]. Comparator 251 can output the address comparison signal ACMP as the comparison result.

[0056] When the comparison result indicates an address match, comparator 251 can determine that the address signal ADDR[X:Y] for the specified read operation does not include a memory error, and outputs the address comparison signal ACMP as, for example, logic "0". When the comparison result indicates an address mismatch, comparator 251 can determine that the address signal ADDR[X:Y] for the specified read operation includes a memory error, and outputs the address comparison signal ACMP as, for example, logic "1". Therefore, the address comparison signal ACMP can provide fault detection functionality for memory errors. The address comparison signal ACMP can be provided to processor 112.

[0057] Figure 3 It is a description Figure 2 The circuit diagram shows the memory cells MC in the first memory cell array 211 and the second memory cell array 212. For ease of description, bit line BL represents one of the bit lines BLF and BLS in the first memory cell array 211 and the second memory cell array 212, and one of the bit line BLT in the third memory cell array 213, which will be referred to later. Figure 8A and Figure 8B Describe it.

[0058] Reference Figure 3The memory cell MC can be an SRAM cell configured with 6 transistors. The memory cell MC can also be referred to as a 6T SRAM cell. However, the inventive concept is not limited to this example. For example, the memory cell MC can be an SRAM cell configured with 4 transistors and 2 resistors. The memory cell MC can also be referred to as a 4T and 2R SRAM cell. The memory cell MC may include: PMOS transistors P1 and P2, respectively connected between the power supply voltage (VDD) line and nodes A and B; and NMOS transistors N1 and N2, respectively connected between the ground voltage (VSS) line and nodes A and B. Node A can be connected to the gates of PMOS transistor P2 and NMOS transistor N2, and node B can be connected to the gates of PMOS transistor P1 and NMOS transistor N1. Nodes A and B can be connected to bit line BL and complementary bit line / BL via NMOS transistors N3 and N4, respectively. The gates of NMOS transistors N3 and N4 can be connected to word line WL. NMOS transistors N3 and N4 can be referred to as access transistors or passtransists. The storage cell MC can store data and complementary data at nodes A and B, and can be maintained in the state of latched data and complementary data. At nodes A and B, inverters configured with PMOS transistor P1 and NMOS transistor N1 are cross-connected or cross-coupled to inverters configured with PMOS transistor P2 and NMOS transistor N2.

[0059] When word line WL is enabled during a write operation, memory cell MC can latch the data transmitted from bit line BL and complementary bit line / BL via NMOS transistors N3 and N4, along with complementary data, at nodes A and B. When word line WL is enabled during a read operation, the data latched at nodes A and B can be transmitted to bit line BL and complementary bit line / BL via NMOS transistors N3 and N4.

[0060] Figure 4A and Figure 4B This is a description based on an example embodiment. Figure 2 A diagram showing a portion of an exemplary structure of the first storage cell array 211 and the second storage cell array 212.

[0061] Reference Figure 2 and Figure 4AThe first memory cell array 211 can be configured to have, for example, a memory capacity of 64KB and a 32-bit data input / output (I / O) structure. The first memory cell array 211 may include 32 memory blocks BLK0 to BLK31. Each of the memory blocks BLK0 to BLK31 may include a memory cell MC located at a corresponding intersection of 512 word lines WL and 32 bit lines BLF. When one of the 512 word lines WL is activated and one of the 32 bit lines BLF is selected in each of the memory blocks BLK0 to BLK31, operations of writing data to or reading data from the memory cell MC connected to the activated word line WL and the selected bit line BLF can be performed.

[0062] Each of the 512 word lines WL in memory blocks BLK0 to BLK31 can be addressed by the 9-bit row address signal ADDR[X], and each of the 32 bit lines BLF in memory blocks BLK0 to BLK31 can be addressed by the 5-bit column address signal ADDR[Y]. Therefore, the address signal ADDR[X:Y] can be configured with a total of 14 bits, which is the sum of the 9 bits of the row address signal ADDR[X] and the 5 bits of the column address signal ADDR[Y].

[0063] like Figure 4B As shown, the second memory cell array 212 may include 14 memory blocks BLK0a to BLK13a. The second memory cell array 212 may include multiple memory cells MC located at the corresponding intersections of 512 word lines WL extending from the word lines WL of the first memory cell array 211 and 32×14 bit lines BLS (e.g., 14 is the sum of the number of bits in the row address signal ADDR[X] and the number of bits in the column address signal ADDR[Y]). For example, the number of memory cells connected to one word line WL of the 512 word lines WL can be 32×14 memory cells. That is, in the second memory cell array 212, the number of memory cells MC connected to one word line WL can be equal to 2. X Multiply by the sum of the number of bits in the row address signal ADDR[X] and the number of bits in the column address signal ADDR[Y], where X is the number of bits in the column address signal ADDR[Y]. When one of the 512 word lines WL is activated and 14 bit lines BLS are selected in the second memory cell array 212, operations can be performed to write to or read from the address of the memory cell MC connected to the activated word line WL and the selected bit line BLS.

[0064] When a write operation is performed, the address signal ADDR[X:Y] specifying the write operation can be received by the storage device 114. In the first storage cell array 211, the word line WL corresponding to the 9-bit row address signal ADDR[X] can be activated, and in storage blocks BLK0 to BLK31, storage cells MC connected to the bit line BLF corresponding to the 5-bit column address signal ADDR[Y] can be selected from the storage cells MC connected to the activated word line WL, thereby selecting 32 storage cells MC in the first storage cell array 211. Therefore, 32 input data DIN[31:0] can be written to the 32 selected storage cells MC in storage blocks BLK0 to BLK31 respectively through the first input / output circuit 241. Moreover, in the second storage cell array 212, a copy of the address signal ADDR[X:Y] specifying the write operation can be written to the 14 storage cells MC connected to the activated word line WL through the second input / output circuit 242. Each of the 14 memory cells MC connected to the active word line WL is selected by the second input / output circuit 242 from the 32 memory cells MC corresponding to the 5-bit column address signal ADDR[Y]. For example, the second memory cell array 212 can store copies of the 9-bit row address signal ADDR[X] and the 5-bit column address signal ADDR[Y] in the 14 memory cells MC of the second memory cell array 212, and the input data DIN[31:0] is written to the first memory cell array 211 through the 9-bit row address signal ADDR[X] and the 5-bit column address signal ADDR[Y].

[0065] When a read operation is performed, the address signal ADDR[X:Y] specifying the read operation can be received by the storage device 114. In the first storage cell array 211, the word line WL corresponding to the 9-bit row address signal ADDR[X] can be activated, and in storage blocks BLK0 to BLK31, storage cells MC connected to the bit line BLF corresponding to the 5-bit column address signal ADDR[Y] can be selected from the storage cells MC connected to the activated word line WL, thereby selecting 32 storage cells MC of the first storage cell array 211. The data of the 32 selected storage cells MC can be read and output as 32 output data DOUT[31:0] through the first input / output circuit 241. Moreover, in the second storage cell array 212, the data of the 14 storage cells MC connected to the activated word line WL can be read and output as internal address signals iADDR[X:Y] through the second input / output circuit 242. The internal address signal iADDR[X:Y] can be configured with a 9-bit internal row address signal iADDR[X] and a 5-bit internal column address signal iADDR[Y].

[0066] The internal address signal iADDR[X:Y] read from the second memory cell array 212 can be provided to comparator 251. Comparator 251 can determine whether the address signal ADDR[X:Y] specifying the read operation matches the internal address signal iADDR[X:Y] read from the second memory cell array 212. Comparator 251 can compare each bit of the 9-bit row address signal ADDR[X] with the corresponding bit of the 9-bit internal row address signal iADDR[X], and compare each bit of the 5-bit column address signal ADDR[Y] with the corresponding bit of the 5-bit internal column address signal iADDR[Y]. Comparator 251 can output an address comparison signal ACMP indicating address match or address mismatch as the comparison result, and provide the address comparison signal ACMP to processor 112. Comparator 251 may include multiple XOR logic gates or multiple XNOR logic gates. Therefore, comparator 251 can perform XOR or XNOR operations to compare the address signal ADDR[X:Y] with the internal address signal iADDR[X:Y].

[0067] In an example embodiment, when storage device 114 has two row addresses X1 and X2 and two column addresses Y1 and Y2, the second storage cell array 212 may include 64 (16×4) storage cells. For example, the data of the address signal [X:Y] is stored in 64 storage cells, as shown in Table 1 below. In Table 1, when the address signal [X:Y] is [X1:X2] "01" and [Y1:Y2] "11", the second word line WL1 and each bit line BLS of the storage cell corresponding to [Y1:Y2] "11" (e.g., 4 storage cells) are selected, as shown in the marker cell. In a write operation, when the address signal [X:Y] is "0111", four memory cells (e.g., marker cells) connected to the second word line WL1 corresponding to the row address signal [X1:X2] "01" and the bit line BLS corresponding to the column address signal [Y1:Y2] "11" are selected, and the bit value of the address signal [X:Y] is stored in the four selected memory cells (e.g., marker cells) as the data "0111". In a read operation, when the address signal [X:Y] is "0111", four memory cells (e.g., marker cells) connected to the second word line WL1 corresponding to the row address signal [X1:X2] "01" and the bit line BLS corresponding to the column address signal [Y1:Y2] "11" are selected, and the bit value of the address signal [X:Y] is read from the four selected memory cells (e.g., marker cells) as the data "0111".

[0068] [Table 1]

[0069]

[0070] Figures 5 to 7 This is a description based on an example embodiment. Figure 2 Timing diagram of the operation of storage device 114. Figure 5 The operation of outputting an address comparison signal ACMP indicating an address match is shown according to the operation of storage device 114, and... Figure 6 and Figure 7 This illustrates the operation of the address comparison signal ACMP, which outputs an address mismatch signal. Combined with... Figure 2 , Figure 3 , Figure 4A and Figure 4B , Figures 5 to 7 This is a timing diagram when the storage device 114 operates based on the clock signal CK. For example, the timing diagrams described in this disclosure are not necessarily shown at a certain scale.

[0071] Reference Figure 5 At time point T1, the clock signal CK can be received by storage device 114. The clock signal CK can be provided by processor 112, so that processor 112 (see...) Figure 1 The time it takes to write data to / read data from storage device 114 while running a task or process.

[0072] For example, at time point T1, the rising edge of the clock signal CK can be received, and before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the write operation can be received from the processor 112, and the write enable signal WE can be activated to a logic high level. Assume that in the address signals ADDR[X:Y], the 9 bits of the row address signal ADDR[X] are configured with all bits set to the hexadecimal code 0x1FF, and the 5 bits of the column address signal ADDR[Y] are configured with all bits set to the hexadecimal code 0x1F.

[0073] At time point T2, the word line WL in the 512 word lines WL<511:0> <511> It can be activated to a logic high level in response to the 0x1FF code bit of the row address signal ADDR[X].

[0074] At time T2, the second memory cell array 212 is connected to the active word line WL. <511> The memory cell MC can perform a write operation in response to the active write enable signal WE. This is achieved when connected to the active word line WL. <511> In the memory cell MC of the second memory cell array 212, a copy of the address signal ADDR[X:Y] configured with a row address signal ADDR[X] of 0x1FF code bit and a column address signal ADDR[Y] of 0x1F code bit can be written.

[0075] Furthermore, at time point T2, in the first memory cell array 211, on the word line WL connected to the active word line... <511> Among the memory cells MC of each of the memory blocks BLK0 to BLK31, the memory cell MC connected to the bit line BLF corresponding to the column address signal ADDR[Y] of the 0x1F code bit can be selected. Memory cells MC can be selected from each of the memory blocks BLK0 to BLK31, and input data DIN[31:0] can be written to the 32 selected memory cells MC respectively. The write operation of the storage device 114 can be performed during the time period from time point T1 to time point T3.

[0076] At time T3, the rising edge of the clock signal CK can be received by the storage device 114. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the read operation can be received. Assume that the address signal ADDR[X:Y] is configured with the row address signal ADDR[X] at the 0x1FF code bit and the column address signal ADDR[Y] at the 0x1F code bit specified in the previously executed write operation.

[0077] At time point T4, word line WL<511:0> is one of the 512 word lines. <511> It can be activated to a logic high level in response to the 0x1FF code bit of the row address signal ADDR[X]. The second memory cell array 212 is connected to the activated word line WL. <511> The memory cell MC can perform a read operation in response to the deactivated write enable signal WE. Copies of the 0x1FF row address signal ADDR[X] and the 0x1F column address signal ADDR[Y] stored in the memory cell MC of the second memory cell array 212 can be read and output as internal address signals iADDR[X:Y]. The internal address signals iADDR[X:Y] can be configured with the 0x1FF internal row address signal iADDR[X] and the 0x1F internal column address signal iADDR[Y], and are provided to comparator 251.

[0078] Comparator 251 can latch the address signal ADDR[X:Y] for a specified read operation and compare the latched address signal ADDR[X:Y] with the internal address signal iADDR[X:Y] to output an address comparison signal ACMP. Comparator 251 can compare the row address signal ADDR[X] at the 0x1FF code point with the internal row address signal iADDR[X] at the 0x1FF code point, and compare the column address signal ADDR[Y] at the 0x1F code point with the internal column address signal iADDR[Y] at the 0x1F code point. Comparator 251 can determine an address match as the comparison result and output an address comparison signal of logic "0" level indicating an address match.

[0079] Reference Figure 6 At time point T1a, the clock signal CK can be received by the storage device 114. Before the rising edge of the clock signal CK is received, the address signal ADDR[X:Y] specifying the write operation can be received from the processor 112, and the write enable signal WE can be activated to a logic high level. For example, the address signal ADDR[X:Y] configured with a 0x1FF code bit row address signal ADDR[X] and a 0x1F code bit column address signal can be received.

[0080] At time T2a, the word line WL<511:0> among the 512 word lines WL<511:0> corresponds to the 0x1FF code point of the row address signal ADDR[X]. <511> It can be activated to a logic high level in response to the 0x1FF code bit of the row address signal ADDR[X]. Connected to the active word line WL <511> In the memory cell MC of the second memory cell array 212, it is expected that copies of the row address signal ADDR[X] with the 0x1FF code bit and the column address signal ADDR[Y] with the 0x1F code bit can be written.

[0081] However, when connected to the word line WL <511> Memory errors may occur in the memory cells MC of the second memory cell array 212. Memory errors can be soft-bit memory errors and / or fixed memory errors. When in memory cell MC (see...) Figure 3 A soft-bit memory error may occur when the values ​​of the data bits latched at nodes A and B of the storage device 114 are temporarily flipped (e.g., from "1" to "0" or vice versa) by alpha rays emitted from radioactive material included in the integrated circuit IC of the storage device 114. A fixed memory error may be caused by a failure of the IC of the storage device 114 (e.g., the presence of open / short circuits / bridging and / or defective transistors).

[0082] For example, a memory error can occur when connected to the word line WL. <511> It is generated in the memory cell MC of the second memory cell array 212. Therefore, it is connected to the activated WL <511> In the memory cell MC of the second memory cell array 212, the row address signal ADDR[X] can be stored as 0x1FF code bit, while due to memory error, the column address signal ADDR[Y] may be stored as, for example, 0x0F code bit instead of 0x1F code bit.

[0083] At time point T3a, the rising edge of the clock signal CK can be received by the storage device 114. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the read operation can be received. The address signal ADDR[X:Y] specifying the read operation can be configured with a row address signal ADDR[X] of 0x1FF code bit and a column address signal ADDR[Y] of 0x1F code bit specified in a write operation performed during the previous time period from time point T1a to time point T3a.

[0084] At time point T4a, connect the active word line WL among the 512 word lines WL<511:0>. <511> The memory cell MC of the second memory cell array 212 can perform a read operation in response to the deactivated write enable signal WE. The row address signal ADDR[X] at the 0x1FF code bit and the column address signal ADDR[Y] at the 0x0F code bit are stored in the memory cell MC of the second memory cell array 212 and connected to the active word line WL. <511> The memory cell MC can be read and output as an internal address signal iADDR[X:Y]. The internal address signal iADDR[X:Y] can be configured with an internal row address signal iADDR[X] at the 0x1FF code point and an internal column address signal iADDR[Y] at the 0x0F code point, and is provided to comparator 251.

[0085] Comparator 251 compares the row address signal ADDR[X] at the 0x1FF code bit with the internal row address signal iADDR[X] at the 0x1FF code bit, and compares the column address signal ADDR[Y] at the 0x1F code bit with the internal column address signal iADDR[Y] at the 0x0F code bit. Comparator 251 determines an address mismatch as the comparison result and outputs an address comparison signal ACMP, which is a logic "1" level indicating an address mismatch.

[0086] Reference Figure 7 At time point T1b, the clock signal CK can be received by the storage device 114. Before the rising edge of the clock signal CK is received, the address signal ADDR[X:Y] specifying the write operation can be received from the processor 112, and the write enable signal WE can be activated to a logic high level. For example, the address signal ADDR[X:Y] configured with a row address signal ADDR[X] of 0x1FF code bits and a column address signal of 0x1F code bits can be received.

[0087] At time point T2b, word line WL<511:0> is one of the 512 word lines. <511> It can be activated to a logic high level in response to the 0x1FF code bit of the row address signal ADDR[X]. This is achieved when connected to the activated word line WL. <511> In the memory cell MC of the second memory cell array 212, copies of the row address signal ADDR[X] with a code position of 0x1FF and the column address signal ADDR[Y] with a code position of 0x1F can be written.

[0088] At time point T3b, the rising edge of the clock signal CK can be received by the storage device 114. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the read operation can be received. The address signal ADDR[X:Y] specifying the read operation can be configured with a row address signal ADDR[X] of 0x1FF code bit and a column address signal ADDR[Y] of 0x1F code bit specified in a write operation performed during the previous time period from time point T1b to time point T3b.

[0089] At time point T4b, word line WL<511:0> is one of the 512 word lines. <511> The 0x1FF code bit in response to the row address signal ADDR[X] can be expected to be activated. However, due to a memory error generated in storage device 114, word line WL... <510> Instead of the word line WL <511> It may be activated. The connection of the second memory cell array 212 to the activated word line WL <510> The memory cell MC can perform a read operation in response to the deactivated write enable signal WE. When connected to the word line WL... <510> The second storage cell array 212 can store the row address signal ADDR[X] of the 0x1FE code position and the column address signal ADDR[Y] of the 0x1F code position in the storage cell MC.

[0090] From the memory cell MC of the second memory cell array 212—the MC is connected to the active word line WL <510> The internal address signal iADDR[X:Y] can be configured with an internal row address signal iADDR[X] at the 0x1FE code position and an internal column address signal iADDR[Y] at the 0x1F code position, and is provided to comparator 251.

[0091] Comparator 251 compares the row address signal ADDR[X] at the 0x1FF code bit with the internal row address signal iADDR[X] at the 0x1FE code bit, and compares the column address signal ADDR[Y] at the 0x1F code bit with the internal column address signal iADDR[Y] at the 0x1F code bit. Comparator 251 determines an address mismatch as the comparison result and outputs an address comparison signal ACMP, which is a logic "1" level indicating an address mismatch.

[0092] Figure 8A , Figure 8B and Figure 9 This is a diagram illustrating a storage device according to an exemplary embodiment of the present disclosure. Figure 8A and Figure 8B This is a block diagram of storage devices 114a and 114b, and Figure 9 It shows Figure 8A and Figure 8B Part of the structure of the first memory cell array to the third memory cell arrays 211, 212 and 213.

[0093] Reference Figure 8A and Figure 8B Storage devices 114a and 114b may include the same as those referenced above. Figure 2 The components described are the same as those in the storage device 114. For example, the first storage cell array 211 and the second storage cell array 212 of storage devices 114a and 114b can be the same as those in storage devices 114a and 114b. Figure 2 The first memory cell array 211 and the second memory cell array 212 of the storage device 114 are the same as or similar to those of the storage device 114a and 114b, and the first I / O circuit 241 and the second I / O circuit 242 of the storage devices 114a and 114b can be the same as those of the storage device 114a and 114b. Figure 2 The first I / O circuit 241 and the second I / O circuit 242 of the storage device 114 are the same as or similar to those of the storage device 114a and the storage device 114b, and the first comparator 251 of the storage device 114a and the storage device 114b can be connected to... Figure 2 The comparator 251 is the same as or similar to the one described above. In the example embodiment, each of the storage devices 114a and 114b may further include a third memory cell array 213, a third input / output circuit 243, a second comparator 252, and an error correction code (ECC) circuit 260. In the following text, references to the above will be omitted. Figure 2 The descriptions of storage devices 114a and 114b are the same.

[0094] Reference Figure 8A Storage device 114a may include ECC circuitry 260 for ensuring data integrity. ECC circuitry 260 may be connected to the first storage cell array 211. Input data DIN[31:0] to be stored in the first storage cell array 211 may have soft or hard data errors. The data value of a data bit may change when one or more data bits of the input data DIN[31:0] are toggled while being stored in or read from the first storage cell array 211. Furthermore, a damaged storage cell in the first storage cell array 211 may prevent one or more data bits from being correctly stored and read. Therefore, data read from the first storage cell array 211 may be considered to include such data errors.

[0095] To reduce such data errors, storage device 114a may include ECC circuitry 260 to generate a parity check, the parity check including one or more parity bits for input data DIN[31:0], generated by encoding the original input data DIN[31:0], and storing the encoding result in a first storage cell array 211. The encoding result may include a codeword having the input data DIN[31:0] and the parity check. The first storage cell array 211 may store the codeword. The first storage cell array 211 may also include multiple storage cells to store the parity check. Data output from data access operations (i.e., read operations) through the first storage cell array 211 may be a codeword generated by adding the parity check to the original input data DIN[31:0], and the codeword may be provided to ECC circuitry 260. ECC circuitry 260 may decode the codeword using the parity check and correct data errors included in the data read from the first storage cell array 211, and output output data DOUT[31:0]. The output data DOUT[31:0] from the ECC circuit 260 can be provided to the second comparator 252 for comparison with the internal data iDOUT[31:0] read from the third memory cell array 213.

[0096] exist Figure 8A In this configuration, the third memory cell array 213 can store the input data DIN[31:0] of the codeword output from the ECC circuit 260. The input data DIN[31:0] of the codeword output from the ECC circuit 260 can be written into the memory cells MC of the first memory cell array 211, where each memory cell MC corresponds to an address signal ADDR[X:Y] specifying a write operation. The third memory cell array 213 can be adjacent to the second memory cell array 212 in the column direction. Each row of memory cells in the third memory cell array 213 can be connected to the word line WL to which the corresponding rows of memory cells in the first and second memory cell arrays 211 and 212 are connected. The word line WL can extend to all the first to third memory cell arrays 211, 212, and 213 and can be connected to the corresponding rows of memory cells in the first to third memory cell arrays 211, 212, and 213. Bit lines BLT can be provided to each column of memory cells in the third memory cell array 213, and each bit line BLT can be implemented as a pair of bit lines including bit line BL and complementary bit line / BL.

[0097] like Figure 9As shown, the third memory cell array 213 may include 32 memory blocks BLK0b to BLK31b. The third memory cell array 213 may include multiple memory cells MC located at corresponding intersections of 32×32 bit lines (e.g., 32 blocks and 32 bit lines BLT in each block) and 512 word lines WL extending from the word lines WL of the first memory cell array 211 and the second memory cell array 212 (see [reference]). Figure 3 ). 32-bit input data DIN[31:0] can be provided to the third memory cell array 213 through 32 bit lines BLT, and 32-bit internal data iDOUT[31:0] can be output from the third memory cell array 213.

[0098] During the write operation, under the control of the control logic block 230, the third input / output circuit 243 can receive from the ECC circuit 260 a codeword generated by adding parity to the original input data DIN[31:0]. Through the third input / output circuit 243, the codeword of the input data DIN[31:0] can be written to the memory cell MC of the third memory cell array 213 via the bit line BLT corresponding to the column address signal ADDR[Y]. The memory cell MC is connected to the word line WL activated by the row address signal ADDR[X]. For example, the memory cell MC of the third memory cell array 213 corresponding to the address signal ADDR[X:Y] can store the codeword of the input data DIN[31:0] output from the ECC circuit 260, the memory cell MC corresponding to the row address signal ADDR[X] and the column address signal ADDR[Y].

[0099] In a read operation, the address signal ADDR[X:Y] specifying the read operation can be received by the storage device 114a. In the third storage cell array 213, the word line WL corresponding to the row address signal ADDR[X] can be activated, and data in the storage cell MC connected to the activated word line WL and the bit line BLT corresponding to the column address signal ADDR[Y] can be read, and the read data can be provided to the ECC circuit 260. The ECC circuit 260 can decode the codeword and correct data errors included in the data read from the third storage cell array 213. The internal data iDOUT[31:0] output from the ECC circuit 260 can be provided to the second comparator 252.

[0100] The internal data iDOUT[31:0] read from the third memory cell array 213 via ECC circuit 260 can be provided to the second comparator 252. The second comparator 252 can determine whether the output data DOUT[31:0] read from the first memory cell array 211 via ECC circuit 260 matches the internal data iDOUT[31:0] read from the third memory cell array 213 via ECC circuit 260, corresponding to the address signal ADDR[X:Y] of the specified read operation. The second comparator 252 can compare each bit of the 32-bit output data DOUT[31:0] with the corresponding bit in the 32-bit internal data iDOUT[31:0]. The second comparator 252 can output a data comparison signal DCMP indicating a data match or mismatch as the comparison result and provide the data comparison signal DCMP to the processor 112. The data comparison signal DCMP can provide fault detection functionality for data errors.

[0101] Reference Figure 8B The references above will be omitted. Figure 8A The same description as that for storage device 114a. (e.g.) Figure 8A As shown, the first storage cell array 211 can store the raw input data DIN[31:0] received from the processor 112 instead of the codeword received from the ECC circuit 260, and the third storage cell array 213 can store the raw input data DIN[31:0] received from the processor 112 instead of the codeword received from the ECC circuit 260.

[0102] During a write operation, the third input / output circuit 243 can receive and copy the original input data DIN[31:0] according to the control of the control logic block 230. Through the third input / output circuit 243, a copy of the original input data DIN[31:0] can be written into the memory cell MC of the third memory cell array 213 via the bit line BLT corresponding to the column address signal ADDR[Y]. The memory cell MC is connected to the word line WL activated by the row address signal ADDR[X]. For example, the memory cell MC of the third memory cell array 213 corresponding to the address signal ADDR[X:Y] can store a copy of the 32-bit original input data DIN[31:0] to be written into the memory cell MC of the first memory cell array 211 via the ECC circuit 260, the memory cell MC corresponding to the row address signal ADDR[X] and the column address signal ADDR[Y].

[0103] In a read operation, the address signal ADDR[X:Y] specifying the read operation can be received by the storage device 114b. In the third storage cell array 213, the word line WL corresponding to the row address signal ADDR[X] can be activated, and the data in the storage cell MC connected to the activated word line WL and the bit line BLT corresponding to the column address signal ADDR[Y] can be read out. The read data can be output as internal data iDOUT[31:0] through the third input / output circuit 243. The internal data iDOUT[31:0] can be a copy of the 32-bit original input data DIN[31:0] to be written to the storage cell MC of the first storage cell array 211 via the ECC circuit 260, the storage cell MC corresponding to the address signal ADDR[X:Y].

[0104] Figure 10 and Figure 11 This is a description based on an example embodiment. Figure 8A Timing diagram of the operation of storage device 114a. Figure 10 The operation of the data comparison signal DCMP, representing data matching, is shown according to the operation output of storage device 114a, and... Figure 11 The operation of the DCMP signal, which outputs a data comparison signal indicating a data mismatch, is shown.

[0105] Reference Figure 8A , Figure 9 and Figure 10 At time TD1, the rising edge of the clock signal CK can be received by the storage device 114a, and the logic high-level write enable signal WE can be received. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] and input data DIN[31:0] specifying the write operation can be received from the processor 112. Assume that the address signal ADDR[X:Y] is configured with a row address signal ADDR[X] of 0x1FF code bits and a column address signal ADDR[Y] of 0x1F code bits, and the input data DIN[31:0] is configured with a 32-bit hexadecimal code 0x00000000 where all bits are "0".

[0106] At time TD2, in response to the 0x1FF code bit of the row address signal ADDR[X], word line WL in the 512 word lines WL<511:0> <511> It can be activated to a logic high level.

[0107] At time TD2, in the first memory cell array 211, connected to the active word line WL <511> Among the memory cells MC of each of the memory blocks BLK0 to BLK31, the memory cell MC connected to the bit line BLF corresponding to the column address signal ADDR[Y] of the 0x1F code bit can be selected. Memory cells MC can be selected from each of the memory blocks BLK0 to BLK31, and the input data DIN[31:0] of the 0x00000000 code bit can be written to the selected 32 memory cells MC respectively. A copy of the input data DIN[31:0] of the 0x00000000 code bit can be written to the memory cells MC of the third memory cell array 213, and the memory cell MC corresponds to the row address signal ADDR[X].

[0108] Furthermore, at time point TD2, copies of the row address signal ADDR[X] at the 0x1FF code bit and the column address signal ADDR[Y] at the 0x1F code bit can be written into the memory cell MC of the second memory cell array 212. The memory cell MC of the second memory cell array 212 corresponds to the row address signal ADDR[X].

[0109] At time point TD3, the rising edge of the clock signal CK can be received by the storage device 114a. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the read operation can be received. Assume that the address signal ADDR[X:Y] is configured with a row address signal ADDR[X] of 0x1FF code bits and a column address signal ADDR[Y] of 0x1F code bits, similar to the address signal ADDR[X:Y] specified in the previous write operation.

[0110] At time point TD4, word line WL<511:0> is one of the 512 word lines. <511> It can be activated to a logic high level in response to the 0x1FF code bit of the row address signal ADDR[X]. The connection of the first memory cell array to the third memory cell arrays 211, 212 and 213 to the activated word line WL <511> The memory cell MC can perform a read operation in response to the deactivated write enable signal WE. The 0x00000000 code bit stored in the memory cell MC of the first memory cell array 211 can be output as output data DOUT[31:0]. The internal address signal iADDR[X:Y], which is configured with the internal row address signal iADDR[X] and the internal column address signal iADDR[Y] configured with the internal row address signal iADDR[Y], can be output from the memory cell MC of the second memory cell array 212. The 0x00000000 code bit stored in the memory cell MC of the third memory cell array 213 can be output as internal data iDOUT[31:0].

[0111] The first comparator 251 compares the address signal ADDR[X:Y] for the specified read operation with the internal address signal iADDR[X:Y] and outputs an address comparison signal ACMP. The second comparator 252 compares the output data DOUT[31:0] at code point 0x00000000 with the internal data iDOUT[31:0] at code point 0x00000000. The second comparator 252 determines a data match as the comparison result and outputs a data comparison signal DCMP indicating a logic "0" level representing the data match.

[0112] Reference Figure 8A , Figure 9 and Figure 11 At time TD1a, the clock signal CK can be received by the storage device 114a. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the write operation can be received from the processor 112, and the write enable signal WE at a logic high level can also be received. For example, the address signal ADDR[X:Y] configured with a row address signal ADDR[X] of 0x1FF code bits and a column address signal ADDR[Y] of 0x1F code bits, as well as the input data DIN[31:0] of 0x0000000 code bits, can be received.

[0113] At time point TD2a, the word line WL<511:0> in the 512 word lines WL<511:0> corresponds to the 0x1FF code point of the row address signal ADDR[X]. <511> It can be activated to a logic high level. In the first memory cell array 211, the word line WL connected to the activated word line... <511> In each of the memory cells MC in memory blocks BLK0 to BLK31, the memory cell MC connected to the bit line BLF corresponding to the column address signal ADDR[Y] of code point 0x1F can be selected, and the input data DIN[31:0] of code point 0x00000000 can be written into the selected memory cell MC. When connected to the active word line WL... <511> In the memory cell MC of the second memory cell array 212, copies of the row address signal ADDR[X] with a code position of 0x1FF and the column address signal ADDR[Y] with a code position of 0x1F can be written.

[0114] For example, when connected to the word line WL <511> Memory errors may occur in the memory cells MC of the third memory cell array 213. Therefore, in the connection to the active word line WL <511> In the storage cell MC of the third storage cell array 213, for example, 0x00000001 code bit may be written instead of 0x00000000 code bit of the input data DIN[31:0].

[0115] At time point TD3a, the rising edge of the clock signal CK can be received by the storage device 114a. Before receiving the rising edge of the clock signal CK, the address signal ADDR[X:Y] specifying the read operation can be received. The address signal ADDR[X:Y] specifying the read operation can be configured with a row address signal ADDR[X] of 0x1FF code point and a column address signal ADDR[Y] of 0x1F code point specified in a write operation performed during the previous time period from time point TD1a to time point TD3a.

[0116] At time point TD4a, word line WL<511:0> is one of the 512 word lines. <511> It can be activated to a logic high level in response to the 0x1FF code bit of the row address signal ADDR[X]. The connection of the first memory cell array to the third memory cell arrays 211, 212 and 213 to the activated word line WL <511> The memory cell MC can perform a read operation in response to the deactivated write enable signal WE. The 0x00000000 code bit stored in the memory cell MC of the first memory cell array 211 can be output as output data DOUT[31:0], the internal address signal iADDR[X:Y] can be output from the memory cell MC of the second memory cell array 212, and the 0x00000001 code bit stored in the memory cell MC of the third memory cell array 213 can be output as internal data iDOUT[31:0].

[0117] The first comparator 251 compares the address signal ADDR[X:Y] for the specified read operation with the internal address signal iADDR[X:Y] and outputs an address comparison signal ACMP. The second comparator 252 compares the output data DOUT[31:0] at code point 0x00000000 with the internal data iDOUT[31:0] at code point 0x00000001. The second comparator 252 determines a data mismatch as the comparison result and outputs a data comparison signal DCMP indicating a logic "1" level representing the data mismatch.

[0118] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: The first memory cell array includes a plurality of first memory cells located at corresponding intersections of a plurality of first bit lines and word lines, each word line being connected to a corresponding memory cell row of a plurality of memory cell rows; The second memory cell array is located adjacent to the first memory cell array and includes a plurality of second memory cells located at corresponding intersections of a plurality of second bit lines and word lines extending from the first memory cell array. The control logic block is configured as follows: Control the write and read operations of the storage device. Receive the row address for addressing the word lines and the column address for addressing the plurality of first bit lines. When a write operation is performed, the bit values ​​of the row address and the column address are stored in a plurality of second storage units corresponding to the row address and the column address, and When a read operation is performed, the bit values ​​of the row address and the column address stored in a plurality of second storage units corresponding to the row address and the column address are output as internal row address and internal column address; as well as The first comparator is configured as follows: Receives the row address and column address specified for the read operation. The row address is compared with the inner row address, and the column address is compared with the inner column address. The output address comparison signal is used as the comparison result.

2. The storage device according to claim 1, wherein, The address comparison signal indicates a fault detection function for data errors in the storage device.

3. The storage device according to claim 1, wherein, The multiple first storage cells and multiple second storage cells are static random access memory (SRAM) cells.

4. The storage device according to claim 1, wherein, The number of bit lines selected from the plurality of second bit lines and the number of memory cells selected from the plurality of second memory cells that are connected to the active word line corresponding to the row address are respectively equal to the sum of the number of bits in the row address and the number of bits in the column address.

5. The storage device according to claim 1, wherein, The control logic block is further configured as follows: When a write operation is performed, the input data is stored in a plurality of first storage units corresponding to the row address and the column address; and When a read operation is performed, the input data stored in a plurality of first storage units corresponding to the row address and the column address is output as output data.

6. The storage device according to claim 5, further comprising: A first input / output circuit is configured to select a first bit line from a plurality of first bit lines in response to a column address, and to store input data in a first set of memory cells from a plurality of first memory cells, the first set of memory cells being connected to the word line activated in response to the row address and connected to the selected first bit line.

7. The storage device according to claim 6, further comprising: The second input / output circuit is configured to select a second bit line from a plurality of second bit lines in response to a column address, and to store the bit values ​​of the row address and column address in a second set of memory cells from the plurality of second memory cells, the second set of memory cells being connected to the active word line and to the selected second bit line.

8. The storage device according to claim 1, wherein, The number of memory cells connected to word lines among the plurality of second memory cells is equal to 2. X X is the number of bits in the column address, multiplied by the sum of the number of bits in the row address and the number of bits in the column address.

9. The storage device according to claim 1, wherein, The storage device includes one of static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, resistive RAM (RRAM), magnetic RAM (MRAM), and phase change RAM (PRAM).

10. A method for operating a storage device to provide fault detection for the storage device, the storage device comprising a first storage cell array and a second storage cell array, the method comprising: Receives the row address and column address of the write operation for the specified storage device; The input data is stored in the first storage cell of the first storage cell array corresponding to the row address and the column address; The bit values ​​of the row address and the column address are stored in the second storage cell of the second storage cell array corresponding to the row address and the column address; Receive the row address and column address of the read operation for the specified storage device; Output the bit values ​​of the row address and column address stored in the second storage unit corresponding to the row address and column address, as the internal row address and internal column address; The row address is compared with the internal row address, and the column address is compared with the internal column address; as well as The output is an address comparison signal indicating whether the address matches or mismatches, serving as the comparison result. The first memory cell array includes multiple first memory cells located at corresponding intersections of multiple first bit lines and word lines, with each word line connected to a corresponding memory cell row among multiple memory cell rows. The second memory cell array is located adjacent to the first memory cell array and includes a plurality of second memory cells located at corresponding intersections of a plurality of second bit lines and word lines extending from the first memory cell array.

11. The method of claim 10, further comprising: Fault detection for errors in the storage device is provided to the control system, including the storage device, by using an address comparison signal.

12. The method according to claim 10, wherein, Storing the input data in the first storage unit includes: In each of the storage blocks included in the first storage cell array, the word line corresponding to the row address among the word lines connected to the plurality of storage cell rows is activated, each storage block corresponding to the number of bits of the input data; In each of the storage blocks, a first bit line corresponding to the column address is selected from a plurality of first bit lines connected to the first storage cell; and In each of the storage blocks, the input data is stored in a first set of storage cells in a first storage cell, the first set of storage cells being connected to an active word line and a selected first bit line.

13. The method according to claim 12, wherein, Storing the bit values ​​of the row address and the column address in the second storage unit includes: In each of the storage blocks, a second bit line corresponding to the column address is selected from a plurality of second bit lines connected to the second storage cell; The bit values ​​of the row address and the column address are stored in a second set of storage cells of the second storage cell, the second set of storage cells being connected to a word line extending from the active word line of the first storage cell array and connected to a selected second bit line.

14. A control system for controlling the operation of an electronic system, the control system comprising: A storage device is configured to store input data related to the operation of the electronic system; as well as A processor, connected to and communicating with a storage device, and configured to detect data errors in the storage device. The storage device includes: The first memory cell array includes multiple first memory cells located at corresponding intersections of multiple first bit lines and word lines, each word line connecting to a corresponding memory cell row among multiple memory cell rows. The second memory cell array is located adjacent to the first memory cell array and includes a plurality of second memory cells located at corresponding intersections of a plurality of second bit lines and word lines extending from the first memory cell array. The control logic block is configured as follows: Control the write and read operations of the storage device. When a write operation is performed, the bit values ​​of the row address and column address of the first memory cell are stored in the second memory cell, and When a read operation is performed, the bit values ​​of the row address and the column address stored in the second storage unit are output as the internal row address and the internal column address; and The first comparator is configured as follows: Receive the row address and column address specified in the read operation. The row address is compared with the internal row address, and the column address is compared with the internal column address. The output address comparison signal serves as the comparison result, and Provide the address comparison signal to the processor. The processor is further configured to detect data errors in the storage device based on an address comparison signal.

15. The control system according to claim 14, wherein, The control logic block is also configured to output the input data stored in the first storage unit corresponding to the row address and the column address as output data when a read operation is performed.

16. The control system according to claim 14, wherein, The first memory cell array includes first memory cells located at corresponding intersections of the first bit line and the word line, and each word line connects to a corresponding memory cell row among a plurality of memory cell rows. The second memory cell array is located adjacent to the first memory cell array and includes second memory cells located at corresponding intersections of a second bit line and a word line extending from the first memory cell array.

17. The control system according to claim 16, wherein, The first storage cell array includes storage blocks corresponding to the number of bits of input data, and Each of the storage blocks is configured to store input data in a first storage cell connected to a word line corresponding to the row address being activated and connected to the first bit line corresponding to the first bit line selected by the column address.

18. The control system according to claim 17, wherein, The second storage cell array is configured to store the bit values ​​of the row address and the column address in a second set of storage cells connected to the word line corresponding to the row address being activated.

19. The control system according to claim 14, wherein, The first storage cell of the first storage cell array and the second storage cell of the second storage cell array are static random access memory (SRAM) cells.

20. The control system according to claim 14, wherein, The electronic system is included in the vehicle.

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