Semiconductor Structure and Method of Manufacturing the Same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a first dielectric layer located on the substrate; a plurality of grooves located in the first dielectric layer, the top size of the grooves being larger than the bottom size of the grooves; a second dielectric layer located on the sidewalls of the grooves; and conductive plugs located in the grooves. The semiconductor structure and the manufacturing method thereof according to the present disclosure can improve the filling effect of the conductive material forming the conductive plugs and their electrical properties.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technologies, and more particularly, to a semiconductor structure capable of improving filling effects and electrical properties and a manufacturing method thereof. Background Art

[0002] A storage contact plug is a conductive semiconductor structure used to connect a transistor to a storage capacitor in a DRAM (Dynamic Random Access Memory) structure. As the sizes of transistors and storage capacitors continue to shrink, the process window of the storage contact plug becomes smaller and smaller, increasing the difficulty of filling conductive materials. At the same time, the reduced spacing between storage contact plugs will also enhance the mutual interference effect and thus reduce electrical properties.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] An object of the present disclosure is to provide a semiconductor structure and a manufacturing method thereof, which are used to at least to some extent overcome the problems of poor filling effect of conductive materials and reduced electrical properties during the manufacturing process of semiconductor structures due to limitations of related technologies.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor structure, including:

[0006] A substrate;

[0007] A first dielectric layer located on the substrate;

[0008] A plurality of grooves located in the first dielectric layer, wherein a top size of the groove is larger than a bottom size of the groove;

[0009] A second dielectric layer located on sidewalls of the groove;

[0010] A conductive plug located in the groove.

[0011] In an exemplary embodiment of the present disclosure, a dielectric constant of the first dielectric layer is less than a dielectric constant of the second dielectric layer.

[0012] In an exemplary embodiment of the present disclosure, sidewalls of the groove are in any one or any combination of a slant shape, a stepped shape, and a curved shape.

[0013] In an exemplary embodiment of the present disclosure, a spacing between the grooves is the same as a top size of the groove.

[0014] In an exemplary embodiment of the present disclosure, the aspect ratio of the groove is greater than 3:1 and / or less than 10:1.

[0015] In an exemplary embodiment of the present disclosure, the cross-section of the groove is any one of square, polygonal, circular or elliptical.

[0016] In an exemplary embodiment of the present disclosure, the plurality of grooves are arranged in an array.

[0017] In an exemplary embodiment of the present disclosure, the thickness of the second dielectric layer is less than 5 nm.

[0018] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes a third dielectric layer located on the upper surface of the first dielectric layer.

[0019] According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including:

[0020] Providing a substrate on which a first dielectric layer is formed;

[0021] Forming a plurality of grooves in the first dielectric layer, where the top size of the groove is larger than the bottom size of the groove;

[0022] Forming a second dielectric layer on the sidewalls of the grooves;

[0023] Filling the grooves with a conductive material.

[0024] In an exemplary embodiment of the present disclosure, the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer.

[0025] In an exemplary embodiment of the present disclosure, the sidewalls of the grooves are any one or any combination of diagonal, stepped and curved.

[0026] In an exemplary embodiment of the present disclosure, the spacing between the grooves is the same as the top size of the grooves.

[0027] In an exemplary embodiment of the present disclosure, the manufacturing method further includes:

[0028] Before forming the grooves, forming a third dielectric layer on the surface of the first dielectric layer.

[0029] In an exemplary embodiment of the present disclosure, the manufacturing method further includes, before filling the grooves with the conductive material: in-situ cleaning of the bottoms and sidewalls of the grooves.

[0030] In an exemplary embodiment of the present disclosure, the manufacturing method further includes back-etching the conductive material.

[0031] Embodiments of the present disclosure can improve the filling effect and electrical properties of the conductive material by improving the morphology of the groove and the first dielectric layer with a low dielectric constant, thereby improving the product yield.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Brief Description of the Drawings

[0033] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0034] Figure 1 It is a schematic diagram of the arrangement and cross-sectional direction of storage contact plugs in an exemplary embodiment of the present disclosure.

[0035] Figure 2 It is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0036] Figure 3 is Figure 2 A flowchart of a method for manufacturing a semiconductor structure in the illustrated embodiment.

[0037] Figures 4A to 4C is Figure 3 A process schematic diagram of the illustrated steps.

[0038] Figure 5 It is a schematic diagram of a semiconductor structure in another embodiment of the present disclosure.

[0039] Figures 6A to 6B is Figure 5 A process schematic diagram of the illustrated semiconductor structure. Detailed Embodiments

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0041] In addition, the accompanying drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0042] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof that can avoid generating air gaps in a semiconductor structure. The example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] Figure 2 is a schematic diagram of the semiconductor structure provided by the present disclosure.

[0044] Referring to Figure 2 , the semiconductor structure 200 includes:

[0045] a substrate 21;

[0046] a first dielectric layer 22 located on the substrate 21;

[0047] a plurality of grooves 23 located in the first dielectric layer 22, where the top dimension L1 of the groove 23 is greater than the bottom dimension L2 of the groove 23;

[0048] a second dielectric layer 24 located on the sidewalls of the grooves 23;

[0049] a conductive plug 25 located in the grooves 23.

[0050] In one embodiment, the substrate 21 is a semiconductor silicon substrate of a DRAM memory cell including an active region and a shallow trench isolation structure. As Figure 1As shown, the substrate 21 includes an active region 211 and a shallow trench isolation structure 212. In one embodiment, the conductive plug is a storage contact plug. The present disclosure Figure 2 , Figures 4A to 4C , Figure 5 , Figure 6A and Figure 6B The structures shown are all cross-sectional views along the A-A position of the structure shown in Figure 1 . In the DRAM structure shown in Figure 1 , the A-A position is perpendicular to the word line (WL) and parallel to the bit line structure 11 (BL). There is an isolation structure 12 mainly composed of a first dielectric layer 22 and a second dielectric layer 24 under the word line. The storage contact plug 25 (SNC structure) is located between two adjacent isolation structures 12 and two adjacent bit line structures 11. Since the bit line structure 11 is parallel to the cross-section of the embodiment of the present disclosure, it is not shown in other drawings. Those skilled in the art can understand that there are bit line structures 11 in front of and behind the viewing direction of Figure 2 , Figures 4A to 4C , Figure 5 , Figure 6A and Figure 6B .

[0051] In one embodiment, the side wall of the groove 23 can be, for example, any one or any combination of diagonal, stepped, and curved shapes. The top dimension L1 of the groove 23 is greater than the bottom dimension L2 of the groove 23. The fact that the top dimension of the groove 23 is greater than the bottom dimension of the groove 23 helps the subsequent filling of conductive materials in the groove and reduces filling defects such as voids.

[0052] In one embodiment, the cross-section of the groove 23 along the direction parallel to the substrate can be any one of a polygon, a circle, or an ellipse. Preferably, the cross-section is a quadrilateral, with two pairs of opposite sides being straight and the other two pairs of opposite sides being arc-shaped. The center of the arc-shaped sides protrudes towards the outside of the quadrilateral to facilitate expanding the area of the quadrilateral cross-section and provide convenient conditions for the subsequent filling of conductive materials. More preferably, the extending direction of the arc-shaped sides is substantially the same as the extending direction of the word line of the DRAM memory cell to utilize the isolation layer on the word line to increase the etching process window.

[0053] In one embodiment, multiple grooves 23 can be arranged in an array, and the array can be an aligned or misaligned dot array.

[0054] In one embodiment, the interval L3 between the grooves 23 can be the same as the top dimension L1 of the grooves, for example. The interval L3 or the top dimension L1 can be, for example, the minimum dimension that can be resolved by a lithography process, so as to increase the arrangement density of the grooves and increase the storage capacity per unit area of the chip. Specifically, in the lithography process, the above dimensions L1 and L3 in the mask can be set as the minimum dimensions that can be exposed under specific process conditions, and the specific process conditions include lithography exposure illumination conditions, types of photoresists, etc. Preferably, the interval between the grooves is the feature dimension of the photoresist pattern defining the grooves, and the top dimension of the grooves is the gap dimension between the photoresist patterns defining the grooves. For example, the photoresist pattern defining the grooves is a line arranged at equal intervals, and the line has a feature dimension and a gap dimension between the lines; the grooves are formed in the first dielectric layer by using the lines. The interval between the grooves can be understood as the feature dimension of the lines, and the top dimension of the grooves can be understood as the gap dimension between the lines.

[0055] In one embodiment, due to the high arrangement density of the grooves, if the aspect ratio of the grooves is too large, it will increase the difficulty of filling the conductive material. Therefore, considering comprehensively the arrangement density of the grooves and the difficulty of filling the conductive material, the aspect ratio of the grooves can be set to be greater than 3:1 and / or less than 10:1, and / or less than 10:1, for example, 5.3:1, 4.8:1, etc. Among them, the aspect ratio of the grooves is the ratio of the opening dimension of the grooves to the depth of the grooves. Specifically, the opening dimension can be the top dimension, the middle dimension or the bottom dimension of the grooves, and can be set according to the actual requirements of the process. In this embodiment, the aspect ratio of the grooves is the ratio of the middle dimension of the grooves to the depth of the grooves.

[0056] In the embodiment of the present disclosure, both the first dielectric layer 22 and the second dielectric layer 24 are insulators, which is beneficial to the electrical insulation between the conductive plug 25 and the adjacent structures. In one embodiment, the dielectric constant of the first dielectric layer 22 is less than the dielectric constant of the second dielectric layer 24. The first dielectric layer with a low dielectric constant is beneficial to reducing the parasitic capacitance between the conductive plug 25 and the adjacent structures and improving the electrical characteristics. For example, the first dielectric layer can be made of a low dielectric constant material such as silicon oxide, and the second dielectric layer is a nitride such as silicon nitride (Si3N4).

[0057] In one embodiment, the thickness of the second dielectric layer is, for example, less than 5 nm, such as 2 nm, 4 nm, etc., and preferably 2 - 4 nm. The second dielectric layer with a thickness of 2 - 4 nm can not only protect the first dielectric layer, but also is beneficial to increasing the size of the conductive plug and reducing the contact resistance.

[0058] Figure 3 is Figure 2 a flowchart of a manufacturing method of the semiconductor structure shown.

[0059] Refer to Figure 3, the method 300 for manufacturing a semiconductor structure may include:

[0060] Step S31: Provide a substrate with a first dielectric layer formed thereon.

[0061] Step S32: Form a plurality of grooves in the first dielectric layer, where the top size of the grooves is larger than the bottom size of the grooves.

[0062] Step S33: Form a second dielectric layer on the sidewalls of the grooves.

[0063] Step S34: Fill the grooves with a conductive material.

[0064] In the embodiments of the present disclosure, both the first dielectric layer and the second dielectric layer are insulators, which is beneficial to the electrical insulation between the conductive plug and the adjacent structures. In one embodiment, the dielectric constant of the first dielectric layer is less than that of the second dielectric layer. The first dielectric layer with a low dielectric constant is beneficial to reducing the parasitic capacitance between the conductive plug and the adjacent structures and improving the electrical characteristics. For example, the first dielectric layer may be a low dielectric constant material such as silicon oxide, and the second dielectric layer is a nitride such as silicon nitride (Si4N3).

[0065] Figures 4A to 4C is Figure 3 a process schematic diagram of the steps shown.

[0066] Refer to Figure 4A , first provide a substrate 21 with a first dielectric layer 22 formed thereon.

[0067] In one embodiment, the substrate 21 is a semiconductor silicon substrate of a DRAM memory cell including an active region and a shallow trench isolation structure. The first dielectric layer 22 is a low dielectric constant material such as silicon oxide, and the present disclosure is not limited thereto.

[0068] As Figure 4A shown, in step S32, form a plurality of grooves 23 in the first dielectric layer 22, where the top size of the grooves is larger than the bottom size of the grooves.

[0069] In one embodiment, a plurality of grooves 23 can be formed in the first dielectric layer 22 through an etching process such as photolithography.

[0070] In one embodiment, the sidewalls of the grooves can be in any one or any combination of a slanted shape, a stepped shape, and a curved shape.

[0071] In one embodiment, the aspect ratio of the grooves is controlled to be greater than 2:1 and / or less than 10:1.

[0072] In one embodiment, the spacing between the grooves is the same as the top size of the grooves.

[0073] In addition, in lithography processes such as masking, exposure, and etching, the opening shape of the groove (i.e., the cross-section of the groove) can be set to a square to make the size of the groove smaller and improve device density. The process method for making a square opening is, for example, SADP (Self-aligned Double Patterning), that is, after one lithography is completed, non-lithography process steps (such as thin film deposition and etching) are successively used to achieve spatial frequency doubling of the lithography pattern. Finally, another lithography process is used to remove the redundant pattern.

[0074] In other embodiments of the present disclosure, the opening shape of the groove can also be set to a polygon, a circle, an ellipse, etc. to simplify the process requirements, and the present disclosure does not make special restrictions on this.

[0075] Reference Figure 4B , in step S32, a second dielectric layer 24 is formed on the sidewall of the groove 23. Specifically, the second dielectric layer can be formed on the sidewall, bottom of the groove, and the upper surface of the first dielectric layer 22 by means of CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), and then the second dielectric layer on the bottom of the groove and the upper surface of the first dielectric layer 22 is removed by means of a dry etching process.

[0076] In the embodiments of the present disclosure, both the first dielectric layer and the second dielectric layer are insulators to facilitate electrical insulation between the conductive plug and the adjacent structure. In one embodiment, the dielectric constant of the first dielectric layer is less than that of the second dielectric layer. The first dielectric layer with a low dielectric constant is beneficial to reducing the parasitic capacitance between the conductive plug and the adjacent structure and improving the electrical characteristics. For example, the first dielectric layer can be made of a low dielectric constant material such as silicon oxide, and the second dielectric layer is a nitride such as silicon nitride (Si3N4).

[0077] As Figure 4C shown, in step S34, the groove is filled with a conductive material. Specifically, the groove can be filled with a conductive material such as tungsten, aluminum, cobalt, polysilicon, etc. by means of PVD (Physical Vapor Deposition), epitaxial growth, etc. Those skilled in the art can set the material of the conductive material and the specific deposition method by themselves, and the present disclosure is not limited thereto.

[0078] Figure 5 is a schematic diagram of another semiconductor structure 500 provided by the embodiments of the present disclosure.

[0079] Figure 6A and Figure 6B are Figure 5 schematic diagrams of the manufacturing process of the semiconductor structure 500 shown. ReferenceFigure 6A and Figure 6B , before forming the groove, a third dielectric layer 26 can be formed on the surface of the first dielectric layer 22. The third dielectric layer 26 remains at least partially on the surface of the first dielectric layer 22 after the groove 23 is formed to reduce the damage to the first dielectric layer caused by the etching ions for removing the second dielectric layer at the bottom of the groove 23.

[0080] In one embodiment, the deposition thickness of the third dielectric layer 26 can be controlled such that the thickness of the third dielectric layer 26 deposited on the top of the first dielectric layer 22 is the same as or thicker than the thickness of the second dielectric layer 24 deposited on the sidewalls of the groove, so as to provide better isolation for the subsequent deposition of the conductive material.

[0081] Finally, the formed semiconductor structure 500 as shown in Figure 5 has better surface characteristics.

[0082] In one embodiment, in order to avoid the influence of residual impurities (natural oxides, etching residues) on the electrical properties of the conductive material deposition interface (such as the sidewalls and bottom surfaces of the second dielectric layer in the groove), and the interface damage caused during the formation of the second dielectric layer on the sidewalls of the groove, the bottom and sidewalls of the groove can be in-situ cleaned by dry cleaning or other means before filling the conductive material to repair the interface damage and ensure the purity of the interface.

[0083] In one embodiment, after depositing the conductive material, the conductive material can be re-etched to form a conductive plug, so that the conductive plug has a flat upper surface and a suitable length.

[0084] In one embodiment, the conductive plug is a storage contact plug. After forming the storage contact plug, an interface platform (Landing Pad) made of metal can be formed on the storage contact plug for manufacturing a capacitor on the interface platform subsequently. Since connecting the interface platform made of metal on the storage contact plug belongs to the manufacturing of a metal-semiconductor contact structure, in yet another embodiment of the present disclosure, after filling the groove, metals can also be simultaneously deposited on the surfaces of the conductive materials of the metal-semiconductor contact structure corresponding to the transistor and the conductive materials of the semiconductor structure. That is, the interface platform and the contact structure (Contact) of the MOS transistor in the peripheral circuit are manufactured simultaneously. Since the manufacturing conditions for both are the same, both are metal-plug contacts, and manufacturing them together can make the process condition requirements simpler, improve the performance of the contact structure, and reduce the manufacturing cost.

[0085] In summary, the embodiments of the present disclosure deposit a second dielectric layer on the sidewalls of the groove to manufacture a trapezoidal spacer, which can provide a groove that is easier to operate for the deposition of the conductive material, thereby effectively reducing the air gap generation rate during the deposition of the conductive material on the basis of saving the process flow and materials, and improving the yield.

[0086] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and concept of the present disclosure are pointed out by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A first dielectric layer located on the substrate; A plurality of grooves located in the first dielectric layer, the top size of the groove being larger than the bottom size of the groove; A second dielectric layer located on the sidewalls of the grooves, the dielectric constant of the first dielectric layer being less than the dielectric constant of the second dielectric layer; A conductive plug located in the groove, the top surface of the conductive plug being lower than the top surface of the first dielectric layer; A third dielectric layer located on the upper surface of the first dielectric layer, the thickness of the third dielectric layer being greater than or equal to the thickness of the second dielectric layer, and the third dielectric layer not overlapping with the conductive plug.

2. The semiconductor structure according to claim 1, wherein, Further comprising: The sidewalls of the grooves are any one or any combination of diagonal, stepped, and curved.

3. The semiconductor structure according to claim 2, wherein, Further comprising: The spacing between the grooves is the same as the top size of the grooves.

4. The semiconductor structure according to claim 1, wherein, The depth-to-width ratio of the grooves is greater than 3:1 and / or less than 10:

1.

5. The semiconductor structure according to claim 1, characterized in that, The cross-section of the grooves is any one of polygonal, circular, or elliptical.

6. The semiconductor structure according to claim 5, wherein, The plurality of grooves are arranged in an array.

7. The semiconductor structure according to claim 1, wherein, The thickness of the second dielectric layer is less than 5 nm.

8. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Providing a substrate with a first dielectric layer formed thereon; Forming a third dielectric layer on the surface of the first dielectric layer; Forming a plurality of grooves in the first dielectric layer, the top size of the groove being larger than the bottom size of the groove. After forming the plurality of grooves, the third dielectric layer is on the surface of the first dielectric layer; Forming a second dielectric layer on the sidewalls of the grooves, the dielectric constant of the first dielectric layer being less than the dielectric constant of the second dielectric layer, and the thickness of the second dielectric layer being less than or equal to the thickness of the third dielectric layer; Filling the grooves with a conductive material; Performing back-etching on the conductive material to form a conductive plug, the conductive plug not overlapping with the third dielectric layer on the upper surface of the remaining first dielectric layer, and the top surface of the conductive plug being lower than the top surface of the first dielectric layer.

9. The manufacturing method according to claim 8, characterized in that, Further comprising: The sidewalls of the grooves are any one or any combination of diagonal, stepped, and curved.

10. The manufacturing method according to claim 8, characterized in that, Further comprising: The spacing between the grooves is the same as the top size of the grooves.

11. The manufacturing method according to claim 8, characterized in that, Before filling the grooves with the conductive material, further comprising: Performing in-situ cleaning on the bottom and sidewalls of the grooves.

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