Bonding of semiconductor devices with sintered nanoparticles

Abstract

In the described example, a packaged device (100) includes a substrate (101) having a device mounting surface, the substrate (101) having conductive bumps (103) having a first thickness spaced apart from each other on the device mounting surface. A first polymer layer (105) is disposed on the device mounting surface between the conductive bumps (103), the first polymer layer (105) having a second thickness equal to the first thickness. The conductive bumps (103) have outer surfaces not covered by the first polymer layer (105). A second polymer layer (107) is disposed on the first polymer layer (105), the outer surfaces of the conductive bumps (103) not covered by the second polymer layer (107). A conductive nanoparticle material (109) is disposed on the outer surfaces of the conductive bumps (103). A third polymer layer (111) is disposed on the second polymer layer (107) between the conductive nanoparticle material (109) on the conductive bumps (103). At least one semiconductor device die (121) is mounted to the third polymer layer (111), the at least one semiconductor device die (121) having electrical terminals (123) bonded to the conductive nanoparticle material (109).

Description

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices mounted on substrates. Background Art

[0002] As semiconductor processes continue to advance, semiconductor devices are getting smaller and smaller. The distance ("pitch") between the terminals on the surface of the semiconductor device continues to shrink. Further, the desire for chip-scale packaging (where the package size is approximately the same area as the die area) and the continued demand for mounting the semiconductor device die to a chip carrier or circuit board without the need for an additional substrate, interposer, or carrier are increasing. Flip-chip mounting is used to mount the terminals on the semiconductor device die to a carrier or substrate. Flip-chip packaging requires a vertical or "z" connection between the terminals of the semiconductor device die and the conductive pads or convex areas on the substrate. In order to reduce the surface area required for mounting the die, connections extending in the "x" or "y" direction (such as bonding wires, ribbon bonding, or redistribution layers) are not desirable because these connections increase the board area. Solder bumps, solder balls, conductive pillars (e.g., copper pillar bumps), and copper studs are used to make vertical connections between bonding pads on the circuit side of a semiconductor device die and conductive convex areas on a substrate (e.g., a chip carrier or circuit board), which saves overall board area by extending from the bonding pads on the semiconductor device die to the convex areas in the vertical or "z" direction.

[0003] In order to make electrical connections between devices and boards, anisotropic conductive films (ACFs) and anisotropic conductive adhesives (ACAs) have been used. Conductive spheres are placed in a tape, film, or adhesive. The film carrying the conductive spheres is placed between the die bonding pads or copper pads on the semiconductor device die and the convex areas on the substrate. By using a combination of thermal energy and compression energy, a conductive path is formed through the ACF in the vertical direction between the bonding pads on the semiconductor die and the conductive convex areas on the substrate. However, because the conductive spheres in the ACF are randomly distributed, unnecessary short circuits may be formed between the pads because the conductive paths occasionally appear in the "x" or "y" direction. Further, due to the random distribution of the conductive spheres in the ACF, the number of spheres that form the conductive path may also vary, so the conductivity or resistance characteristics of different electrical connections in the finished device may vary.

[0004] The spheres may be fixedly placed in a tape or film, which increases the cost of the film and requires alignment with the bond pads and bumps of the semiconductor device and board being used. Metal studs may be formed and placed at known locations in the film, again increasing cost. Summary of the invention

[0005] In the described examples, a packaged device includes a substrate having a device mounting surface, the substrate having conductive bumps having a first thickness spaced apart from one another on the device mounting surface. A first polymer layer is disposed on the device mounting surface between the conductive bumps, the first polymer layer having a second thickness equal to the first thickness. The conductive bumps have outer surfaces not covered by the first polymer layer. A second polymer layer is disposed on the first polymer layer, the outer surfaces of the conductive bumps not covered by the second polymer layer. A conductive nanoparticle material is disposed on the outer surfaces of the conductive bumps. A third polymer layer is disposed on the second polymer layer between the conductive bumps. At least one semiconductor device die is mounted to the third polymer layer, the at least one semiconductor device die having electrical terminals bonded to the conductive nanoparticle material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1G are cross-sectional views illustrating steps of an example process for forming an arrangement.

[0007] Figure 2 is a flow chart of a method for forming an arrangement.

[0008] Figure 3 is a flow chart of an alternative method for forming an arrangement.

[0009] Figure 4 An arrangement for packaging a device is shown in cross-section.

[0010] Figure 5 It is a projection diagram of the packaging device.

[0011] Figure 6 is a cross section of a packaged device arrangement for a multi-chip module.

[0012] Figure 7 It is a projection and plan view of an alternative packaging device. DETAILED DESCRIPTION

[0013] Corresponding numerals and symbols in the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

[0014] In this description, the term "semiconductor device" is a device formed on a semiconductor substrate. Semiconductor devices include integrated circuits, in which several, hundreds, or thousands of individual devices (such as transistors) are formed on a semiconductor substrate and then coupled to each other using conductive conductors formed above the active surface of the semiconductor substrate to form a complete circuit function. Integrated circuits may include processors, analog-to-digital converters, memories, and other integrated devices. The term semiconductor device also includes discrete devices formed on a semiconductor substrate, such as discrete transistors, power field effect transistors (FETs), switching power converters, relays, diodes, optocouplers, microwave circuits, and other devices, such as passive devices, such as silicon-controlled rectifiers (SCRs), resistors, capacitors, transformers, inductors, and transducers. In this description, the term "semiconductor device die" is a single semiconductor device that is initially formed on a semiconductor wafer with many other semiconductor devices and then separated from the semiconductor wafer by a dicing process known as "singling". In this description, the term "substrate" includes molded interconnect substrate (MIS), laminate, plastic, ceramic, film or tape-based substrate, printed circuit board (PCB), metal lead frame including fiber reinforced glass substrate (such as FR4), BT resin substrate, conductive metal (including copper, stainless steel, alloy 42), and pre-molded lead frame (PMLF), which includes metal leads and molding compound formed in the substrate. Further, the term "substrate" includes another semiconductor device die or a portion of a semiconductor wafer, so that in the arrangement, the semiconductor device dies can be stacked face to face for additional integration in a packaged device.

[0015] In this description, the term "inkjet deposition" is an additional process for depositing material on a surface. In printing technology, the term "inkjet printing" refers to the use of nozzles to distribute ink droplets in a pattern on a surface to form characters and symbols, thereby additionally depositing ink droplets. In industrial applications, inkjet nozzles can deposit materials in the form of additive deposition to form layers on a surface. Inkjet deposition uses many fine nozzles coupled to an ink tank containing an electric actuator. A piezoelectric actuator in a reservoir can force a small known volume of liquid material through the nozzle in response to an electrical signal. Thermal inkjet nozzles have a resistive element in a reservoir that heats and expands the ink, forcing a known volume of ink through the nozzle. In both cases, surface tension causes spherical drops to form as the ink falls. Because inkjet nozzles are very fine, and because the nozzles contain a mechanism to form droplets in response to an electrical signal, the term "drops on demand" or "DOD" is used to describe the inkjet deposition tool that precisely deposits small amounts of liquid as the nozzle moves relative to the surface (moving the surface or the nozzle relative to the other). This precise drop placement allows for very efficient use of material to precisely place material, reducing waste, and eliminating the need for cleaning or etching steps to remove unwanted material from surface portions. In contrast to sputtering or other methods, inkjet deposition does not require masking and patterning steps. When inkjet deposition is used to deposit material, removal of excess or unwanted material is also eliminated.

[0016] In this description, the term "electrical terminal" is a terminal for electrically connecting to a semiconductor device die. The electrical terminal may include aluminum, copper or other conductive metals forming a bonding pad. Solder bumps, copper bumps, copper pillars and copper pillar bumps may be formed on the bonding pad as part of the electrical terminal. The bumps of the electrical terminal may include additional plating layers, such as a combination of nickel, palladium, tin, gold, solder and electroless nickel immersion gold (ENIG) and electroless nickel electroless palladium immersion gold (ENEPIG) to promote solderability, increase adhesion, and reduce or prevent corrosion or oxidation of metals (such as copper or aluminum). The term "electrical terminal" includes all of these arrangements for electrically connecting to a semiconductor device die. In this description, the term "thermal compression" refers to the simultaneous application of high temperature and mechanical pressure. In an example, a layer comprising conductive nanoparticles is bonded to a surface using thermal compression, while the nanoparticles are sintered to form a conductive path. In this description, the terms "nanoparticles" and "nanospheres" are particles or spheres with a diameter between 1 and 100 nanometers. In this description, the term "conductive nanoparticles" includes nanoparticles and nanospheres coated with metal to form nanoparticles, which will form conductors under heat treatment by sintering. An example sinterable ink material containing metal conductive nanoparticles is silver nanoparticle ink. In an additional alternative, the conductive nanospheres can be gold, copper, palladium, nickel and combinations thereof. In this description, the term "conductive bump" on a substrate is a conductive area for electrically connecting to a conductor in a substrate. Copper bumps are usually used, and aluminum, gold and other conductors can also be used. Copper bumps can be plated with nickel, gold, tin, palladium and combinations thereof to increase solderability, increase adhesion, and reduce or prevent corrosion or oxidation. In this description, a material described as a "B-stage" material is a material, such as a liquid, that can be partially cured to form a stable solid layer while remaining available for full curing in a later step. The B-stage polymer used for bonding the device can be partially cured to form a layer of the B-stage material. In an example arrangement, the polymer layer can be partially cured to form the B-stage material, and this layer can then be further and fully cured to bond the two surfaces together.

[0017] In this description, elements are described as having "equal thickness". Two elements have equal thickness when the outer surface of each element forms a common surface with the outer surface of the other element. However, during the manufacturing process, the thickness of either element may deviate, and such deviations may result in slight differences in thickness between the two elements, and due to these manufacturing differences, some portions of the common surface may be raised or lowered relative to other portions of the common surface. If two elements are intended to have equal thickness to form a common surface, as used herein, then the two elements are said to have equal thickness, even though some manufacturing deviations can and do occur.

[0018] In the arrangement, the problem of providing electrical connection between a semiconductor device die and a substrate is solved by dispensing a material having conductive nanoparticles over conductive bumps on a substrate, while a polymer dielectric layer is dispensed between bumps on the substrate to form a layer over the substrate. The semiconductor device die is aligned with the substrate and placed on the layer. Thermal compression can be used to bond the terminals of the semiconductor device die to the bumps on the substrate by sintering the conductive nanoparticles in the layer, thereby forming a conductive path between the devices. In the example arrangement, the sintered nanoparticles provide a low resistance conductive path in the z direction without forming an unwanted conductive path in the x and y directions, thereby preventing unwanted short circuits between pads.

[0019] The arrangements described herein are applicable to many "flip chip" device packages and flip chip mounted devices. In a flip chip arrangement, a semiconductor device die has electrical terminals that may include bonding pads arranged on a circuit side surface and / or conductive bumps or posts on the bonding pads. The semiconductor device die is mounted on a substrate with the circuit side surface facing the device mounting area on the substrate, or "flipped" (compared to an arrangement where the circuit side surface faces away from the substrate). A flip chip package may include a substrate with an array of solder balls on an exposed outer surface to form a ball grid array (BGA) package. Figure 7 BGA packages useful with these arrangements are shown in . Example applications include mounting multiple semiconductor device dies to a substrate by flip chip to form multiple chip modules. In an example arrangement, the substrate is a printed circuit board (PCB). The printed circuit board may include multiple layers of conductors laminated together and may be formed of dielectric materials. Materials used for printed circuit boards include copper, aluminum, gold, and brass for conductors, and insulating materials such as fiber reinforced glass (FR4), BT resin, plastic film, ceramic, polyimide, plastic layers, and tape. A semiconductor device package may be formed, the substrate is a conductive lead frame, and the semiconductor device is encapsulated in a molding compound after the semiconductor device die is mounted to the lead frame. Examples include quad flat no-lead (QFN) packages and leaded packages. Figure 5 A QFN package is shown for use with these arrangements.

[0020] Although some of the examples described use a single semiconductor device die on a substrate, multiple devices may be packaged together in an arrangement. The die may be stacked in an additional arrangement. A high voltage component (e.g., a FET device) may be provided as a discrete device and packaged using a substrate, and may be packaged with another device, for example, with a FET gate drive circuit. A sensor or analog-to-digital converter IC may be packaged with a digital integrated circuit to form a system-on-chip (SOC or SOIC) packaged device. A packaged device including multiple semiconductor devices may be referred to as a system-in-package (SIP). In some example arrangements, the substrate may be a portion of a semiconductor wafer that includes conductors for forming connections. In another example, the substrate itself may be another semiconductor device die, forming a stacked die arrangement.

[0021] In order to couple a flip-chip mounted semiconductor device die to a substrate, a vertical or "z" connection is required. In some arrangements, an additional molding step is required.

[0022] In the arrangement, the substrate has a conductive convex area arranged to receive at least one semiconductor device die. The conductive convex area is arranged corresponding to the electrical terminal on the semiconductor device die. Using inkjet deposition or other types of deposition, a liquid material is distributed to form a layer and cover the substrate surface between and around the conductive convex areas, while the upper surface of the conductive convex area remains exposed. The material is a dielectric and can be provided as a polymer ink, which is configured to be distributed by an inkjet nozzle, or as a liquid suitable for template printing. In one example, the conductive convex area extends from the surface of the substrate, and the polymer ink is distributed to a thickness sufficient to form a layer of approximately equal thickness to form a surface substantially continuous with the outermost surface of the convex area. In an example useful with the arrangement, the polymer may be one of a polyimide, an epoxy resin, a bismaleimide resin, an acrylate, or a mixture thereof. The thickness of the polymer may be between about 10 microns and several hundred microns. The polymer may be cured to make it more difficult to better implement subsequent processes, such as by thermal curing or UV curing. In an alternative example, this step may be omitted.

[0023] In one example, additional distribution of two other materials is performed simultaneously by using an inkjet deposition nozzle that traverses the surface area of ​​the substrate. The two materials include additional polymers in the portion of the substrate between the conductive convex areas, and materials including conductive nanoparticles, which are distributed to cover the exposed surface of the conductive convex areas. The two materials are distributed to form a layer of substantially uniform thickness, and the thickness of the two materials is approximately equal, so that the outermost exposed surface of the two materials forms a substantially continuous surface. In another additional example arrangement, the two materials are distributed in sequence, one nozzle is used for the two materials in sequence, or different nozzles are used to distribute the materials in sequence, but the distribution is performed in sequence. The second polymer can be a B-stage material, which can be partially cured by heating or UV to form a stable solid layer so that the opening for the conductive convex area is not disturbed by further processes. This step is optional and can be omitted. The conductive nanoparticle material can then be distributed in the second deposition process by the same or another inkjet nozzle tool. The inkjet deposition nozzle can very accurately distribute each of the materials to form the desired pattern without the need for photoresist, mask or etching steps, even in very fine geometric structures. Therefore, the deposition process is cost-effective and time-effective, and no acid or chemical treatment is required. The material is used very efficiently, and no excess material needs to be removed. The thickness of the second polymer layer can be approximately equal to the thickness of the bump, which is typically between a few microns and hundreds of microns.

[0024] After the conductive nanoparticles are deposited over the conductive bumps on the substrate, additional polymer material is deposited over the areas between the conductive bumps to form openings in the third polymer layer to expose the conductive nanoparticle material. These openings correspond to electrical terminals on a semiconductor device die to be mounted to the substrate, and the thickness of the deposited polymer layer corresponds to the thickness of the electrical terminals, whether in the form of copper bumps, pillar bumps, balls, or studs, as further described below, so that a semiconductor device having electrical terminals can be mounted on the conductive nanoparticle material.

[0025] In the arrangement, after the metal nanoparticles and the third polymer are distributed on the substrate, the semiconductor device die is flip-chip mounted to the substrate. In the example process, the semiconductor device die is aligned with the substrate so that the electrical terminals of the semiconductor device die are aligned correspondingly with the openings above the conductive bumps on the substrate, and then the semiconductor device die is placed in contact with the metal nanoparticle material and the third polymer. A thermal compression bonding step is performed, which sinters the conductive nanoparticles to form a low-resistance conductive path between the electrical terminals of the semiconductor device die and the conductive bumps on the substrate. In this process, the second and third polymer layers are cured to harden the materials. In one example, a temperature of 130 to 250 degrees Celsius can be used, and the thermal compression step is performed for about 5 to 15 seconds at a pressure of about 5 megapascals (MPa). Depending on the characteristics of the selected nanoparticle ink and polymer, in some arrangements, additional curing and additional sintering can be performed by using a thermal process without using pressure to further cure the polymer layer and increase the conductivity in the nanoparticle ink. In an additional alternative arrangement, the first polymer layer may be stencil printed on the substrate rather than inkjet deposited.

[0026] Figures 1A to 1G is a series of cross sections showing selected steps of an example process. Figure 1A , substrate 101 is shown oriented such that device mounting surface 104 faces upward (eg, Figures 1A to 1G oriented), the device mounting surface 104 has a plurality of conductive bumps 103 in a pattern. In one example, the conductive bumps are copper and may include additional electroplating layers as described above. In additional arrangements, the bumps 103 are made of other conductive materials. Figure 1B In the embodiment, the first polymer is dispensed to form a first polymer layer 105 between the conductive bumps 103 having a thickness approximately equal to the thickness of the conductive bumps 103. The first polymer layer 105 is an insulating dielectric and can be dispensed using inkjet deposition. Figure 1B As shown, the first polymer layer 105 may be dispensed by an inkjet deposition nozzle labeled 116. In an alternative arrangement, a template deposition process may be used to dispense the first polymer layer 105. The upper surface of the conductive bump 103 (eg, Figure 1B 103, the conductive bump 103 is at least partially exposed from the first polymer layer 105. In an example process, the first polymer layer 105 can be a B-stage material, which can be partially cured to form a B-stage layer to improve stability and strength before additional processing. The partial curing of the first polymer layer 105 can be completed by a thermal curing or UV curing process. In another example process, this partial curing may not be completed. The first polymer layer 105 forms a surface 106 that is substantially coextensive with the upper surface of the conductive bump 103, wherein the conductive bump is exposed from the first polymer layer 105 at the surface 106.

[0027] Figure 1C The next steps in the example process are shown in cross-section. Figure 1C In FIG. 1 , two inkjet deposition nozzles are used to simultaneously dispense additional polymer material from nozzle 116 and conductive nanoparticle material from nozzle 118. Because in inkjet deposition, the nozzle includes the ability to form "drops on demand" by sending electrical signals to the nozzle, when the inkjet nozzle is moved relative to the substrate surface, such as in a raster pattern, the two ink materials can be precisely deposited so that the conductive nanoparticles from 118 form conductive nanoparticle regions 109 in a layer just above the conductive bumps 103, while the additional polymer material from 116 forms a second polymer layer 107 in a layer just above the first polymer layer 105 and not covering the bumps 103. In this way, the second polymer layer 107 and the conductive nanoparticle regions 109 form an additional layer. The second polymer layer 107 can be partially cured, such as thermally or UV-cured, depending on the material selected, to harden this layer before further processing. The second polymer layer 107 has a surface 108, which is generally a continuous surface between the second polymer layer 107 and the conductive nanoparticle region 109, but some deviations may occur during the manufacturing process, so that the thickness of the layer may have slight deviations. In order to form a uniform and desired thickness layer, multiple thinner layers can be deposited in multiple passes. Or a single pass can be used. Although two nozzles 116, 118 are shown in these examples to clearly illustrate, in an inkjet deposition tool, many nozzles, such as tens or hundreds of nozzles, can be used in each ink distribution tool. In addition, the deposition tool may have multiple heads that pass through the substrate at the same time or in a certain sequential pattern to distribute materials more quickly.

[0028] Figure 1D Another cross-sectional view depicts the additional step of depositing a third polymer layer. Figure 1D In the embodiment, inkjet deposition tool 116 deposits third polymer layer 111. Third polymer layer 111 is deposited to a thickness 112 selected to be approximately equal to the thickness of semiconductor device die ( Figure 1D The height of the electrical terminals on the surface 108 (not shown) is substantially corresponding to the height of the electrical terminals on the surface 108 (not shown), and the semiconductor device die will be flip-chip mounted to the substrate 101, as further described below. The third polymer layer 111 is deposited on the second polymer layer 107 on the surface 108, and the surface of the conductive nanoparticle area 109 is still covered by this third polymer layer 111, so that the electrical terminals ( Figure 1D Not shown, but see below Figure 1E) to satisfy the conductive nanoparticle area when the semiconductor device die is flip-chip mounted. The materials used for the polymer layers described so far, i.e., the first polymer layer 105, the second polymer layer 107, and the third polymer layer 111, can be the same polymer material. In alternative arrangements, the polymer layers can be different. For example, some of the polymer layers can be UV-curable, while others are thermally cured materials. The materials used for the first polymer layer 105 and the second polymer layer 107 can be B-stage materials, which can be partially cured to form B-stage layers, and additional curing occurs during the later thermal treatment described below. Combinations of various polymer layer types form additional alternative arrangements.

[0029] Figure 1E The next step in the example process is depicted in cross-section. Figure 1E 1 , a semiconductor device die 121 is placed in a flip chip orientation in correspondence with the substrate 101, such as by a pick and place tool (not shown). The electrical terminals 123 are aligned correspondingly to the conductive nanoparticle regions 109 covering the conductive bumps 103 on the substrate 101. The semiconductor device die 121 is then brought into physical contact with the third polymer layer 111 and the conductive nanoparticle regions 109. The height 112 of the third polymer layer is selected to substantially correspond to the thickness of the electrical terminals 123, so that when the semiconductor device die 121 is in contact with the upper surface 114 of the third polymer layer 111, the electrical terminals 123 will be in contact with the conductive nanoparticle regions 109.

[0030] exist Figure 1F , it is shown that the semiconductor device die 121 and the substrate 101 are bonded together using a combination of heat and pressure (thermocompression) to simultaneously solidify the first polymer layer 105, the second polymer layer 107, and the third polymer layer 111, and to sinter the sinterable nanoparticles in the conductive nanoparticle region 109 and form a low resistance conductive path between the electrical terminal 123 on the semiconductor device die 121 and the conductive bump 103 on the substrate 101. In the example process, the thermal compression step can be followed by additional heat treatment to further solidify the first polymer layer 105, the second polymer layer 107, and the third polymer layer 111, and further sinter the metal nanoparticles in the conductive nanoparticle region 109 without applying mechanical pressure. In a further example arrangement, this additional curing is omitted. In one example, a temperature of 130 to 250 degrees Celsius can be used, and the thermal compression step is performed at a pressure of approximately 5 megapascals (MPa) for about 5 to 15 seconds. Other temperature and pressure values ​​can be used to form alternative arrangements.

[0031] Figure 1G The completed packaged semiconductor device arrangement 100 is shown in another cross-sectional view. Figure 1G, a semiconductor device die 121 is bonded to a substrate 101 through a conductive nanoparticle region 109 and sintered nanoparticles in the first, second, and third polymer layers 105, 107, and 111. A molding compound 122 covers a portion of the substrate 101 on the device mounting side, but does not cover the opposite side, and can be described as "overmolded." This molding compound layer 122 protects the semiconductor device die 121 and the first, second, and third polymer layers 105, 107. Alternatively, a metal cap (not shown) can be used to cover the die without the use of a molding compound. Figure 1G The substrate 101 in the embodiment further includes an array of solder balls or bumps 125 that complete the package 100, which is a ball grid array (BGA) type package. These solder balls or bumps may be added after the semiconductor device die 121 is mounted to the substrate 101. The molding compound 122 may be formed using an encapsulation process using a resin or epoxy. Note that although the molding process is referred to as "encapsulation", even when the molding compound is encapsulated by the molding process, portions of the substrate 101 are not covered by the molding compound, e.g. Figure 1G The bottom surface of the substrate 101 in the mold compound 122 may include fillers to improve heat transfer performance. The mold compound may be liquid or solid at room temperature. If it is solid at room temperature, a transfer mold or a block mold may be used by first heating the mold compound in a hot chamber and then pressing it through a flow channel into a mold containing the semiconductor device die and substrate assembly. Liquid resins may be used as a substitute. A block mold press may be used. Multiple mounted devices may be molded simultaneously and then separated from each other after the molding process is completed.

[0032] Figure 2 is used to form Figures 1A to 1G A flowchart of an example process of the arrangement shown. Figure 2 In the process 200, from step 202, inkjet deposition is performed to deposit a first polymer layer on the substrate between the conductive convex areas, filling the gaps between the convex areas with the polymer layer, the thickness of the polymer layer being approximately equal to the thickness of the convex areas. At step 204, a curing step is performed to at least partially cure the first polymer layer before further processing, the curing being used to harden and stabilize the first polymer layer. The curing can be thermal curing or UV curing, depending on the type of polymer used for the first polymer layer.

[0033] At step 206, process 200 continues by simultaneously depositing a second polymer layer and a region of conductive nanoparticles. Figure 1C In one example, an inkjet deposition tool is used to simultaneously deposit the second polymer layer and the nanoparticle region, such that the nanoparticle material is deposited on the surface of the conductive convex region on the substrate. Figure 1BAs shown, when the first polymer layer is deposited, the upper surface of the conductive protrusion remains exposed. The second polymer layer is deposited on the first polymer layer between the conductive protrusions, so that the second polymer layer is not deposited over the conductive protrusions, and the second polymer layer and the metal nanoparticle area form a substantially continuous upper surface between the two types of materials.

[0034] At step 208, the second polymer layer may be partially cured to stabilize the layer and make it less likely to be damaged by subsequent processes. Curing may also be UV curing or other light curing, thermal curing, or both, depending on the materials used. The second polymer layer may be the same material as the first polymer layer, or in an alternative arrangement, may be a different material.

[0035] At step 209, a third polymer layer is deposited over the second polymer layer and between the conductive nanoparticle material regions, such as Figure 1D The third polymer layer has a thickness that substantially corresponds to the thickness of electrical terminals on a semiconductor die that will be flip-chip mounted on a substrate described below. Figure 1D Deposition of a third polymer layer is shown.

[0036] At step 210, a pick and place tool places a semiconductor device die over the substrate, with electrical terminals on die pads of the semiconductor device die corresponding to openings in the third polymer layer, the openings corresponding to conductive bumps on the substrate. Figure 1E The semiconductor device die is in physical contact with the metal nanoparticle region and the second polymer layer.

[0037] At step 212, a thermal compression step is performed. Heat and pressure are applied to press the semiconductor device die onto the second and third polymer layers and the metal nanoparticle regions, and the heat of the thermal process cures the polymer layers and sinters the nanoparticles. Due to the sintering of the nanoparticles, a conductive path is formed between the conductive bumps on the bonding pads of the semiconductor device die and the conductive bumps on the substrate. This step is performed at Figure 1F In one example, a temperature of 130 to 250 degrees Celsius may be used, and the hot compression step may be performed at a pressure of approximately 5 megapascals (MPa) for approximately 5 to 15 seconds. Other temperature and pressure values ​​may be used to form alternative arrangements.

[0038] exist Figure 2 At step 213 in the embodiment, an optional additional thermal step is shown. In some example processes, the additional thermal step is used to further solidify the polymer layer and further sinter the sinterable nanoparticles. In other example processes, this step 213 can be omitted.

[0039] Figure 2Step 214 in FIG. 1 depicts the final step of the process, where the substrate and semiconductor device die are further protected by molding compound, and additional processes are performed to complete the process. Figure 1G A packaged semiconductor device is shown.

[0040] Figure 3 The steps of an alternative process 300 for forming an arrangement are depicted in a flow chart. Beginning at step 302, a first polymer layer is deposited on the substrate on the device mounting surface between the conductive pads to form a layer that fills the gaps between the pads. In one example process, an inkjet deposition process is used to dispense the first polymer layer. In another alternative arrangement, a template deposition process may be used.

[0041] exist Figure 3 In step 304, the process continues by performing at least a partial cure of the first polymer layer. The first polymer layer may be thermally cured or UV cured or other frequency light cured depending on the polymer. A full cure may also be performed depending on the material selected for the first polymer layer. Figure 1B As shown, the first polymer fills the gaps between the conductive protrusions on the substrate but does not cover the upper surfaces of the conductive protrusions, and the first polymer layer forms a substantially continuous surface with the upper surfaces of the conductive protrusions.

[0042] exist Figure 3 At step 306, another deposition is performed. In the example process, the second polymer layer is deposited only on the first polymer layer using an inkjet deposition tool, leaving the upper surface of the conductive bump exposed. At step 307, the second polymer layer can be cured. Depending on the polymer material, thermal curing, light curing, or UV polymer curing can also be used. If the second polymer layer is a B-stage material, then a B-stage layer can be formed to make the layer stable and less likely to be damaged by subsequent steps.

[0043] At step 308, another deposition is performed to deposit the conductive nanoparticle material on the exposed surface of the conductive bumps and form a substantially continuous surface with the second polymer layer. The result of the process after this step is similar to Figure 1C As shown, the upper surface of the second polymer layer and the upper surface of the metal nanoparticles form a surface layer.

[0044] exist Figure 3 At step 309 in the method, a third polymer layer is deposited on the second polymer layer between the regions of the conductive nanoparticle material. Figure 1D Displayed in.

[0045] exist Figure 3At step 310 in the method, a pick and place tool positions a semiconductor device die over a substrate with a circuit side surface facing a conductive bump on the substrate and aligns the semiconductor device die so that electrical terminals on the semiconductor device die and the conductive nanoparticle material are placed over the substrate and aligned with the conductive bump on the substrate. This step corresponds to Figure 1E cross section.

[0046] At step 312, a semiconductor device die is placed in contact with the second polymer layer and the conductive nanoparticle region, and the semiconductor device die is bonded to the substrate using a combination of pressure and heat energy (i.e., thermocompression). The heat in the thermocompression process both cures the first, second, and third polymer layers (if not previously cured) and sinters the conductive nanoparticle material to form a low resistance conductive path between the conductive terminals on the semiconductor device die and the conductive bumps on the substrate, forming a z-direction connection rather than an x- or y-direction connection. In one example, a temperature of 130 to 250 degrees Celsius may be used, and the thermocompression step may be performed at a pressure of approximately 5 megapascals (MPa) for approximately 5 to 15 seconds. Other temperature and pressure values ​​may be used to form alternative arrangements.

[0047] The results of this step are, for example, Figure 1F In addition, additional heat curing and sintering can be performed without the use of pressure to further cure the polymer layer and further sinter the conductive nanoparticle material. In another alternative process, the additional heat treatment can be omitted, depending on the materials used and the layer thickness.

[0048] At step 314, the assembly of the semiconductor device package is completed. Figure 1G As shown in , the semiconductor device die can be covered by a molding compound by encapsulation or overmolding. Alternatively, a metal cover can be used to cover the die without molding. In addition, a ball grid array package can include a plurality of solder balls on opposite surfaces of a substrate for surface mounting to a system printed circuit board, such as Figure 1F shown.

[0049] Figure 4 An arrangement is shown in cross-section in which a semiconductor device die 421 is mounted on a substrate 401 having vertical connections formed using one of the deposition processes described above and forming a leadless package arrangement. Figure 4 For the sake of clarity, it is used in conjunction with Figure 1G The reference numerals for similar elements are similar. For example, semiconductor device die 421 corresponds to Figure 1G The semiconductor device bare chip 121 in the Figure 44, a semiconductor device die 421 is flip-chip mounted to a substrate 401. An electrical terminal 423 on the semiconductor device die 421 is aligned and coupled to a conductive bump 403 on the substrate 401. A first polymer layer 405 surrounds the conductive bump 403. A second polymer layer 407 has an upper surface that forms a substantially continuous surface with an upper surface of a conductive nanoparticle region 409 on the bump 403. A third polymer layer 411 is formed on the second polymer layer 407 between the conductive nanoparticle regions 409. A low resistance path formed by sintering the conductive nanoparticle region 409 connects in the z direction between the semiconductor device die electrical terminal 423 and the conductive bump 403 on the substrate 401. In this example, the substrate 401 is a metal lead frame that undergoes a partial etching process (sometimes referred to as a "half-etched" lead frame) to form an upper layer 402 and a lower layer including a lead 413 and a thermal or electrical pad 412. The lead frame can be formed by performing a partial etch from one side of the substrate 401 to remove material, and performing a second partial etch from the opposite side to remove material, in some areas, the two partial etches can be combined to form an opening extending through the thickness of the lead frame, and in other cases, a ledge or corner can be formed in one layer or another of the lead frame. Molding compound 422 can be placed in the opening and removed areas to complete the substrate 401. These etching and molding steps can be completed before using the substrate to form a pre-molded lead frame (PMLF) used as the substrate 401. After the semiconductor device die 421 is mounted to the substrate 401 and the above-mentioned thermal compression step is performed to cure the polymer layer and sinter the conductive nanoparticles to form a low resistance electrical path, an overmolding step can be performed to form the molding compound 422 to complete the packaged device 400.

[0050] Figure 5 Describe the projection diagram corresponding to Figure 4 A cross-section of a quad flat no-lead (QFN) arrangement 500 is shown. Figure 5 In FIG. 5 , the molding compound 522 covers at least the upper portion of the semiconductor device die and the substrate. The package terminals 513 arranged for surface mounting of the packaged device 500 are shown, which correspond to Figure 4 Because the package terminals do not extend from the body of the packaged semiconductor device, the package is described as a "leadless" semiconductor package.

[0051] Figure 6 An arrangement 600 is shown in cross-section including a plurality of semiconductor device dies mounted to a substrate 601 using one of the example processes described above. Figure 6 In FIG. 6 , as described above, semiconductor device 631 and another semiconductor device 633 are shown mounted to substrate 601 and electrically coupled to conductive bumps on substrate 601 using sintered conductive nanoparticles and a polymer layer. Figure 6In the example of FIG. 2 , two semiconductor devices are shown, but in alternative examples, additional semiconductor device dies may be mounted to the substrate. Figure 6 In FIG. 6 , a ball grid array package is formed using solder balls 625, wherein an overmold of a molding compound 635 covers at least the upper surface of the substrate 601 and the semiconductor device die.

[0052] Figure 7 A ball grid array package 700 is depicted for deployment in projection view and bottom plan view. Figure 7 In FIG. 7 , the molding compound body 735 of the ball grid array package 700 is shown together with the ball grid array terminals 725. The BGA package 700 corresponds to Figure 6 Arrangement 600 with multiple semiconductor devices or Figure 1G The BGA package 100 in FIG. These arrangements may be packaged as other package types for semiconductor devices.

[0053] Modifications may be made in the arrangements described and other alternative arrangements may be devised within the scope of the claims.

Claims

1. A packaged semiconductor device, comprising: a substrate having a device mounting surface and an opposing surface, the substrate having conductive bumps having a first thickness spaced apart from one another on the device mounting surface; a first polymer layer located on the device mounting surface of the substrate between and around the conductive bumps and having a second thickness equal to the first thickness of the conductive bumps, the conductive bumps having outer surfaces not covered by the first polymer layer, the outer surfaces of the first polymer layer forming a common surface with the outer surfaces of the conductive bumps; a second polymer layer on the first polymer layer, the second polymer layer having a third thickness, the outer surface of the conductive convex area not being covered by the second polymer layer; a conductive nanoparticle material on the outer surface of the conductive convex region and having a fourth thickness equal to the third thickness, the outer surface of the second polymer layer forming a common surface with the outer surface of the conductive nanoparticle material; a third polymer layer located on the second polymer layer between the conductive nanoparticle materials on the conductive bumps, the conductive nanoparticle materials having surfaces exposed from the third polymer layer; and At least one semiconductor device die is mounted to the third polymer layer and has electrical terminals bonded to the conductive nanoparticle material. 2 . The packaged semiconductor device of claim 1 , wherein the third polymer layer has a thickness corresponding to a thickness of the electrical terminals of the semiconductor device die. 3 . The packaged semiconductor device of claim 1 , wherein the first polymer layer is one selected from the group consisting of polyimide, epoxy resin, bismaleimide resin, acrylate, and combinations thereof. 4 . The packaged semiconductor device of claim 1 , wherein the first polymer layer, the second polymer layer, and the third polymer layer are one selected from the group consisting of: polyimide, epoxy resin, bismaleimide resin, acrylate, and combinations thereof.

5. The packaged semiconductor device of claim 1, wherein the conductive nanoparticle material is a sinterable nanoparticle material. The packaged semiconductor device of claim 5 , wherein the conductive nanoparticle material comprises a metal. The packaged semiconductor device of claim 6 , wherein the conductive nanoparticle material comprises silver.

8. The packaged semiconductor device of claim 1, wherein the conductive nanoparticle material is one selected from the group consisting of: silver, tin, nickel, copper, gold, palladium, and combinations thereof.

9. The packaged semiconductor device of claim 1 and further comprising package terminals on a surface of the substrate opposite to the device mounting surface. 10 . The packaged semiconductor device of claim 9 , wherein the package terminals further comprise an array of solder balls to form a ball grid array package.

11. The packaged semiconductor device according to claim 9, wherein the package terminals form a leadless package.

12. The packaged semiconductor device of claim 1, wherein the substrate comprises a printed circuit board.

13. The packaged semiconductor device of claim 1, wherein the substrate comprises a pre-molded lead frame.

14. The packaged semiconductor device of claim 1, wherein the substrate comprises an additional semiconductor device die.

15. A method for forming an arrangement, comprising: dispensing a first polymer layer around spaced apart conductive bumps on a device mounting surface of a substrate, the first polymer layer having a first thickness equal to a second thickness of the conductive bumps; curing the first polymer layer, wherein the outer surface of the conductive convex area is exposed from the first polymer layer; dispensing a second polymer layer over the first polymer layer; dispensing a conductive nanoparticle material on the exposed outer surfaces of the conductive bumps; dispensing a third polymer layer on the second polymer layer between the conductive bumps, the conductive nanoparticle material being exposed from the third polymer layer; mounting a semiconductor device die on the third polymer layer, the semiconductor device die having electrical terminals aligned with and in contact with the conductive nanoparticle material over the conductive bumps; and Pressure and heat are applied to bond the semiconductor device die to the substrate, the heat curing the second polymer layer and the third polymer layer and sintering the conductive nanoparticle material to form electrical connections between the electrical terminals of the semiconductor device die and the conductive bumps of the substrate.

16. The method of claim 15, wherein the dispensing of the first polymer layer is performed by an inkjet deposition process. The method of claim 15 , wherein the dispensing of the first polymer layer is performed by a template deposition process.

18. The method of claim 15, wherein the first polymer layer is UV curable.

19. The method of claim 15, wherein the first polymer layer is thermally curable.

20. The method of claim 15, wherein dispensing the second polymer layer and dispensing the conductive nanoparticle material are performed simultaneously.

21. The method of claim 15, wherein dispensing the second polymer layer is performed before dispensing the conductive nanoparticle material.

22. The method of claim 15, wherein dispensing the first polymer layer further comprises dispensing one selected from the group consisting of polyimide, epoxy resin, bismaleimide resin, acrylate, and combinations thereof.

23. The method of claim 15, wherein dispensing the first polymer layer, the second polymer layer, and the third polymer layer each further comprises dispensing one selected from the group consisting of polyimide, epoxy resin, bismaleimide resin, acrylate, and combinations thereof.

24. The method of claim 15, wherein dispensing the conductive nanoparticle material comprises dispensing one selected from the group consisting of: silver, tin, nickel, copper, gold, palladium, and combinations thereof.

25. The method of claim 15, wherein dispensing the second polymer layer and dispensing the third polymer layer further comprise inkjet deposition.

26. The method of claim 15, wherein the third polymer layer is dispensed to a thickness corresponding to a height of the electrical terminals on the semiconductor device die.

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