Shift register, control method, light emitting control circuit and display device

Abstract

The present application discloses a shift register, a light emitting control circuit and a display device. The shift register includes an input module, a first node, a second node, a first control module, a second control module, a third node, a light emitting signal output module and a gate control module. The input module is connected to the first node and the second node, and is used to receive an input signal and control the potential of the first node and the second node. The first control module is connected to the first node and the second node, and is used to control the potential of the second node according to the potential of the first node. The second control module is connected to the first node, the third node and the gate control module, and is used to control the potential of the first node and the third node and control the gate control module to output a gate control signal. The light emitting signal output module is connected to the second node and the third node, and is used to output a light emitting control signal according to the potential of the second node or the third node. In this way, the shift register can output a gate control signal and a light emitting control signal, which simplifies the circuit design.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register, a control method, a light emitting control circuit and a display device. Background Art

[0002] Generally, in the existing driving scheme of the internal compensation pixel circuit of PMOSOLED, two groups of GOA outputs, EMGOA and GateGOA, are required, wherein EMGOA provides N-type output to output EM (luminous) signal, and GateGOA provides P-type output to output Gate signal. However, setting two groups of GOA units will make the left and right borders of the display panel wider, and the requirements for the driving circuit process to achieve intelligent display and low-power display are relatively complex. Therefore, how to simplify the process of the driving circuit and ensure that both N and P types of outputs are provided at the same time has become an urgent problem to be solved. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application needs to provide a shift register, a control method, a light emitting control circuit and a display device.

[0004] The shift register of the embodiment of the present application includes an input module, a first node, a second node, a first control module, a second control module, a third node, a light emitting signal output module and a gate control module; wherein,

[0005] The input module is connected to the first node and the second node, and is used to receive an input signal and control the potential of the first node and the second node;

[0006] The first control module is connected to the first node and the second node, and is used to control the potential of the second node according to the potential of the first node;

[0007] The second control module is connected to the first node, the third node and the gate control module, and is used to control the potential of the first node and the third node and control the gate control module to output a gate control signal; and

[0008] The light emitting signal output module is connected to the second node and the third node, and is used to output the light emitting control signal according to the potential of the second node or the third node.

[0009] In some embodiments, the shift register is connected to a signal input terminal, and the gate control module includes a first sub-gate control module, a second sub-gate control module, and a first output terminal;

[0010] The first sub-gate control module is connected to the first level end, the signal input end and the first output end, and the first sub-gate control module is used to transmit the first level of the first level end to the first output end according to the input signal transmitted by the signal input end;

[0011] The second sub-gate control module is connected to the second control module, the first clock signal terminal and the first output terminal, and is used to transmit the first clock signal of the first clock signal terminal to the first output terminal according to the potential input by the second control module.

[0012] In some embodiments, the first sub-gate control module includes a first output control transistor, a first output transistor and a first storage capacitor; wherein,

[0013] A first electrode of the first output control transistor is connected to the first level end, a second electrode of the first output control transistor is connected to the first storage capacitor, and a gate of the first output control transistor is connected to the signal input end;

[0014] A first electrode of the first output transistor is connected to the first level end, a second electrode of the first output transistor is connected to the first output end, and a gate of the first output control transistor is connected to the signal input end;

[0015] A first storage capacitor, wherein a first end of the first storage capacitor is connected to the second electrode of the first output control transistor, and a second end of the first storage capacitor is connected to the first output end.

[0016] In some embodiments, the second sub-gate control module includes a second output control transistor and a second output transistor; wherein,

[0017] A first electrode and a gate of the second output control transistor are connected to the second control module, and a second electrode of the second output control transistor is connected to the first storage capacitor and the second output transistor;

[0018] A first electrode of the second output transistor is connected to the first clock signal terminal, a second electrode of the second output transistor is connected to the first output terminal, and a gate of the first output transistor is connected to a second electrode of the second output control transistor.

[0019] In some embodiments, the luminous signal output module includes a third output transistor, a fourth output transistor and a second output terminal.

[0020] A first electrode of the third output transistor is connected to the second level end, a second electrode of the third output transistor is connected to the second output end, and a gate of the third output transistor is connected to the second node;

[0021] A first electrode of the fourth output transistor is connected to the first level end, a second electrode of the fourth output transistor is connected to the second output end, and a gate of the fourth output transistor is connected to the third node.

[0022] In some embodiments, the shift register is connected to a signal input terminal, and the input module includes a first transistor, a second transistor, and a third transistor; wherein

[0023] A first electrode of the first transistor is connected to the signal input terminal, a second electrode of the first transistor is connected to the second node, and a gate of the first transistor is connected to a first clock signal terminal;

[0024] A first electrode of the second transistor is connected to a second level terminal, a second electrode of the second transistor is connected to the first node, and a gate of the second transistor is connected to the first clock signal terminal;

[0025] A first electrode of the third transistor is connected to the first clock signal, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the second node;

[0026] In some embodiments, the input module further comprises:

[0027] A second storage capacitor, wherein a first end of the second storage capacitor is connected to the second clock signal end, and a second end of the second storage capacitor is connected to the second node.

[0028] In some embodiments, the first control module includes a fourth transistor and a fifth transistor,

[0029] A first electrode of the fourth transistor is connected to the first level end, a second electrode of the fourth transistor is connected to the fifth transistor, and a gate of the fourth transistor is connected to the first node;

[0030] A first electrode of the fifth transistor is connected to a second electrode of the fourth transistor, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to a second clock signal terminal.

[0031] In some embodiments, the shift register further includes a fifth node and a sixth node, the first control module includes a fourth transistor, a fifth transistor and a second storage capacitor, wherein

[0032] A first electrode of the fourth transistor is connected to the first level end, a second electrode of the fourth transistor is connected to the second storage capacitor, and a gate of the fourth transistor is connected to the fifth node;

[0033] A first electrode of the fifth transistor is connected to the second clock signal terminal, a second electrode of the fifth transistor is connected to the second storage capacitor, and a gate of the fifth transistor is connected to the second node;

[0034] A first end of the second storage capacitor is connected to the second electrode of the fourth transistor and the second electrode of the fifth transistor, and a second end of the second storage capacitor is connected to the second node.

[0035] In some embodiments, the shift register further includes an isolation module, the isolation module includes a first isolation transistor and a second isolation transistor, the first isolation transistor is used to isolate the first node and the fifth node, and the second isolation transistor is used to isolate the second node and the sixth sub-node;

[0036] A first electrode of the first isolation transistor is connected to the fifth node, a second electrode of the first isolation transistor is connected to the first node, and a gate of the first isolation transistor is connected to the second level end;

[0037] A first electrode of the second isolation transistor is connected to the sixth node, a second electrode of the first isolation transistor is connected to the second node, and a gate of the second isolation transistor is connected to the second level end.

[0038] In some embodiments, the second control module includes a sixth transistor, a seventh transistor, an eighth transistor, a third storage capacitor, a fourth storage capacitor and a fourth node; wherein

[0039] A first electrode of the sixth transistor is connected to the second clock signal terminal, a second electrode of the sixth transistor is connected to the fourth node, and a gate of the sixth transistor is connected to the first node;

[0040] A first electrode of the seventh transistor is connected to the fourth node, a second electrode of the seventh transistor is connected to the third node, and a gate of the seventh transistor is connected to the second clock signal terminal;

[0041] A first electrode of the eighth transistor is connected to the first level end, a second electrode of the eighth transistor is connected to the third node, and a gate of the eighth transistor is connected to the second node;

[0042] A first end of the third storage capacitor is connected to the third node, and a second end of the third storage capacitor is connected to the first level end;

[0043] A first end of the fourth storage capacitor is connected to the first node, and a second end of the fourth storage capacitor is connected to the fourth node.

[0044] The shift register light emitting control circuit of the present application comprises a shift register as described in any one of the above items.

[0045] The display device according to the embodiment of the present application includes a pixel driving circuit and the light emitting control circuit as described above.

[0046] In some embodiments, the pixel driving circuit is connected to any one of the shift registers described above, and the pixel driving circuit includes a light-emitting signal input terminal and a gate signal input terminal, the light-emitting signal input terminal is connected to the light-emitting signal output module, the gate signal input terminal is connected to the gate control module, the light-emitting signal input terminal is used to receive the light-emitting control signal output by the light-emitting signal output module, and the gate signal input terminal is used to receive the gate control signal output by the gate signal output module.

[0047] The control method of the embodiment of the present application is used to control any one of the shift registers described above, and the control method includes:

[0048] After the input module receives the first hour of the input signal of 3H, controlling the light-emitting signal output module to output a light-emitting control signal of 3H; and

[0049] After the input module receives the 2H of the input signal of 3H, the gate control module is controlled to output a gate control signal less than 1H.

[0050] In the shift register, control circuit, light control circuit and display device of the embodiment of the present application, by setting the input module, the first node, the second node, the first control module, the second control module, the third node, the light signal output module and the gate control module, after the input module receives the input signal, the light signal output module can output the light control signal, and the gate control module can output the gate control signal. In this way, the circuit design is simplified, thereby reducing the cost and achieving a narrow frame.

[0051] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0053] Figure 1 It is a module schematic diagram of a shift register according to an embodiment of the present application.

[0054] Figure 2 It is another module schematic diagram of the shift register according to the implementation mode of the present application.

[0055] Figure 3It is a circuit connection diagram of the shift register according to the embodiment of the present application.

[0056] Figure 4 It is a circuit connection diagram of the shift register according to the embodiment of the present application.

[0057] Figure 5 It is a timing diagram of the shift register according to the embodiment of the present application.

[0058] Figure 6 It is a module schematic diagram of a display device according to an embodiment of the present application.

[0059] Description of main component symbols:

[0060] Input module 11, first transistor M1, second transistor M2, third transistor M3, second storage capacitor C2;

[0061] A first control module 12, a fourth transistor M4, and a fifth transistor M5;

[0062] A second control module 13, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a third storage capacitor C3, and a fourth storage capacitor C4;

[0063] A light emitting signal output module 14, a third output transistor M10, a fourth output transistor M9, and a second output terminal Out2;

[0064] The gate control module 15, the first sub-gate control module 152, the first output control transistor M12, the first output transistor M14, the first storage capacitor C1, the second sub-gate control module 154, the second output control transistor M13, the second output transistor M11, and the first output terminal Out1;

[0065] Isolation module 16, first isolation transistor M15, second isolation transistor M16;

[0066] A first node P1, a second node P2, a third node P3, a fourth node P4, a fifth node P5, and a sixth node P6;

[0067] Signal input terminal IN, input signal Input, first level terminal VGH, first level Vgh, second level terminal VGL, second level Vgl, first clock signal terminal CLK, first clock signal clk, second clock signal terminal CLKB, second clock signal clkb;

[0068] Shift register 10 , light emitting control circuit 100 , gate driving circuit 200 , and display device 1000 . DETAILED DESCRIPTION

[0069] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0070] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0071] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0072] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0073] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0074] In addition, it should be noted that in the embodiments of the present application, the transistors used can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is directly described as the second pole, so the source and drain of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0075] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. The embodiments of the present disclosure are all described by taking P-type transistors as an example, that is, in the embodiments of the present application, when the gate of the transistor receives a low-level signal, the first and second electrodes of the transistor are turned on. Based on the description and teaching of the implementation of the P-type transistor in the present disclosure, ordinary technicians in this field can easily think of the implementation of the present disclosure using N-type transistors without making creative work. Therefore, these implementations are also within the protection scope of the present disclosure.

[0076] See also Figure 1 The present application provides a shift register 10, including an input module 11, a first node P1, a second node P2, a first control module 12, a second control module 13, a third node P3, a gate control module 15 and a light emitting signal output module 14.

[0077] The input module 11 is connected to the first node P1 and the second node P2, and is used to control the potential of the first node P1 and the second node P2. The first control module 12 is connected to the first node P1 and the second node P2, and is used to control the potential of the second node P2 according to the potential of the first node P1. The second control module 13 is connected to the first node P1, the third node P3 and the gate control module 15, and is used to control the potential of the first node P1 and the third node P3. The second control module 13 is also used to control the gate control module 15 to output a gate control signal. The light-emitting signal output module 14 is connected to the second node P2 and the third node P3, and is used to output a light-emitting control signal according to the potential of the second node P2 or the third node P3.

[0078] In the shift register 10 of the present application, by setting the input module 11, the first node P1, the second node P2, the first control module 12, the second control module 13, the third node P3, the light signal output module 14 and the gate control module 15, after the input module 11 receives the input signal Input, the light signal output module 14 can output the light control signal, and the gate control module 15 can output the gate control signal. In this way, the shift register 10 can provide two types of outputs, simplifying the process of the driving circuit, reducing the cost, and being conducive to simplifying the structure of the display panel, so that the display panel can achieve a narrow frame design and improve the user experience.

[0079] See also Figure 3 or Figure 4 Specifically, the shift register 10 is respectively connected to a first clock signal terminal CLK, a second clock signal terminal CLKB, a first level terminal VGH, a second level terminal VGL, a signal input terminal IN, and a pixel driving circuit, wherein the first clock signal terminal CLK is used to transmit a first clock signal clk to the shift register 10, the second clock signal terminal CLKB is used to transmit a second clock signal clkb to the shift register 10, and the signal input terminal IN is used to transmit an input signal Input to the shift register 10. The first level terminal VGH is used to transmit a first level Vgh to the shift register 10, and the second level terminal VGL is used to transmit a second level Vgl to the shift register 10.

[0080] Among them, the first clock signal clk and the second clock signal clkb include a high level signal and a low level signal, and the cycle duration of the first clock signal clk and the second clock signal clkb is the same. In one clock cycle, the duration of the high level signal is greater than the duration of the low level signal. The input signal Input includes a high level signal and a low level signal, and the duration of the high level signal of the input signal Input is greater than the clock cycle of the first clock signal clk or the second clock signal clkb, for example. The duration of the high level signal of the input signal Input is 3H, then one clock cycle is less than 3H. The first level Vgh is inverted with the second level Vgl, for example, in the present application, the first level Vgh is a high level, and the second level Vgl is a low level.

[0081] Furthermore, the potential of the first clock signal clk and the second clock signal clkb when they are high-level signals can be the same as the potential of the first voltage, and the potential of the first clock signal clk and the second clock signal clkb when they are low-level signals can be the same as the potential of the second voltage. In addition, the potential of the high-level signal of the first clock signal clk can be equal to the first level Vgh, and the potential of the low-level signal of the first clock signal clk can be equal to the second level Vgl.

[0082] The shift register 10 includes an input module 11, a first control module 12, a second control module 13, a gate control module 15, a light emitting signal output module 14, a first node P1, a second node P2, a third node P3 and a fourth node P4.

[0083] The input module 11 is connected to the first control module 12, the second control module 13 and the light signal output module 14 by connecting to the first node P1 and the second node P2. The first control module 12 is connected to the light signal output module 14 and the second control module 13 by connecting to the first node P1 and the second node P2. The second control module 13 is connected to the light signal output module 14 by connecting to the third node P3, and is connected to the gate control module 15 by connecting to the fourth node P4.

[0084] Please further combine Figure 3 The input module 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a second storage capacitor C2. Of course, in some embodiments, the input module 11 may not include the second storage capacitor C2 (such as Figure 4 shown).

[0085] Among them, the first electrode of the first transistor M1 is connected to the signal input terminal IN, the second electrode of the first transistor M1 is connected to the second node P2, the gate of the first transistor M1 is connected to the first clock signal terminal CLK, and the first transistor M1 is used to transmit the input signal Input of the signal input terminal IN to the second node P2 according to the first clock signal clk of the first clock signal terminal CLK to change the potential of the second node P2.

[0086] The first electrode of the second transistor M2 is connected to the second level terminal VGL, the second electrode of the second transistor M2 is connected to the first node P1, the gate of the second transistor M2 is connected to the first clock signal terminal CLK, and the second transistor M2 is used to transmit the first clock signal clk according to the first clock signal terminal CLK to the first node P1.

[0087] The first electrode of the third transistor M3 is connected to the first clock signal terminal CLK, the second electrode of the third transistor M3 is connected to the first node P1, and the gate of the third transistor M3 is connected to the second node P2. The third transistor M3 is used to transmit the first clock signal clk of the first clock signal terminal CLK to the first node P1 according to the potential of the second node P2.

[0088] A first end of the second storage capacitor C2 is connected to the second clock signal terminal CLKB, and a second end of the second storage capacitor C2 is connected to the second node P2 for compensating the potential of the second node P2.

[0089] Please further combine Figure 3 In some embodiments, the first control module 12 includes a fourth transistor M4 and a fifth transistor M5.

[0090] A first electrode of the fourth transistor M4 is connected to the first level end VGH, a second electrode of the fourth transistor M4 is connected to the fifth transistor M5, a gate of the fourth transistor M4 is connected to the first node P1, and the fourth transistor M4 is used to transmit the first level Vgh of the first level end VGH to the fifth transistor M5 according to the potential of the first node P1.

[0091] The first electrode of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4, the second electrode of the fifth transistor M5 is connected to the second node P2, and the gate of the fifth transistor M5 is connected to the second clock signal terminal CLKB, for writing the first level Vgh transmitted by the fourth transistor M4 to the second node P2 according to the second clock signal clkb of the second clock signal terminal CLKB.

[0092] Please combine Figure 4 In some other embodiments, the shift register 10 further includes a fifth node P5 and a sixth node P6, and the first control module 12 includes a fourth transistor M4 and a fifth transistor M5 and a second storage capacitor C2.

[0093] Among them, the first electrode of the fourth transistor M4 is connected to the first level end VGH, the second electrode of the fourth transistor M4 is connected to the second storage capacitor C2, the gate of the fourth transistor M4 is connected to the fifth node P5, and the fourth transistor M4 is used to transfer the first level Vgh of the first level end VGH to the second storage capacitor C2 according to the potential of the fifth node P5.

[0094] A first electrode of the fifth transistor M5 is connected to the second clock signal terminal CLKB, a second electrode of the fifth transistor M5 is connected to the second storage capacitor C2, and a gate of the fifth transistor M5 is connected to the second node P2, for writing the second clock signal clkb of the second clock signal terminal CLKB into the second storage capacitor C2 according to the potential of the second node P2.

[0095] A first end of the second storage capacitor C2 is connected to the second electrode of the fourth transistor M4 and the second electrode of the fifth transistor M5 , and a second end of the second storage capacitor C2 is connected to the second node P2 .

[0096] See also Figure 2 and Figure 4 In some embodiments, the shift register 10 further includes an isolation module 16, which includes a first isolation transistor M15 and a second isolation transistor M16, wherein the first isolation transistor M15 is used to isolate the fifth node P5 from the first node P1, and the second isolation transistor M16 is used to isolate the sixth node P6 from the second node P2.

[0097] Specifically, a first electrode of the first isolation transistor M15 is connected to the fifth node P5 , a second electrode of the first isolation transistor M15 is connected to the first node P1 , and a gate of the first isolation transistor M15 is connected to the second level terminal VGL.

[0098] A first electrode of the second isolation transistor M16 is connected to the sixth node P6 , a second electrode of the first isolation transistor M15 is connected to the second node P2 , and a gate of the second isolation transistor M16 is connected to the second level terminal VGL.

[0099] Please further combine Figure 3 or Figure 4 In some embodiments, the second control module 13 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a third storage capacitor C3 and a fourth storage capacitor C4.

[0100] A first electrode of the sixth transistor M6 is connected to the second clock signal terminal CLKB, a second electrode of the sixth transistor M6 is connected to the fourth node P4, and a gate of the sixth transistor M6 is connected to the first node P1, for writing the second clock signal clkb of the second clock signal terminal CLKB into the fourth node P4 according to the potential of the first node P1.

[0101] A first electrode of the seventh transistor M7 is connected to the fourth node P4, a second electrode of the seventh transistor M7 is connected to the third node P3, and a gate of the seventh transistor M7 is connected to the second clock signal terminal CLKB, for writing the potential of the fourth node P4 into the third node P3 according to the second clock signal clkb of the second clock signal terminal CLKB.

[0102] A first electrode of the eighth transistor M8 is connected to the first level terminal VGH, a second electrode of the eighth transistor M8 is connected to the third node P3, and a gate of the eighth transistor M8 is connected to the second node P2, for writing the first level Vgh of the first level terminal VGH into the third node P3 according to the potential of the second node P2.

[0103] A first end of the third storage capacitor C3 is connected to the third node P3 , and a second end of the third storage capacitor C3 is connected to the first level end VGH for compensating the potential of the third node P3 .

[0104] A first end of the fourth storage capacitor C4 is connected to the first node P1 , and a second end of the fourth storage capacitor C4 is connected to the fourth node P4 for compensating the potential of the first node P1 .

[0105] The gate control module 15 includes a first sub-gate control module 152, a second sub-gate control module 154 and a first output terminal Out1. The first sub-gate control module 152 is connected to the first level terminal VGH, the signal input terminal IN and the first output terminal Out1, and the first sub-gate control module 152 is used to transmit the first level Vgh of the first level terminal VGH to the first output terminal Out1 according to the input signal Input transmitted by the signal input terminal IN. The second sub-gate control module 154 is connected to the second control module 13, the first clock signal terminal CLK and the first output terminal Out1, and is used to transmit the first clock signal clk of the first clock signal terminal CLK to the first output terminal Out1 according to the potential input by the second control module 13.

[0106] Specifically, the first sub-gate control module 152 includes a first output control transistor M12, a first output transistor M14 and a first storage capacitor C1. The first electrode of the first output control transistor M12 is connected to the first level terminal VGH, the second electrode of the first output control transistor M12 is connected to the first storage capacitor C1, and the gate of the first output control transistor M12 is connected to the signal input terminal IN. The first electrode of the first output transistor M14 is connected to the first level terminal VGH, the second electrode of the first output transistor M14 is connected to the first output terminal Out1, and the gate of the first output control transistor M12 is connected to the signal input terminal IN.

[0107] A first end of the first storage capacitor C1 is connected to the second electrode of the first output control transistor M12 , and a second end of the first storage capacitor C1 is connected to the first output end Out1 .

[0108] The first output control transistor M12 is used to write the first level Vgh of the first level terminal VGH into the first end of the first storage capacitor C1 according to the input signal Input of the signal input terminal IN. The first output transistor M14 is used to write the first level Vgh of the first level terminal VGH into the first output terminal Out1 according to the input signal Input of the signal input terminal IN. The first storage capacitor C1 is used to compensate the potential of the first output terminal Out1.

[0109] The second sub-gate control module 154 includes a second output control transistor M13 and a second output transistor M11. The first electrode and the gate of the second output control transistor M13 are connected to the second control module 13, and the second electrode of the second output control transistor M13 is connected to the first storage capacitor C1 and the second output transistor M11. The first electrode of the second output transistor M11 is connected to the first clock signal terminal CLK, the second electrode of the second output transistor M11 is connected to the first output terminal Out1, and the gate of the first output transistor M14 is connected to the second electrode of the second output control transistor M13.

[0110] The second output control transistor M13 is used to write the potential of the fourth node P4 into the first end of the first storage capacitor C1 and the gate of the second output transistor M11 according to the potential of the fourth node P4, and the second output transistor M11 is used to transmit the first clock signal clk of the first clock signal terminal CLK to the first output terminal Out1 according to the potential of the fourth node P4 transmitted by the second output control transistor M13.

[0111] The light signal output module 14 includes a third output transistor M10, a fourth output transistor M9 and a second output terminal Out2. Specifically, a first electrode of the third output transistor M10 is connected to the second level terminal VGL, a second electrode of the third output transistor M10 is connected to the second output terminal Out2, and a gate of the third output transistor M10 is connected to the second node P2. A first electrode of the fourth output transistor M9 is connected to the first level terminal VGH, a second electrode of the fourth output transistor M9 is connected to the second output terminal Out2, and a gate of the fourth output transistor M9 is connected to the third node P3.

[0112] The third output transistor M10 is used to transmit the second level Vgl of the second level terminal VGL to the second output terminal Out2 according to the potential of the second node P2. The fourth output transistor M9 is used to transmit the first level Vgh of the first level terminal VGH to the second output terminal Out2 according to the potential of the third node P3.

[0113] The present application also provides a control method for controlling the shift register 10 of any one of the above embodiments. The control method includes:

[0114] S12: after the input module receives the first hour of the 3H input signal, control the light-emitting signal output module to output a 3H light-emitting control signal; and

[0115] S14: After the input module receives the 2H of the 3H input signal, the gate control module is controlled to output a gate control signal less than 1H.

[0116] The working process of the shift register 10 of the present application includes a starting stage, an input stage, and an output stage, and the duration of the input signal Input is 3H, the duration of the high-level signal of the first clock signal clk and the second clock signal clkb is less than 2H, and the duration of the low-level signal is less than 1H.

[0117] Please combine the following Figure 3 The shift register and Figure 5 The working process of the shift register 10 is introduced by taking the timing diagram of FIG. 1 as an example.

[0118] In the initial stage, the input signal Input is a low level signal, and the potential of the second node P2 is the second level Vgl (low level) or lower than the second level Vgl. The third output transistor M10 is turned on, the second level terminal VGL is turned on with the second output terminal Out2, the second level Vgl is transmitted to the second output terminal Out2 through the third output transistor M10, and the second output terminal Out2 outputs a low level. At the same time, since the input signal Input is a low level signal, the first output control transistor M12 and the first output transistor M14 are turned on, the first level terminal VGH is connected with the first storage capacitor C1 and the first output terminal Out1, the first level Vgh of the first level terminal VGH is transmitted to the first storage capacitor C1 and the first output terminal Out1, and the first output terminal Out1 outputs a high level.

[0119] At the input stage:

[0120] In the input stage, the input signal Input inputted by the signal input terminal IN is a high level signal. The potential of the second node P2 is high level, and the third output transistor M10 is turned off. The first clock signal clk is a low level signal, the second transistor M2 is turned on, the second level terminal VGL is connected to the first node, and the second level Vgl of the second level terminal VGL is written to the first node P1, so that the potential of the first node is low level, so that the sixth transistor M6 is turned on, the fourth node P4 is written with the first level Vgh (high level), the third node P3 maintains a high level, the fourth output transistor M9 is turned off, and the second output terminal Out2 maintains an output low level. The second output control transistor M13 is disconnected, and the input signal Input of the signal input terminal IN turns off the first output control transistor M12 and the first output transistor M14, and the first output terminal Out1 maintains a high level.

[0121] The output stage includes a first output sub-stage, a second output sub-stage and a third output sub-stage, wherein:

[0122] First output sub-stage: the input signal Input inputted by the signal input terminal IN is a high-level signal, the second clock signal clkb is a low-level signal, the first clock signal clk is a high-level signal, the second transistor M2 is turned off, the first node maintains a low level, the sixth transistor M6 is turned on, the second clock signal clkb is written into the fourth node P4 and the third node P3, and the third node P3 and the fourth node P4 are low levels. The fourth output transistor M9 is turned on, the second output terminal Out2 is connected to the first level terminal VGH, and the first level Vgh of the first level terminal VGH is written into the second output terminal Out2. The first output terminal Out1 maintains a high level. At the same time, the second output control transistor M13 is turned on, the potential of the third node P3 is written into the gate of the second output transistor M11, the second output transistor M111 is turned on, the first clock signal terminal CLK is connected to the first output terminal Out1, and the potential of the first output terminal Out1 is the first clock signal clk (high level).

[0123] The second output sub-stage: the input signal Input is a high-level signal, the first clock signal clk is a low-level signal, the second clock signal clkb is a high-level signal, the second transistor M2 is turned off, the first node P1 maintains a low level, so that the sixth transistor M6 remains turned on, the second clock signal clkb is written into the fourth node P4, the second output control transistor M13 and the seventh transistor are turned off, the third node P3 maintains a low level, the fourth output transistor M9, the second output terminal Out2 is connected to the first level terminal VGH, the first level Vgh of the first level terminal VGH is written into the second output terminal Out2, and the second output terminal Out2 maintains a high level. At the same time, since the input signal Input is a high-level signal, the first output control transistor M12 and the first output transistor 14 are turned off, and since the second output control transistor M13 is turned off, the first end of the first storage capacitor C1 maintains a low level, the second output transistor M11 is turned on according to the potential of the first storage capacitor C1 at the first end, the first clock signal terminal CLK is connected to the first output terminal OUT1, the first clock signal terminal CLK outputs the first clock signal clk (low level) to the first output terminal Out1 through the second output transistor M11, and the first output terminal Out1 outputs a low level.

[0124] The third output sub-stage: the input signal Input is a low-level signal, the first clock signal clk becomes a high-level signal, the second clock signal clkb becomes a low-level signal, the second transistor M2 is turned off, the first node maintains a low level so that the sixth transistor M6 is turned on, the seventh transistor is turned on, and the second clock signal clkb is written into the fourth node P4 and the third node P3. The fourth output transistor M9 is turned on, the first level terminal VGH is connected to the second output terminal Out2, the first level Vgh is written into the second output terminal Out2, and the second output terminal Out2 outputs a high level. At the same time, the second output control transistor M13 is turned on, the first output control transistor M12 and the first output transistor M14 are turned on according to the low-level signal of the signal input terminal IN, the first output terminal Out1 is connected to the first level terminal VGH, the first level Vgh is written into the first output terminal Out1, and the first output terminal Out1 outputs a high level.

[0125] Please combine the following Figure 4 The shift register and Figure 5 The working process of the shift register 10 is introduced by taking the timing diagram of FIG. 1 as an example.

[0126] In the initial stage, the input signal Input is a low level signal, and the potential of the second node P2 is the second level Vgl (low level) or lower than the second level Vgl under the action of the low level signal and the second storage capacitor C2. The third output transistor M10 is turned on, the second level terminal VGL is turned on with the second output terminal Out2, the second level Vgl is transmitted to the second output terminal Out2 through the third output transistor M10, and the second output terminal Out2 outputs a low level. At the same time, since the input signal Input is a low level signal, the first output control transistor M12 and the first output transistor M14 are turned on, the first level terminal VGH is connected with the first storage capacitor C1 and the first output terminal Out1, the first level Vgh of the first level terminal VGH is transmitted to the first storage capacitor C1 and the first output terminal Out1, and the first output terminal Out1 outputs a high level.

[0127] At the input stage:

[0128] In the input stage, the input signal Input is a high-level signal. The first clock signal clk is a low-level signal, the second clock signal is a high-level signal, the input signal Input is input to the sixth node P6 and the second node P2, the potential of the second node P2 is high, and the third output transistor M10 is turned off. The second transistor M2 and the second isolation transistor M16 are turned on, the second level terminal VGL connects the fifth node P5 and the first node P1, and the second level Vgl of the second level terminal VGL is written into the fifth node P5 and the first node P1, so that the potential of the fifth node P5 and the first node P1 is low, the sixth transistor M6 is turned on, the fourth node P4 is written into the second clock signal (high level), the third node P3 remains high, the fourth output transistor M9 is turned off, and the second output terminal Out2 maintains the output low level. The second output control transistor M13 is disconnected, and the input signal Input of the signal input terminal IN turns off the first output control transistor M12 and the first output transistor M14, and the first output terminal Out1 maintains a high level.

[0129] The output stage includes a first output sub-stage, a second output sub-stage and a third output sub-stage, wherein:

[0130] First output sub-stage: the input signal Input inputted by the signal input terminal IN is a high-level signal, the second clock signal clkb is a low-level signal, the first clock signal clk is a high-level signal, the second transistor M2 is turned off, the fifth node P5 and the first node P1 maintain a low level, the sixth transistor M6 is turned on, the second clock signal clkb (low level) is written into the fourth node P4 and the third node P3, and the third node P3 and the fourth node P4 are low levels. The fourth output transistor M9 is turned on, the second output terminal Out2 is connected to the first level terminal VGH, and the first level Vgh of the first level terminal VGH is written into the second output terminal Out2. The first output terminal Out1 outputs a high level. At the same time, the second output control transistor M13 is turned on, the potential of the third node P3 is written into the gate of the second output transistor M111, the second output transistor M111 is turned on, the first clock signal terminal CLK is connected to the first output terminal Out1, and the potential of the first output terminal Out1 is the first clock signal clk (high level).

[0131] The second output sub-stage: the input signal Input is a high-level signal, the first clock signal clk is a low-level signal, the second clock signal clkb is a high-level signal, the second transistor M2 is turned off, the fifth node P5 and the first node P1 maintain a low level, so that the sixth transistor M6 remains turned on, the second clock signal clkb is written into the fourth node P4, the second output control transistor M13 and the seventh transistor are turned off, the third node P3 maintains a low level, the fourth output transistor M9 is turned on, the second output terminal Out2 is connected to the first level terminal VGH, the first level Vgh of the first level terminal VGH is written into the second output terminal Out2, and the second output terminal Out2 outputs a high level. At the same time, since the input signal Input is a high-level signal, the first output control transistor M12 and the first output transistor 14 are turned off, and since the second output control transistor M13 is turned off, the first end of the first storage capacitor C1 maintains a low level, the second output transistor 1 is turned on according to the potential of the first storage capacitor C1 at the first end, the first clock signal terminal CLK is connected to the first output terminal OUT1, the first clock signal terminal CLK outputs the first clock signal clk (low level) to the first output terminal Out1 through the second output transistor M11, and the first output terminal Out1 outputs a low level.

[0132] The third output sub-stage: the input signal Input is a low-level signal, the first clock signal clk becomes a high-level signal, the second clock signal clkb becomes a low-level signal, the second transistor M2 is turned off, the fifth node P5 and the first node P1 maintain a low level so that the sixth transistor M6 is turned on, the seventh transistor M7 is turned on, the second clock signal clkb is written into the fourth node P4 and the third node P3, the fourth output transistor M9 is turned on, the first level terminal VGH is connected to the second output terminal Out2, the first level Vgh is written into the second output terminal Out2, and the second output terminal Out2 outputs a high level. At the same time, the second output control transistor M13 is turned on, the first output control transistor M12 and the first output transistor M14 are turned on according to the low-level signal of the signal input terminal IN, the first output terminal Out1 is connected to the first level terminal VGH, the first level Vgh is written into the first output terminal Out1, and the first output terminal Out1 outputs a high level.

[0133] Please combine Figure 6 The present application also provides a light emitting control circuit 100, comprising a plurality of cascaded shift registers 10, wherein the first stage shift register 10 is completely Figure 3 or Figure 4 In the shift register 10 of other stages, the second output control transistor M13 can be used as follows Figure 3 or Figure 4The fourth node P4 can also be connected to the first output terminal Out1 of the previous stage shift register 10 by using the second output control transistor M13, and the rest of the parts are connected to the fourth node P4 by using the second output control transistor M13. Figure 3 or Figure 4 The connection method in .

[0134] In addition, in some embodiments, in multiple cascaded shift registers 10, the second output terminal Out2 of the current stage shift register 10 can be connected to the input module 11 of the next stage shift register 10, so that the light control signal output by the second output terminal Out2 of the current stage shift register 10 can be used as the input signal of the next stage shift register 10.

[0135] Please further combine Figure 6 The present application also provides a display device 1000, including a pixel driving circuit 20 and the above-mentioned light emitting control circuit 100. The shift register 10 is connected to the pixel driving circuit 20, and the shift register 20 is used to transmit a gate control signal and a light emitting control signal to the pixel driving circuit 20 after receiving an input signal.

[0136] In some embodiments, the pixel driving circuit 20 includes a light-emitting signal input terminal and a gate signal input terminal. The light-emitting signal input terminal is connected to the light-emitting signal output module, and the gate signal input terminal is connected to the gate control module. The light-emitting signal input terminal is used to receive the light-emitting control signal output by the light-emitting signal output module, and the gate signal input terminal is used to receive the gate control signal output by the gate signal output module.

[0137] The display device 1000 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

[0138] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0139] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A shift register, characterized in that: The shift register includes an input module, a first node, a second node, a first control module, a second control module, a third node, a light emitting signal output module and a gate control module; wherein, The input module is connected to the first node and the second node, and is used to receive an input signal and control the potential of the first node and the second node, wherein the potential of the second node can be transformed into a first level potential or a second level potential according to the input signal received by the input module; The first control module is connected to the first node and the second node, and is used to control the potential of the second node according to the potential of the first node; The second control module is connected to the first node, the third node and the gate control module, and is used to control the potential of the first node and the third node. The second control module is also used to control the gate control module to output a gate control signal; and The light emitting signal output module is connected to the second node and the third node, and is used to output the light emitting control signal according to the potential of the second node or the third node.

2. The shift register according to claim 1, wherein: The shift register is connected to the signal input terminal, and the gate control module includes a first sub-gate control module, a second sub-gate control module and a first output terminal; The first sub-gate control module is connected to the first level end, the signal input end and the first output end, and the first sub-gate control module is used to transmit the first level of the first level end to the first output end according to the input signal transmitted by the signal input end; The second sub-gate control module is connected to the second control module, the first clock signal terminal and the first output terminal, and is used to transmit the first clock signal of the first clock signal terminal to the first output terminal according to the potential input by the second control module.

3. The shift register according to claim 2, wherein: The first sub-gate control module includes a first output control transistor, a first output transistor and a first storage capacitor; wherein, A first electrode of the first output control transistor is connected to the first level end, a second electrode of the first output control transistor is connected to the first storage capacitor, and a gate of the first output control transistor is connected to the signal input end; A first electrode of the first output transistor is connected to the first level end, a second electrode of the first output transistor is connected to the first output end, and a gate of the first output control transistor is connected to the signal input end; A first storage capacitor, wherein a first end of the first storage capacitor is connected to the second electrode of the first output control transistor, and a second end of the first storage capacitor is connected to the first output end.

4. The shift register according to claim 3, wherein: The second sub-gate control module includes a second output control transistor and a second output transistor; wherein, A first electrode and a gate of the second output control transistor are connected to the second control module, and a second electrode of the second output control transistor is connected to the first storage capacitor and the second output transistor; A first electrode of the second output transistor is connected to the first clock signal terminal, a second electrode of the second output transistor is connected to the first output terminal, and a gate of the first output transistor is connected to a second electrode of the second output control transistor.

5. The shift register according to claim 1, wherein: The luminous signal output module includes a third output transistor, a fourth output transistor and a second output terminal. A first electrode of the third output transistor is connected to the second level end, a second electrode of the third output transistor is connected to the second output end, and a gate of the third output transistor is connected to the second node; A first electrode of the fourth output transistor is connected to the first level end, a second electrode of the fourth output transistor is connected to the second output end, and a gate of the fourth output transistor is connected to the third node.

6. The shift register according to claim 1, wherein: The shift register is also connected to the signal input terminal, and the input module includes a first transistor, a second transistor and a third transistor; wherein, A first electrode of the first transistor is connected to the signal input terminal, a second electrode of the first transistor is connected to the second node, and a gate of the first transistor is connected to a first clock signal terminal; A first electrode of the second transistor is connected to a second level terminal, a second electrode of the second transistor is connected to the first node, and a gate of the second transistor is connected to the first clock signal terminal; A first electrode of the third transistor is connected to the first clock signal, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the second node.

7. The shift register according to claim 6, wherein: The input module also includes: A second storage capacitor, wherein a first end of the second storage capacitor is connected to the second clock signal end, and a second end of the second storage capacitor is connected to the second node.

8. The shift register according to claim 1, wherein: The first control module includes a fourth transistor and a fifth transistor, A first electrode of the fourth transistor is connected to the first level end, a second electrode of the fourth transistor is connected to the fifth transistor, and a gate of the fourth transistor is connected to the first node; A first electrode of the fifth transistor is connected to a second electrode of the fourth transistor, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to a second clock signal terminal.

9. The shift register according to claim 1, wherein: The shift register further includes a fifth node and a sixth node, the first control module includes a fourth transistor, a fifth transistor and a second storage capacitor, wherein A first electrode of the fourth transistor is connected to the first level end, a second electrode of the fourth transistor is connected to the second storage capacitor, and a gate of the fourth transistor is connected to the fifth node; A first electrode of the fifth transistor is connected to the second clock signal terminal, a second electrode of the fifth transistor is connected to the second storage capacitor, and a gate of the fifth transistor is connected to the second node; A first end of the second storage capacitor is connected to the second electrode of the fourth transistor and the second electrode of the fifth transistor, and a second end of the second storage capacitor is connected to the second node.

10. The shift register according to claim 9, wherein: The shift register further includes an isolation module, the isolation module includes a first isolation transistor and a second isolation transistor, the first isolation transistor is used to isolate the first node and the fifth node, and the second isolation transistor is used to isolate the second node and the sixth node; A first electrode of the first isolation transistor is connected to the fifth node, a second electrode of the first isolation transistor is connected to the first node, and a gate of the first isolation transistor is connected to the second level end; A first electrode of the second isolation transistor is connected to the sixth node, a second electrode of the first isolation transistor is connected to the second node, and a gate of the second isolation transistor is connected to the second level end.

11. The shift register according to claim 1, wherein: The shift register further includes a fourth node, and the second control module includes a sixth transistor, a seventh transistor, an eighth transistor, a third storage capacitor and a fourth storage capacitor; wherein, A first electrode of the sixth transistor is connected to the second clock signal terminal, a second electrode of the sixth transistor is connected to the fourth node, and a gate of the sixth transistor is connected to the first node; A first electrode of the seventh transistor is connected to the fourth node, a second electrode of the seventh transistor is connected to the third node, and a gate of the seventh transistor is connected to the second clock signal terminal; A first electrode of the eighth transistor is connected to the first level end, a second electrode of the eighth transistor is connected to the third node, and a gate of the eighth transistor is connected to the second node; A first end of the third storage capacitor is connected to the third node, and a second end of the third storage capacitor is connected to the first level end; A first end of the fourth storage capacitor is connected to the first node, and a second end of the fourth storage capacitor is connected to the fourth node.

12. A light emitting control circuit, characterized in that: Comprising a shift register as described in any one of claims 1-11.

13. A display device, characterized in that: The invention comprises a pixel driving circuit and the shift register as claimed in claim 11.

14. The display device according to claim 13, wherein: The pixel driving circuit is connected to the shift register, and the pixel driving circuit includes a light-emitting signal input terminal and a gate signal input terminal, the light-emitting signal input terminal is connected to the light-emitting signal output module, the gate signal input terminal is connected to the gate control module, the light-emitting signal input terminal is used to receive the light-emitting control signal output by the light-emitting signal output module, and the gate signal input terminal is used to receive the gate control signal output by the gate signal output module.

15. A shift register control method, characterized in that: Used to control the shift register according to any one of claims 1 to 11, the control method comprising: After the input module receives the first hour of the input signal of 3H, controlling the light-emitting signal output module to output a light-emitting control signal of 3H; and After the input module receives the 2H of the input signal of 3H, the gate control module is controlled to output a gate control signal less than 1H.

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