Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate having a conductive layer therein, and the surface of the substrate exposes the surface of the conductive layer; forming a groove adjacent to the conductive layer in the substrate, and the sidewalls of the groove expose the sidewall surfaces of the conductive layer; forming a lower electrode layer in the groove and on the top surface of the conductive layer; and forming a magnetic tunnel material film on the surface of the lower electrode layer. The electrical performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] MRAM (Magnetic Random Access Memory) is a non-volatile magnetic random access memory. It has the high-speed read and write capabilities of static random access memory (SRAM), the high integration of dynamic random access memory (DRAM), and its power consumption is much lower than that of DRAM. Compared with flash memory (Flash), its performance does not degrade with the increase of usage time. Due to the above characteristics of MRAM, it is called universal memory and is considered capable of replacing SRAM, DRAM, EEPROM, and Flash.

[0003] Different from the manufacturing technology of traditional random access memory chips, the data in MRAM is not stored in the form of charge or current, but in a magnetic state, and is sensed by measuring resistance without disturbing the magnetic state. MRAM uses a magnetic tunnel junction (MTJ) structure for data storage. Generally, an MRAM cell consists of a transistor (1T) and a magnetic tunnel junction (MTJ) to form a storage cell together. The magnetic tunnel junction (MTJ) structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. Current vertically flows through or "crosses" one electromagnetic layer through the insulating layer from another electromagnetic layer. One of the electromagnetic layers is a fixed magnetic layer, and the electrode is fixed in a specific direction through a strong fixing field. The other electromagnetic layer is a freely rotatable magnetic layer, and the electrode is maintained in one of the directions.

[0004] However, the performance of the magnetic tunnel junctions prepared by the prior art is poor. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the electrical performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate, in which a conductive layer is provided, and the surface of the conductive layer is exposed on the surface of the substrate; a groove adjacent to the conductive layer in the substrate, and the side wall of the groove exposes the side wall surface of the conductive layer; a lower electrode layer located in the groove and on the top surface of the conductive layer, and the lower electrode layer covers the top surface and the side wall surface of the conductive layer; a magnetic tunnel material film located on the surface of the lower electrode layer.

[0007] Optionally, the distance from the bottom of the groove to the top of the conductive layer is a first distance, the distance from the bottom of the conductive layer to the bottom of the conductive layer is a second distance, and the ratio range of the first distance to the second distance is 1 / 3 to 1 / 2.

[0008] Optionally, the material of the lower electrode layer includes one or a combination of several of: copper, tungsten, aluminum, titanium, titanium nitride, tantalum.

[0009] Optionally, the magnetic tunnel material film includes: a lower electromagnetic material film located on the substrate and the surface of the lower electrode layer; an insulating film located on the surface of the lower electromagnetic material film; an upper electromagnetic material film located on the surface of the insulating film.

[0010] Optionally, the material of the insulating film includes one or a combination of several of: magnesium oxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium dioxide, and zirconium dioxide.

[0011] Optionally, the lower electromagnetic material film includes: a lower composite film located on the surface of the substrate and the surface of the lower electrode film, and a lower electromagnetic film located on the surface of the lower composite film; the upper electromagnetic material film includes: an upper composite film located on the surface of the insulating film, and an upper electromagnetic film located on the surface of the upper composite film.

[0012] Optionally, the material of the upper electromagnetic film includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite; the material of the lower electromagnetic film includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0013] Optionally, the upper composite film is a single-layer structure or a composite structure; when the upper composite film is a single-layer structure, the material of the upper composite film includes: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, or lanthanum strontium manganite; when the upper composite film is a composite structure, the upper composite film includes several overlapping conductive layers, and the material of each of the conductive layers includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0014] Optionally, the lower composite film is a single-layer structure or a composite structure; when the lower composite film is a single-layer structure, the material of the lower composite film includes: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, or lanthanum strontium manganite; when the lower composite film is a composite structure, the lower composite film includes several overlapping conductive layers, and the material of each of the conductive layers includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0015] Correspondingly, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate having a conductive layer therein, and the surface of the substrate exposes the surface of the conductive layer; forming a groove adjacent to the conductive layer in the substrate, and the sidewall of the groove exposes the sidewall surface of the conductive layer; forming a lower electrode layer in the groove and on the top surface of the conductive layer; forming a magnetic tunnel material film on the surface of the lower electrode layer.

[0016] Optionally, the method for forming the groove includes: forming a hard mask structure on the surface of the substrate and the surface of the conductive layer; forming a first patterned layer on the surface of the hard mask structure, the first patterned layer has an opening, and the opening exposes the hard mask structure on the conductive layer and on a part of the substrate on the sidewall of the conductive layer; using the first patterned layer as a mask, etching the hard mask structure and a part of the substrate to expose the top surface of the conductive layer and a part of the sidewall surface of the conductive layer, forming the groove; after forming the groove, removing the hard mask structure and the first patterned layer.

[0017] Optionally, further including: forming a stop layer on the surface of the substrate and the surface of the conductive layer before forming the groove.

[0018] Optionally, the material of the stop layer is different from the material of the conductive layer; the material of the stop layer is different from the material of the substrate; the material of the stop layer is different from the material of the magnetic tunnel material film; the material of the stop layer includes: silicon nitride, silicon carbonitride or silicon oxynitride.

[0019] Optionally, the surface of the lower electrode layer is flush with the surface of the stop layer; the method for forming the lower electrode layer includes: forming a lower electrode film in the groove and on the surface of the stop layer; planarizing the lower electrode film until the surface of the stop layer is exposed, and forming a lower electrode layer in the groove.

[0020] Optionally, the process of planarizing the lower electrode film includes: chemical mechanical polishing process or dry etching process.

[0021] Optionally, further including: patterning the magnetic tunnel material film to form a magnetic tunnel junction.

[0022] Optionally, the method for patterning the magnetic tunnel material film includes: forming a second patterned layer on the surface of the magnetic tunnel material film, the second patterned layer covers the surface of the magnetic tunnel material film on the lower electrode layer; using the second patterned layer as a mask, etching the magnetic tunnel material film until the surface of the stop layer is exposed, forming the magnetic tunnel junction.

[0023] Optionally, it further includes: after forming the magnetic tunnel material film and before patterning the magnetic tunnel material film, forming an upper electrode film on the surface of the magnetic tunnel material film; the method for forming the semiconductor structure further includes: using the second patterned layer as a mask to etch the upper electrode film to form an upper electrode layer, and the upper electrode layer is located on the surface of the magnetic tunnel junction.

[0024] Optionally, it further includes: after forming the magnetic tunnel junction, forming sidewalls on the sidewall surfaces of the magnetic tunnel junction.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the semiconductor structure provided by the technical solution of the present invention, since the sidewalls of the groove expose the sidewall surfaces of the conductive layer, the lower electrode layer located in the groove can cover the top surface and the sidewall surfaces of the conductive layer. Moreover, the lower electrode layer not only covers the top surface of the conductive layer, but also covers the sidewall surfaces of the conductive layer, thereby increasing the contact area between the lower electrode layer and the conductive layer, which is beneficial to reducing the contact resistance between the subsequently formed magnetic tunnel junction and the conductive layer, and is beneficial to improving the electrical performance of the formed semiconductor structure.

[0027] Furthermore, the height at which the lower electrode layer covers the sidewall surface of the conductive layer is a first distance, the conductive layer has a second distance, and the ratio range of the first distance to the second distance is 1 / 3 to 1 / 2. The significance of selecting the ratio range between the first distance and the second distance is as follows: if the ratio is less than 1 / 3, that is, the height at which the lower electrode layer covers the sidewall surface of the conductive layer is too small, the contact area between the lower electrode layer and the conductive layer still cannot be effectively increased, and thus the performance of the formed semiconductor structure is still poor; if the ratio is greater than 1 / 2, the height at which the lower electrode covers the sidewall surface of the conductive layer is relatively large, which requires a relatively large depth of the groove formed by etching the substrate, that is, the aspect ratio of the groove is relatively large, making it difficult to form the groove and is not conducive to improving the performance of the formed semiconductor structure.

[0028] In the method for forming the semiconductor structure provided by the technical solution of the present invention, by forming a groove in the substrate and the sidewalls of the groove exposing the sidewall surfaces of the conductive layer, the lower electrode layer formed in the groove can cover the top surface and the sidewall surfaces of the conductive layer. Moreover, the lower electrode layer not only covers the top surface of the conductive layer, but also covers the sidewall surfaces of the conductive layer, thereby increasing the contact area between the lower electrode layer and the conductive layer, which is beneficial to reducing the contact resistance between the subsequently formed magnetic tunnel junction and the conductive layer, and is beneficial to improving the electrical performance of the formed semiconductor structure.

[0029] Further, the height of the lower electrode layer covering the sidewall surface of the conductive layer is a first distance, the conductive layer has a second distance, and the ratio range of the first distance to the second distance is 1 / 3 to 1 / 2. The significance of selecting the ratio range between the first distance and the second distance is as follows: If the ratio is less than 1 / 3, that is, the height of the lower electrode layer covering the sidewall surface of the conductive layer is too small, the contact area between the lower electrode layer and the conductive layer cannot be effectively increased, and thus the performance of the formed semiconductor structure is still poor; if the ratio is greater than 1 / 2, the height of the lower electrode covering the sidewall surface of the conductive layer is large, which requires a larger depth of the groove formed by etching the substrate, that is, the aspect ratio of the groove is large, making it difficult to form the groove and is not conducive to improving the performance of the formed semiconductor structure.

[0030] Further, the method for forming the semiconductor structure further includes: forming a stop layer on the surface of the substrate and the surface of the conductive layer before forming the groove. Since the planarization process uses a chemical mechanical polishing process, in the subsequent process of planarizing the lower electrode film to form the lower electrode layer, the chemical mechanical polishing process can use the surface of the stop layer as a flat surface, which is beneficial to reducing the roughness of the formed lower electrode layer, and thus is beneficial to improving the performance of the formed magnetic tunnel junction. At the same time, when patterning the magnetic tunnel material film to form the magnetic tunnel junction, the etching process can stop on the surface of the stop layer, which is beneficial to avoiding affecting the devices in the substrate. In summary, it is beneficial to the better electrical performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0032] Figures 2 to 12 is a schematic structural diagram of each step of the method for forming the semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] As described in the background art, the performance of the semiconductor structure is poor.

[0034] The following will be described in detail with reference to the drawings the reasons for the poor performance of the semiconductor structure. Figure 1 is a schematic structural diagram of a semiconductor structure.

[0035] Please refer to Figure 1 , the semiconductor structure includes: a substrate 100, a conductive layer 110 is disposed in the substrate 100, and the surface of the conductive layer 110 is exposed on the substrate 100; a lower electrode layer 120 located on the surface of the conductive layer 110; a magnetic tunnel junction 130 located on the surface of the lower electrode layer 120; and an upper electrode layer 140 located on the surface of the magnetic tunnel junction 130.

[0036] In the above structure, the magnetic tunnel junction 130 is electrically connected to the conductive layer 110 in the substrate 100 through the lower electrode layer 120. However, as semiconductor technology increasingly develops towards higher integration, the feature size of semiconductor devices correspondingly decreases, and the size of the conductive layer 110 also decreases accordingly. Furthermore, the contact area between the lower electrode layer 120 and the conductive layer 110 is small, resulting in a large contact resistance between the magnetic tunnel junction 130 and the conductive layer 110, and reducing the performance of the formed semiconductor structure.

[0037] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate having a conductive layer therein, and exposing the surface of the conductive layer on the surface of the substrate; forming a groove in the substrate, and the groove exposing the top surface and the side wall surface of the conductive layer; forming a lower electrode layer in the groove, and the lower electrode layer covering the top surface and the side wall surface of the conductive layer; forming a magnetic tunnel material film on the surface of the lower electrode layer. The method is beneficial to improving the electrical performance of the formed semiconductor structure.

[0038] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention with reference to the accompanying drawings.

[0039] Figures 2 to 12 It is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0040] Please refer to Figure 2 , provide a substrate 200 having a conductive layer 210 therein, and exposing the surface of the conductive layer 210 on the surface of the substrate 200.

[0041] In this embodiment, the substrate 200 includes: a substrate (not shown in the figure) and a dielectric layer (not shown in the figure) located on the surface of the substrate, and the conductive layer 210 is located in the dielectric layer.

[0042] The material of the substrate is a semiconductor material. In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator.

[0043] In this embodiment, the substrate has a device structure (not shown in the figure), and the device structure includes one or more of a PMOS transistor, an NMOS transistor, a CMOS transistor, a resistor, a capacitor, and an inductor.

[0044] The material of the dielectric layer includes: silicon oxide, a low-K dielectric material, or an ultra-low-K dielectric material.

[0045] In this embodiment, the material of the dielectric layer is silicon oxide.

[0046] The material of the conductive layer 210 includes one or a combination of several of: copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0047] In this embodiment, the material of the conductive layer 210 is copper.

[0048] Please refer to Figure 3 , a stop layer 220 is formed on the surface of the substrate 200 and the surface of the conductive layer 210.

[0049] The function of the stop layer 220 is as follows: on the one hand, it is used as a subsequent planarization of the lower electrode film to form a flat layer of the lower electrode layer in the groove; on the other hand, it is used as a subsequent patterning of the magnetic tunnel material film to form a stop layer of the magnetic tunnel junction, thereby reducing the impact on the devices in the substrate 200.

[0050] The material of the stop layer 220 is different from the material of the conductive layer 210; the material of the stop layer 220 is different from the material of the substrate 200; the material of the stop layer 220 is different from the material of the subsequent formed magnetic tunnel material film.

[0051] The material of the stop layer 220 includes: silicon nitride, silicon carbonitride, or silicon oxynitride.

[0052] In this embodiment, the material of the stop layer 220 is silicon carbonitride.

[0053] In other embodiments, the stop layer may not be formed.

[0054] Next, a groove adjacent to the conductive layer is formed in the substrate, and the side wall of the groove exposes the side wall surface of the conductive layer. For the specific process of forming the groove, please refer to Figures 4 to 6 .

[0055] Please refer to Figure 4 , a hard mask structure 230 is formed on the surface of the substrate 200 and the surface of the conductive layer 210.

[0056] The hard mask structure 230 is beneficial to improving the stability and accuracy of pattern transfer.

[0057] Specifically, in this embodiment, the hard mask structure 230 is formed on the surface of the stop layer 220.

[0058] In this embodiment, the hard mask structure 230 is a multi-layer structure, and the hard mask structure 230 includes: a first hard mask layer 231 located on the surface of the stop layer 220, and a second hard mask layer 232 located on the surface of the first hard mask layer 231.

[0059] In this embodiment, the material of the first hard mask layer 231 is silicon carbonitride doped with nitrogen. The first hard mask layer 231 formed by silicon carbonitride doped with nitrogen has good bonding ability with the substrate 200. When etching the substrate 200 using the etched first hard mask layer 231 as a mask in the subsequent process, the first hard mask layer 231 is not easily peeled off or warped. Therefore, the first hard mask layer 231 has good ability to maintain the etched pattern, which is beneficial to improving the accuracy of pattern transfer.

[0060] The material of the second hard mask layer 232 is titanium nitride. The second hard mask layer 232 has good bonding ability with the first hard mask layer 231. The second hard mask layer 232 can protect the surface of the first hard mask layer 231 during the subsequent etching process, so that the first hard mask layer 231 will not be thinned. Moreover, the second hard mask layer 232 has relatively high physical strength. During the subsequent etching process, the patterns of the second hard mask layer 232 and the first hard mask layer 231 can remain stable, which is beneficial to further improving the accuracy of pattern transfer.

[0061] In other embodiments, the hard mask structure can also be a single-layer structure.

[0062] Please refer to Figure 5 , a first patterned layer 240 is formed on the surface of the hard mask structure 230. The first patterned layer 240 has an opening 241, and the opening 241 exposes the surface of the hard mask structure 230 on the substrate 200 above the conductive layer 210 and on the sidewalls of the conductive layer 210.

[0063] The first patterned layer 240 is used as a mask for etching the substrate 200 in the subsequent process.

[0064] The opening 241 is used to define the position and size of the groove formed subsequently.

[0065] In this embodiment, the opening 241 not only exposes the surface of the hard mask structure 230 on the conductive layer 210, but also exposes the surface of the hard mask structure 230 on the part of the substrate 200 on both sides of the conductive layer 210.

[0066] Since the opening 241 not only exposes the surface of the hard mask structure 230 on the conductive layer 210, but also exposes the surface of the hard mask structure 230 on the partial substrate 200 on both sides of the conductive layer 210, the projected pattern of the conductive layer 210 on the surface of the substrate 200 is located within the projected pattern of the subsequently formed groove on the surface of the substrate 200.

[0067] In other embodiments, the opening exposes the surface of the hard mask structure on the conductive layer, and also exposes the surface of the hard mask structure on the partial substrate on one side of the conductive layer.

[0068] Please refer to Figure 6 , using the first patterning layer 240 as a mask, etching the hard mask structure 230 and the partial substrate 200 to expose the top surface of the conductive layer 210 and the sidewall surface of the partial conductive layer 210, and forming the groove 250 in the substrate 200.

[0069] The groove 250 is used to form a lower electrode layer with a subsequent filling material.

[0070] It should be noted that, in this embodiment, the groove 250 is located in the substrate 200 and the stop layer 220.

[0071] In this embodiment, the groove 250 exposes the top surface of the conductive layer 210 and the sidewall surfaces on both sides of the partial conductive layer 210, that is, the projected pattern of the conductive layer 210 on the surface of the substrate 200 is located within the projected pattern of the groove 250 on the surface of the substrate 200.

[0072] The distance from the bottom of the groove 250 to the top of the conductive layer 210 is a first distance H1, the distance from the bottom of the conductive layer 210 to the bottom of the conductive layer 210 is a second distance H2, and the ratio range of the first distance H1 to the second distance H2 is 1 / 3 to 1 / 2.

[0073] The process of etching the hard mask structure 230 and the partial substrate 200 includes: one or a combination of two of a dry etching process and a wet etching process.

[0074] In this embodiment, the process of etching the hard mask structure 230 and the partial substrate 200 is an anisotropic dry etching.

[0075] In this embodiment, after forming the groove 250, it further includes: removing the hard mask structure 230 and the first patterning layer 240.

[0076] Then, a lower electrode layer is formed in the groove, and the lower electrode layer covers the top surface and the sidewall surface of the conductive layer.

[0077] In this embodiment, the surface of the lower electrode layer is flush with the surface of the stop layer. For the specific process of forming the lower electrode layer, please refer to Figures 7 to 8 .

[0078] Please refer to Figure 7 , and a lower electrode film 260 is formed in the groove 250 and on the surface of the stop layer 220.

[0079] The lower electrode film 260 is used to provide materials for forming the lower electrode layer subsequently.

[0080] The materials of the lower electrode film 260 include one or a combination of several of the following: copper, tungsten, aluminum, titanium, titanium nitride, tantalum.

[0081] In this embodiment, the material of the lower electrode film 260 is tantalum.

[0082] Please refer to Figure 8 , planarize the lower electrode film 260 until the surface of the stop layer 220 is exposed, and a lower electrode layer 261 is formed in the groove 250.

[0083] In this embodiment, the surface of the lower electrode layer 261 is flush with the surface of the stop layer 220.

[0084] The process of planarizing the lower electrode film 260 includes: chemical mechanical polishing process or dry etching process.

[0085] Since the sidewalls of the groove 250 expose the sidewall surfaces of the conductive layer 210, the lower electrode layer 261 formed in the groove 250 not only covers the top surface of the conductive layer 210, but also covers the sidewall surfaces of the conductive layer 210.

[0086] Since the lower electrode layer 261 is formed by planarizing the lower electrode film 260, the materials of the lower electrode layer 261 include one or a combination of several of the following: copper, tungsten, aluminum, titanium, titanium nitride, tantalum.

[0087] In this embodiment, the material of the lower electrode layer 261 is tantalum.

[0088] In this embodiment, the lower electrode layer 261 covers the top surface of the conductive layer 210 and the sidewall surfaces on both sides of the conductive layer 210.

[0089] By forming a groove 250 within the substrate 200, and exposing the sidewall surface of the conductive layer 210 on the sidewalls of the groove 250, a lower electrode layer 261 formed within the groove 250 can cover the top surface and the sidewall surface of the conductive layer 210. The lower electrode layer 261 not only covers the top surface of the conductive layer 210, but also covers the sidewall surface of the conductive layer 210, thereby increasing the contact area between the lower electrode layer 261 and the conductive layer 210, which is beneficial to reducing the contact resistance between the subsequently formed magnetic tunnel junction and the conductive layer 210, and is beneficial to improving the electrical performance of the formed semiconductor structure.

[0090] In this embodiment, the process of planarizing the lower electrode film 260 is a chemical mechanical polishing process.

[0091] Since a stop layer 220 is formed on the surface of the substrate 200, and the planarization process uses a chemical mechanical polishing process, the stop layer 220 can make the chemical mechanical polishing process take the surface of the stop layer 220 as the planar surface during the process of planarizing the lower electrode film 260 to form the lower electrode layer 261, which is beneficial to reducing the roughness of the formed lower electrode layer 261, and further beneficial to improving the performance of the formed magnetic tunnel junction.

[0092] Please refer to Figure 9 , and form a magnetic tunnel material film 270 on the surface of the lower electrode layer 261.

[0093] In this embodiment, the magnetic tunnel material film 270 is formed on the surface of the lower electrode layer 261 and the surface of the stop layer 220.

[0094] The magnetic tunnel material film 270 is used to form a magnetic tunnel junction subsequently.

[0095] The formation method of the magnetic tunnel material film 270 includes: forming a lower electromagnetic material film 271 on the surface of the substrate 200 and the lower electrode layer 261; forming an insulating film 272 on the surface of the lower electromagnetic material film 271, and forming an upper electromagnetic material film 273 on the surface of the insulating film 272.

[0096] The lower electromagnetic material film 271 includes: a lower composite film (not marked in the figure) located on the substrate 200 and the surface of the lower electrode film 261, and a lower electromagnetic film (not marked in the figure) located on the surface of the lower composite film.

[0097] In this embodiment, the lower composite film is located on the surface of the stop layer 220 and the surface of the lower electrode film 261.

[0098] The material of the lower electromagnetic film includes one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0099] The lower composite film is a single-layer structure or a composite structure; when the lower composite film is a single-layer structure, the materials of the lower composite film include: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, or lanthanum strontium manganite; when the lower composite film is a composite structure, the lower composite film includes several overlapping conductive layers, and the materials of each of the conductive layers include: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0100] In this embodiment, the lower electromagnetic film is a single-layer structure, and the material of the lower electromagnetic film is cobalt iron boron; the lower composite film is a double-layer structure, and the lower composite film includes a conductive layer formed of cobalt material and a conductive layer formed of platinum material, so that the lower electromagnetic material film 271 is a fixed layer, that is, the magnetization direction of the lower electromagnetic material film 271 is fixed.

[0101] The upper electromagnetic material film 273 includes: an upper composite film (not marked in the figure) on the surface of the insulating film 272, and an upper electromagnetic film (not marked in the figure) on the surface of the upper composite film.

[0102] The materials of the upper electromagnetic film include: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0103] The upper composite film is a single-layer structure or a composite structure; when the upper composite film is a single-layer structure, the materials of the upper composite film include: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, or lanthanum strontium manganite; when the upper composite film is a composite structure, the upper composite film includes several overlapping conductive layers, and the materials of each of the conductive layers include: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0104] In this embodiment, the upper electromagnetic film is a single-layer structure, and the material of the upper electromagnetic film is cobalt iron boron; the upper composite film is a double-layer structure, and the upper composite film includes a conductive layer formed of cobalt material and a conductive layer formed of nickel material, so that the upper electromagnetic material film 273 is a free layer, that is, the magnetization direction of the upper electromagnetic material film 273 is not fixed.

[0105] The materials of the insulating film 272 include: one or several combinations of magnesium oxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium dioxide, and zirconium dioxide.

[0106] In this embodiment, the insulating film 272 is a single-layer structure, and the material of the insulating film 272 is magnesium oxide.

[0107] In this embodiment, it further includes: forming an upper electrode film 274 on the surface of the magnetic tunnel material film 270.

[0108] The material of the upper electrode film 274 includes one or a combination of several of: copper, tungsten, aluminum, titanium, titanium nitride, tantalum.

[0109] In this embodiment, the upper electrode film 274 is a single-layer structure, and the material of the upper electrode film is tantalum.

[0110] Next, pattern the magnetic tunnel material film to form a magnetic tunnel junction. For the specific process of forming the magnetic tunnel junction, please refer to Figures 10 to 11 .

[0111] Please refer to Figure 10 , and form a second patterned layer 280 on the surface of the magnetic tunnel material film 270. The second patterned layer 280 covers the surface of the magnetic tunnel material film 270 on the lower electrode layer 261.

[0112] Specifically, in this embodiment, the second patterned layer 280 is formed on the surface 274 of the upper electrode film on the surface of the magnetic tunnel material film 270.

[0113] The second patterned layer 280 is used to define the size and position of the magnetic tunnel junction to be formed subsequently.

[0114] In this embodiment, the second patterned layer 280 not only covers the surface 274 of the upper electrode film on the lower electrode layer 261, but also covers the surface 274 of the upper electrode film on the part of the substrate 200 on both sides of the lower electrode layer 261.

[0115] Please refer to Figure 11 , and use the second patterned layer 280 as a mask to etch the magnetic tunnel material film 270 until the surface of the stop layer 220 is exposed, forming the magnetic tunnel junction 275.

[0116] Since the stop layer 220 is provided on the surface of the substrate 200, during the process of patterning the magnetic tunnel material film 270 to form the magnetic tunnel junction 275, the etching process can stop on the surface of the stop layer 220, which is beneficial to avoiding affecting the devices in the substrate 200 and is beneficial to improving the electrical performance of the formed semiconductor structure.

[0117] Graphically represent the magnetic tunnel material film 270 such that the lower-layer electromagnetic material film 271 forms the lower-layer electromagnetic layer 2751; the insulating film 272 forms the insulating layer 2752; the upper-layer electromagnetic material film 272 forms the upper-layer electromagnetic layer 2753. The magnetic tunnel junction 275 includes: the lower-layer electromagnetic layer 2751 located on the surface of the lower-layer electrode layer 261, the insulating layer 2752 located on the surface of the lower-layer electromagnetic layer 2751, and the upper-layer electromagnetic layer 2753 located on the surface of the insulating layer 2752.

[0118] In this embodiment, the method for forming the semiconductor structure further includes: using the second patterned layer 280 as a mask to etch the upper-layer electrode film 274 to form the upper-layer electrode layer 276, and the upper-layer electrode layer 276 is located on the surface of the magnetic tunnel junction 275.

[0119] In this embodiment, after forming the magnetic tunnel junction 275, it further includes: removing the second patterned layer 280.

[0120] Please refer to Figure 12 , after forming the magnetic tunnel junction 275, a sidewall 290 is formed on the sidewall surface of the magnetic tunnel junction 275.

[0121] Specifically, in this embodiment, the sidewall 290 is formed on the sidewall surface of the magnetic tunnel junction 275 and the sidewall surface of the upper-layer electrode layer 276.

[0122] The method for forming the sidewall 290 includes: forming a sidewall material film (not shown in the figure) on the surface of the substrate 200, the sidewall surface of the magnetic tunnel junction 275, and the top surface and sidewall surface of the upper-layer electrode layer 276; etching back the sidewall material film until the surface of the substrate 200 and the top surface of the upper-layer electrode layer 276 are exposed to form the sidewall 290.

[0123] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please refer to Figure 9 , including: a substrate 200 having a conductive layer 210 therein, and the surface of the substrate 200 exposes the surface of the conductive layer 210; a groove 250 adjacent to the conductive layer 210 within the substrate 200, and the sidewall of the groove 250 exposes the sidewall surface of the conductive layer 210; a lower-layer electrode layer 261 located within the groove 250 and on the top surface of the conductive layer 210; a magnetic tunnel material film 270 located on the surface of the lower-layer electrode layer 261.

[0124] Since the lower electrode layer 261 not only covers the top surface of the conductive layer 210, but also covers the sidewall surface of the conductive layer 210, the contact area between the lower electrode layer 261 and the conductive layer 210 is increased, which is beneficial to reducing the contact resistance between the formed magnetic tunnel junction and the conductive layer 210, and is beneficial to improving the electrical performance of the formed semiconductor structure.

[0125] The following will be described in detail with reference to the accompanying drawings.

[0126] In this embodiment, the distance from the bottom of the groove 250 ( Figure 6 as shown in ) to the top of the conductive layer 210 is the first distance H1 ( Figure 6 as shown in ), and the distance from the bottom of the conductive layer 210 to the bottom of the conductive layer 210 is the second distance H2 ( Figure 6 as shown in ), and the ratio range of the first distance H1 to the second distance H2 is 1 / 3 to 1 / 2.

[0127] The significance of selecting the ratio range between the first distance H1 and the second distance H2 is as follows: If the ratio is less than 1 / 3, that is, the height of the lower electrode layer 261 covering the sidewall surface of the conductive layer 210 is too small, the contact area between the lower electrode layer 261 and the conductive layer 210 cannot be effectively increased, and the performance of the formed semiconductor structure is still poor; if the ratio is greater than 1 / 2, the height of the lower electrode 261 covering the sidewall surface of the conductive layer 210 is relatively large, which requires a relatively large depth of the groove 250 formed by etching the substrate 200, that is, the aspect ratio of the groove 250 is relatively large, making it difficult to form the 250 groove, which is not conducive to improving the performance of the formed semiconductor structure.

[0128] The material of the lower electrode layer 261 includes one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, etc.

[0129] The magnetic tunnel material film 270 includes: a lower electromagnetic material film 271 located on the substrate 200 and the surface of the lower electrode layer 261; an insulating film 272 located on the surface of the lower electromagnetic material film 271; an upper electromagnetic material film 273 located on the surface of the insulating film 272.

[0130] The material of the insulating film 272 includes one or a combination of magnesium oxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium dioxide, zirconium dioxide, etc.

[0131] The lower electromagnetic material film 271 includes: a lower composite film (not marked in the figure) located on the surface of the substrate and the surface of the lower electrode film, and a lower electromagnetic film (not marked in the figure) located on the surface of the lower composite film; the upper electromagnetic material film 273 includes: an upper composite film (not marked in the figure) located on the surface of the insulating film, and an upper electromagnetic film (not marked in the figure) located on the surface of the upper composite film.

[0132] The material of the upper electromagnetic film includes: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite; the material of the lower electromagnetic film includes: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0133] The upper composite film is a single-layer structure or a composite structure; when the upper composite film is a single-layer structure, the material of the upper composite film includes: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, or lanthanum strontium manganite; when the upper composite film is a composite structure, the upper composite film includes several overlapping conductive layers, and the material of each of the conductive layers includes: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0134] The lower composite film is a single-layer structure or a composite structure; when the lower composite film is a single-layer structure, the material of the lower composite film includes: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, or lanthanum strontium manganite; when the lower composite film is a composite structure, the lower composite film includes several overlapping conductive layers, and the material of each of the conductive layers includes: one or several combinations of iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, and lanthanum strontium manganite.

[0135] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, within which there is a conductive layer, and the surface of the substrate exposes the surface of the conductive layer; A groove adjacent to the conductive layer within the substrate, and the sidewall of the groove exposes the sidewall surface of the conductive layer; A stop layer located on the surface of the substrate; A lower electrode layer located within the groove and on the top surface of the conductive layer, and the lower electrode layer covers the top surface of the conductive layer and extends to the sidewall surface of the conductive layer, and the surface of the lower electrode layer is flush with the surface of the stop layer; A magnetic tunnel material film located on the surface of the lower electrode layer.

2. The semiconductor structure according to claim 1, wherein The distance from the bottom of the groove to the top of the conductive layer is a first distance, the distance from the bottom of the conductive layer to the bottom of the conductive layer is a second distance, and the ratio range of the first distance to the second distance is 1 / 3 to 1 / 2.

3. The method for forming a semiconductor structure according to claim 1, wherein, The material of the lower electrode layer includes one or a combination of several of: copper, tungsten, aluminum, titanium, titanium nitride, tantalum.

4. The method for forming a semiconductor structure according to claim 1, wherein, The magnetic tunnel material film includes: a lower electromagnetic material film located on the substrate and the surface of the lower electrode layer; an insulating film located on the surface of the lower electromagnetic material film; an upper electromagnetic material film located on the surface of the insulating film.

5. The method for forming a semiconductor structure according to claim 4, wherein, The material of the insulating film includes one or a combination of several of: magnesium oxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium dioxide, zirconium dioxide.

6. The method for forming a semiconductor structure according to claim 4, wherein The lower electromagnetic material film includes: a lower composite film located on the surface of the substrate and the lower electrode film, and a lower electromagnetic film located on the surface of the lower composite film; the upper electromagnetic material film includes: an upper composite film located on the surface of the insulating film, and an upper electromagnetic film located on the surface of the upper composite film.

7. The method for forming a semiconductor structure according to claim 6, wherein The material of the upper electromagnetic film includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, lanthanum strontium manganite; the material of the lower electromagnetic film includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, lanthanum strontium manganite.

8. The method for forming a semiconductor structure according to claim 6, wherein, The upper composite film is a single-layer structure or a composite structure; when the upper composite film is a single-layer structure, the material of the upper composite film includes: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron or lanthanum strontium manganite; when the upper composite film is a composite structure, the upper composite film includes several overlapping conductive layers, and the material of each of the conductive layers includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, lanthanum strontium manganite.

9. The method for forming a semiconductor structure according to claim 6, wherein The lower composite film is a single-layer structure or a composite structure; when the lower composite film is a single-layer structure, the material of the lower composite film includes: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron or lanthanum strontium manganite; when the lower composite film is a composite structure, the lower composite film includes several overlapping conductive layers, and the material of each of the conductive layers includes one or a combination of several of: iron, platinum, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron, lanthanum strontium manganite.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, within which there is a conductive layer, and the surface of the substrate exposes the surface of the conductive layer; Forming a groove adjacent to the conductive layer within the substrate, and the sidewall of the groove exposes the sidewall surface of the conductive layer; Form a lower electrode layer in the groove and on the top surface of the conductive layer; Form a magnetic tunnel material film on the surface of the lower electrode layer.

11. The method for forming a semiconductor structure according to claim 10, wherein, The method for forming the groove includes: forming a hard mask structure on the surface of the substrate and the conductive layer; forming a first patterned layer on the surface of the hard mask structure, the first patterned layer having an opening, and the opening exposing the hard mask structure on the conductive layer and on a part of the substrate on the sidewall of the conductive layer; using the first patterned layer as a mask, etching the hard mask structure and a part of the substrate to expose the top surface of the conductive layer and the sidewall surface of a part of the conductive layer, forming the groove; after forming the groove, removing the hard mask structure and the first patterned layer.

12. The method for forming a semiconductor structure as claimed in claim 10, wherein, Further include: Before forming the groove, form a stop layer on the surface of the substrate and the conductive layer.

13. The method for forming a semiconductor structure according to claim 12, wherein, The material of the stop layer is different from that of the conductive layer; the material of the stop layer is different from that of the substrate; The material of the stop layer is different from that of the magnetic tunnel material film; The material of the stop layer includes: silicon nitride, silicon carbonitride or silicon oxynitride.

14. The method for forming a semiconductor structure according to claim 13, wherein The surface of the lower electrode layer is flush with the surface of the stop layer; the method for forming the lower electrode layer includes: forming a lower electrode film in the groove and on the surface of the stop layer; planarizing the lower electrode film until the surface of the stop layer is exposed, and forming a lower electrode layer in the groove.

15. The method for forming a semiconductor structure according to claim 14, wherein, The process for planarizing the lower electrode film includes: a chemical mechanical polishing process or a dry etching process.

16. The method for forming a semiconductor structure according to claim 10, wherein, Further include: Pattern the magnetic tunnel material film to form a magnetic tunnel junction.

17. The method for forming a semiconductor structure as described in claim 16, wherein, Further include: Before forming the groove, form a stop layer on the surface of the substrate and the conductive layer; The method for patterning the magnetic tunnel material film includes: forming a second patterned layer on the surface of the magnetic tunnel material film, the second patterned layer covering the surface of the magnetic tunnel material film on the lower electrode layer; Using the second patterned layer as a mask, etching the magnetic tunnel material film until the surface of the stop layer is exposed, forming the magnetic tunnel junction.

18. The method for forming a semiconductor structure according to claim 17, wherein, Further include: After forming the magnetic tunnel material film and before patterning the magnetic tunnel material film, form an upper electrode film on the surface of the magnetic tunnel material film; The method for forming the semiconductor structure further includes: using the second patterned layer as a mask, etching the upper electrode film to form an upper electrode layer, and the upper electrode layer is located on the surface of the magnetic tunnel junction.

19. The method for forming a semiconductor structure according to claim 16, wherein, Further include: After forming the magnetic tunnel junction, form a sidewall on the sidewall surface of the magnetic tunnel junction.

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