Method for driving circuit with energy recovery capability

Abstract

The present invention discloses a method for a drive circuit capable of energy recovery, for use in a drive circuit. The drive circuit is coupled between a voltage source and a load and is used to drive the load. The method includes forming a first current from the voltage source to the load by the drive circuit; and forming a second current from the load back to the voltage source by the drive circuit. The present invention utilizes a DC-DC converter circuit as a charging circuit to charge a capacitive load, utilizes another DC-DC converter circuit as a discharging circuit to recover energy stored in the capacitive load, utilizes a pulse width modulation controller to compensate for the imbalance in the charge transfer capabilities of the charging circuit and the discharging circuit, utilizes a toggle module to implement a bridge-tied load topology, and utilizes a high-resolution auxiliary amplifier circuit to reduce total harmonic distortion.

Description

Technical Field

[0001] The present application relates to a method for driving a circuit, and in particular to a method for driving a circuit capable of recovering energy. Background Art

[0002] Piezoelectric-actuated speakers (piezo-speakers) have recently come to the fore. Due to the capacitive properties of thin-film piezoelectric actuators, these piezo-actuated speakers present a high capacitive load to amplifiers. However, conventional driver circuits (such as Class AB, Class D, Class G, and Class H amplifiers) were developed under the assumption that the load (a coil made of very thin wire) is primarily resistive and slightly inductive. As a result, these amplifiers are inefficient when driving highly capacitive loads such as piezo-actuated speakers.

[0003] Furthermore, due to the capacitive nature of the load, the current is approximately 90° out of phase with the driving voltage. Consequently, the piezoelectric speaker does not actually consume much power during the charging phase. Most of the energy drawn during the charging phase is stored in the load's capacitance. However, during the discharge phase, when the voltage across the speaker drops, conventional Class AB, D, G, and H amplifiers simply waste energy by discharging it from the load's capacitance to ground (or to the negative power supply).

[0004] Therefore, it is necessary to improve the existing technology. Summary of the Invention

[0005] Therefore, the main purpose of the present application is to provide a method for a driving circuit with energy recovery capability to improve the shortcomings of the prior art.

[0006] Embodiments of the present application disclose a method for a drive circuit capable of energy recovery, the method being applied to a drive circuit. The drive circuit is coupled between a voltage source and a load and configured to drive the load. The method includes generating, by the drive circuit, a first current from the voltage source to the load; and generating, by the drive circuit, a second current from the load back to the voltage source. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0008] Figure 2 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0009] Figure 3 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0010] Figure 4 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0011] Figure 5 FIG. 4 is a schematic diagram of a pulse width modulation controller according to an embodiment of the present application.

[0012] Figure 6 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0013] Figure 7 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0014] Figure 8 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0015] Figure 9 is a schematic diagram of a driving circuit according to an embodiment of the present application.

[0016] Figure 10a and Figure 10b The waveform of the comparison signal according to the embodiment of the present application is shown.

[0017] Figure 11a and Figure 11b The waveform of the comparison signal according to the embodiment of the present application is shown.

[0018] Figure 12 Curves showing the charge transfer capabilities of a charging circuit and a discharging circuit.

[0019] Figure 13 The waveform of the input signal according to the embodiment of the present application is shown.

[0020] Figure 14 Schematic diagram of an auxiliary amplifier circuit according to a first embodiment of the present application.

[0021] Figure 15 FIG. 1 is a schematic diagram of a source bypass capacitor and a load bypass capacitor according to an embodiment of the present application.

[0022] Figure 16 The charging circuit and the discharging circuit of the embodiment of the present application are shown.

[0023] Figure 17 It is a schematic diagram of a process of an embodiment of the present application.

[0024] The description of the accompanying drawings is as follows:

[0025]

[0026] DETAILED DESCRIPTION

[0027] In this application, the term “coupled to” may refer to a direct or indirect connection. “Couple component A to component B” may mean that component A is directly connected to component B or that component A is connected to component B through a component C.

[0028] Figure 1 FIG2 is a schematic diagram of a driving circuit 10 according to an embodiment of the present invention. The driving circuit 10 is coupled between a voltage source 11 and a load 13, and receives an input signal IN to drive the load 13 according to the input signal IN.

[0029] The voltage source 11 may have energy storage capabilities. For example, the voltage source 11 may include a battery (which may or may not be a rechargeable battery) or a direct current (DC) power supply, such as a DC-DC switching power supply. In one embodiment, the voltage source 11 (such as a DC-DC switching power supply) may include a capacitor or have capacitive properties.

[0030] In one embodiment, load 13 may include a speaker, or equivalently, a sound-generating device or acoustic transducer. In this case, input signal IN may be an audio signal. In one embodiment, the speaker within load 13 may include a piezoelectrically actuated speaker. Specifically, driver circuit 10 may be connected to a piezoelectric actuator of the piezoelectrically actuated speaker. The piezoelectric actuator within load 13 may include a piezoelectric layer sandwiched between a first / top electrode and a second / bottom electrode. Furthermore, driver circuit 10 may be connected to the electrodes of the actuator. Note that significant capacitance exists between the first / top electrode and the second / bottom electrode.

[0031] The driving circuit 10 is configured to generate a charging current from the voltage source 11 to the load 13 during a charging phase, and also to generate a discharging current from the load 13 back to the voltage source 11 during a discharging phase. In this regard, the energy stored in the capacitance within the load 13 during the charging phase is recovered and returned to the capacitance within (or associated with) the voltage source 11 during the discharging phase, thereby reducing the total energy consumption.

[0032] Specifically, the driving circuit 10 includes a charging circuit 12, a discharging circuit 14, and a pulse width modulation (PWM) controller 16. The charging circuit 12 and the discharging circuit 14 have a first terminal coupled to the voltage source 11 and a second terminal coupled to the load 13. The charging circuit 12 is used to generate a first / charging current I from the voltage source 11 to the load 13. ch(or provide a first / charging current path). The discharge circuit 14 is used to form a second / discharging current I from the load 13 back to the voltage source 11. DIS (or provide a second / discharge current path).

[0033] In conjunction with the capacitor within load 13, charging circuit 12 is similar to a boost converter (a boost converter is a type of DC-DC converter), and discharging circuit 14 is similar to a buck converter (a buck converter is another type of DC-DC converter). In other words, driver circuit 10 can be considered to utilize the boost converter (charging circuit 12) to charge the capacitor within load 13 and the buck converter (discharging circuit 14) to discharge the capacitor within load 13.

[0034] In one embodiment, during the charging phase (ie, a time interval corresponding to the upswing portion of the input signal IN), the boost converter (charging circuit 12) charges the charging current I ch The voltage source 11 is supplied to the load 13 to perform a charging operation; in the discharge phase (i.e., a time interval corresponding to the downswing portion of the input signal IN), the discharge circuit 14 guides the discharge current I dis The voltage is returned from the load 13 to the voltage source 11 to perform a discharge operation.

[0035] exist Figure 1 In the illustrated embodiment, the charging circuit 12 includes a switch S1, a diode D1, and an inductor L1. The discharging circuit 14 includes a switch S2, a diode D2, and an inductor L2. Switch S1 is controlled by a first pulse-width modulation signal SU, while switch S2 is controlled by a second pulse-width modulation signal SD. The pulse-width modulation signals SU and SD are generated by a pulse-width modulation controller 16. The pulse-width modulation controller 16 has a first input terminal for receiving an input signal IN and a second input terminal coupled to the load 13 for receiving a feedback signal FB1. The pulse-width modulation controller 16 generates the pulse-width modulation signals SU and SD based on the input signal IN and the feedback signal FB1, so that the driver circuit 10 drives the load 13 according to the input signal IN. Diodes D1 and D2 function as rectifying components, which will be described in detail later.

[0036] The connections between the components within the driver circuit 10 are described in detail below. In the charging circuit 12, an anode of the diode D1 is coupled to the voltage source 11 via the inductor L1, and a cathode of the diode D1 is coupled to the load 13. A first terminal of the switch S1 is coupled to the anode of the diode D1. That is, a first terminal of the inductor L1 is coupled to the voltage source 11, and a second terminal of the inductor L1 is coupled to the anode of the diode D1 and the first terminal of the switch S1. In one embodiment, a second terminal of the switch S1 may be as shown in FIG. Figure 1 As shown, the switch S2 is coupled to the ground terminal, but is not limited thereto. In the discharge circuit 14, a first terminal of the switch S2 is coupled to the voltage source 11 via the inductor L2, and a second terminal of the switch S2 is coupled to the load 13. A cathode of the diode D2 is coupled to the first terminal of the switch S2. That is, a first terminal of the inductor L2 is coupled to the voltage source 11, and a second terminal of the inductor L2 is coupled to the cathode of the diode D2 and the first terminal of the switch S2. In one embodiment, an anode of the diode D2 may be as shown. Figure 1 The circuit is shown coupled to ground, but is not limited thereto.

[0037] In one embodiment, diodes D1 and D2 may be replaced by a synchronous rectifier (SR), which includes a switch / metal-oxide-semiconductor field-effect transistor (MOSFET) with an appropriate (gate) control signal, as will be described in detail later.

[0038] In one embodiment, the voltage source 11 and the load 13 may be as follows: Figure 1 The circuit is shown coupled to ground, but is not limited thereto.

[0039] The voltage source 11 provides a supply / power voltage V S , and the load 13 has a load voltage V L The driver circuit 10 can operate at a supply / power voltage V S Not higher than the load voltage V L (i.e. V S ≤V L ) situation.

[0040] Although the circuit topology is similar to that of a DC-DC switching power supply (e.g., a step-up converter and / or a step-down converter), the control mechanism of switches S1 / S2 is similar to that of a conventional Class-D amplifier. Switches S1 / S2 are controlled by a pulse-width modulation signal and a pulse-width modulation controller. The pulse-width modulation signal is generated based on an input signal IN and a feedback signal FB1. The pulse-width modulation controller will be described in detail later.

[0041] Different from the driving circuit in the prior art, the discharge current I dis The discharged current is diverted toward the voltage source 11 rather than toward the ground or another voltage source (e.g., a negative voltage source). This can be considered as the energy / charge stored in the capacitor within the load 13 being recovered and stored in the voltage source 11. This significantly reduces the power consumption of the driving circuit.

[0042] In addition, since inductors increase cost and occupy more physical space, inductors L1 and L2 can be combined. For example, Figure 2 FIG2 is a schematic diagram of a driving circuit 20 according to an embodiment of the present application. The driving circuit 20 is similar to the driving circuit 10, and thus the same components are represented by the same symbols. Unlike the driving circuit 10, the inductors L1 and L2 are replaced by an inductor L12. The driving circuit 20 includes a charging circuit 22 and a discharging circuit 24 that share the same inductor L12. Figure 2 As shown, a first terminal of the inductor L12 is coupled to the voltage source 11 , and a second terminal of the inductor L12 is coupled to the anode of the diode D1 , the first terminal of the switch S1 , the cathode of the diode D2 , and the first terminal of the switch S2 .

[0043] Since the driving circuit 20 (relative to the driving circuit 10) omits an inductor, the driving circuit 20 can be smaller than the driving circuit 10, and the inductor L21 used in the driving circuit 20 can have a larger core and bring a higher saturation current I SAT , to enhance driving ability.

[0044] In addition, the driving circuit of the present application can be operated at V S ≥V L Please refer to Figure 3 , Figure 3 Schematic diagram of a driving circuit 30 according to an embodiment of the present invention. The driving circuit 30 can be S ≥V L The driving circuit 30 includes a charging circuit 32 and a discharging circuit 34. Unlike the driving circuit 10, the charging circuit 32 is similar to a buck converter, and the discharging circuit 34 is similar to a boost converter. In other words, the driving circuit 30 uses a buck converter (charging circuit 32) to add charge to the capacitor (such as I ch As shown), and the boost converter (discharge circuit 34) is used to remove the charge from the capacitor in the load 13 (as shown in FIG. dis shown).

[0045] The connections between the components within the driver circuit 30 are described in detail below. In the charging circuit 32, a first terminal of the switch S1 is coupled to the voltage source 11, and a second terminal of the switch S1 is coupled to the load 13 via the inductor L1. The cathode of the diode D1 is coupled to the second terminal of the switch S1. A first terminal of the inductor L1 is coupled to the cathode of the diode D1, and the second terminal of the inductor L1 is coupled to the load 13. In one embodiment, an anode of the diode D1 may be as shown in FIG. Figure 3 As shown, the diode D2 is coupled to the ground terminal, but is not limited thereto. In the discharge circuit 34, the cathode of the diode D2 is coupled to the voltage source 11, and the anode of the diode D2 is coupled to the load 13 via the inductor L2. A first terminal of the switch S2 is coupled to the anode of the diode D2. A first terminal of the inductor L2 is coupled to the cathode of the diode D2 and the first terminal of the switch S2. A second terminal of the inductor L2 is coupled to the load 13. In one embodiment, a second terminal of the switch S2 can be as shown. Figure 3 The circuit is shown coupled to ground, but is not limited thereto.

[0046] Similar to the change from the driving circuit 10 to the driving circuit 20 , the inductors L1 and L2 in the driving circuit 30 may also be combined into the inductor L21 . Figure 4 FIG. 4 is a schematic diagram of a driving circuit 40 according to an embodiment of the present application. Figure 4 As shown, a first terminal of the inductor L12 is coupled to the cathode of the diode D1 , the second terminal of the switch S1 , the anode of the diode D2 , and the first terminal of the switch S2 . A second terminal of the inductor L12 is coupled to the load 13 .

[0047] It is worth noting that the boost converter and / or the buck converter can be used in the charging circuit and / or the discharging circuit, but is not limited thereto. Other types of DC-DC converters can also be used as the charging circuit and / or the discharging circuit, which is also within the scope of this application.

[0048] The pulse width modulation controller is described in detail below. Figure 5 FIG2 is a schematic diagram of a pulse width modulation controller 56 according to an embodiment of the present application. The pulse width modulation controller 56 can be used to implement the pulse width modulation controller 16. Compared to the control mechanism of a traditional Class D amplifier, the pulse width modulation controller 56 generates two pulse width modulation signals instead of one. This is achieved by a comparison signal generator 560, an error amplifier circuit 566, and two comparators 562 and 564.

[0049] The error amplifier 566 generates an error signal Verr from the input signal IN and the feedback signal FB1. In one embodiment, the positive input of the error amplifier 566 receives the input signal IN, and the negative input of the error amplifier 566 receives the feedback signal FB1, but the present invention is not limited thereto. In other words, when the error amplifier 566 does not enter the saturation region, the error signal Verr represents an amplified version of the error / difference (IN - FB1).

[0050] In one embodiment, the error amplifier 566 may be a differential amplifier including an operational amplifier or a differential transistor pair, but is not limited thereto.

[0051] The comparison signal generator 560 is used to generate a first comparison signal UU and a second comparison signal DD. In one embodiment, the first comparison signal UU and the second comparison signal DD may have a triangular (or sawtooth) waveform. In one embodiment, the first comparison signal UU is as follows: Figure 10a and Figure 10b The figure shows only the offset form of the second comparison signal DD. That is, the first comparison signal UU can be expressed as UU=DD+Δ, where Δ represents the offset.

[0052] The comparator 562 compares the error signal Verr with the first comparison signal UU to generate a first pulse-width modulation signal SU. The comparator 564 compares the error signal Verr with the second comparison signal DD to generate a second pulse-width modulation signal SD. In one embodiment, a positive input terminal of the first comparator 562 receives the error signal Verr, and a negative input terminal of the first comparator 562 receives the first comparison signal UU. A negative input terminal of the second comparator 564 receives the error signal Verr, and a positive input terminal of the second comparator 564 receives the second comparison signal DD.

[0053] In one embodiment, except that the first comparison signal UU is merely a shifted version of the second comparison signal DD, the first comparison signal UU is as follows: Figure 11a and Figure 11b The second comparison signal DD may be an offset-and-scaled version, or vice versa. In other words, the comparison signal UU / DD may be expressed as UU = a·DD + Δ', where Δ' represents the offset and a represents a scaling factor, which may be greater than 1 (i.e., a>1) or less than 1 (i.e., a<1). The value of the offset Δ / Δ' (the value of the offset Δ or Δ') and the scaling factor a may be designed based on actual circumstances and are within the scope of the present application.

[0054] In one embodiment, the offset Δ can be designed such that the lowest (voltage) level LLU of the first comparison signal UU is lower than the highest (voltage) level LHD of the second comparison signal DD, which means that the difference between the lowest level LLU and the highest level LHD is as follows: Figure 10a As shown, there is an overlapping region a0. In this case, when the error signal Verr is within the overlapping region (i.e., when LLU < Verr < LHD), comparator 562 generates a pulse-width modulated signal SU with a low duty factor, and comparator 564 generates a pulse-width modulated signal SD with a low duty factor. Furthermore, the pulses PU of the pulse-width modulated signal SU with a low duty factor and the pulses PD of the pulse-width modulated signal SD with a low duty factor are staggered in time. The staggered pulse-width modulated signals SU and SD generate a small current flowing through inductors L1 and L2. This small current (caused by the staggered pulses PU and PD) functions similarly to the quiescent current of a conventional class AB amplifier and helps reduce errors or distortion (such as total harmonic distortion (THD)) at load 13.

[0055] It should be noted that in the driving circuits 10-40, the amount of electron charge Q transferred in each cycle of the pulse width modulation signal of a given duty cycle depends on a voltage difference ΔV between the voltage source 11 and the load 13, wherein the voltage difference ΔV can be expressed as ΔV = |V S –V L |, where V S and V L like Figures 1 to 4 As shown in Figure 2, the transferred electron charge Q (in each cycle of a pulse-width modulation signal with a given duty cycle) has a nonlinear relationship with the voltage difference ΔV. Furthermore, the relationship between Q and ΔV exhibits different / opposite trends for the charging and discharging circuits.

[0056] For example, Figure 12 The relationship between the transferred charge Q and the voltage difference ΔV is shown. A curve 121 represents Figure 1 The charging circuit 12 or Figure 2 The relationship between the transferred charge Q and the voltage difference ΔV of the charging circuit 22 is shown by a curve 122. Figure 1 The discharge circuit 14 or Figure 2 The relationship between the transferred charge Q and the voltage difference ΔV of the discharge circuit 24 is shown in FIG. When ΔV is close to 0 or less than a threshold value th1, the slope of the curve 121 corresponding to the charging circuit is greater than the slope of the curve 122 corresponding to the discharge circuit. In other words, when ΔV is Figure 12When referring to a region I as shown, the charging circuit can be more sensitive (or have a stronger charge transfer ability) than the discharging circuit. On the other hand, when the voltage difference ΔV is greater than a threshold th2, the slope of curve 121 corresponding to the discharging circuit is larger than the slope of curve 122 corresponding to the charging circuit. That is, when ΔV is large enough or lies in Figure 12 a region II as shown, the discharging circuit can be more sensitive (or have a stronger charge transfer ability) than the charging circuit. Here, the sensitivity and charge transfer ability can be evaluated by the amount of charge Q transferred per voltage difference ΔV, or expressed as the tangent slope of the "Q vs. ΔV curve" (such as curve 121 or 122) at a specific ΔV.

[0057] To compensate for the imbalance in sensitivity or charge transfer ability between the charging circuit and the discharging circuit, the disparity between the pulse width of pulse PU of the pulse-width modulation signal SU and the pulse width of pulse PD of the pulse-width modulation signal SD can be combined to cancel the above imbalance. The difference in pulse width can be adjusted according to the slope difference. For example, when the slope difference between curve 121 and curve 122 increases, the difference in pulse width at certain ΔV also increases.

[0058] The above object can be achieved by appropriately designing the comparison signals UU and DD. For example, when the sensitivity of the charging (or discharging) circuit is high, the spread at the tip of the triangular waveform may become narrower, so as to reduce the pulse width of the pulse-width modulation signal and shorten the charging (or discharging) time period in each charging (or discharging) cycle. On the other hand, when the sensitivity of the charging (or discharging) circuit is low, the spread at the tip of the triangular waveform may become wider, so as to increase the pulse width of the pulse-width modulation signal and extend the charging (or discharging) time period in each charging (or discharging) cycle.

[0059] In other words, when the charge transfer ability of the charging circuit corresponding to a ΔV is stronger than that of the discharging circuit (such as in Figure 12 region I), for an error signal Verr of the same magnitude, the pulse-width modulation controller 16 / 56 can generate a pulse-width modulation signal SU with pulse PU when Verr < 0, and generate a pulse-width modulation signal SD with pulse PD when Verr > 0, where pulse PU has a pulse width PWU and pulse PD has a pulse width PWD, and the pulse width PWU can be less than the pulse width PWD (i.e., PWU < PWD). Conversely, when the charge transfer ability of the charging circuit corresponding to a ΔV is weaker than that of the discharging circuit (such as in Figure 12 region II), for an error signal Verr of the same magnitude, the pulse width PWU can be greater than the pulse width PWD (i.e., PWU > PWD).

[0060] For example, when the sensitivity of the charging circuit is higher than that of the discharging circuit, the following can be applied: Figure 11a The waveforms of the comparison signals UU and DD are shown (in the PWM controller 56), wherein in the linear region between Verr_max and Verr_min, UU can be expressed as UU=a·DD+Δ' and a>1. That is, ΔV is at Figure 12 In the area I shown, you can apply Figure 11a On the other hand, when the sensitivity of the charging circuit is lower than that of the discharging circuit, the following can be applied: Figure 11b The waveforms of the comparison signals UU and DD are shown in FIG. 1 , where UU can be expressed as UU=a·DD+Δ” and a<1. That is, ΔV is at Figure 12 When the area II is shown, it can be applied Figure 11b The waveforms of signals UU and DD are shown.

[0061] When ΔV is Figure 12 In the region III shown, the sensitivity of the charging circuit and the discharging circuit are more or less the same (meaning the slope difference is less than a predetermined threshold). Figure 10a and Figure 10b The waveforms of the comparison signals UU and DD are shown to have equal amplitudes. In other words, the proportional factor a can be selected according to the voltage difference Δ between the voltage source 11 and the load 13V.

[0062] In one embodiment, assuming the supply voltage V S Usually a fixed value, it can be adjusted according to the load voltage V L Select the scaling factor a. In one embodiment, the comparison signal generator 560 can be coupled to the load 13 to receive the load voltage V L And determine the scaling factor a.

[0063] It should be noted that the waveforms of the first comparison signal UU and the second comparison signal DD are not limited to triangular waveforms. Depending on actual design criteria, the waveforms of the first comparison signal UU and the second comparison signal DD may be truncated triangular waveforms (e.g., with flat tops and bottoms), trapezoidal waveforms, or other types of waveforms, which are also within the scope of the present application.

[0064] The operation of the driving circuits 10 to 40 can be as follows: Figure 17 The process is summarized as a process B0, which includes the following steps.

[0065] Step B02: forming a charging current from the voltage source to the load.

[0066] Step B04: generating a discharge current from the load back to the voltage source.

[0067] Step B02 is performed by the charging circuit and step B04 is performed by the discharging circuit. The details of step B02 and step B04 can be found in the above paragraphs and will not be repeated for the sake of brevity.

[0068] In addition, a bridge-tied-load (BTL) effect can be incorporated into the driving circuit of the present application. For example, Figure 6 FIG2 is a schematic diagram of a drive circuit 60 according to an embodiment of the present application. Drive circuit 60 is similar to drive circuit 10, and thus identical components are represented by identical symbols. Unlike drive circuit 10, drive circuit 60 also includes a polarity toggle module 62. Polarity toggle module 62 receives an input signal IN and generates an input signal IN′ to pulse-width modulation controller 16.

[0069] First determine the input signal IN relative to a voltage V AC,0V When the input signal IN is greater than the voltage V AC,0V When the input signal IN is judged to be "positive". When the input signal IN is less than the voltage V AC,0V When the input signal IN is judged to be "negative", the voltage V can be selected according to the actual situation. AC,0V , according to the voltage V AC,0V The polarity of the input signal IN can be determined. On the one hand, for an alternating current (AC) signal, the voltage V AC,0V It can be regarded as a ground voltage. In one embodiment, the voltage V AC,0V It can be an average value of the input signal IN. In the embodiment where the input signal IN is a digital 2's compliment format, V AC,0V Will only correspond to "0".

[0070] Please refer to Figure 6 and Figure 13 ,in Figure 13 The waveform of the input signal IN is shown in the upper half and the waveform of the input signal IN' is shown in the lower half. Figure 13 In the IN waveform shown in FIG, during one of the time intervals T+, the input signal IN is positive (at Figure 13 Indicated as IN+), the input signal waveform IN is replicated in waveform IN' and fed to the polarity switching module 62, so that the pulse width modulation controller 16 generates the pulse width modulation signal SU / SD according to the signal IN+. In this case, a first terminal of the load 13 (at Figure 6 Indicated as T 1L ) is connected to a first node N1, a second end of the load 13 (at Figure 6Indicated as T 2L ) is connected to a second node N2. Figure 13 When the input signal IN is negative (in the time interval T- shown) Figure 13 The polarity switching module 62 generates an inverted form of the input signal IN (denoted as -IN-), so that the first terminal T 1L is connected to the second node N2 and the second terminal T 2L When connected to the first node N1, the PWM controller 16 generates a PWM signal SU / SD according to -IN-.

[0071] exist Figure 6 In the embodiment shown, nodes N1 and N2 are referred to as two ends of the charging (or discharging) circuit, but are not limited thereto. As long as the input signal IN changes its sign (or crosses the voltage V AC,0V ), the polarity of the voltage applied to / across the load 13 (i.e., the polarity of the load 13) is reversed / swapped, which is all within the scope of the present application.

[0072] like Figure 6 As shown, the polarity toggle module 62 includes a first toggle switch 621, a second toggle switch 622, a third toggle switch 623 and an inverter 624. The toggle switch 621 is connected to the first terminal T 1L The toggle switch 622 is connected to the second terminal T 2L and nodes N1 and N2. The third toggle switch 623 is coupled to an inverter 624. The inverter 624 is used to generate an inverted version of the input signal IN. In the case where the input signal IN is in digital format, the functions of the switch 623 and the inverter 624 can be replaced by the mathematical "absolute value" operator.

[0073] The operation of the polarity toggle module 62 is as follows. When the input signal IN is positive (or in the time interval T+), the toggle switch 623 outputs the input signal IN (i.e., the positive component IN+) to the first input terminal of the pulse width modulation controller 16, and the toggle switch 621 conducts the first terminal T of the load 13. 1L The second toggle switch 622 is connected to the first node N1, and the second end T of the load 13 is turned on. 2L When the input signal IN is negative (or in the time interval T-), the toggle switch 623 outputs the inverted form of the input signal IN (i.e., the inverted form of the negative component IN-, represented as -IN-) to the first input terminal of the pulse width modulation controller 16, and the toggle switch 621 turns on the first terminal T of the load 13. 1LThe second toggle switch 622 is connected to the second end T of the load 13. 2L A connection between the first node N1 and the second node N2.

[0074] The signal received at the first input terminal of the pulse width modulation controller 16 is denoted as IN'. The input signal IN' comprises Figure 13 Shown is a positive component IN+ at time interval T+ and an inverted negative component -IN- at time interval T-.

[0075] In one embodiment, each toggle switch 621 - 623 can be implemented as a single-pole double-throw (SPDT) switch. In one embodiment, through appropriate routing, the three toggle switches 621 - 623 (all) can be combined into a three-pole double-throw (3PDT) switch.

[0076] In addition, the polarity switching module 62 may include a sign detector ( Figure 6 (not shown). The sign detector is used to determine the polarity of the input signal IN and generate an output signal to control the toggle switches 621-623. In one embodiment, the toggle switches 621-623 can be controlled by a control signal, and the control signal can be synchronized with the output signal of the sign detector. In this application, the two signals are synchronized to indicate that the rising / falling edges of the two signals are aligned in time. In another embodiment, the toggle switches 621-623 can be controlled by control signals ctr1-ctr3, respectively, and the control signals ctr1-ctr3 are all synchronized with the output signal of the sign detector.

[0077] In one embodiment, the sign detector can be implemented by a comparator, wherein a first input terminal of the comparator receives an input signal IN, a second input terminal receives a voltage V AC,0V And an output terminal outputs an output signal.

[0078] In one embodiment, the second node N2 can receive a supply voltage V S In one embodiment, the second node N2 may be connected to a voltage source 11 to receive a supply voltage V S .

[0079] In addition, the driving circuit 60 may include a differential feedback circuit 64. In one embodiment, the feedback circuit 64 may include a differential amplifier having a voltage divider at an input stage, with FB1 = r·V L The feedback signal FB1 is generated in the form of L Indicates that it spans both ends T1L and T 2L In one embodiment, the feedback circuit 64 can be implemented by a resistor or a capacitor, but is not limited thereto. It should be noted that the feedback circuit as a voltage divider can also be used between the load 13 of the drive circuits 10-40 and the pulse width modulation controller 16, but is not limited thereto.

[0080] The benefit of the bridge-tied load driver circuit 60 is that it can amplify (or double) the overall voltage swing applied to the load 13 at a given breakdown voltage of the charging / discharging circuit. In other words, assuming that the charging circuit 12 and the discharging circuit 14 have the same breakdown voltage (denoted as V B ) process to manufacture, Figure 6 The peak-to-peak voltage across the load 13 in the circuit 60 shown can reach 2.V B ,Right now Figure 1 In addition to doubling the drive voltage range, the efficiency of the charge / discharge circuit is also improved.

[0081] Similarly, a bridge-tied load topology using the polarity switching module 62 can be used in the driver circuits 20, 30, and 40. For example, Figure 7 FIG2 is a schematic diagram of a driving circuit 70 according to an embodiment of the present invention. The driving circuit 70 is similar to the driving circuit 20 , but differs from the driving circuit 20 in that the polarity switching module 62 is used.

[0082] From another perspective, the PWM signals SU and SD may be in a low level state at the same time, causing the switches S1 and S2 to be turned off in a switching cycle. Figure 10b For example, if the offset Δ is designed so that the lowest (voltage) level LLU of the first comparison signal UU is greater than the highest (voltage) level LHD of the second comparison signal DD, it means that Figure 10b As shown, there is a non-overlapping gap a2 between the highest (voltage) level LHD of the second comparison signal DD and the lowest (voltage) level LLU of the first comparison signal UU. When the error signal Verr is within the non-overlapping gap a2, that is, LLU>Verr>LHD, the pulse width modulation signals SU and SD will be in a low level state, and the switches S1 and S2 will be turned off during the switching cycle. Similar to a conventional class B amplifier, the switches S1 and S2 that are turned off at the same time will be at the first terminal T 1L This causes errors and produces total harmonic distortion.

[0083] It should be noted that, in one embodiment, the comparison signals UU and DD are outside the linear range of Verr (between Verr_max and Verr_min) (e.g. Figure 10a and Figure 10b and Figure 11a and Figure 11b The dotted line in the figure does not serve any practical purpose and does not need to be generated.

[0084] In order to reduce the first end T 1L To reduce the error and total harmonic distortion, an auxiliary amplifier can be used to drive the second terminal T 2L . Figure 8 FIG is a schematic diagram of a driving circuit 80 according to an embodiment of the present invention. The driving circuit 80 is similar to the driving circuit 20. Unlike the driving circuit 20, the driving circuit 80 further includes an auxiliary amplifier circuit 82. The auxiliary amplifier circuit 82 (details are shown in FIG. Figure 14 A first input terminal (indicated by “1”) of the auxiliary amplifier circuit 82 receives the input signal IN. A second input terminal (indicated by “2”) of the auxiliary amplifier circuit 82 is coupled to the first terminal T of the load 13. 1L An output terminal of the auxiliary amplifier circuit 82 is coupled to the second terminal T of the load 13. 2L .

[0085] In the driving circuit 80, the charging circuit 22 and the discharging circuit 24 can be regarded as generating an output voltage Vout, and the auxiliary amplifier circuit 82 generates a compensation voltage Vcp. The output voltage Vout is applied to the first terminal T of the load 13. 1L , and the compensation voltage Vcp is applied to the second terminal T of the load 13 2L .

[0086] It should be noted that the charging and discharging circuits with pulse width modulation controllers in the driving circuit 80 can be regarded as amplifier circuits with a wide dynamic range, high efficiency but low resolution, while the auxiliary amplifier circuit 82 can be regarded as an amplifier circuit with a narrow dynamic range, low efficiency but high resolution. In other words, the resolution of the compensation voltage Vcp is higher / finer than the resolution of the output voltage Vout, the peak-to-peak voltage swing range of the compensation voltage Vcp is smaller than the peak-to-peak voltage swing range of the output voltage Vout, and thus the amplifier circuit (including the charging circuit and the discharging circuit) has a higher efficiency than the auxiliary amplifier circuit 82. When the amplifier circuit and the auxiliary amplifier circuit 82 thus constructed are as shown in FIG. Figure 8 When combined together as shown, the driver circuit 80 will benefit from the wide dynamic range and high efficiency of the pulse width modulation controlled charging circuit 22 and discharging circuit 24 while achieving the high resolution of the auxiliary amplifier circuit 82.

[0087] Please note that Figure 8The charging circuit 22 and the discharging circuit 24 used in the figure are for illustration only. The driving circuit including the auxiliary amplifier circuit 82 may use the charging circuit 12 / 32 / 42 and the discharging circuit 14 / 34 / 44, which is also within the scope of the present application.

[0088] Similarly, the auxiliary amplifier circuit 82 can be used in other driving circuits of the present application. For example, Figure 9 FIG2 is a schematic diagram of a driver circuit 90 according to an embodiment of the present application. Driver circuit 90 is similar to driver circuits 70 and 80. Unlike driver circuit 70, driver circuit 90 includes an auxiliary amplifier circuit 82. Unlike driver circuit 80, the first input terminal (indicated by "1") of auxiliary amplifier circuit 82 in driver circuit 90 receives input signal IN', the second input terminal (indicated by "2") of auxiliary amplifier circuit 82 in driver circuit 90 is coupled to a first node N1, and the output terminal of auxiliary amplifier circuit 82 is coupled to a second node N2.

[0089] Figure 14 FIG. 8 is a diagram illustrating an auxiliary amplifier circuit 82 according to an embodiment of the present application. Figure 14 As shown, the auxiliary amplifier circuit 82 may include an amplifier 820 (which may be an operational amplifier) ​​and impedance components Z1-Z4. The impedance components Z1-Z4 may be resistors or capacitors. The values ​​of Z1-Z4 may be selected so that the output generated by the amplifier 820 is equal to the output at the node V L For example, Z3 / Z4=Z2 / Z1=r, where r is the error when node V L The error ε is zero when V L The ideal ratio between V / IN, ε=V L If the output amplifier 820 perfectly matches ε, the voltage across the load 13 is equal to V L -V 820 =V L -ε=V L -(V L =r·IN) = r·IN, which is a perfect result. Therefore, the resolution of the driver circuit 80 is determined by the resolution of the amplifier 820, and the output voltage swing range (dynamic range) of the amplifier 820 is equal to the range of ε.

[0090] It should be noted that the embodiments described above are intended to illustrate the concepts of the present application, and modifications and variations may be made accordingly by those skilled in the art, without limitation. For example, bias / offset voltages may be appropriately added to nodes / endpoints within the driver circuit, voltage source, and load to achieve a better operating (bias) point. For example, (if load 13 includes a piezoelectrically actuated speaker) a bias voltage may be applied to one of the electrodes of an actuator within load 13 to shift the actuator into a more linear operating region. Applying bias voltages to nodes / endpoints to achieve a better dynamic range, voltage comparison basis, etc. is also within the scope of the present application.

[0091] Alternatively, switches S1 and S2 may be implemented with appropriate transistors. Diodes D1 and D2 may be simple diodes with a single PN junction, transistors with appropriate wiring configurations, or synchronous switches / MOSFETs controlled by appropriate gate drive signals.

[0092] Diodes D1 and D2 limit current flow in one direction (but not in the opposite direction) and can be considered a rectifying component. Note that this application is not limited to using diodes as rectifying components. As previously mentioned, synchronous rectifiers can also be used as rectifying components. Synchronous rectifiers include a rectifying switch controlled by a synchronization signal.

[0093] For example, Figure 16 The charging circuits 12', 32' and the discharging circuits 14', 34' are shown. The charging circuits 12', 32' and the discharging circuits 14', 34' can be used in the driving circuit of the present application. Figure 16 As shown, charging circuits 12' and 32' are obtained by replacing diode D1 with a rectifier switch S1' controlled by a synchronization signal SU'. The rectifier switch S1' and the synchronization signal SU' form a synchronous rectifier. Synchronous rectifiers are well known in the art. The rectifier switch S1' can be turned on when the current flows in the desired direction and turned off before the current direction is reversed. Similarly, the discharge circuits 14' and 34' are obtained by replacing diode D2 with a rectifier switch S2' controlled by a synchronization signal SD'. Similar to diodes D1 / D2, by appropriately designing the control signals SU' / SD', the rectifier switches S1' / S2' can also allow current to flow in a specific direction while inhibiting current from flowing in the opposite direction.

[0094] In other words, the diode and the synchronous rectifier (such as Figure 16The rectifier switches shown include a rectifier switch controlled by a synchronization signal and can be considered two different implementations / embodiments of the rectifier component. The use of synchronous rectifiers is also within the scope of this application. Furthermore, in some embodiments, both the diode and the synchronous rectifier can be used in a single charging (or discharging) circuit, which is also within the scope of this application.

[0095] In one embodiment, the first terminal T connected to the load 13 may include 1L and a load bypass capacitor C connected to the ground terminal L , in order to improve the efficiency and stability of the driving circuit of the present application. In addition, a source bypass capacitor C connected to the voltage source 11 and the ground terminal may be included. S , to reduce V S Schematically, in Figure 15 The source bypass capacitor C is shown in the figure S and load bypass capacitor C L , which is also within the scope of this application.

[0096] It should be noted that the driving circuit of the present application is applicable to capacitive speaker loads, but is not limited thereto. In addition to speakers, the driving circuit of the present application can also be used to drive different types of capacitive loads.

[0097] In summary, the present application utilizes a DC-DC converter circuit as a charging circuit to charge a capacitive load, utilizes another DC-DC converter circuit as a discharge circuit to recover energy stored in the capacitive load, utilizes a pulse width modulation controller to compensate for the imbalance in the charge transfer capabilities of the charging circuit and the discharge circuit, utilizes a toggle module to implement a bridge-tied load topology, and utilizes a high-resolution auxiliary amplifier circuit to reduce total harmonic distortion.

[0098] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for a driving circuit capable of recovering energy, wherein the driving circuit is coupled between a voltage source and a load and is used to drive the load, characterized in that: The method comprises: A first pulse width modulation signal and a second pulse width modulation signal are generated according to an input signal and a feedback signal, wherein the feedback signal is proportional to a load voltage of the load, and the steps of generating the first pulse width modulation signal and the second pulse width modulation signal include: Determining a polarity of the input signal; When the polarity of the input signal is positive, generating the first pulse width modulation signal and the second pulse width modulation signal according to a positive component of the input signal; and When the polarity of the input signal is negative, generating the first pulse width modulation signal and the second pulse width modulation signal according to a negative component of the input signal; a first DC-DC converter of the driving circuit controlled by the first pulse width modulation signal and a second DC-DC converter of the driving circuit controlled by the second pulse width modulation signal; generating a first current from the voltage source to the load by the driving circuit according to the first pulse width modulation signal; and generating, by the driving circuit, a second current flowing from the load back to the voltage source according to the second pulse width modulation signal; wherein the pulse width of the first pulse width modulation signal or the second pulse width modulation signal is determined according to the difference between the input signal and the feedback signal; The load is a capacitive speaker load, and the input signal is an input audio signal.

2. The method according to claim 1, wherein The driving circuit includes the first DC-DC converter and the second DC-DC converter, and the method includes: forming the first current from the voltage source to the load by the first DC-DC converter; and The second DC-DC converter forms the second current flowing from the load back to the voltage source.

3. The method according to claim 2, wherein The first DC-DC converter includes a boost converter, and the second DC-DC converter includes a buck converter.

4. The method according to claim 2, wherein The first DC-DC converter includes a buck converter, and the second DC-DC converter includes a boost converter.

5. The method according to claim 1, wherein The step of generating the first pulse width modulation signal and the second pulse width modulation signal according to the input signal and the feedback signal comprises: The input signal and the feedback signal are obtained.

6. The method according to claim 5, wherein The step of generating the first pulse width modulation signal and the second pulse width modulation signal according to the input signal and the feedback signal comprises: generating a first comparison signal and a second comparison signal; generating an error signal according to the input signal and the feedback signal; generating the first pulse width modulation signal by comparing the first comparison signal and the error signal; and The second pulse width modulation signal is generated by comparing the second comparison signal and the error signal.

7. The method according to claim 6, wherein The steps of generating the first comparison signal and the second comparison signal include: The first comparison signal is generated, where the first comparison signal is an offset version of the second comparison signal.

8. The method according to claim 6, wherein The steps of generating the first comparison signal and the second comparison signal include: The first comparison signal is generated, wherein the first comparison signal is a scaled shifted version of the second comparison signal.

9. The method according to claim 8, wherein The proportional offset form corresponds to a proportional factor, and the step of generating the first comparison signal includes: obtaining the load voltage of the load; and The proportional factor is determined according to the load voltage.

10. The method according to claim 6, wherein The step of generating the first pulse width modulation signal and the second pulse width modulation signal further includes: obtaining a first sensitivity of the first DC-DC converter and a second sensitivity of the second DC-DC converter, wherein the first sensitivity corresponds to a voltage difference between a supply voltage and the load voltage, and the second sensitivity corresponds to the voltage difference; determining whether the first sensitivity is higher than the second sensitivity; The first pulse width modulation signal is generated, and the second pulse width modulation signal is generated, wherein the first pulse width modulation signal includes a first pulse having a first pulse width, and the second pulse width modulation signal includes a second pulse having a second pulse width, wherein when the first sensitivity is higher than the second sensitivity, the first pulse width is narrower than the second pulse width.

11. The method according to claim 6, wherein The step of generating the first pulse width modulation signal and the second pulse width modulation signal further includes: obtaining a first sensitivity of the first DC-DC converter and a second sensitivity of the second DC-DC converter, wherein the first sensitivity corresponds to a voltage difference between a supply voltage and the load voltage, and the second sensitivity corresponds to the voltage difference; determining whether the first sensitivity is lower than the second sensitivity; The first pulse width modulation signal is generated, and the second pulse width modulation signal is generated, wherein the first pulse width modulation signal includes a first pulse having a first pulse width, and the second pulse width modulation signal includes a second pulse having a second pulse width, wherein when the first sensitivity is lower than the second sensitivity, the first pulse width is greater than the second pulse width.

12. The method according to claim 5, wherein Also includes: When the input signal exceeds a voltage, the polarity of the load is switched.

13. The method according to claim 1, wherein A charging circuit and a discharging circuit generate an output voltage, and the method includes: applying the output voltage to a first terminal of the load; and A compensation voltage is generated according to an error between the input signal and the output voltage, and the compensation voltage is applied to a second end of the load.

14. The method according to claim 13, wherein A resolution of the compensation voltage is higher than a resolution of the output voltage.

15. The method according to claim 13, wherein The peak-to-peak voltage swing range of the compensation voltage is smaller than the peak-to-peak voltage swing range of the output voltage.

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