Device and method for feature point tracking using inter-frame prediction

Abstract

Devices and methods for inter-frame prediction. For example, one embodiment of the method includes: extracting a first set of key points from a current frame and a second set of key points from a reference frame; based on a motion vector associated with a region in the current frame where the key points are found p projecting the key points p into the reference frame as p '; locating the key point in the reference frame that is closest to p '; n key points; and based on the descriptor distance between each of the n key points and p ', matching one of the n key points in the reference frame to the key point p。

Description

Technical Field

[0001] The present invention generally relates to the field of graphics processors. More particularly, the present invention relates to devices and methods for tracking feature points in video images using inter-frame prediction. Background Art

[0002] Feature point tracking is a technique used in many video processing and graphics fields such as Structure from Motion (SFM) and panoramic processing (e.g., for virtual reality implementations). The first step in any implementation is camera calibration, which uses feature point tracking to determine the extrinsic parameters of the camera, which is a complex problem.

[0003] Feature point tracking and matching techniques are required to detect feature points from each image or video stream frame. Then, feature points are matched between image pairs. For each pair of images, an approximate nearest neighbor method can be used to match key point descriptors between the pair of images. Brief Description of the Drawings

[0004] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

[0005] Figure 1 is a block diagram of an embodiment of a computer system with a processor having one or more processor cores and a graphics processor;

[0006] Figure 2 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;

[0007] Figure 3 is a block diagram of an embodiment of a graphics processor, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores;

[0008] Figure 4 is a block diagram of an embodiment of a graphics processing engine for a graphics processor;

[0009] Figure 5 is a block diagram of another embodiment of a graphics processor;

[0010] Figure 6 is a block diagram of thread execution logic including an array of processing elements;

[0011] Figure 7 illustrates a graphics processor execution unit instruction format according to an embodiment;

[0012] Figure 8A block diagram of another embodiment of a graphics processor, the graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline;

[0013] Figure 9A A block diagram showing a graphics processor command format according to an embodiment;

[0014] Figure 9B A block diagram showing a graphics processor command sequence according to an embodiment;

[0015] Figure 10 Shows an exemplary graphics software architecture for a data processing system according to an embodiment;

[0016] Figure 11 Shows an exemplary IP core development system that can be used to fabricate an integrated circuit to perform operations according to an embodiment;

[0017] Figure 12 Shows an exemplary system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment;

[0018] Figure 13 Shows an exemplary graphics processor of a system-on-chip integrated circuit that can be fabricated using one or more IP cores;

[0019] Figure 14 Shows another exemplary graphics processor of a system-on-chip integrated circuit that can be fabricated using one or more IP cores;

[0020] Figure 15 A block diagram showing a computer system configured to implement one or more aspects of the embodiments described herein;

[0021] Figure 16A - 16D Shows a parallel processor component according to an embodiment;

[0022] Figure 17A - 17B A block diagram of a graphics multiprocessor according to an embodiment;

[0023] Figure 18A - 18F Shows an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0024] Figure 19 Shows a graphics processing pipeline according to an embodiment;

[0025] Figure 20 Shows a key point mapping technique;

[0026] Figure 21 Shows motion vectors associated with inter-blocks of a video stream;

[0027] Figure 22 shows an inter-frame block mapped from a first frame to a second frame based on a motion vector;

[0028] Figure 23 shows an embodiment of an architecture for mapping key points using the motion vector of an inter-frame block;

[0029] Figure 24 shows an embodiment of a method for mapping key points using the motion vector of an inter-frame block; and

[0030] Figure 25 shows an example of a pair of points for showing a match between a current frame and a reference frame. DETAILED DESCRIPTION

[0031] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention described below. However, one of ordinary skill in the art will appreciate that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the fundamental principles of embodiments of the invention.

[0032] Exemplary Graphics Processor Architecture and Data Types

[0033] System Overview

[0034] Figure 1 is a block diagram of a processing system 100 according to an embodiment. In various embodiments, system 100 includes one or more processors 102 and one or more graphics processors 108, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, hand-held, or embedded device.

[0035] Embodiments of system 100 may include or be incorporated within the following: a server-based gaming platform, a game console, including a gaming and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 100 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. Data processing system 100 may also include a wearable device, coupled to or integrated within the wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 100 is a television or set-top box device having one or more processors 102 and a graphical interface generated by one or more graphics processors 108.

[0036] In some embodiments, one or more of the processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The multiple processor cores 107 may each process a different instruction set 109, which may include instructions for facilitating the emulation of other instruction sets. The processor cores 107 may also include other processing devices such as a digital signal processor (DSP).

[0037] In some embodiments, the processor 102 includes a cache 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache is shared among the various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherence techniques. The processor 102 also includes a register file 106, which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0038] In some embodiments, processor 102 is coupled to processor bus 110 to transfer communication signals such as address, data, or control signals between processor 102 and other components in system 100. In one embodiment, system 100 uses an exemplary "hub" system architecture that includes a memory controller hub 116 and an input / output (I / O) controller hub 130. Memory controller hub 116 facilitates communication between memory devices and other components of system 100, while I / O controller hub (ICH) 130 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 116 is integrated within the processor.

[0039] Memory device 120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having performance suitable for acting as a process memory. In one embodiment, memory device 120 can operate as the system memory of system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute an application or process. Memory controller hub 116 is also coupled to an optional external graphics processor 112, which can communicate with one or more graphics processors 108 in processor 102 to perform graphics and media operations.

[0040] In some embodiments, ICH 130 enables peripheral devices to be connected to memory device 120 and processor 102 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, audio controller 146, firmware interface 128, wireless transceiver 126 (e.g., Wi-Fi, Bluetooth), data storage device 124 (e.g., hard disk drive, flash memory, etc.), and a legacy I / O controller 140 for coupling legacy (e.g., personal system 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 142 connect input devices such as a keyboard and mouse 144 combination. Network controller 134 is also coupled to ICH 130. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 110. It will be appreciated that the system 100 shown is exemplary and not restrictive, as other types of data processing systems with different configurations can also be used. For example, I / O controller hub 130 can be integrated within the one or more processors 102, or memory controller hub 116 and I / O controller hub 130 can be integrated into a discrete external graphics processor (such as external graphics processor 112).

[0041] Figure 2is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A - 202N, an integrated memory controller 214, and an integrated graphics processor 208. Elements having the same reference numeral (or name) as elements in any other figure herein Figure 2 can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to such. Processor 200 can include additional cores, up to and including additional core 202N represented by the dashed box. Each of the processor cores 202A - 202N includes one or more internal cache units 204A - 204N. In some embodiments, each processor core may also have access to one or more shared cache units 206.

[0042] The internal cache units 204A - 204N and the shared cache units 206 represent the cache memory hierarchy within processor 200. The cache memory hierarchy can include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid - level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest - level cache before the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 206 and 204A - 204N.

[0043] In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 210 provides management functionality for the various processor components. In some embodiments, the system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

[0044] In some embodiments, one or more of the processor cores 202A - 202N include support for simultaneous multi - threading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A - 202N during multi - threaded processing. The system agent core 210 may additionally include a power control unit (PCU), which includes logic and components for regulating the power states of the processor cores 202A - 202N and the graphics processor 208.

[0045] In some embodiments, the processor 200 further includes a graphics processor 208 for performing graphics processing operations. In some embodiments, the graphics processor 208 is coupled to a set of shared cache units 206 and a system agent core 210 including one or more integrated memory controllers 214. In some embodiments, a display controller 211 is coupled to the graphics processor 208 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 211 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 208 or the system agent core 210.

[0046] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of the processor 200. However, alternative interconnect units can be used, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques well known in the art. In some embodiments, the graphics processor 208 is coupled to the ring interconnect 212 via an I / O link 213.

[0047] The exemplary I / O link 213 represents at least one of multiple types of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218 such as an eDRAM module. In some embodiments, each of the processor cores 202A - 202N and the graphics processor 208 uses the embedded memory module 218 as a shared last-level cache.

[0048] In some embodiments, the processor cores 202A - 202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A - 202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 202A - 202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A - 202N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled to one or more power-efficient cores. Additionally, the processor 200 can be implemented on one or more chips, or as a SoC integrated circuit having the illustrated components among other components.

[0049] Figure 3is a block diagram of a graphics processor 300, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and uses commands placed in the processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0050] In some embodiments, the graphics processor 300 further includes a display controller 302 for driving display output data to a display device 320. The display controller 302 includes hardware for one or more overlay planes for displaying and combining multiple layers of video or user interface elements. In some embodiments, the graphics processor 300 includes a video codec engine 306 to encode media into one or more media encoding formats, decode media from one or more media encoding formats, or transcode media between one or more media encoding formats, the media encoding formats including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0051] In some embodiments, the graphics processor 300 includes a Block Image Transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations (including, for example, bit boundary block transfer). However, in one embodiment, one or more components of the Graphics Processing Engine (GPE) 310 are used to perform 2D graphics operations. In some embodiments, the GPE 310 is a computing engine for performing graphics operations including three-dimensional (3D) graphics operations and media operations.

[0052] In some embodiments, the GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions for 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 312 includes programmable and fixed-function elements that perform various tasks within the element and / or spawn execution threads to the 3D / media subsystem 315. Although the 3D pipeline 312 can be used to perform media operations, embodiments of the GPE 310 also include a media pipeline 316 specifically for performing media operations (such as video post-processing and image enhancement).

[0053] In some embodiments, media pipeline 316 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in lieu of or on behalf of video codec engine 306. In some embodiments, media pipeline 316 additionally includes a thread spawning unit to spawn threads for execution on 3D / media subsystem 315. The spawned threads perform computations for media operations on one or more graphics execution units included in 3D / media subsystem 315.

[0054] In some embodiments, 3D / media subsystem 315 includes logic for executing threads spawned by 3D pipeline 312 and media pipeline 316. In one embodiment, the pipeline sends thread execution requests to 3D / media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. Execution resources include an array of graphics execution units for handling 3D and media threads. In some embodiments, 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, which includes registers and addressable memory for sharing data between threads and storing output data.

[0055] Graphics Processing Engine

[0056] Figure 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, graphics processing engine (GPE) 410 is Figure 3 a certain version of GPE 310 shown in Figure 4 Elements with the same reference numeral (or name) as elements in any other figure herein Figure 3 can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto. For example, 3D pipeline 312 and media pipeline 316 of

[0057] In some embodiments, GPE 410 is coupled to, or includes, a command stream converter 403 that provides a command stream to 3D pipeline 312 and / or media pipeline 316. In some embodiments, command stream converter 403 is coupled to a memory, which can be system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 403 receives commands from the memory and sends the commands to 3D pipeline 312 and / or media pipeline 316. The commands are indications fetched from a ring buffer that stores commands for 3D pipeline 312 and media pipeline 316. In one embodiment, the ring buffer can additionally include a batch command buffer that stores a batch of multiple commands. Commands for 3D pipeline 312 can also include references to data stored in the memory, such as, but not limited to, vertex and geometry data for 3D pipeline 312 and / or image data and memory objects for media pipeline 316. 3D pipeline 312 and media pipeline 316 process commands and data by performing operations via logic within the respective pipeline or by dispatching one or more execution threads to graphics core array 414.

[0058] In various embodiments, 3D pipeline 312 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 414. Graphics core array 414 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution units) within graphics core array 414 includes support for various 3D API shader languages and can execute multiple simultaneously executing threads associated with multiple shaders.

[0059] In some embodiments, graphics core array 414 also includes execution logic for performing media functions, such as video and / or image processing. In one embodiment, the execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computing operations in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel with, or in conjunction with, the (one or more) processor cores 107 as in Figure 1 or the general-purpose logic within cores 202A - 202N as in Figure 2 and perform processing operations in parallel with, or in conjunction with, the general-purpose logic within cores 202A - 202N as in

[0060] Output data generated by threads executing on graphics core array 414 can output data to memory in unified return buffer (URB) 418. URB 418 can store data for multiple threads. In some embodiments, URB 418 can be used to send data between different threads executing on graphics core array 414. In some embodiments, URB 418 can additionally be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 420.

[0061] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0062] Graphics core array 414 is coupled to shared function logic 420, which includes a plurality of resources shared among the graphics cores within the graphics core array. The shared functions within shared function logic 420 are hardware logic units that provide dedicated complementary functionality to graphics core array 414. In various embodiments, shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 within shared function logic 420.

[0063] In cases where the demand for a given dedicated function is not sufficient to be included within graphics core array 414, the shared function is implemented. Alternatively, a single instantiation of the dedicated function is implemented as a stand-alone entity within shared function logic 420 and shared among the execution resources within graphics core array 414. The exact set of functions shared among and included within graphics core array 414 varies between embodiments.

[0064] Figure 5 is a block diagram of another embodiment of graphics processor 500. Elements having the same reference numeral (or name) as elements in any other figure herein Figure 5 can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to such.

[0065] In some embodiments, the graphics processor 500 includes a ring interconnect 502, a pipeline front end 504, a media engine 537, and graphics cores 580A - 580N. In some embodiments, the ring interconnect 502 couples the graphics processor to other processing units, including other graphics processors or one or more general - purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi - core processing system.

[0066] In some embodiments, the graphics processor 500 receives batches of commands via the ring interconnect 502. Incoming commands are interpreted by a command - stream converter 503 in the pipeline front end 504. In some embodiments, the graphics processor 500 includes scalable execution logic for performing 3D geometry processing and media processing by means of (one or more of) the graphics cores 580A - 580N. For 3D geometry processing commands, the command - stream converter 503 provides the commands to a geometry pipeline 536. For at least some media processing commands, the command - stream converter 503 provides the commands to a video front end 534, which is coupled to the media engine 537. In some embodiments, the media engine 537 includes a video quality engine (VQE) 530 for video and image post - processing and a multi - format codec (MFX) engine 533 for providing hardware - accelerated encoding and decoding of media data. In some embodiments, the geometry pipeline 536 and the media engine 537 each generate execution threads for the thread execution resources provided by at least one of the graphics cores 580A.

[0067] In some embodiments, the graphics processor 500 includes modular cores 580A-580N (sometimes referred to as core slices) characterized by scalable thread execution resources, each having a plurality of sub-cores 550A-550N, 560A-560N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 500 can have any number of graphics cores 580A through 580N. In some embodiments, the graphics processor 500 includes a graphics core 580A having at least a first sub-core 550A and a second sub-core 560A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 550A). In some embodiments, the graphics processor 500 includes a plurality of graphics cores 580A-580N, each including a set of first sub-cores 550A-550N and a set of second sub-cores 560A-560N. Each sub-core in the set of first sub-cores 550A-550N includes at least an execution unit 552A-552N and a first set of media / texture samplers 554A-554N. Each sub-core in the set of second sub-cores 560A-560N includes at least an execution unit 562A-562N and a second set of samplers 564A-564N. In some embodiments, each sub-core 550A-550N, 560A-560N shares a set of shared resources 570A-570N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0068] Execution Unit

[0069] Figure 6 Thread execution logic 600 showing an array of processing elements employed in some embodiments of the GPE. Elements having the same reference number (or name) as elements in any other figure in this document Figure 6 can operate or function in any manner similar to the ways described elsewhere in this document, but are not limited to such.

[0070] In some embodiments, the thread execution logic 600 includes a shader processor 602, a thread dispatcher 604, an instruction cache 606, a scalable execution unit array including a plurality of execution units 608A - 608N, a sampler 610, a data cache 612, and a data port 614. In one embodiment, the scalable execution unit array is capable of dynamically scaling by enabling or disabling one or more execution units (e.g., any of the execution units 608A, 608B, 608C, 608D through 608N - 1 and 608N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, the thread execution logic 600 includes one or more connections to memory (such as system memory or a cache) via the instruction cache 606, the data port 614, the sampler 610, and one or more of the execution units 608A - 608N. In some embodiments, each execution unit (e.g., 608A) is an independently programmable general - purpose computing unit that can execute multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A - 608N is scalable to include any number of individual execution units.

[0071] In some embodiments, the execution units 608A - 608N are primarily used to execute shader programs. The shader processor 602 is capable of processing various shader programs and dispatches execution threads associated with the shader programs via the thread dispatcher 604. In one embodiment, the thread dispatcher includes logic for arbitrating requests for threads initiated from the graphics and media pipelines and instantiating the requested threads on one or more of the execution units 608A - 608N. For example, a geometry pipeline (e.g., Figure 5 536) can dispatch vertex, tessellation, or geometry shaders to the thread execution logic 600 ( Figure 6 ) for processing. In some embodiments, the thread dispatcher 604 is also capable of handling runtime thread spawning requests from executed shader programs.

[0072] In some embodiments, execution units 608A - 608N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (such as Direct3D and OpenGL) to execute with minimal translation. The execution units support vertex and geometry processing (such as vertex programs, geometry programs, vertex shaders), pixel processing (such as pixel shaders, fragment shaders), and general - purpose processing (such as compute and media shaders). Each of the execution units 608A - 608N can perform multi - issue single - instruction multiple - data (SIMD) execution, and multi - threaded operations achieve an efficient execution environment in the face of higher - latency memory accesses. Each hardware thread within each execution unit has a dedicated high - bandwidth register file and associated independent thread state. Execution is multi - issue per clock on a pipeline capable of integer, single - precision, and double - precision floating - point operations, SIMD branch capabilities, logical operations, transcendental operations, and other miscellaneous operations. When waiting for data from one of memory or a shared function, the dependency logic within execution units 608A - 608N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution unit can perform operations for pixel shaders, fragment shaders, or another type of shader program (including a different vertex shader).

[0073] Each of the execution units 608A - 608N operates on an array of data elements. The number of data elements is the "execution size" or the number of lanes for an instruction. Execution lanes are the logical units for data - element access, masking, and flow - control execution within an instruction. The number of lanes can be independent of the number of physical arithmetic - logic units (ALUs) or floating - point units (FPUs) for a particular graphics processor. In some embodiments, execution units 608A - 608N support integer and floating - point data types.

[0074] The execution - unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256 - bit - wide vector, the 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64 - bit packed data elements (quad - word (QW) size data elements), eight separate 32 - bit packed data elements (double - word (DW) size data elements), sixteen separate 16 - bit packed data elements (word (W) size data elements), or thirty - two separate 8 - bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0075] The thread execution logic 600 includes one or more internal instruction caches (e.g., 606) to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 612) are included to cache thread data during thread execution. In some embodiments, a sampler 610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 610 includes dedicated texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0076] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 600 via the thread spawning and dispatching logic. Once a group of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 602 is called to further compute the output information and write the result to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes the values of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 602 then executes the pixel or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 602 dispatches threads to the execution units (e.g., 608A) via the thread dispatcher 604. In some embodiments, the pixel shader 602 uses the texture sampling logic in the sampler 610 to access texture data stored in a texture map in memory. Arithmetic operations on the texture data and the input geometric data compute the pixel color data for each geometric fragment or discard one or more pixels from further processing.

[0077] In some embodiments, the data port 614 provides a memory access mechanism for the thread execution logic 600 to output the processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 614 includes or is coupled to one or more caches (e.g., the data cache 612) to cache data for memory access via the data port.

[0078] Figure 7is a block diagram showing a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid boxes show components generally included in the execution unit instructions, while the dashed boxes include optional or components only included in a subset of the instructions. In some embodiments, the instruction formats 700 described and illustrated are macro-instructions, as they are the instructions supplied to the execution unit, as opposed to micro-operations generated by instruction decoding once the instruction is processed.

[0079] In some embodiments, a graphics processor execution unit natively supports instructions in a 128-bit instruction format 710. Based on the selected instructions, instruction options, and number of operands, a 64-bit compact instruction format 730 may be used for some instructions. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit instruction format 730. The available native instructions in the 64-bit instruction format 730 vary by embodiment. In some embodiments, a set of index values in an index field 713 is used to partially compress the instructions. The execution unit hardware references a set of compression tables based on the index values and uses the compressed table output to reconstruct the native instructions in the 128-bit instruction format 710.

[0080] For each format, an instruction opcode 712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, an instruction control field 714 enables control of certain execution options such as channel selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, an execution size field 716 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 716 is not available for use in the 64-bit compact instruction format 730.

[0081] Some execution unit instructions have up to three operands, which include two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions can have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. The last source operand of the instruction can be an immediate (e.g., hard-coded) value passed with the instruction.

[0082] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are directly provided by bits in the instruction.

[0083] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes including a 16-byte alignment access mode and a 1-byte alignment access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

[0084] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction will use direct addressing or indirect addressing. When using direct register addressing mode, the bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0085] In some embodiments, instructions are grouped based on the 712-bit opcode fields to simplify opcode decoding 740. For an 8-bit opcode, bits 4, 5, and 6 allow the execution units to determine the type of the opcode. The exact opcode groupings shown are merely examples. In some embodiments, the move and logic opcode group 742 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares the five most significant bits (MSBs), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 748 includes per-component arithmetic instructions (e.g., add, multiply (mul)) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

[0086] Graphics Pipeline

[0087] Figure 8 is a block diagram of another embodiment of the graphics processor 800. Elements having the same reference numeral (or name) as elements in any other figure in this document Figure 8 of the document can operate or function in any manner similar to the manner described elsewhere in this document, but are not limited to such.

[0088] In some embodiments, the graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870. In some embodiments, the graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by writing to one or more control registers (not shown) or via commands issued to the graphics processor 800 through the ring interconnect 802. In some embodiments, the ring interconnect 802 couples the graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 802 are interpreted by a command stream converter 803, which supplies instructions to the various components of the graphics pipeline 820 or the media pipeline 830.

[0089] In some embodiments, the command stream converter 803 directs the operation of the vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 803. In some embodiments, the vertex fetcher 805 provides vertex data to the vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 805 and the vertex shader 807 execute vertex processing instructions by dispatching execution threads to the execution units 852A - 852B via the thread dispatcher 831.

[0090] In some embodiments, the execution units 852A - 852B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, the execution units 852A - 852B have attached L1 caches 851, which are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0091] In some embodiments, the graphics pipeline 820 includes a tessellation component to perform hardware - accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides the backend evaluation of the tessellation output. The tessellator 813 operates under the guidance of the hull shader 811 and contains dedicated logic to generate a set of detailed geometric objects based on a coarse geometric model provided as an input to the graphics pipeline 820. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 811, the tessellator 813, and the domain shader 817) can be bypassed.

[0092] In some embodiments, the complete geometric object can be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A - 852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on the entire geometric object, rather than on vertices or vertex patches as in the previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0093] Before rasterization, the clipper 829 processes vertex data. The clipper 829 can be a programmable clipper or a fixed-function clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access the un-rasterized vertex data via the stream output unit 823.

[0094] The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the major components of the processor. In some embodiments, the execution units 852A - 852B and associated cache(s) 851, texture and media sampler 854, and texture / sampler cache 858 are interconnected via a data port 856 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 854, caches 851, 858, and execution units 852A - 852B each have separate memory access paths.

[0095] In some embodiments, the render output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated render cache 878 and depth cache 879 are also available in some embodiments. The pixel operations component 877 performs pixel-based operations on the data, although in some instances, pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 841 or, at display time, by the display controller 843 using an overlay display plane instead. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing data to be shared without using the main system memory.

[0096] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command stream converter 803. In some embodiments, the media pipeline 830 includes a separate command stream converter. In some embodiments, the video front end 834 processes media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes thread spawning functionality to spawn threads for dispatch to the thread execution logic 850 via the thread dispatcher 831.

[0097] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled to the graphics processor via the ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0098] In some embodiments, the graphics pipeline 820 and the media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for all of the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with a compatible 3D pipeline will also be supported if a mapping can be made from the future API's pipeline to the graphics processor's pipeline.

[0099] Graphics Pipeline Programming

[0100] Figure 9A is a block diagram showing a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram showing a graphics processor command sequence 910 according to an embodiment. Figure 9A The solid boxes in show the components that are generally included in a graphics command, while the dashed lines include optional or components that are only included in a subset of the graphics commands. Figure 9A The exemplary graphics processor command format 900 of includes data fields for identifying the target client 902 of the command, a command operation code (opcode) 904, and associated data 906 of the command. Some commands also include a sub-opcode 905 and a command size 908.

[0101] In some embodiments, client 902 designates a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition further processing of the command and routes the command data to an appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a client unit receives a command, the client unit reads the opcode 904 and sub-opcode 905 (if the sub-opcode 905 exists) to determine the operation to be performed. The client unit uses the information in the data field 906 to execute the command. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of a double word.

[0102] Figure 9B The flowchart in FIG. shows an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the shown command sequence to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only as embodiments are not limited to these particular commands or this command sequence. Additionally, commands can be issued as a batch of commands in a command sequence such that the graphics processor processes the sequence of commands at least partially concurrently.

[0103] In some embodiments, the graphics processor command sequence 910 can begin with a pipeline flush command 912 to cause any active graphics pipeline to complete the current outstanding commands of that pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate concurrently. The pipeline flush is executed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline flush, the command parser for the graphics processor will suspend command processing until the active drawing engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked "dirty" in the render cache can be flushed to memory. In some embodiments, the pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0104] In some embodiments, the pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, unless the context will issue commands for both pipelines, the pipeline select command 913 is only required once within the execution context before issuing a pipeline command. In some embodiments, immediately before the pipeline switch via the pipeline select command 913, the pipeline dump clear command 912 is required.

[0105] In some embodiments, the pipeline control command 914 configures the graphics pipeline for operation and is used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, the pipeline control command 914 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and clears data from one or more caches within the active pipeline before processing a batch of commands.

[0106] In some embodiments, the command for returning buffer status 916 is used to configure a set of return buffers for the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring the return buffer status 916 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0107] The remaining commands in the command sequence vary based on the active pipeline for operation. Based on the pipeline determination 920, the command sequence is customized to the 3D pipeline 922 starting with the 3D pipeline state 930 or the media pipeline 924 starting with the media pipeline state 940.

[0108] The commands used to configure the 3D pipeline state 930 include 3D state set commands for vertex buffer status, vertex element status, constant color status, depth buffer status, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if they will not be used.

[0109] In some embodiments, 3D primitive 932 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via 3D primitive 932 commands are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 932 commands are used to perform vertex operations on 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0110] In some embodiments, the 3D pipeline 922 is triggered via execution of 934 commands or events. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via "go" or "kick" commands in a command sequence. In one embodiment, a pipeline synchronization command used to dump and clear the command sequence passing through the graphics pipeline is used to trigger command execution. The 3D pipeline will perform geometric processing for 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. For those operations, additional commands can also be included to control pixel shading and pixel backend operations.

[0111] In some embodiments, when performing media operations, the graphics processor command sequence 910 follows the media pipeline 924 path. Generally, the specific use and manner of programming for the media pipeline 924 depend on the media or compute operation to be performed. Specific media decoding operations can be offloaded to the media pipeline during media decoding. In some embodiments, it is also possible to bypass the media pipeline and use the resources provided by one or more general-purpose processing cores to perform all or part of the media decoding. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to the rendering of graphics primitives.

[0112] In some embodiments, the media pipeline 924 is configured in a manner similar to the 3D pipeline 922. A set of commands used to configure the media pipeline state 940 are dispatched or placed into a command queue prior to the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding and decoding formats. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements containing a batch of state settings.

[0113] In some embodiments, the media object commands 942 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers that contain video data to be processed. In some embodiments, all media pipeline states must be valid prior to issuing the media object commands 942. Once the pipeline state is configured and the media object commands 942 are queued, the media pipeline 924 is triggered via an execute command 944 or an equivalent execution event (e.g., register write). The output from the media pipeline 924 can then be post-processed by operations provided by either the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0114] Graphics Software Architecture

[0115] Figure 10 An exemplary graphics software architecture for a data processing system 1000 is shown. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute in the system memory 1050 of the data processing system.

[0116] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions can be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 1014 in machine language suitable for execution by the general-purpose processor cores 1034. The application also includes graphics objects 1016 defined by vertex data.

[0117] In some embodiments, the operating system 1020 is from Microsoft Corporation An operating system, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a Linux kernel variant. The operating system 1020 is capable of supporting a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation can be Just-In-Time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0118] In some embodiments, the user-mode graphics driver 1026 includes a backend shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. When the OpenGL API is in use, the shader instructions 1012 in the high-level GLSL language are passed to the user-mode graphics driver 1026 for compilation. In some embodiments, the user-mode graphics driver 1026 uses the operating system kernel-mode functionality 1028 to communicate with the kernel-mode graphics driver 1029. In some embodiments, the kernel-mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

[0119] IP Core Implementation

[0120] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium can include instructions representing various logics within the processor. When read by a machine, the instructions can cause the machine to fabricate the logic to perform the techniques described herein. Such a representation, referred to as an "IP core", is a reusable unit of logic for an integrated circuit and can be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model can be supplied to various customers or manufacturing facilities that load the hardware model onto a fabrication machine for manufacturing the integrated circuit. The integrated circuit can be fabricated such that the circuit performs the operations described in association with any of the embodiments herein.

[0121] Figure 11FIG. is a block diagram showing an IP core development system 1100 that can be used to fabricate an integrated circuit to perform operations. The IP core development system 1100 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). The design facility 1130 is capable of generating a software simulation 1110 of an IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of an integrated circuit that models the digital signal flow between hardware registers, including the associated logic executed using the modeled digital signals. In addition to the RTL design 1115, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0122] The RTL design 1115 or equivalent can be further synthesized by the design facility into a hardware model 1120, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party fabrication facility 1165. Alternatively, the IP core design can be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The fabrication facility 1165 can then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0123] Exemplary System - on - Chip Integrated Circuit

[0124] Figure 12 - 14 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores in accordance with various embodiments described herein are shown. In addition to what is shown, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0125] Figure 12FIG. is a block diagram showing an exemplary system-on-chip integrated circuit 1200 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., processors), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, and any of the above processors may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic, which includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I2S / I2C controller 1240. Additionally, the integrated circuit can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage can be provided by a flash memory subsystem 1260 that includes a flash memory and a flash memory controller. A memory interface can be provided via a memory controller 1265 to access SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

[0126] Figure 13 FIG. is a block diagram showing an exemplary graphics processor 1310 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 1310 can be Figure 12 a variant of the graphics processor 1210. The graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D through 1315N-1 and 1315N). The graphics processor 1310 is capable of executing different shader programs via separate logic such that the vertex processor 1305 is optimized to perform operations for a vertex shader program, while the one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. The vertex processor 1305 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (one or more) fragment processors 1315A-1315N use the primitives and vertex data generated by the vertex processor 1305 to produce a frame buffer that is displayed on a display device. In one embodiment, the (one or more) fragment processors 1315A-1315N are optimized to execute a fragment shader program as provided in the OpenGL API, which can be used to perform operations similar to those of a pixel shader program as provided in the Direct 3D API.

[0127] The graphics processor 1310 further includes one or more memory management units (MMUs) 1320A - 1320B, one or more caches 1325A - 1325B, and one or more circuit interconnects 1330A - 1330B. The one or more MMUs 1320A - 1320B provide virtual address to physical address mapping for the graphics processor 1310 (including for the vertex processor 1305 and / or one or more fragment processors 1315A - 1315N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1325A - 1325B. In one embodiment, the one or more MMUs 1320A - 1320B may be synchronized with other MMUs within the system, the other MMUs including one or more MMUs associated with Figure 12 one or more application processors 1205, image processors 1215, and / or video processors 1220 such that each of the processors 1205 - 1220 can participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 1330A - 1330B enable the graphics processor 1310 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0128] Figure 14 is a block diagram showing an additional exemplary graphics processor 1410 of a system - on - chip integrated circuit that may be fabricated using one or more IP cores. The graphics processor 1410 may be Figure 12 a variant of the graphics processor 1210. The graphics processor 1410 includes Figure 13 one or more MMUs 1320A - 1320B, one or more caches 1325A - 1325B, and one or more circuit interconnects 1330A - 1330B of the integrated circuit 1300.

[0129] The graphics processing unit 1410 includes one or more shader cores 1415A - 1415N (e.g., 1415A, 1415B, 1415C, 1415D, 1415E, 1415F to 1415N - 1, and 1415N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In embodiments and implementations, the exact number of shader cores present may vary. Additionally, the graphics processing unit 1410 includes: an inter - core task manager 1405 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1415A - 1415N; and a tiling unit 1418 that is used to accelerate tiling operations for tile - based rendering, where rendering operations for a scene are subdivided in image space, e.g., to take advantage of local spatial coherence within the scene or to optimize the use of internal caches.

[0130] Exemplary Graphics Micro - architecture

[0131] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine - learning operations, pattern - analysis operations, and various general - purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high - speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0132] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of ordinary skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well - known features are not described to avoid obscuring the details of the embodiments.

[0133] System Overview

[0134] Figure 15FIG. is a block diagram of a computing system 1500 configured to implement one or more aspects of the embodiments described herein. The computing system 1500 includes a processing subsystem 1501 having one or more processors 1502 and a system memory 1504, which communicate via an interconnect path that may include a memory hub 1505. The memory hub 1505 may be a separate component within a chipset component or may be integrated within one or more of the processors 1502. The memory hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. The I / O subsystem 1511 includes an I / O hub 1507 that enables the computing system 1500 to receive input from one or more input devices 1508. Additionally, the I / O hub 1507 may implement a display controller that may be included within one or more of the processors 1502 to provide output to one or more display devices 1510A. In one embodiment, one or more of the display devices 1510A coupled to the I / O hub 1507 may include a local, internal, or embedded display device.

[0135] In one embodiment, the processing subsystem 1501 includes one or more parallel processors 1512 coupled to the memory hub 1505 via a bus or other communication link 1513. The communication link 1513 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In one embodiment, one or more of the parallel processors 1512 form a parallel or vector processing system in a computing cluster that includes a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In one embodiment, one or more of the parallel processors 1512 form a graphics processing subsystem that may output pixels to one of the one or more display devices 1510A coupled to the I / O hub 1507. One or more of the parallel processors 1512 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1510B.

[0136] Within the I / O subsystem 1511, the system storage unit 1514 can be connected to the I / O hub 1507 to provide a storage mechanism for the computing system 1500. The I / O switch 1516 can be used to provide an interface mechanism to enable connections between the I / O hub 1507 and other components, such as network adapter 1518 and / or wireless network adapter 1519 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 1520. The network adapter 1518 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 1519 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless radio devices.

[0137] The computing system 1500 can include other components (including USB or other port connections, optical storage drives, video capture devices, etc.) not explicitly shown, which can also be connected to the I / O hub 1507. The Figure 15 communication paths interconnecting the various components therein can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or (one or more) protocols, such as NV-Link high-speed interconnect or interconnect protocols known in the art.

[0138] In one embodiment, one or more parallel processors 1512 incorporate circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a Graphics Processing Unit (GPU). In another embodiment, one or more parallel processors 1512 incorporate circuitry optimized for general-purpose processing while retaining the underlying computing architecture, as described in more detail herein. In yet another embodiment, the components of the computing system 1500 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 1512, the memory hub 1505, (one or more) processors 1502, and the I / O hub 1507 can be integrated into a System-on-Chip (SoC) integrated circuit. Alternatively, the components of the computing system 1500 can be integrated into a single package to form a System-in-Package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 1500 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0139] It will be appreciated that the computing system 1500 shown herein is illustrative and that variations and modifications are possible. The connection topology (including the number and arrangement of bridges), the number of processors 1502, and the number of parallel processors 1512 may be modified as desired. For example, in some embodiments, the system memory 1504 is connected directly to the processors 1502 rather than through a bridge, and other devices communicate with the system memory 1504 via the memory hub 1505 and the processors 1502. In other alternative topologies, the parallel processors 1512 are connected to the I / O hub 1507 or directly to one of the processors 1502 rather than to the memory hub 1505. In other embodiments, the I / O hub 1507 and the memory hub 1505 may be integrated into a single chip. Some embodiments may include two or more sets of processors 1502 attached via multiple slots, which may be coupled to two or more instances of the parallel processors 1512.

[0140] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 1500. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be removed. Additionally, some architectures may use different terms for components similar to those shown Figure 15 herein. For example, in some architectures, the memory hub 1505 may be referred to as the north bridge, while the I / O hub 1507 may be referred to as the south bridge.

[0141] Figure 16A A parallel processor 1600 is shown in accordance with an embodiment. The various components of the parallel processor 1600 may be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). The parallel processor 1600 shown is a variant of one or more of the parallel processors 1512 shown in Figure 15 an embodiment.

[0142] In one embodiment, the parallel processor 1600 includes a parallel processing unit 1602. The parallel processing unit includes an I / O unit 1604 that enables communication with other devices including other instances of the parallel processing unit 1602. The I / O unit 1604 may be directly connected to other devices. In one embodiment, the I / O unit 1604 is connected to other devices via a hub or switch interface such as a memory hub 1505. The connection between the memory hub 1505 and the I / O unit 1604 forms a communication link 1513. Within the parallel processing unit 1602, the I / O unit 1604 is connected to a host interface 1606 and a memory crossbar 1616, where the host interface 1606 receives commands for performing processing operations and the memory crossbar 1616 receives commands for performing memory operations.

[0143] When the host interface 1606 receives a command buffer via the I / O unit 1604, the host interface 1606 may direct the work operations for executing those commands to a front end 1608. In one embodiment, the front end 1608 is coupled to a scheduler 1610 configured to distribute commands or other work items to an array of processing clusters 1612. In one embodiment, the scheduler 1610 ensures that the array of processing clusters 1612 is properly configured and in an active state before tasks are distributed to the processing clusters of the array of processing clusters 1612. In one embodiment, the scheduler 1610 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 1610 can be configured to perform complex scheduling and work distribution operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the processing array 1612. In one embodiment, host software may attest to a workload for scheduling on the processing array 1612 via one of a plurality of graphics processing doorbells. The workload can then be automatically distributed across the processing array 1612 by the scheduler 1610 logic within the scheduler microcontroller.

[0144] The processing cluster array 1612 can include up to “N” processing clusters (e.g., cluster 1614A, cluster 1614B to cluster 1614N). Each of the clusters 1614A - 1614N of the processing cluster array 1612 can execute a large number of concurrent threads. The scheduler 1610 can use various scheduling and / or work distribution algorithms to allocate work to the clusters 1614A - 1614N of the processing cluster array 1612, and these algorithms can vary according to the workload generated for each type of program or computation. Scheduling can be handled dynamically by the scheduler 1610, or can be assisted in part by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1612. In one embodiment, different clusters 1614A - 1614N of the processing cluster array 1612 can be assigned to process different types of programs or to perform different types of computations.

[0145] The processing cluster array 1612 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 1612 is configured to perform general - purpose parallel computing operations. For example, the processing cluster array 1612 can include logic for performing processing tasks, including filtering of video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0146] In one embodiment, the processing cluster array 1612 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 1600 is configured to perform graphics processing operations, the processing cluster array 1612 can include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, tessellation logic, and other vertex processing logic. Additionally, the processing cluster array 1612 can be configured to execute graphics - processing - related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 1602 can transfer data from the system memory via the I / O unit 1604 for processing. During processing, the transferred data can be stored in on - chip memory (e.g., parallel processor memory 1622) during processing and then written back to the system memory.

[0147] In one embodiment, when the parallel processing unit 1602 is used to perform graphics processing, the scheduler 1610 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 1614A through 1614N of the processing cluster array 1612. In some embodiments, portions of the processing cluster array 1612 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. Intermediate data generated by one or more of the clusters 1614A - 1614N can be stored in a buffer to allow the intermediate data to be transferred between the clusters 1614A - 1614N for further processing.

[0148] During operation, the processing cluster array 1612 can receive processing tasks to be executed via the scheduler 1610, which receives commands defining the processing tasks from the front end 1608. For graphics processing operations, the processing tasks can include indices of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data), as well as status parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 1610 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 1608. The front end 1608 can be configured to ensure that the processing cluster array 1612 is configured in a valid state before initiating the workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0149] Each instance of one or more instances of the parallel processing unit 1602 can be coupled to the parallel processor memory 1622. The parallel processor memory 1622 can be accessed via a memory crossbar 1616, which can receive memory requests from the array of processing clusters 1612 as well as the I / O unit 1604. The memory crossbar 1616 can access the parallel processor memory 1622 via a memory interface 1618. The memory interface 1618 can include a plurality of partitioning units (e.g., partitioning unit 1620A, partitioning unit 1620B to partitioning unit 1620N), each of which can be coupled to a portion (e.g., a memory unit) of the parallel processor memory 1622. In one implementation, the number of partitioning units 1620A - 1620N is configured to be equal to the number of memory units, such that the first partitioning unit 1620A has a corresponding first memory unit 1624A, the second partitioning unit 1620B has a corresponding memory unit 1624B, and the Nth partitioning unit 1620N has a corresponding Nth memory unit 1624N. In other embodiments, the number of partitioning units 1620A - 1620N may not be equal to the number of memory devices.

[0150] In various embodiments, the memory units 1624A - 1624N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 1624A - 1624N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 1624A - 1624N can vary and can be selected from one of various conventional designs. Rendering targets such as frame buffers or texture maps can be stored across the memory units 1624A - 1624N, allowing the partitioning units 1620A - 1620N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 1622. In some embodiments, local instances of the parallel processor memory 1622 can be excluded in favor of a unified memory design that utilizes system memory in conjunction with a local cache.

[0151] In one embodiment, any one of clusters 1614A - 1614N in processing cluster array 1612 is capable of processing data to be written to any of memory cells 1624A - 1624N within parallel processor memory 1622. Memory crossbar 1616 is configurable to pass the output of each cluster 1614A - 1614N to any partition unit 1620A - 1620N or to another cluster 1614A - 1614N, and the other cluster 1614A - 1614N may perform additional processing operations on the output. Each cluster 1614A - 1614N may communicate through memory crossbar 1616 with memory interface 1618 to read from or write to various external memory devices. In one embodiment, memory crossbar 1616 has connections to memory interface 1618 to communicate with I / O unit 1604 and has connections to a local instance of parallel processor memory 1622 such that processing units within different processing clusters 1614A - 1614N can communicate with system memory or other memory not local to parallel processing unit 1602. In one embodiment, memory crossbar 1616 is capable of using virtual channels to separate traffic flows between clusters 1614A - 1614N and partition units 1620A - 1620N.

[0152] Although a single instance of parallel processing unit 1602 is shown within parallel processor 1600, any number of instances of parallel processing unit 1602 may be included. For example, multiple instances of parallel processing unit 1602 may be provided on a single plug - in card, or multiple plug - in cards may be interconnected. Different instances of parallel processing unit 1602 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in one embodiment, some instances of parallel processing unit 1602 may include higher - precision floating - point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 1602 or parallel processor 1600 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0153] Figure 16B is a block diagram of partition unit 1620 according to an embodiment. In one embodiment, partition unit 1620 is Figure 16AAn example of one of the partition units 1620A - 1620N. As shown, the partition unit 1620 includes an L2 cache 1621, a frame buffer interface 1625, and a ROP 1626 (raster operation unit). The L2 cache 1621 is a read / write cache configured to perform load and store operations received from the memory crossbar 1616 and the ROP 1626. Read misses and urgent write-back requests are output by the L2 cache 1621 to the frame buffer interface 1625 for processing. Updates can also be sent via the frame buffer interface 1625 to the frame buffer for processing. In one embodiment, the frame buffer interface 1625 interfaces with one of the memory units in the parallel processor memory, such as the memory units 1624A - 1624N of FIG. 16 (e.g., within the parallel processor memory 1622).

[0154] In a graphics application, the ROP 1626 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. The ROP 1626 then outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 1626 includes compression logic to compress depth or color data written to the memory and decompress depth or color data read from the memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 1626 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0155] In some embodiments, the ROP 1626 is included within each processing cluster (e.g., clusters 1614A - 1614N of FIG. 16) rather than within the partition unit 1620. In such embodiments, read and write requests for pixel data are transmitted through the memory crossbar 1616 rather than pixel fragment data. The processed graphics data can be displayed on a display device (such as Figure 15 one of the one or more display devices 1510), routed for further processing by one or more processors 1502, or routed for further processing by Figure 16A one of the processing entities within the parallel processor 1600.

[0156] Figure 16CIt is a block diagram of a processing cluster 1614 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 1614A - 1614N in FIG. 16. The processing cluster 1614 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In some embodiments, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster in the processing cluster. Different from the SIMD execution mechanism, where all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0157] The operation of the processing cluster 1614 can be controlled via a pipeline manager 1632 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 1632 receives instructions from the scheduler 1610 in FIG. 16 and manages the execution of those instructions via the graphics multiprocessor 1634 and / or the texture unit 1636. The illustrated graphics multiprocessor 1634 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 1614. One or more instances of the graphics multiprocessor 1634 can be included within the processing cluster 1614. The graphics multiprocessor 1634 can process data, and a data crossbar 1640 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). The pipeline manager 1632 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 1640.

[0158] Each graphics multiprocessor 1634 within the processing cluster 1614 can include the same set of functional execution logic (e.g., arithmetic logic units, load - store units, etc.). The functional execution logic can be configured in a pipeline manner where new instructions can be issued before the completion of previous instructions. The functional execution logic supports various operations, including integer and floating - point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In one embodiment, the same functional unit hardware can be utilized to perform different operations, and any combination of functional units can exist.

[0159] Instructions sent to processing cluster 1614 constitute a thread. A set of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group may be assigned to a different processing engine within graphics multiprocessor 1634. A thread group may include fewer threads than the number of processing engines within graphics multiprocessor 1634. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle of processing the thread group. A thread group may also include more threads than the number of processing engines within graphics multiprocessor 1634. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 1634, processing may be performed on consecutive clock cycles. In one embodiment, multiple thread groups may execute concurrently on graphics multiprocessor 1634.

[0160] In one embodiment, graphics multiprocessor 1634 includes an internal cache memory to perform load and store operations. In one embodiment, graphics multiprocessor 1634 may forego the internal cache and use the cache memory (e.g., L1 cache 308) within processing cluster 1614. Each graphics multiprocessor 1634 may also access an L2 cache within a partitioning unit (e.g., partitioning units 1620A - 1620N of FIG. 16), the L2 cache being shared among all processing clusters 1614 and available for passing data between threads. Graphics multiprocessor 1634 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 1602 may be used as global memory. Embodiments in which processing cluster 1614 includes multiple instances of graphics multiprocessor 1634 may share common instructions and data that may be stored in L1 cache 1708.

[0161] Each processing cluster 1614 may include an MMU 1645 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 1645 may reside within memory interface 1618 of FIG. 16. MMU 1645 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more discussion of tiling) and an optional cache line index. MMU 1645 may include a cache or translation lookaside buffer (TLB) that may reside within graphics multiprocessor 1634 or L1 cache or processing cluster 1614. Physical addresses are processed to distribute surface data access locality to allow for efficient request interleaving between partitioning units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0162] In graphics and computing applications, the processing cluster 1614 can be configured such that each graphics multiprocessor 1634 is coupled to a texture unit 1636 to perform texture mapping operations, e.g., determining texture sample locations, reading texture data, and filtering texture data. The texture data is read from an internal texture L1 cache (not shown), or in some embodiments from an L1 cache within the graphics multiprocessor 1634, and is fetched from the L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 1634 outputs the processed tasks to the data crossbar 1640 to provide the processed tasks to another processing cluster 1614 for further processing, or stores the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 1616. The preROP 1642 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1634 and direct the data to the ROP units, which may be located together with partitioning units (e.g., the partitioning units 1620A - 1620N of FIG. 16) as described herein. The preROP 1642 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0163] It will be appreciated that the core architectures described herein are illustrative and that variations and modifications are possible. Any number of processing units, such as graphics multiprocessors 1634, texture units 1636, preROP 1642, etc., may be included within the processing cluster 1614. Additionally, although only one processing cluster 1614 is shown, the parallel processing units as described herein may include any number of instances of the processing cluster 1614. In one embodiment, each processing cluster 1614 may be configured to operate independently of other processing clusters 1614 using separate and distinct processing units, L1 caches, etc.

[0164] Figure 16D A graphics multiprocessor 1634 is shown according to one embodiment. In such embodiments, the graphics multiprocessor 1634 is coupled to the pipeline manager 1632 of the processing cluster 1614. The graphics multiprocessor 1634 has an execution pipeline that includes, but is not limited to, an instruction cache 1652, an instruction unit 1654, an address mapping unit 1656, a register file 1658, one or more general-purpose graphics processing unit (GPGPU) cores 1662, and one or more load / store units 1666. The GPGPU cores 1662 and the load / store units 1666 are coupled to the cache memory 1672 and the shared memory 1670 via a memory and cache interconnect 1668.

[0165] In one embodiment, the instruction cache 1652 receives a stream of instructions to be executed from the pipeline manager 1632. The instructions are cached in the instruction cache 1652 and dispatched for execution by the instruction unit 1654. The instruction unit 1654 may dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 1662. Instructions can access any one of the local, shared, or global address spaces by specifying an address within a unified address space. The address mapping unit 1656 can be used to translate an address in the unified address space into a different memory address accessible by the load / store unit 1666.

[0166] The register file 1658 provides a set of registers for the functional units of the graphics multiprocessor 1724. The register file 1658 provides temporary storage for operands on data paths connecting to the functional units (e.g., GPGPU cores 1662, load / store unit 1666) of the graphics multiprocessor 1724. In one embodiment, the register file 1658 is partitioned among each of the functional units in the functional unit such that each functional unit is assigned a dedicated portion of the register file 1658. In one embodiment, the register file 1658 is partitioned among different warps executed by the graphics multiprocessor 1724.

[0167] The GPGPU cores 1662 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1724. According to embodiments, the GPGPU cores 1662 may be architecturally similar or may be architecturally different. For example, in one embodiment, a first portion of the GPGPU core 1662 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 1724 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blend operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0168] In one embodiment, the GPGPU core 1662 includes SIMD logic capable of executing a single instruction on multiple data sets. In one embodiment, the GPGPU core 1662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0169] The memory and cache interconnect 1668 is an interconnect network that connects each functional unit in the graphics multiprocessor 1724 to the register file 1658 and the shared memory 1670. In one embodiment, the memory and cache interconnect 1668 is a crossbar interconnect that allows the load / store unit 1666 to implement load and store operations between the shared memory 1670 and the register file 1658. The register file 1658 is capable of operating at the same frequency as the GPGPU core 1662, so the data transfer between the GPGPU core 1662 and the register file 1658 has a very low latency. The shared memory 1670 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 1634. The cache memory 1672 can be used as a data cache, for example, to cache texture data transferred between the functional units and the texture unit 1636. The shared memory 1670 can also be used as a program-managed cache. In addition to the automatically cached data stored in the cache memory 1672, threads executing on the GPGPU core 1662 are also able to programmatically store data in the shared memory.

[0170] Figure 17A - 17B Additional graphics multiprocessors according to embodiments are shown. The shown graphics multiprocessors 1725, 1750 are Figure 16C variations of the graphics multiprocessor 1634. The shown graphics multiprocessors 1725, 1750 can be configured as stream multiprocessors (SMs) capable of simultaneously executing a large number of execution threads.

[0171] Figure 17A A graphics multiprocessor 1725 according to an additional embodiment is shown. The graphics multiprocessor 1725 includes with respect to Figure 16DMultiple additional instances of the execution resource units of the graphics multiprocessor 1634. For example, the graphics multiprocessor 1725 may include multiple instances of instruction units 1732A - 1732B, register files 1734A - 1734B, and (one or more) texture units 1744A - 1744B. The graphics multiprocessor 1725 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 1736A - 1736B, GPGPU cores 1737A - 1737B, GPGPU cores 1738A - 1738B) and multiple sets of load / store units 1740A - 1740B. In one embodiment, the execution resource units have a common instruction cache 1730, a texture and / or data cache 1742, and a shared memory 1746.

[0172] The various components may communicate via an interconnect fabric 1727. In one embodiment, the interconnect fabric 1727 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 1725. In one embodiment, the interconnect fabric 1727 is a separate high - speed network fabric layer on which each component of the graphics multiprocessor 1725 is stacked. The components of the graphics multiprocessor 1725 communicate with remote components via the interconnect fabric 1727. For example, the GPGPU cores 1736A - 1736B, 1737A - 1737B, and 1738A - 1738B may each communicate with the shared memory 1746 via the interconnect fabric 1727. The interconnect fabric 1727 may arbitrate communication within the graphics multiprocessor 1725 to ensure fair bandwidth allocation between components.

[0173] Figure 17B Illustrates a graphics multiprocessor 1750 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 1756A - 1756D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load - store units, as Figure 16D and Figure 17A shown. The execution resources 1756A - 1756D may work in conjunction with (one or more) texture units 1760A - 1760D for texture operations while sharing an instruction cache 1754 and a shared memory 1762. In one embodiment, the execution resources 1756A - 1756D may share the instruction cache 1754 and the shared memory 1762, as well as multiple instances of texture and / or data caches 1758A - 1758B. The various components may communicate via an interconnect fabric 1752 similar to the Figure 17A interconnect fabric 1727.

[0174] Those skilled in the art will understand that Figure 15 、 16AThe architectures described in -16D and 17A-17B are descriptive and not limiting of the scope of this embodiment. Thus, the techniques described herein may be implemented on any suitably configured processing unit without departing from the scope of the embodiments described herein, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as the parallel processing unit 1602 of FIG. 16), and one or more graphics processors or specialized processing units.

[0175] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or die as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or die). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses specialized circuitry / logic to efficiently process these commands / instructions.

[0176] Techniques for GPU - to - Host Processor Interconnect

[0177] Figure 18A An exemplary architecture is shown in which multiple GPUs 1810-1813 are communicatively coupled to multiple multi-core processors 1805-1806 via high-speed links 1840-1843 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 1840-1843 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0178] Additionally, in one embodiment, two or more of the GPUs 1810 - 1813 are interconnected by high - speed links 1844 - 1845, which may be implemented using the same or different protocols / links as those used for the high - speed links 1840 - 1843. Similarly, two or more of the multi - core processors 1805 - 1806 may be connected by a high - speed link 1833, which can be a symmetric multi - processor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 18A All communication between the various system components shown in Figure 18A can be implemented using the same protocol / link (e.g., via a common interconnect fabric). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0179] In one embodiment, each multi - core processor 1805 - 1806 is communicatively coupled to a processor memory 1801 - 1802 via a memory interconnect 1830 - 1831 respectively, and each GPU 1810 - 1813 is communicatively coupled to a GPU memory 1820 - 1823 via a GPU memory interconnect 1850 - 1853 respectively. The memory interconnects 1830 - 1831 and 1850 - 1853 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 1801 - 1802 and the GPU memories 1820 - 1823 can be volatile memories such as dynamic random - access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high - bandwidth memory (HBM), and / or can be non - volatile memories such as 3D XPoint or Nano - Ram. In one embodiment, some portions of the memory can be volatile memory and another portion can be non - volatile memory (e.g., using a two - level memory (2LM) hierarchy).

[0180] As described below, although the various processors 1805 - 1806 and GPUs 1810 - 1813 may be physically coupled to specific memories 1801 - 1802, 1820 - 1823 respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as the “effective address” space) is distributed across all of the various physical memories. For example, each of the processor memories 1801 - 1802 may include 64GB of system memory address space, and each of the GPU memories 1820 - 1823 may include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0181] Figure 18B Additional details of the interconnect between the multi-core processor 1807 and the graphics acceleration module 1846 according to one embodiment are shown. The graphics acceleration module 1846 can include one or more GPU chips integrated on a line card that is coupled to the processor 1807 via a high-speed link 1840. Alternatively, the graphics acceleration module 1846 can be integrated on the same package or chip as the processor 1807.

[0182] The illustrated processor 1807 includes multiple cores 1860A - 1860D, each having a translation lookaside buffer 1861A - 1861D and one or more caches 1862A - 1862D. The cores can include various other components for executing instructions and processing data (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.), which are not shown to avoid obscuring the basic principles of the present invention. The caches 1862A - 1862D can include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1826 can be included in the cache hierarchy and shared by a set of cores 1860A - 1860D. For example, one embodiment of the processor 1807 includes 24 cores (each having its own L1 cache), twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 1807 and the graphics accelerator integrated module 1846 are connected to the system memory 1841, which can include processor memories 1801 - 1802.

[0183] Data and instructions stored in the respective caches 1862A - 1862D, 1856, and the system memory 1841 are kept consistent via inter-core communication on the coherence bus 1864. For example, each cache can have cache coherence logic / circuit associated therewith to communicate via the coherence bus 1864 in response to detected reads or writes to a particular cache line. In one implementation, a cache snooping protocol is implemented on the coherence bus 1864 to snoop cache accesses. Cache snooping / coherence techniques are well known to those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0184] In one embodiment, the proxy circuit 1825 communicatively couples the graphics acceleration module 1846 to the coherence bus 1864, allowing the graphics acceleration module 1846 to participate in the cache coherence protocol as a peer of the cores. In particular, the interface 1835 provides connectivity to the proxy circuit 1825 via a high-speed link 1840 (e.g., a PCIe bus, NVLink, etc.), and the interface 1837 connects the graphics acceleration module 1846 to the link 1840.

[0185] In one implementation, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1831, 1832, N of the graphics acceleration module 1846. The graphics processing engines 1831, 1832, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1831, 1832, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 1831 - 1832, N, or the graphics processing engines 1831 - 1832, N may be separate GPUs integrated on a common package, line card, or chip.

[0186] In one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 that performs various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing the system memory 1841. The MMU 1839 may also include a translation lookaside buffer (TLB) (not shown) that caches virtual / effective-to-physical / real address translations. In one implementation, the cache 1838 stores commands and data for efficient access by the graphics processing engines 1831, 1832, N. In one embodiment, the data stored in the cache 1838 and the graphics memories 1833 - 1834, N remains coherent with the core caches 1862A - 1862D, 1856 and the system memory 1811. As mentioned, this can be achieved via the proxy circuit 1825, which participates in the cache coherence mechanism on behalf of the cache 1838 and the memories 1833 - 1834, N (e.g., sending updates related to cache line modifications / accesses on the processor caches 1862A - 1862D, 1856 to the cache 1838 and receiving updates from the cache 1838).

[0187] The set of registers 1845 stores context data of threads executed by the graphics processing engines 1831-1832, N, and the context management circuit 1848 manages the thread contexts. For example, the context management circuit 1848 can perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored such that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1848 can store the current register values into a specified area in memory (e.g., identified by a context pointer). Then, when returning to the context, it can restore the register values. In one embodiment, the interrupt management circuit 1847 receives and processes interrupts received from system devices.

[0188] In one implementation, the virtual / valid addresses from the graphics processing engine 1831 are converted by the MMU 1839 into real / physical addresses in the system memory 1811. One embodiment of the accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. The graphics accelerator module 1846 can be dedicated to a single application executed on the processor 1807 or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1831-1832, N are shared among multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0189] Thus, the accelerator integrated circuit acts as a bridge from the graphics accelerator module 1846 to the system and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 1836 can provide virtualization tools for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0190] Since the hardware resources of the graphics processing engines 1831-1832, N are explicitly mapped to the real address space seen by the host processor 1807, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1836 is the physical separation of the graphics processing engines 1831-1832, N such that they appear as independent units to the system.

[0191] As mentioned, in the illustrated embodiments, one or more graphics memories 1833 - 1834, M are respectively coupled to each of the graphics processing engines 1831 - 1832, N. The graphics memories 1833 - 1834, M store instructions and data processed by each of the graphics processing engines 1831 - 1832, N. The graphics memories 1833 - 1834, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6) or HBM, and / or can be non - volatile memories such as 3D XPoint or Nano - Ram.

[0192] In one embodiment, to reduce data traffic on link 1840, a biasing technique is used to ensure that the data stored in the graphics memories 1833 - 1834, M is the data that will be most frequently used by the graphics processing engines 1831 - 1832, N and preferably not used (at least not frequently) by the cores 1860A - 1860D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 1831 - 1832, N) within the caches 1862A - 1862D, 1856 of the cores and the system memory 1811.

[0193] Figure 18C Another embodiment is shown in which the accelerator integrated circuit 1836 is integrated within the processor 1807. In this embodiment, the graphics processing engines 1831 - 1832, N communicate directly to the accelerator integrated circuit 1836 over the high - speed link 1840 via interface 1837 and interface 1835 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 1836 can perform the same operations as those Figure 18B described, but potentially perform those operations with higher throughput considering its very close proximity to the coherence bus 1862 and the caches 1862A - 1862D, 1826.

[0194] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0195] In one embodiment of the dedicated process model, the graphics processing engines 1831 - 1832, N are dedicated to a single application or process under a single operating system. A single application can aggregate other application requests to the graphics engines 1831 - 1832, N, providing virtualization within a VM / partition.

[0196] In a dedicated process programming model, the graphics processing engines 1831, 1832, N can be shared by multiple VM / application partitions. The sharing model requires the hypervisor to virtualize the graphics processing engines 1831 - 1832, N to allow access by each operating system. For a single - partition system without a hypervisor, the graphics processing engines 1831 - 1832, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 1831 - 1832, N to provide access to each process or application.

[0197] For a shared programming model, the graphics acceleration module 1846 or a separate graphics processing engine 1831 - 1832, N uses a process handle to select a process element. In one embodiment, the process element is stored in the system memory 1811 and can be addressed using the effective - address - to - real - address translation techniques described herein. The process handle can be an implementation - specific value provided to the host process when it registers its context with the graphics processing engine 1831 - 1832, N (i.e., calls system software to add the process element to the process - element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process - element linked list.

[0198] Figure 18D An exemplary accelerator integration slice 1890 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1836. The application effective - address space 1882 within the system memory 1811 stores the process element 1883. In one embodiment, the process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on the processor 1807. The process element 1883 contains the process state of the corresponding application 1880. The work descriptor (WD) 1884 contained within the process element 1883 can be a single job requested by the application or can contain a pointer to a job queue. In the latter case, the WD 1884 is a pointer to the job - request queue within the application's address space 1882.

[0199] The graphics acceleration module 1846 and / or the individual graphics processing engines 1831 - 1832, N can be shared by all or a subset of the processes in the system. Embodiments of the present invention include an infrastructure for setting the process state and sending the WD 1884 to the graphics acceleration module 1846 to initiate a job in a virtualized environment.

[0200] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1846 or a separate graphics processing engine 1831. Since the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1836 for the owning partition, and the operating system initializes the accelerator integrated circuit 1836 for the owning process when the graphics acceleration module 1846 is assigned.

[0201] In operation, the WD fetch unit 1891 in the accelerator integration slice 1890 fetches the next WD 1884, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 1846. The data from the WD 1884 can be stored in the register 1845 and used by the MMU 1839, the interrupt management circuit 1847, and / or the context management circuit 1846, as shown. For example, one embodiment of the MMU 1839 includes a segment / page walk circuitry for accessing the segment / page table 1886 within the OS virtual address space 1885. The interrupt management circuit 1847 can handle the interrupt event 1892 received from the graphics acceleration module 1846. When performing a graphics operation, the effective address 1893 generated by the graphics processing engines 1831 - 1832, N is translated to a real address by the MMU 1839.

[0202] In one embodiment, the same set of registers 1845 is replicated for each graphics processing engine 1831 - 1832, N and / or the graphics acceleration module 1846, and can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integration slice 1890. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0203] Table 1 - Registers Initialized by the Hypervisor

[0204] 1 Slice Control Register 2 Process Region Pointer Scheduled by Real Address (RA) 3 Permission Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0205] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0206] Table 2 - Registers Initialized by the Operating System

[0207]

[0208]

[0209] In one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engines 1831 - 1832, N. It contains all the information required for the graphics processing engines 1831 - 1832, N to do their work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0210] Figure 18E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor physical address space 1898 in which a list of process elements 1899 is stored. The hypervisor real address space 1898 can be accessed via the hypervisor 1896 of the graphics acceleration module engine for the operating system 1895 for virtualization.

[0211] The shared programming model allows all or a subset of the processes from all or a subset of the partitions in the system to use the graphics acceleration module 1846. There are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions: time - sliced sharing and graphics - directed sharing.

[0212] In this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. To enable the graphics acceleration module 1846 to support virtualization by the hypervisor 1896, the graphics acceleration module 1846 may comply with the following requirements: 1) The job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context save and restore mechanism. 2) The job requests of the application are guaranteed by the graphics acceleration module 1846 to be completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1846 provides the ability to handle preempted jobs. 3) When operating in the directed - sharing programming model, fairness between processes must be guaranteed for the graphics acceleration module 1846.

[0213] In one embodiment, for a shared model, application 1880 is required to make an operating system 1895 system call with a graphics acceleration module 1846 type, a work descriptor (WD), a privilege mask register (AMR) value, and a context save / restore area pointer (CSRP). The graphics acceleration module 1846 type describes the target acceleration function for the system call. The graphics acceleration module 1846 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 1846 and can take the form of a graphics acceleration module 1846 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1846. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 1836 and the graphics acceleration module 1846 implementation do not support the user privilege mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1896 can optionally apply the current privilege mask override register (AMOR) value before placing the AMR in the process unit 1883. In one embodiment, the CSRP is one of the registers 1845 that contains the valid address of the area in the application's address space 1882 for the graphics acceleration module 1846 to save and restore the context state. This pointer is optional if state saving is not required between jobs or when a job is preempted. The context save / restore area can be fixed system memory.

[0214] Upon receiving the system call, the operating system 1895 can verify that the application 1880 is registered and has been granted permission to use the graphics acceleration module 1846. Then, the operating system 1895 calls the hypervisor 1896 with the information shown in Table 3.

[0215] Table 3 - OS to Hypervisor Call Parameters

[0216]

[0217] Upon receiving the hypervisor call, the hypervisor 1896 verifies that the operating system 1895 is registered and has been granted permission to use the graphics acceleration module 1846. Then, the hypervisor 1896 places the process element 1883 into the process element linked list corresponding to the graphics acceleration module 1846 type. The process element can include the information shown in Table 4.

[0218] Table 4 - Process Element Information

[0219]

[0220] In one embodiment, the hypervisor initializes a plurality of accelerator integrated slice 1890 registers 1845.

[0221] As Figure 18F shown, one embodiment of the present invention employs unified memory addressable via a common virtual memory address space for accessing physical processor memories 1801 - 1802 and GPU memories 1820 - 1823. In such an implementation, operations executed on GPUs 1810 - 1813 utilize the same virtual / effective memory address space to access processor memories 1801 - 1802, and vice versa, thus simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801, a second portion is allocated to second processor memory 1802, a third portion is allocated to GPU memory 1820, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1801 - 1802 and GPU memories 1820 - 1823, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0222] In one embodiment, bias / coherency management circuits 1894A - 1894E within one or more of the MMUs 1839A - 1839E ensure cache coherency between the caches of the host processor (e.g., 1805) and GPUs 1810 - 1813, and implement a biasing technique that indicates the physical memory in which certain types of data should be stored. Although multiple instances of the bias / coherency management circuits 1894A - 1894E are shown Figure 18F in, the bias / coherency circuits may be implemented within the MMU of one or more host processors 1805 and / or within the accelerator integrated circuit 1836.

[0223] One embodiment allows the GPU - attached memories 1820 - 1823 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques without suffering the typical performance penalties associated with full - system cache coherence. The ability to access the GPU - attached memories 1820 - 1823 as system memory without the heavy cache - coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 1805 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU - attached memories 1820 - 1823 without cache - coherence overhead can be critical to the execution time of offloaded computations. For example, in the case of a large number of streaming write - to - memory transactions, the cache - coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1810 - 1813. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0224] In one implementation, the choice between GPU bias and host - processor bias is driven by a bias - tracker data structure. For example, a bias table can be used, which can be a page - granularity structure (i.e., controlled at the granularity of memory pages) that includes 1 or 2 bits per GPU - attached memory page. The bias table can be implemented in the stolen - memory ranges of one or more GPU - attached memories 1820 - 1823, with or without a bias cache in the GPUs 1810 - 1813 (e.g., to cache frequently / most - recently - used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0225] In one implementation, accessing the bias - table entry associated with each access to the GPU - attached memories 1820 - 1823 before actually accessing the GPU memory results in the following operations. First, local requests from the GPUs 1810 - 1813 for pages that are in GPU bias are directly forwarded to the corresponding GPU memories 1820 - 1823. Local requests from the GPUs for pages that are in host bias are forwarded to the processor 1805 (e.g., via the high - speed link as discussed above). In one embodiment, requests from the processor 1805 for pages that are in host - processor bias complete requests similar to normal memory reads. Alternatively, requests for pages in GPU bias can be forwarded to the GPUs 1810 - 1813. If the GPU is not currently using the page, the GPU can then transfer the page to host - processor bias.

[0226] The bias state of a page can be changed by software-based mechanisms, hardware-assisted software-based mechanisms, or, for a limited set of cases, by hardware-only mechanisms.

[0227] One mechanism for changing the bias state employs an API call (such as OpenCL), which in turn calls the device driver of the GPU. The device driver of the GPU then sends a message (or queues a command descriptor) to the GPU, instructing the GPU to change the bias state, and for some transitions, performs a cache dump flush operation in the host. The transition from host processor 1805 bias to GPU bias requires a cache dump flush operation, but the reverse transition does not.

[0228] In one embodiment, cache coherence is maintained by temporarily rendering pages with GPU bias that are not cacheable by the host processor 1805. To access these pages, the processor 1805 may request access from the GPU 1810, which may or may not immediately grant access, depending on the implementation. Thus, to reduce communication between the processor 1805 and the GPU 1810, it is beneficial to ensure that the pages with GPU bias are the pages required by the GPU rather than the host processor 1805, and vice versa.

[0229] Graphics Processing Pipeline

[0230] Figure 19 Illustrates a graphics processing pipeline 1900 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 1900. The graphics processor may be included within a parallel processing subsystem as described herein (such as the parallel processor 1600 of FIG. 16), which in one embodiment is Figure 15Variations of the (one or more) parallel processors 1512. Various parallel processing systems can implement the graphics processing pipeline 1900 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 1602 of FIG. 16) as described herein. For example, a shader unit (e.g., the graphics multiprocessor 1634 of FIG. 17) can be configured to perform the functions of one or more of the vertex processing unit 1904, the tessellation control processing unit 1908, the tessellation evaluation processing unit 1912, the geometry processing unit 1916, and the fragment / pixel processing unit 1924. The functions of the data assembler 1902, the primitive assembler 1906, 1914, 1918, the tessellation unit 1910, the rasterizer 1922, and the raster operation unit 1926 can also be performed by a processing cluster (e.g., the processing cluster 1614 of FIG. 17) and other processing engines within the corresponding partitioning unit (e.g., the partitioning units 220A - 220N of FIG. 16). The graphics processing pipeline 1900 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 1900 can be executed by parallel processing logic within a general - purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 1900 can access on - chip memory (e.g., the parallel processor memory 1622 as in FIG. 16) via a memory interface 1928, which can be an instance of the memory interface 1618 of FIG. 16.

[0231] In one embodiment, the data assembler 1902 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 1902 then outputs the vertex data including vertex attributes to the vertex processing unit 1904. The vertex processing unit 1904 is a programmable execution unit that executes a vertex shader program that lights and transforms the vertex data as specified by the vertex shader program. The vertex processing unit 1904 reads data stored in a cache, local, or system memory for use in processing the vertex data and can be programmed to transform the vertex data from an object - based coordinate representation to a world - space coordinate space or a normalized device coordinate space.

[0232] A first instance of the primitive assembler 1906 receives vertex attributes from the vertex processing unit 1904. The primitive assembler 1906 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 1908. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0233] The tessellation control processing unit 1908 treats the input vertices as control points of a geometric patch. The control points are transformed from an input representation (e.g., the basis of the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 1912. The tessellation control processing unit 1908 may also compute the tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the level of view-dependent detail associated with the edge. The tessellation unit 1910 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch surface into a plurality of geometric primitives (such as line, triangle, or quadrilateral primitives), which are transmitted to the tessellation evaluation processing unit 1912. The tessellation evaluation processing unit 1912 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitives.

[0234] A second instance of the primitive assembler 1914 receives vertex attributes from the tessellation evaluation processing unit 1912, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 1916. The geometry processing unit 1916 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 1914 as specified by the geometry shader program. In one embodiment, the geometry processing unit 1916 is programmed to subdivide the graphics primitives into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0235] In some embodiments, the geometry processing unit 1916 is capable of adding or deleting elements in the geometry stream. The geometry processing unit 1916 outputs the parameters and vertices specifying the new graphics primitives to the primitive assembler 1918. The primitive assembler 1918 receives the parameters and vertices from the geometry processing unit 1916 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 1920. The geometry processing unit 1916 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scale, cull, and clip unit 1920 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 1922.

[0236] The rasterizer 1922 can perform depth culling and other depth-based optimizations. The rasterizer 1922 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 1924. The fragment / pixel processing unit 1924 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. The fragment / pixel processing unit 1924 transforms the fragments or pixels received from the rasterizer 1922 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 1924 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to the raster operations unit 1926. The fragment / pixel processing unit 1924 can read data stored in the parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at the sample, pixel, patch, or other granularity depending on the sampling rate configured for the processing unit.

[0237] The raster operations unit 1926 is a processing unit that performs raster operations including but not limited to stencil, z-test, blending, etc., and outputs pixel data as processed graphics data to be stored in the graphics memory (e.g., the parallel processor memory 1622 as shown in FIG. 16 and / or the system memory 1504 as shown in Figure 15 ), for display on one or more display devices 1510 or for further processing by one of the one or more processors 1502 or the parallel processor 1512. In some embodiments, the raster operations unit 1926 can be configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0238] Devices and methods for feature point tracking using inter-frame prediction

[0239] Feature point tracking is a technique used in many video processing and graphics fields such as structure from motion (SFM) and panoramic processing (e.g., for virtual reality implementations). The first step in any implementation is camera calibration, which uses feature point tracking to determine the extrinsic parameters of the camera, which is a complex problem.

[0240] Feature point tracking and matching techniques are required to detect feature points from each image or video stream frame. Then, the feature points are matched between image pairs. For each pair of images, an approximate nearest neighbor method can be used to match the key point descriptors between the pair of images. Figure 20An exemplary set of points mapped from a first image frame 2001 to a second image frame 2002 is shown, as indicated by lines connecting the points from the two image frames. Instead of encoding the entire second frame, vectors can be used to specify the movement of pixels or pixel sets from the first image frame 2001 to the second image frame 2002.

[0241] Decoder inter-frame prediction is a widely used technique for compressing video streams. Previous decoded frames or sets of frames are used to derive prediction values for the current frame. Modern compressed video bitstream formats such as VP9 use inter-frame prediction techniques. An inter-frame includes a plurality of inter-frame blocks, each of the inter-frame blocks containing a motion vector that includes an offset of a specified portion of a previous frame, which is used as a prediction for the current frame. Figure 21 Examples are shown that show blocks of different sizes and corresponding vector / offset data indicating the movement of the blocks between frames.

[0242] One embodiment of the present invention applies decoder inter-frame prediction techniques to track feature points across different images in an image sequence. Using these techniques, the search range for point comparison and matching is significantly reduced. Since the size of an inter-frame block is typically much smaller than the entire frame, these techniques can be used to reduce the computational complexity of the feature point tracking problem.

[0243] In traditional matching methods, it is assumed that each feature point detected in frame 0 is to be compared with each feature point from frame 1. Although high-performance matrix multiplication can optimize this problem, the computational complexity is still high.

[0244] If the input data of a video stream is evaluated, then inter-frame techniques provide a way to simplify the feature point matching problem. For example, as Figure 22 shown, when frame 2201 is an inter-frame, it is intended to transfer block b0 from reference frame 2200 to block b1 in the current frame 1 according to the associated motion vector. One embodiment of the present invention recognizes that any feature points in b0 are also transferred to b1. Using this inter-frame and motion vector data, key points between two inter-frames are not compared with each other one by one. Instead, key point pairs only appear in pairs of inter-frame blocks between inter-frames.

[0245] The size of an inter-frame block is significantly smaller than the size of the entire frame. Using VP9 as an example, the size of an inter-frame block ranges from 4×4 to 64×64 pixels. Given the significant size difference between a frame and an inter-frame block, the search for feature point pairs is greatly simplified.

[0246] Compared with traditional feature point tracking mechanisms, an embodiment of the present invention projects key point candidates from the current frame to the reference frame through motion vectors, then finds its n nearest points in its relative inter-frame block in the reference frame, and only calculates its distances from these n nearest points. In one embodiment, the "distance" is a descriptor distance. Scale-invariant feature transform (SIFT) feature points have feature vectors of 128-bit length, which may include values of multiple features. Therefore, the "distance" between two points includes the differences between these feature vectors.

[0247] Figure 23 An embodiment of an apparatus implementing these techniques for a current frame 2301 using a reference frame 2300 and associated motion data 2305 (e.g., inter-frame block vectors) is shown. Figure 23 The components shown in may be implemented in circuitry, software, or any combination thereof. In one implementation, the shown components are integrated within a GPU such as Figure 8 the graphics processor 800 in (e.g., in a video decoder unit within the GPU). In one embodiment, some components are implemented within a media pipeline 830, and some components are implemented using software executed on execution logic 850. However, the basic principles of the present invention are not limited to any particular architectural arrangement.

[0248] A key point extractor 2310 extracts key points from the current frame 2301 and the reference frame 2300. The reference frame key points may have been extracted in previous iterations. A point projector 2320 uses the motion data 2305 to project a point p from the current frame 2301 to a point p' in the reference frame 2300 using the motion vectors of the associated inter-frame blocks 2302A - B.

[0249] Then, a neighbor identifier 2330 identifies the n nearest feature points of p' (e.g., p1 - p5), and a point filter 2340 discards any points among these points that are not on the same inter-frame block 2302A. A distance calculator determines the descriptor distances between the unfiltered points and p'. In one embodiment, a comparator 2360 selects the point 2370 having the shortest descriptor distance from the point p'. A threshold 2375 may also be used such that the comparator 2360 determines whether each point is within a defined threshold distance 2375 to identify the matching point 2370.

[0250] Figure 24 A method according to one embodiment is shown. The method may be executed on the system / processor architectures described herein, but is not limited to any particular system / processor architecture.

[0251] At 2400 and 2401, key points are respectively extracted from frames f0 and f1. At 2402, the motion vector associated with the inter-frame block of point p is used to project point p into frame f0 as p'. As mentioned, this motion vector can be extracted from the encoded video stream. At 2403, five nearest feature points p1 - p5 of p' are identified in frame f0. Although five feature points are used in this embodiment, various different numbers can be used while still conforming to the basic principles of the present invention.

[0252] At 2404, any points not in the corresponding inter-frame block (i.e., the same inter-frame block as p') are discarded. At 2405, the descriptor distances between p' and one or more of p1 - p5 (those points not discarded at 2404) are calculated. At 2406, the points that meet the specified distance threshold are identified, and at 2407, the points are identified as matches. As mentioned, in one embodiment, the matching point 2407 is the point closest to p'. In this embodiment, the threshold is set to the current nearest distance between p' and one of p1 - p5. If a closer distance is measured later, then this distance replaces the threshold. Finally, at 2407, the nearest point is identified.

[0253] The simulation of this embodiment provides the following results demonstrating the effectiveness and performance of these techniques. Scale-invariant feature transform (SIFT) is used as the key point detection method. The runtime environment is MATLAB, and VP9 is used as the video bitstream format, where the first 100 frames are extracted from the video bitstream.

[0254] After performing the SIFT key point detection method and traditional matching processing on 100 frames, 29751 point pairs are found in the sequence of frame pairs. Figure 25 An example showing the point pairs that match between the current frame 2501 and its reference frame 2502 is presented. Significantly, 27462 pairs (92.3%) out of the entire set of 29751 pairs are in the corresponding inter-frame blocks matched by the motion vector.

[0255] When implementing the embodiment of the present invention, for the first frame pair (frame 1 and frame 2), 1270 and 1226 key point candidates are respectively found, and 306 pairs are matched. The traditional technique takes 0.118786 seconds to match, while the embodiment of the present invention only takes 0.015110 seconds. Table A below shows the data for the first 10 pairs of frames with an average acceleration of 9.37.

[0256]

[0257] Table A

[0258] To simplify the simulation, all frames starting from the second frame are considered inter-frame frames, and non-inter-frame blocks are discarded. In practice, traditional matching techniques can be performed on the points in those non-inter-frame frames and non-inter-frame blocks to achieve an accuracy rate greater than 92.3%.

[0259] It is also assumed that all reference frames are previous frames, which is not always the case. One embodiment of the present invention uses the same reference strategy as existing video decoders to record multiple reference frames. However, considering that most of the 100 frames in the simulation refer to previous frames, the results are robust.

[0260] To handle the miss tracking / matching problem (which means that the pair will be detected by traditional methods but not by the embodiments of the present invention), one implementation extends the search area in the reference frame outside the inter-frame block by a specified amount. In one embodiment, it is assumed that if some "point pairs" are found in a "block pair", then all relevant "point pairs" should exist. Then, the search area is extended until all point pairs are identified.

[0261] Using these techniques, an additional 460 pairs were matched in the simulation, increasing the accuracy rate to 93.9%. To implement the techniques described herein, the SIFT key point detection process and the tracking / matching method can be added to a video stream decoder (e.g., in the media processing unit of a GPU, such as an FPGA, etc.).

[0262] Embodiments of the present invention may include the various steps described above. The steps can be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps can be performed by specific hardware components that include hardwired logic for performing the steps or by any combination of programmed computer components and custom hardware components.

[0263] As described herein, the instructions can refer to: a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or having a predetermined functionality; or software instructions stored in a memory embodied on a non-transitory computer-readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer machine-readable media to store and (internally and / or over a network with other electronic devices) transfer code and data, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read-only memory; flash memory devices; phase change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.).

[0264] In addition, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connections. The coupling of the collection of processors and the other components is typically through one or more buses and bridges (also known as bus controllers). The storage device and the signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on the collection of one or more processors of the electronic device. Of course, one or more portions of embodiments of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the present invention. However, those skilled in the art will understand that the present invention may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in detail so as not to obscure the subject matter of the present invention. Accordingly, the scope and spirit of the present invention should be judged in accordance with the appended claims.

Claims

1. A method, comprising: extracting a first set of key points from a current frame and extracting a second set of key points from a reference frame; projecting a key point p into the reference frame as p' based on a motion vector associated with a region in the current frame where the key point p is found; locating n key points in the reference frame that are closest to p'; and matching one of the n key points in the reference frame to the key point p in the current frame based on a descriptor distance between each of the n key points and p'.

2. The method according to claim 1, wherein the matching comprises: Generating descriptor distances between all or a subset of the n key points and the point p', and identifying one of the n key points with the shortest descriptor distance.

3. The method according to claim 1, further comprising: discarding one or more of the n key points that are not within a specified region of the reference frame.

4. The method according to claim 3, wherein the region in the current frame comprises an inter-frame block in the current frame.

5. The method according to claim 4, wherein the specified region comprises an inter-frame block in the reference frame corresponding to the inter-frame block in the current frame.

6. The method according to claim 4, wherein the specified region comprises an inter-frame block in the reference frame corresponding to the inter-frame block in the current frame and a specified region outside the periphery of the inter-frame block in the reference frame.

7. The method according to any one of claims 1 to 6, wherein the matching includes: Generating descriptor distances between all or a subset of the n key points and the point p', and comparing each of the descriptor distances with a threshold.

8. The method according to claim 7, wherein the threshold is set to the current shortest descriptor distance between one of the n key points and the point p'.

9. The method according to any one of claims 1 to 6, further comprising: projecting the one or more additional key points into the reference frame based on a motion vector associated with a region where the one or more additional key points are found, and matching the one or more additional key points in the current frame to one or more key points in the reference frame based on the motion vector.

10. A machine-readable medium having program code stored thereon, the program code causing the machine to perform the following operations when executed by the machine: extracting a first set of key points from a current frame and extracting a second set of key points from a reference frame; projecting a key point p into the reference frame as p' based on a motion vector associated with a region in the current frame where the key point p is found; locating n key points in the reference frame that are closest to p'; and matching one of the n key points in the reference frame to the key point p in the current frame based on a descriptor distance between each of the n key points and p'.

11. The machine-readable medium according to claim 10, wherein the matching comprises: Generating descriptor distances between all or a subset of the n key points and the point p', and identifying one of the n key points with the shortest descriptor distance.

12. The machine-readable medium according to claim 10 or 11, further comprising program code for causing the machine to perform the following operations: Discard one or more key points among the n key points that are not within a specified region of the reference frame.

13. The machine-readable medium according to claim 12, wherein the region in the current frame includes an inter-frame block in the current frame.

14. The machine-readable medium according to claim 13, wherein the specified region includes an inter-frame block of the reference frame corresponding to the inter-frame block of the current frame.

15. The machine-readable medium according to claim 13, wherein the specified region includes an inter-frame block of the reference frame corresponding to the inter-frame block of the current frame and a specified region outside the periphery of the inter-frame block of the reference frame.

16. The machine-readable medium according to claim 10 or 11, wherein the matching comprises: Generate a descriptor distance between all or a subset of the n key points and point p', and compare each of the descriptor distances with a threshold.

17. The machine-readable medium according to claim 16, wherein the threshold is set to the current shortest descriptor distance between one of the n key points and point p'.

18. The machine-readable medium according to claim 10 or 11, further comprising program code for performing the following operations: project the one or more additional key points into the reference frame based on a motion vector associated with a region where the one or more additional key points are found, and match the one or more additional key points in the current frame with one or more key points in the reference frame based on the motion vector.

19. An apparatus, comprising: A key point extractor for extracting a first set of key points from a current frame and a second set of key points from a reference frame; A point projector for projecting key point p into the reference frame as p' based on a motion vector associated with a region in the current frame where key point p is found; A neighbor identifier for locating n key points in the reference frame that are closest to p'; And A key point matcher for matching one of the n key points in the reference frame to key point p in the current frame based on a descriptor distance between each of the n key points and p'.

20. The device according to claim 19, wherein the matching comprises: Generate a descriptor distance between all or a subset of the n key points and point p', and identify one key point among the n key points having the shortest descriptor distance.

21. The apparatus according to claim 19 or 20, further comprising: Discard one or more key points among the n key points that are not within a specified region of the reference frame.

22. The apparatus according to claim 21, wherein the region in the current frame includes an inter-frame block in the current frame.

23. The apparatus according to claim 22, wherein the specified region includes an inter-frame block of the reference frame corresponding to the inter-frame block of the current frame.

24. The apparatus according to claim 22, wherein the specified region includes an inter-frame block of the reference frame corresponding to the inter-frame block of the current frame and a specified region outside the periphery of the inter-frame block of the reference frame.

25. The apparatus according to claim 19 or 20, wherein the matching comprises: Generate descriptor distances between all or a subset of the n key points and the point p', and compare each of the descriptor distances with a threshold value.

26. The apparatus according to claim 25, wherein the threshold value is set to the current shortest descriptor distance between one of the n key points and the point p'.

27. The apparatus according to claim 19 or 20, further comprising: means for projecting the one or more additional key points into the reference frame based on a motion vector associated with a region in which the one or more additional key points are found, and means for matching the one or more additional key points in the current frame with one or more key points in the reference frame based on the motion vector.

28. A computer program product comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1-9.

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