Testing method, device, electronic device and computer-readable storage medium

Abstract

The present disclosure discloses a testing method, device, electronic device and computer-readable storage medium, which relate to the field of computers, and in particular to the field of chip testing technology. The specific implementation scheme is as follows: when testing the function to be tested of the tested chip, at least two target test cases are determined from the test cases corresponding to the function to be tested; based on the dependency relationship between the pre-configured target test cases, the execution order of each target test case is determined; each target test case is executed in sequence according to the test order, and the test data is determined. Based on this scheme, the operations required by the tester during the test process can be reduced, the workload during the test can be reduced, and the test efficiency of the chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of chip testing technology. Specifically, the present disclosure relates to a testing method, device, electronic device, and computer-readable storage medium. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the demand for chip computing power is increasing. This is why AI chips, specifically designed for training or inference of AI models, have emerged.

[0003] During the design and use of AI chips, it is necessary to test the various functions of the AI ​​chip. When testing the functions of AI chips, test cases are generally used.

[0004] Because different AI chip functions require different test cases, and when multiple test cases are required, the order in which they are executed also varies, testers typically write test cases for the functions they need to test and specify the order in which they should be tested. This existing approach requires testers to perform numerous operations, increasing the workload and impacting chip testing efficiency. Summary of the Invention

[0005] The purpose of the present disclosure is to solve at least one of the above-mentioned technical deficiencies and to provide a test method, device, electronic device and computer-readable storage medium with higher chip test efficiency.

[0006] According to one aspect of the present disclosure, a testing method is provided, the method comprising:

[0007] When testing a function to be tested of the chip under test, determining at least two target test cases from the test cases corresponding to the function to be tested;

[0008] Determine the execution order of each target test case based on the pre-configured dependency relationship between each target test case;

[0009] Execute each target test case in sequence according to the test order and determine the test data.

[0010] According to a second aspect of the present disclosure, a testing device is provided, the device comprising:

[0011] A target test case determination module is used to determine at least two target test cases from the test cases corresponding to the function to be tested when testing the function to be tested of the tested chip;

[0012] An execution order determination module is used to determine the execution order of each target test case based on the pre-configured dependency relationship between each target test case;

[0013] The test module is used to execute each target test case in sequence according to the test order and determine the test data.

[0014] According to a third aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the test method as shown in the first aspect of the present disclosure.

[0015] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the testing method as shown in the first aspect of the present disclosure.

[0016] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements the testing method as shown in the first aspect of the present disclosure when executed by a processor.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0019] Figure 1 is a flow chart of a testing method provided by an embodiment of the present disclosure;

[0020] Figure 2 is a flow chart of another testing method provided by an embodiment of the present disclosure;

[0021] Figure 3 is a flow chart of another testing method provided by an embodiment of the present disclosure;

[0022] Figure 4 is a structural diagram of a test system provided by an embodiment of the present disclosure;

[0023] Figure 5 This is a flow chart of a specific implementation of the testing method provided in the embodiment of the present disclosure;

[0024] Figure 6 is a structural diagram of a testing device provided by an embodiment of the present disclosure;

[0025] Figure 7 is a structural diagram of another testing device provided by an embodiment of the present disclosure;

[0026] Figure 8 is a structural diagram of another testing device provided by an embodiment of the present disclosure;

[0027] Figure 9 It is a block diagram of an electronic device used to implement the testing method provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0029] Figure 1 A flow chart of a test method provided by an embodiment of the present disclosure is shown. The method provided by an embodiment of the present disclosure can be applied to a test system, such as Figure 1 As shown, the method may mainly include:

[0030] Step S110: when testing the function to be tested of the chip under test, at least two target test cases are determined from the test cases corresponding to the function to be tested.

[0031] The chips under test may include, but are not limited to, AI chips. Functions to be tested may include, but are not limited to, chip stability, chip computing power, chip power consumption, inference model performance, and training model performance.

[0032] Since the test cases required for testing various test functions may not be the same, in the embodiment of the present disclosure, test cases can be pre-configured for various test functions, so that when the function to be tested is tested, the target test case for testing the function to be tested of the tested chip can be determined from the test cases corresponding to the function to be tested, without the need for the tester to write the test case according to the function to be tested, which can reduce the workload of the tester.

[0033] In actual use, a test case set can be pre-configured, which includes test cases corresponding to various test functions. When testing, the user can select a function to be tested, and the test system can determine the test case corresponding to the function to be tested from the test case set.

[0034] Step S120: determining the execution order of each target test case based on the pre-configured dependency relationship between each target test case.

[0035] In actual use, some target test cases may depend on the execution results of other target test cases when they are executed. Therefore, the dependency relationship between the target test cases can be configured to determine the execution order of the target test cases based on the dependency relationship.

[0036] In the embodiment of the present disclosure, since the execution order of the target test cases can be determined based on the dependency relationship, there is no need for the tester to specify the execution order based on actual business experience, which reduces the requirements for the tester's business experience and also reduces the workload during testing.

[0037] Step S130: Execute each target test case in sequence according to the test order and determine the test data.

[0038] After determining the execution order of the target test cases, each target test case can be executed in sequence according to the test order and test data can be collected. The test data can be used to obtain the test results of the function to be tested.

[0039] The testing method disclosed herein determines at least two target test cases from the test cases corresponding to the function to be tested on the chip under test. Based on preconfigured dependencies between the target test cases, the execution order of the target test cases is determined, thereby executing the target test cases in sequence according to the test order and determining the test data. This approach can reduce the number of operations required by testers during the testing process, lowering the workload and improving chip testing efficiency.

[0040] Figure 2 FIG. 1 shows a flow chart of another testing method provided by an embodiment of the present disclosure, such as Figure 2 As shown, the method may mainly include:

[0041] Step S210: when testing the function to be tested of the chip under test, determining at least two target test cases from the test cases corresponding to the function to be tested.

[0042] The chips under test may include, but are not limited to, AI chips. Functions to be tested may include, but are not limited to, chip stability, chip computing power, chip power consumption, inference model performance, and training model performance.

[0043] Since the test cases required for testing various test functions may not be the same, in the embodiment of the present disclosure, test cases can be pre-configured for various test functions, so that when the function to be tested is tested, the target test case for testing the function to be tested of the tested chip can be determined from the test cases corresponding to the function to be tested, without the need for the tester to write the test case according to the function to be tested, which can reduce the workload of the tester.

[0044] In actual use, a test case set can be pre-configured, which includes test cases corresponding to various test functions. When testing, the user can select a function to be tested, and the test system can determine the test case corresponding to the function to be tested from the test case set.

[0045] Step S220: Determine the initial order of each target test case based on the pre-configured dependency relationship between each target test case.

[0046] Step S230: Based on whether the user's adjustment instruction for the initial sequence is obtained and based on the initial sequence, the execution order of each target test case is determined.

[0047] In actual use, some target test cases may depend on the execution results of other target test cases when they are executed. Therefore, the dependency relationship between the target test cases can be configured to determine the execution order of the target test cases based on the dependency relationship.

[0048] In the embodiment of the present disclosure, since the execution order of the target test cases can be determined based on the dependency relationship, there is no need for the tester to specify the execution order based on actual business experience, which reduces the requirements for the tester's business experience and the workload during testing.

[0049] In the disclosed embodiments, the initial order of target test cases can be determined based on dependency relationships. For example, the dependency relationship between target test case a, target test case b, and target test case c is: target test case b depends on target test case a, and target test case a depends on target test case c. Therefore, the initial order can be determined as: target test case c, target test case a, target test case b.

[0050] In actual use, the initial execution order may not meet the actual needs, and the user may need to adjust the initial order. At this time, the user can submit an adjustment instruction for the initial order. The test system can determine the execution order of each target test case based on whether it obtains the user's adjustment instruction for the initial order and the initial order.

[0051] As an optional method, based on whether the user's adjustment instruction for the initial order is obtained and based on the initial order, the execution order of each target test case is determined, including:

[0052] If the user's adjustment instruction for the initial sequence is obtained, the initial sequence is adjusted based on the adjustment instruction to obtain the execution order of each target test case;

[0053] If no user instruction to adjust the initial sequence is obtained, the initial sequence is determined as the execution sequence of each target test case.

[0054] In the disclosed embodiment, the user can adjust the initial sequence according to actual needs to obtain the execution sequence. Specifically, if a user adjustment instruction for the initial sequence is detected, the initial sequence can be adjusted based on the adjustment instruction to obtain the execution sequence; if no user adjustment instruction for the initial sequence is detected, it can be assumed that the initial sequence can meet the actual testing requirements and the initial sequence can be determined as the execution sequence.

[0055] Since the initial sequence can be adjusted according to whether the user has submitted an adjustment instruction, when the initial sequence cannot meet the test requirements, the initial sequence can be adjusted through the adjustment instruction so that the execution sequence obtained after adjustment can meet the test requirements.

[0056] As an optional method, obtain the user's adjustment instructions for the initial sequence, including:

[0057] The display objects corresponding to each target test case are displayed to the user through the execution order adjustment interface, and each display object is arranged in the initial order;

[0058] When a user drag operation on the displayed objects is detected, an adjustment instruction of the user on the initial order is determined based on the drag operation.

[0059] In an embodiment of the present disclosure, an execution order adjustment interface may be displayed to the user, and the execution order adjustment interface may include display objects corresponding to each target test case.

[0060] As an example, the display object may be in the form of a box, and the identifier of the target test case may be displayed in the box.

[0061] The display objects may be arranged in an initial order. As an example, the initial order of the target test cases may be indicated by directional arrows.

[0062] The user can drag the display objects to adjust the order of the display objects, such as dragging one or more display objects to a suitable position so that the arrangement order of the display objects after dragging conforms to the execution order.

[0063] Since an execution order adjustment interface is provided, each display object is arranged in the initial order and displayed, so that the user can understand the initial execution order more intuitively, and supports submitting adjustment instructions by dragging the display objects, making the user's operation easier and more convenient for users.

[0064] Step S240: Execute each target test case in sequence according to the test order and determine the test data.

[0065] After determining the execution order of the target test cases, each target test case can be executed in sequence according to the test order and test data can be collected. The test data can be used to obtain the test results of the function to be tested.

[0066] The testing method disclosed herein determines at least two target test cases from the test cases corresponding to the function to be tested on the chip under test. Based on preconfigured dependencies between the target test cases, the execution order of the target test cases is determined, thereby executing the target test cases in sequence according to the test order and determining the test data. This approach can reduce the number of operations required by testers during the testing process, lowering the workload and improving chip testing efficiency.

[0067] Figure 3 A flow chart of another testing method provided by an embodiment of the present disclosure is shown. Figure 3 As shown, the method may mainly include:

[0068] Step S310: When testing the function to be tested of the chip under test, a test case selection interface is displayed to the user. The test case selection interface includes virtual buttons for each test case corresponding to the function to be tested and relevant information of each test case.

[0069] Step S320: When a click operation of the user on the virtual button is detected, the user's selection instruction for the target test user is obtained.

[0070] The chips under test may include, but are not limited to, AI chips. Functions to be tested may include, but are not limited to, chip stability, chip computing power, chip power consumption, inference model performance, and training model performance.

[0071] The test case selection interface displays the virtual button corresponding to each test case and the relevant information of each test case, wherein the relevant information may include the description information of the test case and the error rate, etc. The error rate can be obtained through historical data statistics.

[0072] Displaying relevant information about test cases helps users select target test cases from the test cases corresponding to the function to be tested. Users can submit the selection instruction by clicking the virtual button corresponding to the target test case, thereby determining the target test case, which also facilitates the user's test case selection.

[0073] Step S330: determining at least two target test cases for testing the function to be tested from the test cases based on the selection instruction.

[0074] Since the test cases required for testing various test functions may not be the same, in the embodiment of the present disclosure, test cases can be pre-configured for various test functions, so that when the function to be tested is tested, the target test case for testing the function to be tested of the tested chip can be determined from the test cases corresponding to the function to be tested, without the need for the tester to write the test case according to the function to be tested, which can reduce the workload of the tester.

[0075] In actual use, a test case set can be pre-configured, which includes test cases corresponding to various test functions. When testing, the user can select a function to be tested, and the test system can determine the test case corresponding to the function to be tested from the test case set.

[0076] Step S340: Determine the execution order of each target test case based on the pre-configured dependency relationship between each target test case.

[0077] In actual use, some target test cases may depend on the execution results of other target test cases when they are executed. Therefore, the dependency relationship between the target test cases can be configured to determine the execution order of the target test cases based on the dependency relationship.

[0078] In the embodiment of the present disclosure, since the execution order of the target test cases can be determined based on the dependency relationship, there is no need for the tester to specify the execution order based on actual business experience, which reduces the requirements for the tester's business experience and also reduces the workload during testing.

[0079] Step S350: Execute each target test case in sequence according to the test order and determine the test data.

[0080] After determining the execution order of the target test cases, each target test case can be executed in sequence according to the test order and test data can be collected. The test data can be used to obtain the test results of the function to be tested.

[0081] The testing method disclosed herein determines at least two target test cases from the test cases corresponding to the function to be tested on the chip under test. Based on preconfigured dependencies between the target test cases, the execution order of the target test cases is determined, thereby executing the target test cases in sequence according to the test order and determining the test data. This approach can reduce the number of operations required by testers during the testing process, lowering the workload and improving chip testing efficiency.

[0082] As an optional method, if the function to be tested is chip stability, the above method further includes:

[0083] Obtain target flow curve;

[0084] The data flow into the chip under test during the execution of each target test case is controlled based on the target flow curve.

[0085] Currently, when testing the chip stability of a chip under test, the data flow flowing into the chip under test is generally specified as a constant value, and the chip stability test is performed under this constant flow pressure. However, in actual use, the flow pressure of the chip may change at different time periods. Therefore, the existing chip stability testing method cannot be close to the actual situation, and the test effect is relatively general.

[0086] In the embodiment of the present disclosure, a target flow curve can be provided to control the data flow into the chip under test during the test period to simulate the actual flow pressure situation, thereby improving the test effect of the chip stability.

[0087] As an example, the horizontal axis of the target flow curve may be the time points within the test period, and the vertical axis may be the flow values.

[0088] As an optional method, obtain the target flow curve, including any of the following:

[0089] determining a user-selected target flow curve from a set of preconfigured flow curves;

[0090] Based on the user's drawing operation in the flow curve drawing interface, a target flow curve is determined.

[0091] In the embodiment of the present disclosure, multiple flow curves may be pre-configured to form a flow curve set, so that the user can select a target flow curve from them.

[0092] As an example, the preconfigured flow curve may be a sine curve, a cosine curve, etc.

[0093] In actual use, the pre-configured flow curves can be displayed so that users can intuitively understand the changes in each flow curve and make accurate choices, which helps to improve the accuracy of the test.

[0094] In an embodiment of the present disclosure, a flow curve drawing interface may be provided, so that a target flow curve may be determined according to a user's drawing operation in the flow curve drawing interface.

[0095] Since a flow curve drawing interface is provided to the user, it is convenient for the user to draw a flow curve, thereby enabling the user to conveniently control the flow within the test period by drawing the flow curve.

[0096] As an optional manner, if obtaining the target flow curve includes determining the target flow curve based on a drawing operation performed by a user in a flow curve drawing interface, determining the target flow curve based on the drawing operation performed by the user in the flow curve drawing interface includes:

[0097] When detecting a user's drawing operation using a virtual brush in the flow curve drawing interface, obtaining the handwriting of the virtual brush in the flow curve drawing interface;

[0098] Determine the target flow curve based on the handwriting.

[0099] The flow curve drawing interface may include a virtual brush, and the user may drag the virtual brush to draw in a blank coordinate axis, thereby obtaining handwriting drawn by the virtual brush and determining a target flow curve based on the virtual handwriting.

[0100] By allowing the user to drag a virtual brush to draw handwriting and determining a target flow curve based on the handwriting, it is convenient for the user to draw the target flow curve.

[0101] As an optional method, execute the target test cases, including:

[0102] The chip under test is called through the test interface corresponding to the function to be tested to execute the target test case.

[0103] The test interface may be an interface configured according to the test requirements of the function to be tested, and is used to access the chip to be tested during testing to execute the test case and obtain test data.

[0104] Since the requirements of each function to be tested are different, such as the parameters and data indicators required during the test, the test interface can be configured according to the test requirements of the function to be tested. For example, the parameters or data indicators required by the function to be tested can be implemented in the test interface. This allows the test interface corresponding to the function to be tested to directly access the chip under test and complete the test when testing the function to be tested, without the need for adaptation processing for the access of the chip under test.

[0105] Specifically, a test case can include multiple test steps, some of which may require the chip under test to execute specific test steps, such as initialization steps and some specific functional test steps. When the test system needs to execute these specific test steps during the test case execution, it can call the chip under test through the test interface to complete the execution of these specific test steps.

[0106] In an embodiment of the present application, the above method can be applied to a test system. When the test system executes a test case, it can call the chip to be tested to execute the above specified test steps through a test interface corresponding to the function to be tested.

[0107] As an optional method, the test data includes interface collection data, and the test data is determined to include:

[0108] The interface collection data of the tested chip during the test process is collected based on the data monitoring interface corresponding to the function to be tested.

[0109] In the disclosed embodiment, the test data may include data collected by the test system framework (such as timestamps, execution time of the test interface, etc.), and interface collection data collected by the data monitoring interface (such as status data of the tested chip, etc.).

[0110] Specifically, different functions to be tested may require different types of interface data collection and different data collection methods. Therefore, a data monitoring interface can be configured for each function to be tested, so that data collection of the interface data required by the function to be tested can be achieved through the data monitoring interface.

[0111] In the disclosed embodiment, the chip under test generates corresponding test data in the test case, and the test data can be collected conveniently through the data monitoring interface corresponding to the function to be tested.

[0112] Figure 4 Schematic diagram of the structure of a test system provided by an embodiment of the present disclosure is shown in FIG.

[0113] like Figure 4As shown in , the test system includes: a core subsystem, a task management subsystem, a monitoring subsystem and a data processing subsystem.

[0114] (1) Core subsystem, including hardware adaptation framework, standard test interface, test case collection, and case extension framework. The hardware adaptation framework provides an adaptation interface for AI chips. The standard test interface is used for data interaction between the core subsystem and the task management subsystem. The test case collection includes test cases used in different functional tests. The case extension framework is for test case developers and is used to develop new test cases.

[0115] The training model performance case plug-in, inference model performance case plug-in, chip function case plug-in, chip stability case plug-in, chip power consumption case plug-in, and chip computing power case plug-in are test cases that may be used in different functional tests.

[0116] (2) The task management subsystem is a system that can be directly operated by users, including: task launch, UI interface or command line, background management, test report and other modules. Among them, the task launch module is used to generate tasks and launch tasks according to the distribution strategy (such as linear distribution, Poisson distribution, etc.), calling the standard test interface. The UI interface or command line is the interface that users directly operate. The background management module can include functions such as user management, test case management, task progress management, and test record management. The test report is used to display the test results.

[0117] (3) The monitoring subsystem is used to monitor the status data of the AI ​​chip and the status data of the test process, including sampling of various indicators. The monitoring reporting module is used to package and organize the sampled data and report it to the data processing subsystem.

[0118] The sampling of various indicators may include power consumption sampling, usage sampling, and temperature sampling.

[0119] (4) Data processing subsystem, which is used to process the test result data and present it to the customer in a standardized form. The test result data processing includes data persistence, data cleaning and data analysis.

[0120] The test system provided in this example is adaptable to a variety of AI chips, compatible with multiple functional tests, and aligned with evaluation metrics, enabling better testing and evaluation of AI chips. This test system is not only suitable for functional and performance testing of AI chip products on the customer side, but also for product delivery evaluation and quality assessment by AI chip R&D and factories.

[0121] Figure 5A flow chart of a specific implementation of the testing method provided in an embodiment of the present disclosure is shown in FIG. Figure 5 The test method shown in Figure 4 The test system implementation shown in .

[0122] like Figure 5 As shown in , the test method includes:

[0123] System initialization and case configuration are to initialize the test system and select the target test case for the current test.

[0124] Task initialization and task startup, that is, generating test tasks according to target test cases and starting the test tasks.

[0125] When the task reaches the core subsystem, the test task is sent to the core subsystem for execution.

[0126] Execute cases in the order in which they are configured, i.e. the core subsystem executes each target test case in sequence according to the order in which the test cases are executed;

[0127] Calling the AI ​​chip interface means calling the chip under test to execute the test steps through the test interface when executing the specified test steps.

[0128] Generate test data, that is, collect test data generated during the execution of test cases.

[0129] Data persistence and data analysis, that is, persisting test data and analyzing test data.

[0130] Generate a test report and present it to the user, that is, generate a test report based on the test data for the user to review.

[0131] Based on Figure 1 The same principle as shown in the method, Figure 6 A schematic diagram of the structure of a testing device provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown in FIG, the testing device 60 may include:

[0132] The target test case determination module 610 is configured to determine at least two target test cases from the test cases corresponding to the function to be tested when testing the function to be tested of the chip under test;

[0133] An execution order determination module 620 is configured to determine the execution order of each target test case based on pre-configured dependencies between the target test cases;

[0134] The test module 630 is used to execute each target test case in sequence according to the test sequence and determine the test data.

[0135] The apparatus provided by the disclosed embodiments determines at least two target test cases from the test cases corresponding to the function to be tested when testing the function to be tested of the chip under test, and determines the execution order of each target test case based on the preconfigured dependencies between the target test cases, thereby executing each target test case in sequence according to the test order and determining test data. Based on this solution, the operations required of the tester during the test process can be reduced, the workload during testing can be lowered, and the chip testing efficiency can be improved.

[0136] It is understandable that the above modules of the test device in the embodiment of the present disclosure have the function of realizing Figure 1 The functions of the corresponding steps of the test method in the embodiment shown in . This function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. The above modules can be software and / or hardware, and the above modules can be implemented separately or integrated with multiple modules. For the functional description of each module of the above test device, please refer to Figure 1 The corresponding description of the test method in the embodiment shown in is not repeated here.

[0137] Based on Figure 2 The same principle as shown in the method, Figure 7 FIG. 1 shows a schematic structural diagram of another testing device provided by an embodiment of the present disclosure, such as Figure 7 As shown in FIG, the testing device 70 may include:

[0138] The target test case determination module 710 is configured to determine at least two target test cases from the test cases corresponding to the function to be tested when testing the function to be tested of the chip under test;

[0139] The initial sequence determination module 720 is configured to determine the initial sequence of each target test case based on the pre-configured dependency relationship between each target test case.

[0140] The execution sequence adjustment module 730 is configured to determine the execution sequence of each target test case based on whether an adjustment instruction to the initial sequence from the user is obtained and based on the initial sequence.

[0141] The test module 740 is used to execute each target test case in sequence according to the test sequence and determine the test data.

[0142] The apparatus provided by the disclosed embodiments determines at least two target test cases from the test cases corresponding to the function to be tested when testing the function to be tested of the chip under test, and determines the execution order of each target test case based on the preconfigured dependencies between the target test cases, thereby executing each target test case in sequence according to the test order and determining test data. Based on this solution, the operations required of the tester during the test process can be reduced, the workload during testing can be lowered, and the chip testing efficiency can be improved.

[0143] In actual use, the initial execution order may not meet actual needs, and the user may need to adjust the initial order. In this case, the user can submit an adjustment instruction for the initial order, and the execution order of each target test case can be determined based on whether the user's adjustment instruction for the initial order is obtained and the initial order.

[0144] As an optional method, the execution order adjustment module is specifically used to:

[0145] If the user's adjustment instruction for the initial sequence is obtained, the initial sequence is adjusted based on the adjustment instruction to obtain the execution order of each target test case;

[0146] If no user instruction to adjust the initial sequence is obtained, the initial sequence is determined as the execution sequence of each target test case.

[0147] Since the initial sequence can be adjusted according to whether the user has submitted an adjustment instruction, when the initial sequence cannot meet the test requirements, the initial sequence can be adjusted through the adjustment instruction so that the execution sequence obtained after adjustment can meet the test requirements.

[0148] As an optional method, when the execution sequence adjustment module obtains the user's instruction to adjust the initial sequence, it is specifically used to:

[0149] The display objects corresponding to each target test case are displayed to the user through the execution order adjustment interface, and each display object is arranged in the initial order;

[0150] When a user drag operation on the displayed objects is detected, an adjustment instruction of the user on the initial order is determined based on the drag operation.

[0151] Since an execution order adjustment interface is provided, each display object is arranged in the initial order and displayed, so that the user can understand the initial execution order more intuitively, and supports submitting adjustment instructions by dragging the display objects, making the user's operation easier and more convenient for users.

[0152] It is understandable that the above modules of the test device in the embodiment of the present disclosure have the function of realizing Figure 2The functions of the corresponding steps of the test method in the embodiment shown in . This function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. The above modules can be software and / or hardware, and the above modules can be implemented separately or integrated with multiple modules. For the functional description of each module of the above test device, please refer to Figure 2 The corresponding description of the test method in the embodiment shown in is not repeated here.

[0153] Based on Figure 3 The same principle as shown in the method, Figure 8 A structural diagram of another testing device provided by an embodiment of the present disclosure is shown. Figure 8 As shown in FIG, the testing device 80 may include:

[0154] The test case display module 810 is used to display a test case selection interface to the user when testing the function to be tested of the tested chip. The test case selection interface includes virtual buttons for each test case corresponding to the function to be tested and relevant information of each test case.

[0155] The selection instruction acquisition module 820 is used to acquire the user's selection instruction for the target test user when detecting the user's click operation on the virtual button.

[0156] The target test case selection module 830 is configured to determine at least two target test cases for testing the function to be tested from the test cases based on the selection instruction.

[0157] An execution order determination module 840 is used to determine the execution order of each target test case based on the pre-configured dependency relationship between each target test case;

[0158] The test module 850 is used to execute each target test case in sequence according to the test sequence and determine the test data.

[0159] The test device provided by the present disclosure determines at least two target test cases from the test cases corresponding to the function to be tested on the chip under test, and determines the execution order of each target test case based on the preconfigured dependencies between the target test cases. This method sequentially executes each target test case according to the test order and determines test data. This solution can reduce the number of operations required by testers during the test process, lower the workload during testing, and improve chip testing efficiency.

[0160] Displaying relevant information about test cases helps users select target test cases from the test cases corresponding to the function to be tested. Users can submit the selection instruction by clicking the virtual button corresponding to the target test case, thereby determining the target test case, which also facilitates the user's test case selection.

[0161] As an optional manner, if the function to be tested is chip stability, the above-mentioned device further includes a test flow control module, and the test flow control module is used to:

[0162] Obtain target flow curve;

[0163] The data flow into the chip under test during the execution of each target test case is controlled based on the target flow curve.

[0164] By providing a target flow curve to control the data flow into the chip under test during the test period, the real flow pressure situation can be simulated, thereby improving the test effect of chip stability.

[0165] As an optional method, the test flow control module is used for any of the following when obtaining the target flow curve:

[0166] determining a user-selected target flow curve from a set of preconfigured flow curves;

[0167] Based on the user's drawing operation in the flow curve drawing interface, a target flow curve is determined.

[0168] Among them, the pre-configured flow curves are displayed, allowing users to intuitively understand the changes in each flow curve and make accurate choices, which helps to improve the accuracy of the test.

[0169] Provide users with a flow curve drawing interface to facilitate users to draw flow curves, so that users can conveniently control the flow during the test period by drawing flow curves.

[0170] As an optional manner, if the test flow control module is specifically configured to determine the target flow curve based on a drawing operation performed by a user in a flow curve drawing interface when obtaining the target flow curve, then the test flow control module is specifically configured to:

[0171] When detecting a user's drawing operation using a virtual brush in the flow curve drawing interface, obtaining the handwriting of the virtual brush in the flow curve drawing interface;

[0172] Determine the target flow curve based on the handwriting.

[0173] By allowing the user to drag a virtual brush to draw handwriting and determining a target flow curve based on the handwriting, it is convenient for the user to draw the target flow curve.

[0174] As an optional method, the test module is used to execute the target test case:

[0175] The chip under test is called through the test interface corresponding to the function to be tested to execute the target test case.

[0176] By configuring the test interface according to the test requirements of the function to be tested, when testing the function to be tested, the test interface corresponding to the function to be tested can be directly called to access the chip under test and complete the test without the need for adaptation processing for the access of the chip under test.

[0177] As an optional method, the test data includes interface collection data. When determining the test data, the test module is specifically used to:

[0178] The interface collection data of the tested chip during the test process is collected based on the data monitoring interface corresponding to the function to be tested.

[0179] Therefore, the data monitoring interface can be configured according to the allocation of the function to be tested, so as to realize the data collection of the interface collection data required by the function to be tested through the data monitoring interface.

[0180] It is understandable that the above modules of the test device in the embodiment of the present disclosure have the function of realizing Figure 3 The functions of the corresponding steps of the test method in the embodiment shown in . This function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. The above modules can be software and / or hardware, and the above modules can be implemented separately or integrated with multiple modules. For the functional description of each module of the above test device, please refer to Figure 3 The corresponding description of the test method in the embodiment shown in is not repeated here.

[0181] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0182] The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the test method provided in the embodiment of the present disclosure.

[0183] Compared to existing technologies, this electronic device, when testing the function to be tested of the chip under test, determines at least two target test cases from the test cases corresponding to the function to be tested, and determines the execution order of each target test case based on the preconfigured dependencies between the target test cases. This allows each target test case to be executed sequentially according to the test order and determine the test data. This solution can reduce the number of operations required by testers during the testing process, lower the workload during testing, and improve chip testing efficiency.

[0184] The readable storage medium is a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the testing method provided by the embodiment of the present disclosure.

[0185] Compared to existing technologies, this readable storage medium determines at least two target test cases from the test cases corresponding to the function to be tested when testing the function to be tested of the chip under test. Based on the preconfigured dependencies between the target test cases, the execution order of the target test cases is determined, thereby executing the target test cases in sequence according to the test order and determining the test data. Based on this solution, the operations required of the tester during the test process can be reduced, the workload during testing can be reduced, and the chip testing efficiency can be improved.

[0186] The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the testing method as shown in the first aspect of the present disclosure.

[0187] Compared to existing technologies, this computer program product determines at least two target test cases from the test cases corresponding to the function under test when testing the function under test of the chip under test. Based on preconfigured dependencies between the target test cases, the program determines the execution order of the target test cases, thereby executing the target test cases in sequence according to the test order and determining test data. This solution can reduce the number of operations required by testers during the testing process, lower the workload during testing, and improve chip testing efficiency.

[0188] Figure 9 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0189] like Figure 9 As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. Various programs and data required for the operation of the device 900 can also be stored in the RAM 903. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0190] Various components in the device 900 are connected to the I / O interface 905, including an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a magnetic disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0191] The computing unit 901 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the test method provided in the embodiments of the present disclosure. For example, in some embodiments, the test method provided in the embodiments of the present disclosure can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the test method provided in the embodiments of the present disclosure can be performed. Alternatively, in other embodiments, the computing unit 901 can be configured to perform the test method provided in the embodiments of the present disclosure by any other appropriate means (e.g., by means of firmware).

[0192] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0193] The program code for implementing the test methods provided herein can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program code is executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0194] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0195] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0196] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0197] Computer systems may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The client and server relationship arises through computer programs running on the respective computers and having a client-server relationship to each other.

[0198] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0199] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A testing method comprising: When testing chip stability of the tested chip, determining at least two target test cases from test cases corresponding to the chip stability; Determining an initial order of the target test cases based on preconfigured dependencies between the target test cases; Displaying the display objects corresponding to each target test case to the user through an execution order adjustment interface, wherein each display object is arranged according to the initial order; When a drag operation of the user on the display object is detected, determining an adjustment instruction of the user on the initial order based on the drag operation; Adjusting the initial sequence based on the adjustment instruction to obtain an execution sequence of each target test case; The target test case is executed by calling the chip to be tested in sequence through the test interface corresponding to the chip stability in accordance with the execution order, and the data flow flowing into the chip to be tested when executing each target test case is controlled based on the target flow curve, and the interface collection data of the chip to be tested during the test process is collected based on the data monitoring interface corresponding to the chip stability; wherein, the horizontal axis of the target flow curve is the time point within the test period, and the vertical axis is the flow value, the test interface corresponding to the chip stability is an interface configured according to the parameters or data indicators required by the chip stability, and the data monitoring interface corresponding to the chip stability is a data monitoring interface configured for the chip stability.

2. The method according to claim 1, wherein The method further comprises: If no user instruction to adjust the initial sequence is obtained, the initial sequence is determined as the execution sequence of each target test case.

3. The method according to claim 1, wherein The determining, from the test cases corresponding to the chip stability, at least two target test cases for testing the chip stability includes: Displaying a test case selection interface to the user, wherein the test case selection interface includes virtual buttons for each test case corresponding to the chip stability and relevant information of each test case; When detecting a click operation of the user on the virtual button, obtaining a selection instruction of the user for a target test user; At least two target test cases for testing the chip stability are determined from the test cases based on the selection instruction.

4. The method according to any one of claims 1 to 3, wherein The method further comprises: Get the target flow curve.

5. The method according to claim 4, wherein The obtaining of the target flow curve includes any of the following: determining a user-selected target flow curve from a set of preconfigured flow curves; Based on the user's drawing operation in the flow curve drawing interface, a target flow curve is determined.

6. The method according to claim 5, wherein: If obtaining the target flow curve includes determining the target flow curve based on a drawing operation performed by a user in a flow curve drawing interface, determining the target flow curve based on the drawing operation performed by the user in the flow curve drawing interface includes: When detecting a user's drawing operation using a virtual brush in the flow curve drawing interface, obtaining the handwriting of the virtual brush in the flow curve drawing interface; A target flow curve is determined based on the handwriting.

7. A testing device comprising: a target test case determination module, configured to determine at least two target test cases from test cases corresponding to the chip stability when testing the chip stability of the tested chip; An execution order determination module, configured to determine an initial order of each of the target test cases based on pre-configured dependencies between the target test cases; Displaying display objects corresponding to each target test case to the user through an execution order adjustment interface, with each display object arranged according to the initial order; when detecting a drag operation of the user on the display object, determining a user adjustment instruction for the initial order based on the drag operation; adjusting the initial order based on the adjustment instruction to obtain an execution order for each target test case; A test module is used to call the tested chip in sequence through the test interface corresponding to the chip stability to execute the target test case in accordance with the execution order, and control the data flow flowing into the tested chip when executing each target test case based on the target flow curve, and collect the interface collection data of the tested chip during the test process based on the data monitoring interface corresponding to the chip stability; wherein the horizontal axis of the target flow curve is the time point within the test period, and the vertical axis is the flow value, the test interface corresponding to the chip stability is an interface configured according to the parameters or data indicators required by the chip stability, and the data monitoring interface corresponding to the chip stability is a data monitoring interface configured for the chip stability.

8. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 6.

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