A universal asynchronous receiver-transmitter and a processor including the same

Abstract

The present invention discloses a data transmitter, comprising an output shift register and a control unit. The output shift register stores transmission data to be serially outputted at a baud rate; and the control unit is coupled to the output shift register, determines a time period suitable for outputting the transmission data according to the operating frequency baud rate of the transmitter, and instructs the output shift register to serially output the transmission data in the determined time period. The time period is closest to the time point of outputting the data at the baud rate. The present invention also discloses a corresponding data receiver and a universal asynchronous receiver-transmitter including the data transmitter and the receiver.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to a universal asynchronous receiver-transmitter in a processor. Background Art

[0002] With the rapid development of the Internet of Things, more and more IoT devices have emerged, and embedded devices are usually used in these devices for data processing. Due to the environment in which these devices are located, they usually have high requirements for power consumption. Therefore, embedded devices usually divide the working mode into a high-power mode (working mode) for normal operation and a low-power mode (idle mode) for idle state, and switch between these two modes according to the working state to reduce power consumption.

[0003] Embedded devices use universal asynchronous receiver-transmitter (UART) to communicate with peripheral devices that support serial communication. In traditional UART, a fixed value V (i.e., the ratio of the working clock frequency to the baud rate) is calculated according to the working clock frequency of the embedded device and the baud rate configured by the UART. The UART samples the serial input signal every V working clock cycles, or sends out the serial signal every V working clock cycles. Since embedded devices generally use UART to communicate with peripheral devices in normal working mode, and the working clock frequency of embedded devices in working mode is much higher than the serial baud rate, the deviation of the sampling time point / transmission time point determined by the ratio V can be ignored.

[0004] When the embedded device is in idle mode, all clocks except the real-time clock RTC are turned off. Therefore, in idle mode, in order to be able to communicate serially with peripheral devices through UART, the RTC clock is usually used as the working clock.

[0005] However, since the baud rate of serial transmission by the UART and the clock frequency of the RTC are relatively close, the accumulated time deviation using the existing solution (ie, the solution using the ratio V) may result in sampling / sending erroneous level values.

[0006] One existing solution is to return the embedded device to normal working mode when the UART is needed for serial communication in idle mode, which significantly increases temporary power consumption. Another solution is to provide a dedicated low-frequency working clock for the UART, which increases additional circuit cost.

[0007] Therefore, a new UART sampling and transmission scheme is needed, which can overcome the defects in the prior art scheme and still accurately perform data sampling / transmission when the baud rate and the working clock are close. Summary of the invention

[0008] To this end, the present invention provides a new universal asynchronous receiver-transmitter, processor and system on chip, in an effort to solve or at least alleviate at least one of the above problems.

[0009] According to one aspect of the present invention, a data transmitter is provided, comprising an output shift register and a control unit. The output shift register stores transmission data to be serially output at a baud rate; and the control unit is coupled to the output shift register, determines a time period suitable for outputting the transmission data according to the operating frequency baud rate of the transmitter, and instructs the output shift register to serially output the transmission data in the determined time period. The time period is closest to the time point of outputting the data at the baud rate.

[0010] Optionally, in the data transmitter according to the present invention, the time period is a time period defined by a periodic signal, the periodic signal sequentially includes a rising edge, a high level phase, a falling edge and a low level phase, and the control unit is adapted to determine a transmission time point corresponding to the rising edge in the determined time period, and instruct the output shift register to serially output the transmission data at the determined time point. The transmission time point is closest to the time point at which the data is output at the baud rate.

[0011] Optionally, in the data transmitter according to the present invention, the control unit includes a frequency register, and the control unit is suitable for initializing the value of the frequency register to the operating frequency before the data is to be serially output; each time a time period is entered, the baud rate is subtracted from the value in the frequency register, and the remaining value is compared with the baud rate; if the value in the frequency register is lower than half of the baud rate, the time period is determined to be the time period for serially outputting the transmitted data, and the value in the frequency register is increased by the operating frequency; and if the value in the frequency register is not lower than half of the baud rate and is lower than the baud rate, the next time period of the time period is determined to be the time period for serially outputting the transmitted data, and the value in the frequency register is increased by the operating frequency.

[0012] Optionally, in the data transmitter according to the present invention, the control unit is adapted to update the value in the frequency register at a time point corresponding to a rising edge in each time period and control the serial output of the output shift register.

[0013] Optionally, the data transmitter according to the present invention also includes an output buffer register, which is suitable for receiving the transmission data to be output in a parallel manner; and a control unit is coupled to the output buffer register and the output shift register, which is suitable for controlling the output buffer register to send the transmission data to the output shift register, and controlling the output shift register to serially output the transmission data in a determined time period.

[0014] According to another aspect of the present invention, there is provided a data receiver, comprising an input shift register and a control unit. The input shift register stores received data to be serially input at a baud rate. The control unit is coupled to the input shift register, determines a time period suitable for serially inputting the received data according to the operating frequency and baud rate of the receiver, and instructs the input shift register to serially input the received data in the determined time period. The time period is closest to the time point at which the data is input at the baud rate.

[0015] Optionally, in a data receiver according to the present invention, the control unit includes a frequency register, and the control unit is suitable for initializing the value of the frequency register to half the operating frequency before data is to be serially input; each time a time period is entered, the baud rate is subtracted from the value in the frequency register, and the remaining value is compared with the baud rate; if the value in the frequency register is lower than half the baud rate, the time period is determined to be a time period for serial input of received data, and the value in the frequency register is increased by the operating frequency; and if the value in the frequency register is not lower than half the baud rate and is lower than the baud rate, the next time period of the time period is determined to be a time period for serial input of received data, and the value in the frequency register is increased by the operating frequency.

[0016] According to another aspect of the present invention, there is provided a universal asynchronous receiver-transmitter transmitter, comprising a data transmitter and a data receiver according to the present invention.

[0017] According to another aspect of the present invention, a processor is provided, comprising an instruction processing device, suitable for performing instruction processing so as to send data to a peripheral device or receive data from a peripheral device; and a universal asynchronous receiver-transmitter according to the present invention, coupled to the instruction processing device and the peripheral device, suitable for asynchronously transmitting data from the instruction processing device to the peripheral device, and asynchronously receiving data from the peripheral device and sending it to the instruction processing device.

[0018] According to still another aspect of the present invention, there is provided a system on chip, comprising an instruction processing device or a processor according to the present invention.

[0019] According to yet another aspect of the present invention, there is provided an intelligent device comprising the system on chip according to the present invention.

[0020] According to the scheme of the present invention, whether it is when serial output (transmitting) data or serial input (sampling) data, the time period closest to the baud rate for data transmission and / or sampling is first determined, and then data transmission and / or sampling is performed in this time period. Utilizing this scheme, the time periods for data transmission and / or sampling are not separated by fixed intervals (i.e., a predetermined number of time periods are separated), the intervals between some time periods are shorter, and the intervals between other time periods are longer, so that the time deviation accumulation caused by the fixed-interval time period can be reduced, thereby ensuring accurate data transmission and / or sampling.

[0021] In addition, according to the solution of the present invention, a special frequency register can be added to the control unit of the UART, and the value in the frequency register is updated in each time period to indicate the difference between the working clock frequency of the UART and the predetermined baud rate, and when the value in the register is lower than the entire baud rate, the time period closest to operating at the baud rate (that is, the current time period when the register value is lower than half of the baud rate value, and the next time period when the register value is greater than half of the baud rate value) is selected to perform data asynchronous transmission, thereby achieving accurate data asynchronous transmission.

[0022] According to the solution of the present invention, when an IoT device such as an embedded device is in a low-power mode, the UART can be operated with, for example, a lower-frequency clock signal in the device as the working clock, and accurately transmit the signal serially at a normal baud rate. For IoT devices, UART can be used to connect peripheral devices such as a network transmission unit and a monitoring unit (heart rate, temperature monitoring unit) that transmits data in a serial manner. Since such signal transmission can be performed in a low-power mode, real-time monitoring of the signal can be performed in a low-power mode, thereby reducing the power consumption of the device and extending the use time of the device, making it possible for such IoT devices to work for a long time when powered by batteries. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other purposes, features and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0024] Figure 1 A schematic diagram of an instruction processing device 100 according to an embodiment of the present invention is shown;

[0025] Figure 2 A schematic diagram of a universal asynchronous receiver-transmitter 200 according to an embodiment of the present invention is shown;

[0026] Figure 3 A schematic diagram of a universal asynchronous receiver-transmitter 300 according to another embodiment of the present invention is shown;

[0027] Figure 4 A timing diagram of a transmitter output signal according to an embodiment of the present invention is shown;

[0028] Figure 5 A schematic diagram showing a timing sequence of a receiver receiving a signal according to an embodiment of the present invention is shown;

[0029] Figure 6 A schematic diagram showing a processor according to an embodiment of the present invention; and

[0030] Figure 7 A schematic diagram of a system on chip (SoC) according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] Figure 1 1 is a schematic diagram of an instruction processing device 100 according to an embodiment of the present invention. In some embodiments, the instruction processing device 100 may be a processor, a processor core of a multi-core processor, or a processing element in an electronic system.

[0033] like Figure 1 As shown, the instruction processing device 100 includes an instruction fetch unit 130. The instruction fetch unit 130 can obtain instructions to be processed from the cache 110, the storage device 120 or other sources, and send them to the decoding unit 140. The instructions fetched by the instruction fetch unit 130 include but are not limited to high-level machine instructions or macro instructions, etc. The processing device 100 performs specific functions by executing these instructions.

[0034] The decoding unit 140 receives the instructions passed in from the instruction fetch unit 130, and decodes these instructions to generate low-level micro-operations, microcode entry points, microinstructions or other low-level instructions or control signals. They reflect the received instructions or are derived from the received instructions. The low-level instructions or control signals can implement the operation of high-level instructions through low-level (e.g., circuit level or hardware level) operations. Various different mechanisms can be used to implement the decoding unit 140. Examples of suitable mechanisms include, but are not limited to, microcode, lookup tables, hardware implementations, programmable logic arrays (PLA). The present invention is not limited to the various mechanisms for implementing the decoding unit 140, and any mechanism that can implement the decoding unit 140 is within the protection scope of the present invention.

[0035] These decoded instructions are then sent to and executed by execution unit 150. Execution unit 150 includes circuitry operable to execute instructions. Execution unit 150 receives data inputs from register file 170, cache 110, and / or storage device 120 and generates data outputs to them when executing these instructions.

[0036] The register set 170 includes architectural registers, which are also referred to as registers. Unless otherwise specified or clearly apparent, in this document, the phrases architectural registers, register set, and registers are used to refer to registers that are visible to software and / or programmers (e.g., software visible) and / or specified by macro instructions to identify operands. These registers are different from other non-architectural registers (e.g., temporary registers, reorder buffers, retirement registers, etc.) in a given microarchitecture. According to one embodiment, the register set 170 may include a set of vector registers 175, each of which may be 512 bits, 256 bits, or 128 bits wide, or different vector widths may be used. Optionally, the register set 170 may also include a set of general registers 176. The general registers 176 may be used when the execution unit executes instructions, such as storing jump conditions, storing instruction operation results, storing addresses of data to be accessed, storing data read from the cache 110 and / or the storage device 120, etc.

[0037] The execution unit 150 may include multiple specific instruction execution units 150a, 150b...150c, etc. These instruction execution units may be, for example, an arithmetic unit, an arithmetic logic unit (ALU), an integer unit, a floating point unit, a data access unit, a peripheral device operation unit, etc., and may respectively execute different types of instructions.

[0038] For example, the instruction execution unit 150a is a data access unit that can execute instructions related to data operations. Instructions related to data operations include data storage instructions and data loading instructions. The data storage instructions are used to write data to the cache 110 or the storage device 120. The data loading instructions are used to read data from the cache 110 or the storage device 120.

[0039] The instruction execution unit 150b is a peripheral device operation unit, which can read data from the peripheral device 160 or send data to the peripheral device 160. Such peripheral devices 160 include, for example, some devices supporting serial data communication, such as printers. Since the instruction processing device 100 receives and sends data in a parallel manner, the instruction processing device 100 includes a universal asynchronous receiver-transmitter (UART) 200. The peripheral device 160 is connected to the UART 200 through a specific interface (such as an RS 232 interface). The UART 200 performs serial communication with the peripheral device 160, so as to transmit the data in the instruction processing device 100 to the peripheral device 160 in serial and receive the serial input data from the peripheral device 160.

[0040] The instruction execution unit 150b is coupled to the UART 200 via the bus 180. Thus, the UART 200 can receive data inputted from the instruction execution unit 150b in parallel through the bus 180 and output it serially to the peripheral device 160, or output the data in parallel to the bus 180 and then send it to the instruction execution unit 150b.

[0041] Although not in Figure 1 , but it should be understood that, in addition to the bus 180, the UART 200 has other interfaces connected to the instruction processing device 100. These interfaces include an interface for receiving a working clock frequency signal, an interface for receiving various status bit settings (enabling transmission of data, enabling reception of data, etc.), an interface for indicating the status of the UART 200 (allowing data to be cached, receiving data errors, etc.), and an interrupt interface (generating an interrupt when receiving data so that the instruction processing device 100 can obtain and process the received data through an interrupt processing program). The present invention is not limited to the specific interface settings of the UART 200, and all specific interface settings and definitions that enable the instruction processing device 100 to communicate with the UART 200 and control the operation of the UART 200 are within the protection scope of the present invention.

[0042] According to one embodiment, the peripheral device 160 can be a monitoring device that can monitor the surrounding environment information, such as temperature, and send the environmental information data to the instruction processing device 100 as the processor of the IoT device in a serial manner via UART 200. When the temperature and other data are normal data, the instruction processing device 100 maintains a low power consumption mode and connects the RTC (real-time clock) signal to UART 200 as a working signal, so that UART200 processes the temperature and other data transmitted at a predetermined baud rate according to the RTC signal. When the temperature and other data are abnormal, the instruction processing device 100 can switch to a normal operating mode, and start to operate UART 200 at a higher operating frequency, and perform subsequent processing on the temperature data. In this way, the power consumption of IoT devices under normal environmental data conditions can be significantly reduced, and the working time of the device can be extended.

[0043] To avoid obscuring the description, a relatively simple instruction processing apparatus 100 has been shown and described. It should be appreciated that instruction processing apparatus 100 may have different forms, for example other embodiments of instruction processing apparatus or processors may have multiple cores, logical processors or execution engines.

[0044] Figure 2 FIG. 1 is a schematic diagram of a universal asynchronous receiver-transmitter (UART) 200 according to an embodiment of the present invention. Figure 3 is a schematic diagram of a universal asynchronous receiver-transmitter (UART) 300 according to another embodiment of the present invention. It should be noted that Figure 2 and 3 In the embodiment, the components in the UART are logically divided according to the serial transmission functions to be implemented in the UART 200 and 300, and these logical divisions are schematic and can be re-divided according to the actual physical layout and business needs. Therefore, these do not depart from the protection scope of the present invention.

[0045] like Figure 2 As shown, the universal asynchronous receiver-transmitter (UART) 200 includes a transmitter 210 and a receiver 220. The transmitter 210 receives data (in parallel) sent by the instruction processing device 100 via the bus 180, buffers the data, and sends the data in serial to the peripheral device 160. The receiver 220, in contrast to the transmitter 210, receives data from the peripheral device 160 in serial, buffers the data, and sends the received data to the instruction processing device 100 via the bus 180 for subsequent processing.

[0046] The transmitter 210 includes an output shift register 212 and a control unit 214. The output shift register 212 stores data to be serially output. Such data includes multiple bits. The output shift register 212 sends the data bits shifted out each time to a data line (also called a transmission line) coupled to the external device 160 through a bit-by-bit shift operation, thereby realizing the serial output of the data. The serial transmission of data has a predetermined data format. According to one embodiment of the present invention, the serial data is a frame of 8 data bits. Before the start of transmission, the level on the transmission line is set to a high level. Subsequently, the initial low level is used to indicate that the transmission is to be initiated. After the initial low level, 8 data bits are transmitted respectively with 8 continuous levels (according to the embodiment of the present invention, the 8 data bits start from the least significant bit to the most significant bit), and then a parity check bit is transmitted (indicating the parity check result of the 8 data bits), and the high stop bit (high level) at the end is sent to the transmission line after the parity check bit to indicate the end of the data frame transmission. In this embodiment, 8 data bits of one data are transmitted as a serial transmission of 11 consecutive bits.

[0047] It should be noted that the above is a format for serial data transmission, and the present invention is not limited thereto. All methods for serial data transmission based on the format are within the protection scope of the present invention.

[0048] The serial transmission of multiple bits is performed at a predetermined time frequency, that is, the transmission of each data bit is to last for a predetermined time period, that is, the level on the transmission line is maintained corresponding to the value of the data bit (high level or low level) for a predetermined period of time. In this way, as long as the transmitter (e.g., transmitter 210) and the receiver (e.g., peripheral device 160) agree on the time frequency in advance, that is, have the same time frequency, the receiver can receive the serial data transmitted by the transmitter on the transmission line at the same time frequency, thereby realizing serial communication.

[0049] In the present invention, the frequency of transmitting data bits on the transmission line is called the baud rate. Ideally, after starting data transmission, the output shift register 212 shifts bit by bit at the baud rate and transmits the shifted data bits to the data line so that the peripheral device coupled to the data line can receive it.

[0050] The control unit 214 is coupled to the output shift register 212 to control the shift frequency of the output shift register 212, i.e., the time point of the shift. The control unit 214 determines the time period of the transmitted data, i.e., the time point of the shift, according to the working clock frequency of the transmitter 210 and the predetermined transmission baud rate. According to one embodiment, the working clock frequency of the transmitter 210 is the working clock frequency of the UART 200, and the working clock frequency of the UART 200 can be obtained from the instruction processing device 100. In one embodiment, the UART 200 has an interface suitable for inputting a clock signal. The instruction processing device 100 can couple the clock signal to the interface, thereby providing the UART 200 with a clock signal, and setting its operating frequency to correspond to the time period of the clock signal.

[0051] According to one embodiment, when the instruction processing device 100 is in a low power consumption mode such as an idle mode, the real-time clock signal RTC can be coupled to the clock signal interface of the UART 200 to provide the RTC as a working clock signal for the UART 200. The clock signal is a periodic signal, and each period lasts for the same period of time and repeats the same level waveform. After starting the serial transmission, the control unit 214 determines whether the time period defined by each clock signal is suitable for transmitting data, and when it is determined that the time period is suitable for transmitting data, instructs the output shift register 212 to shift so that the newly shifted signal is sent to the data line for serial output.

[0052] In one embodiment, the RTC clock frequency and the baud rate are close, for example, the RTC clock frequency is 32.768Khz, and the baud rate is 14.4Khz, therefore, the control unit 214 determines in each time period whether transmitting data in the time period is closest to transmitting data at the baud rate. If the time period is the time period closest to transmitting data at the baud rate, the time period is determined to be a time period suitable for transmitting data.

[0053] According to one embodiment, each signal cycle in the clock cycle signal includes a rising edge, a high level phase, a falling edge, and a low level phase. The data transmission process includes starting from a time point, then maintaining the corresponding level for a period of time, until the next data bit is sent at the next time point. Therefore, when determining the transmission time period, it is determined whether the time point corresponding to the rising edge in the time period is the most suitable time point for transmitting data, that is, whether the time point is closest to the time point for transmitting data at the baud rate.

[0054] Figure 4 FIG. 2 shows a timing diagram of output data of the output shift register 212 according to an embodiment of the present invention. Figure 4The waveform diagram of the ideal output according to the baud rate, the waveform diagram of the transmission clock signal and the waveform diagram of the actual output of the output shift register 212 are shown in sequence.

[0055] like Figure 4 As shown, time 0 is the time to start transmission, so at time 0, both the ideal output and the actual output are set to a low level. Subsequently, at each rising edge of the clock signal, it is determined whether the time point corresponding to the rising edge is closest to the ideal transmission time point. For the ideal transmission time 1, it can be determined that the rising edge of the most recent clock signal is the previous edge, so the rising edge of the previous clock signal of time 1 is set as the actual output signal time. For the ideal transmission time 2, it is determined that the rising edge of the most recent clock signal is the next edge, so the rising edge of the next clock signal of time 2 is set as the actual output signal time, and so on.

[0056] There are various ways to determine the time period that is closest to transmitting data at the baud rate. According to one embodiment of the present invention, the control unit 214 includes a frequency register 216, which is suitable for storing a frequency value that changes with the working clock cycle, so as to determine a time period suitable for data output according to the value in the frequency register 216. Before outputting data, that is, when starting data output, the control unit 214 initializes the value of the frequency register to the working clock frequency of the transmitter 210, that is, the UART 200. Subsequently, each time a new time period is entered, for example, at the rising edge of the time period, the baud rate of the ideal output data is subtracted from the value in the frequency register 216, and the remaining value in the frequency register 216 is compared with the baud rate.

[0057] If the value in the frequency register 216 is higher than the baud rate, it means that the time period is far from the time point of outputting data and is not suitable for outputting data, and it waits for the next time period for processing.

[0058] If the value in the frequency register 216 is lower than half of the baud rate, it means that the current time period is closest to the time point of transmitting data at the baud rate, so the current time period is determined to be the time period for serial transmission of data. Subsequently, the control unit 214 increases the value in the frequency register 216 by the operating frequency value, and instructs the output shift register to perform shift serial output in the current time period (e.g., the rising edge of the current time period).

[0059] If the value in the frequency register 216 is not less than half of the baud rate and is less than the baud rate, it is determined that the next time period of the current time period is closer to the time point of transmitting data at the baud rate than the current time period, so the next time period of the current time period is determined to be the time period for serially transmitting data. Subsequently, the control unit 214 increases the value in the frequency register by the operating frequency value, and instructs the output shift register to perform shift serial output in the next time period of the current time period (for example, the rising edge of the next time period).

[0060] The following is an example of calculating the value in the frequency register 216 and the shift period:

[0061] Cycle 1: Register value: 32768 Initialize shift

[0062] Cycle 2: Register value: 32768-14400=18368, no shift

[0063] Cycle 3: Register value: 18368-14400=3968 shift

[0064] And update the register value to: 3968+32768=36736

[0065] Cycle 4: Register value: 36736-14400=22336, no shift

[0066] Cycle 5: Register value: 22336-14400=7936 does not shift, but indicates the next cycle shift

[0067] Update register value: 32768+7936=40704

[0068] Cycle 6: Register value: 40704–14400=26304 shift (according to the instructions of cycle 5)

[0069] Cycle 7: Register value is: 26304-14400=11904 No shift, indicating the next cycle shift

[0070] Update register value to 32768+11904=44672

[0071] Cycle 8: 44672-14400=30272 shift (according to the instructions of cycle 7)

[0072] Cycle 9: 30272–14400=15872 no shift

[0073] Cycle 10: 15872–14400=1472 shift

[0074] Update register value to 1472+32768=34240

[0075] …

[0076] According to the above calculation results, it can be known that the shifts are performed at periods 1, 3, 6, 8 and 10, and the period distribution is not equal, but some periods are spaced at 3 time periods, while others are spaced at 2 time periods. In this way, while the output is close to the signal waveform output at the baud rate, the influence of the accumulated time error on the serial output caused by the working clock frequency and the baud rate not being an integer multiple is avoided.

[0077] In addition, when the peripheral device 160 samples the serial output data of the transmitter 210, it will try to sample at the time point corresponding to the center position of each data bit. Figure 2 The transmitter 210 does not use the same time frequency as the baud rate when serially outputting data bits, but the value near the center point of each data bit is consistent with the level of data transmitted at the baud rate and will not affect the sampling of the peripheral device 160.

[0078] Alternatively, if Figure 2 As shown, the transmitter 210 further includes an output buffer register 218. The output buffer register 218 is coupled to the bus 180, receives data from the bus 180 that the instruction processing apparatus 100 is to send to the peripheral device 160 in a serial manner and buffers the data. According to one embodiment, the output buffer register 218 performs data operations in a parallel manner, and under the control of the control unit 214, outputs the buffered data to the output shift register 212, so that the output shift register 212 performs shifted serial output.

[0079] The control unit 214 is coupled to the output buffer register 218 and the output shift register 216 and controls the operations of the two units, such control includes controlling the buffer register 218 to obtain data from the bus 180, controlling the buffer register 218 to send data to the output shift register 216, and controlling the output shift register 216 to generate an interrupt after the serial output is completed. The present invention does not impose any restrictions on the control method of the control unit 214 on the output buffer register 218, and all appropriate control methods are within the protection scope of the present invention.

[0080] like Figure 2As shown, the receiver 220 includes an input shift register 222 and a control unit 224. The input shift register 222 stores the data of the serial sampling input. Such data includes multiple bits. The input shift register 222 samples the data bits from the data line (also called the receiving line) cycle by cycle, and stores the serially sampled data in the input shift register 222 through a bit-by-bit shift operation. Thus, the serial input of the data is realized. As described above with reference to the transmitter 210, the serial transmission of the data has a predetermined data format, and the receiver 220 can receive the data according to the same format as the data format followed by the generator 210, and after the low-level start bit, continuously sample 8 data bits to form a data, and perform a parity check according to the subsequent parity check bit, etc.

[0081] Similarly, when performing serial sampling input, the receiver 220 as the receiver reaches an agreement with the transmitter (such as the peripheral device 160) on the time frequency, that is, the baud rate in advance, that is, they have the same baud rate, so that the receiver 220 can sample the serial data transmitted by the transmitter at the same time frequency, thereby realizing serial communication.

[0082] Ideally, the peripheral device 160 transmits data serially to the data line at a baud rate, the input shift register 222 samples the data serially at the baud rate, and stores the received data by shifting bit by bit.

[0083] The control unit 224 is coupled to the input shift register 222 to control the shift frequency of the input shift register 222, i.e., the time point of sampling shift input. The control unit 224 determines the time period of sampling data according to the working clock frequency of the receiver 220 and the predetermined receiving baud rate, i.e., the time point of sampling shift input. According to one embodiment, the working clock frequency of the receiver 220 is the working clock frequency of the UART 200, and the working clock frequency of the UART 200 can be obtained from the instruction processing device 100. In one embodiment, the UART 200 has an interface suitable for inputting a clock signal. The instruction processing device 100 can couple the clock signal to the interface, thereby providing the UART 200 with a clock signal, and setting its working frequency to correspond to the time period of the clock signal.

[0084] According to one embodiment, when the instruction processing device 100 is in a low power consumption mode such as an idle mode, the real-time clock signal RTC can be coupled to the clock signal interface of the UART 200 to provide the RTC as a working clock signal for the UART 200. After starting the serial sampling input, the control unit 224 determines whether the time period defined by each clock signal is suitable for sampling data, and when it is determined that the time period is suitable for sampling data, instructs the input shift register 222 to perform sampling and shift the sampled data into the register 222, so as to be sent to the instruction processing device 100 via the bus 180 for subsequent processing.

[0085] As mentioned above, the RTC clock frequency and the baud rate are relatively close. Therefore, the control unit 224 determines in each time period whether the sampled data is closest to the sampled data at the baud rate in the time period. If the time period is the time period closest to the sampled data at the baud rate, then determine that the time period is the time period suitable for the sampled data.

[0086] As mentioned above, each signal cycle in the clock cycle signal includes a rising edge, a high level phase, a falling edge and a low level phase. The peripheral device 160 sends the data signal to be received to the data line to wait for sampling. According to the above data format, the data signal will maintain the corresponding level for a period of time, and then change to the level corresponding to the next data bit. Therefore, in order to sample the data more accurately, data sampling starts from the middle time point of the level duration cycle corresponding to the data bit, and keeps for a period of time after sampling, so that the data can be smoothly shifted and stored in the input shift register 222. Therefore, when determining the receiving time cycle, determine whether the time point corresponding to the rising edge in the time cycle is the most suitable time point for sampling data, that is, whether the time point is closest to the time point of sampling data at the baud rate.

[0087] Figure 5 FIG. 2 is a timing diagram showing the output data of the input shift register 222 according to an embodiment of the present invention. Figure 5 The waveform diagram of the received clock signal, the waveform diagram of the signal to be received and sampled, the waveform diagram of the ideal sampling according to the baud rate, and the waveform diagram of the actual sampling of the input shift register 222 are shown in sequence.

[0088] like Figure 5As shown, at each rising edge of the clock signal, it is determined whether the time point corresponding to the rising edge is closest to the ideal sampling time point. Moment 0 is the ideal sampling moment, and the most recent rising edge of the clock signal can be determined to be the previous edge, so the rising edge of the previous clock signal of moment 1 is set as the actual sampling signal moment. For the ideal sampling moment 1, it can be determined that the most recent rising edge of the clock signal is the next edge, so the rising edge of the next clock signal of moment 1 is set as the actual sampling moment. For the ideal sampling moment 2, it is determined that the most recent rising edge of the clock signal is the next edge, so the rising edge of the next clock signal of moment 2 is set as the actual sampling signal moment, and so on.

[0089] There are various ways to determine the time period that is closest to sampling or receiving data at the baud rate. According to one embodiment of the present invention, the control unit 224 includes a frequency register 226, which is suitable for storing a frequency value that changes with the working clock cycle, so as to determine a time period suitable for data sampling and input according to the value in the frequency register 226. Before sampling data, the control unit 224 initializes the value of the frequency register 226 to half the working clock frequency of the receiver 220, i.e., the UART 200. Subsequently, each time a new time period is entered, for example, at the rising edge of the time period, the baud rate of the ideal input and sampled data is subtracted from the value in the frequency register 226, and the remaining value in the frequency register 226 is compared with the baud rate.

[0090] If the value in the frequency register 226 is higher than the baud rate, it means that the time period is far from the time point of sampling and inputting data, and is not suitable for sampling data, and waits for the next time period for processing.

[0091] If the value in the frequency register 226 is lower than half of the baud rate, it means that the current time period is closest to the time point of sampling and receiving data at the baud rate, so the current time period is determined to be the time period for serial sampling and data input. Subsequently, the control unit 224 increases the value in the frequency register 226 by the operating frequency value, and instructs the input shift register 222 to perform sampling and serial shift input in the current time period (e.g., the rising edge of the current time period).

[0092] If the value in the frequency register 226 is not less than half of the baud rate and is less than the baud rate, it is determined that the next time period of the current time period is closer to the time point of sampling data at the baud rate than the current time period, so the next time period of the current time period is determined to be the time period for sampling and serial shifting input data. Subsequently, the control unit 224 increases the value in the frequency register 226 by the operating frequency value, and instructs the input shift register 222 to perform sampling and serial shift input at the next time period of the current time period (for example, the rising edge of the next time period).

[0093] In the above manner, the value in the frequency register 226 is used as an indication of whether to perform sampling. The period distribution obtained in this way is not uniform, but some periods are spaced at 3 time periods, while other periods are spaced at 2 time periods. In this way, while sampling and inputting a signal waveform close to that sampled at the baud rate, the influence of the accumulated time error on the serial input caused by the working clock frequency and the baud rate not being an integer multiple is avoided.

[0094] In addition, when the peripheral device 160 sends data to the data line to wait for the receiver 220 to sample and input, each data bit will maintain the corresponding level for a period of time. Figure 2 The receiver 220 does not use the same time frequency as the baud rate when serially inputting data bits, but samples the data bits while they maintain a corresponding level. Such sampling is consistent with the level of data sampling at the baud rate and will not affect the data input of the peripheral device 160.

[0095] Alternatively, if Figure 2 As shown, the receiver 220 also includes an input buffer register 228. The input buffer register 228 is coupled to the input shift register 222 and the bus 180, and obtains and buffers the data obtained by the input shift register 222 after the bits are serially shifted, and then sends the buffered data to the instruction processing device 100 for subsequent processing via the bus 180. According to one embodiment, the input buffer register 228 performs data operations in a parallel manner, and under the control of the control unit 214, receives and buffers the data from the input shift register 222, and sends the buffered data to the bus 160 for subsequent processing by the instruction processing device 100.

[0096] The control unit 224 is coupled to the input buffer register 228 and the input shift register 226 and controls the operations of these two units. Such control includes controlling the buffer register 228 to obtain data from the shift register 222 and send it to the bus 180, controlling the input shift register 222 to generate an interrupt during serial sampling, etc.

[0097] Figure 3 FIG. 4 is a schematic diagram of a universal asynchronous receiver-transmitter (UART) 300 according to another embodiment of the present invention. Figure 3 The UART 300 is shown as Figure 2 A further embodiment of the UART 200 is shown, therefore, in Figure 2 and 3 In the drawings, the same or similar symbols are used to indicate the same or similar components.

[0098] like Figure 3 As shown, UART 300 includes a transmitter 310, a receiver 320 and a control unit 330. Figure 2 The structure of the UART 200 shown in FIG. 1 is different in that the transmitter 310 and the receiver 320 do not include their own control units, but are connected to the same Figure 2 The functions corresponding to the control units 214 and 224 in the UART 300 are integrated into the control unit 330. In this way, the transmitter 310 includes an output shift register 212, the receiver includes an input shift register 222, and after the control unit 330 is coupled to the transmitter 310 and the receiver 320, the output shift register 212 and the input shift register 222 are controlled respectively. The control unit 330 controls the shift frequency of the output shift register 212, that is, the time point of shifting. That is, the control unit 330 determines the time period of transmitting data, that is, the time point of shifting, according to the working clock frequency of the UART 300 and the predetermined transmission baud rate. Similarly, the control unit 224 controls the shift frequency of the input shift register 222, that is, the time point of sampling shift input. That is, the control unit 224 determines the time period of sampling data, that is, the time point of sampling shift input, according to the working clock frequency of the UART 300 and the predetermined receiving baud rate.

[0099] Optionally, the control unit 330 may further include a transmitting frequency register 332 and a receiving frequency register 334 to respectively implement Figure 2 The functions of the frequency registers 216 and 226 in the transmitter 310 and the receiver 320 may also include an output buffer register 218 and an input buffer register 228. The operation of these buffer registers is also controlled by the control unit 330. These units and related operations are described in the above reference. Figure 2 The description has been given in detail in the description and will not be repeated here.

[0100] It should be noted that the above reference Figure 2 and 3The invention provides a method for determining the transmission time period and the sampling time period of the universal asynchronous receiver-transmitter 200 and 300 in a low power consumption mode, for example, when a real-time clock signal such as RTC is used as the working clock signal. When the universal asynchronous receiver-transmitter 200 and 300 is in a normal power consumption mode, for example, when the working clock frequency is significantly greater than the baud rate (for example, more than 8 times the baud rate), the predetermined multiple of the clock period is directly set as the period to be output and sampled (close to output and sampling at the baud rate), and the time accumulation caused by the frequency difference can be ignored.

[0101] According to one embodiment, the UARTs 200 and 300 can also be configured to operate in different power consumption modes according to the reference Figure 2 and 3 The asynchronous receiving and sending mode described herein is switched between the asynchronous receiving and sending mode and the traditional receiving and sending mode. All such modes are within the protection scope of the present invention.

[0102] As described above, the instruction processing device according to the present invention can be implemented as a processor core, and the instruction processing method can be executed in the processor core. The processor core can be implemented in different processors in different ways. For example, the processor core can be implemented as a general-purpose in-order core for general-purpose computing, a high-performance general-purpose out-of-order core for general-purpose computing, and a dedicated core for graphics and / or scientific (throughput) computing. The processor can be implemented as a CPU (central processing unit) and / or a coprocessor, wherein the CPU may include one or more general-purpose in-order cores and / or one or more general-purpose out-of-order cores, and the coprocessor may include one or more dedicated cores. Such a combination of different processors can lead to different computer system architectures. In one computer system architecture, the coprocessor is on a chip separate from the CPU. In another computer system architecture, the coprocessor is in the same package as the CPU but on a separate die. In another computer system architecture, the coprocessor is on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as a dedicated logic such as integrated graphics and / or scientific (throughput) logic, or is referred to as a dedicated core). In another computer system architecture called a system on a chip, the described CPU (sometimes referred to as an application core or application processor), the coprocessor described above, and additional functions may be included on the same die. Figure 6 and 7 to describe exemplary processor and computer architectures.

[0103] Figure 6 FIG. 1 is a schematic diagram of a processor 1100 according to an embodiment of the present invention. Figure 6 As shown in the solid line box in FIG. 1 , according to one embodiment, the processor 1110 includes a single core 1102A, a system agent unit 1110, and a bus controller unit 1116. Figure 6 As shown in the dashed box in , according to another embodiment of the present invention, the processor 1100 may further include multiple cores 1102A-N, an integrated memory controller unit 1114 in the system agent unit 1110, and a dedicated logic 1108.

[0104] According to one embodiment, the processor 1100 may be implemented as a central processing unit (CPU), wherein the dedicated logic 1108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and the cores 1102A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, combinations of the two). According to another embodiment, the processor 1100 may be implemented as a coprocessor, wherein the cores 1102A-N are multiple dedicated cores for graphics and / or science (throughput). According to yet another embodiment, the processor 1100 may be implemented as a coprocessor, wherein the cores 1102A-N are multiple general-purpose in-order cores. Thus, the processor 1100 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), or an embedded processor, etc. The processor may be implemented on one or more chips. Processor 1100 may be part of and / or implemented on one or more substrates using any of a number of processing technologies such as, for example, BiCMOS, CMOS, or NMOS.

[0105] The memory hierarchy includes one or more levels of cache within each core, one or more shared cache units 1106, and external memory (not shown) coupled to an integrated memory controller unit 1114. The shared cache unit 1106 may include one or more intermediate level caches, such as a second level (L2), third level (L3), fourth level (L4), or other level of cache, a last level cache (LLC), and / or combinations thereof. Although in one embodiment, a ring-based interconnect unit 1112 interconnects the integrated graphics logic 1108, the shared cache unit 1106, and the system agent unit 1110 / integrated memory controller unit 1114, the present invention is not limited thereto, and any number of well-known techniques may be used to interconnect these units.

[0106] The system agent 1110 includes those components that coordinate and operate the cores 1102A-N. The system agent unit 1110 may include, for example, a power control unit (PCU) and a display unit. The PCU may include logic and components required to adjust the power state of the cores 1102A-N and the integrated graphics logic 1108. The display unit is used to drive one or more externally connected displays.

[0107] The cores 1102A-N may have the above reference Figure 1 The core architectures described herein may be homogeneous or heterogeneous in terms of the architecture instruction set. That is, two or more of the cores 1102A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0108] Figure 7 A schematic diagram of a system on chip (SoC) 1500 is shown according to one embodiment of the present invention. Figure 7 The system-on-chip shown contains Figure 6 The processor 1100 shown is therefore Figure 6 Similar parts in the drawings have the same reference numerals. Figure 7 As shown, the interconnect unit 1502 is coupled to the application processor 1510, the system agent unit 1110, the bus controller unit 1116, the integrated memory controller unit 1114, one or more coprocessors 1520, a static random access memory (SRAM) unit 1530, a direct memory access (DMA) unit 1532, and a display unit 1540 for coupling to one or more external displays. The application processor 1510 includes a set of one or more cores 1102A-N and a shared cache unit 110. The coprocessor 1520 includes integrated graphics logic, an image processor, an audio processor, and a video processor. In one embodiment, the coprocessor 1520 includes a special processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, or an embedded processor, etc.

[0109] The system on chip (SoC) or processor according to the present invention can be used in various smart devices to implement corresponding functions in the smart devices. Such smart devices include but are not limited to vehicle-mounted devices, smart speakers, smart display devices, IoT devices, mobile terminals, and personal digital terminals.

[0110] The various embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0111] It should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0112] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0113] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0114] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0115] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0116] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0117] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and didactic purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A data transmitter, comprising: an output shift register adapted to store transmit data to be output serially at a baud rate; as well as a control unit, coupled to the output shift register, comprising a frequency register, adapted to determine a time period suitable for outputting the transmission data according to the operating frequency of the transmitter and the baud rate, and instruct the output shift register to serially output the transmission data in the determined time period, wherein the time period is closest to a time point for outputting data at the baud rate; Before the data is to be serially output, the value of the frequency register is initialized to the operating frequency; each time a time period is entered, the baud rate is subtracted from the value in the frequency register, and the remaining value is compared with the baud rate; if the value in the frequency register is lower than half of the baud rate, the time period is determined to be the time period for serially outputting the transmitted data, and the value in the frequency register is increased by the operating frequency; and if the value in the frequency register is not lower than half of the baud rate and is lower than the baud rate, the next time period of the time period is determined to be the time period for serially outputting the transmitted data, and the value in the frequency register is increased by the operating frequency.

2. The data transmitter of claim 1, wherein the time period is a time period defined by a periodic signal, the periodic signal sequentially comprising a rising edge, a high level phase, a falling edge and a low level phase, and The control unit is adapted to determine a sending time point corresponding to the rising edge in the determined time period, and instruct the output shift register to serially output the transmission data at the determined time point, wherein the sending time point is closest to a time point at which data is output at the baud rate.

3. The data transmitter of claim 2, wherein the control unit is adapted to update the value in the frequency register at a time point corresponding to the rising edge in each time period and control the serial output of the output shift register.

4. The data transmitter according to any one of claims 1 to 3, further comprising: an output buffer register adapted to receive the transmit data in parallel; as well as The control unit is coupled to the output buffer register and the output shift register, and is adapted to control the output buffer register to send the transmit data to the output shift register, and control the output shift register to serially output the transmit data in a determined time period.

5. A data receiver, comprising: an input shift register adapted to store received data to be input serially at a baud rate; as well as a control unit, coupled to the input shift register, comprising a frequency register, adapted to determine a time period suitable for serially inputting the received data according to the operating frequency of the receiver and the baud rate, and instruct the input shift register to serially input the received data in the determined time period, wherein the time period is closest to a time point at which data is input at the baud rate; Before the data is serially input, the value of the frequency register is initialized to half of the operating frequency; Each time a time period is entered, the baud rate is subtracted from the value in the frequency register, and the remaining value is compared with the baud rate; if the value in the frequency register is lower than half of the baud rate, the time period is determined to be a time period for serial input of the received data, and the value in the frequency register is increased by the operating frequency; and if the value in the frequency register is not lower than half of the baud rate and is lower than the baud rate, the next time period of the time period is determined to be a time period for serial input of the received data, and the value in the frequency register is increased by the operating frequency.

6. The data receiver of claim 5, wherein the time period is a time period defined by a periodic signal, the periodic signal sequentially comprising a rising edge, a high level phase, a falling edge and a low level phase, and The control unit is adapted to determine a receiving time point corresponding to the rising edge in the determined time period, and instruct the input shift register to serially input the received data at the determined time point, wherein the receiving time point is closest to a time point at which data is input at the baud rate.

7. The data receiver of claim 6, wherein the control unit is adapted to update the value in the frequency register and control the serial input of the input shift register at a time point corresponding to the rising edge in each time period.

8. The data receiver according to any one of claims 5 to 7, further comprising: an input buffer register adapted to output the received data in parallel; as well as The control unit is coupled to the input buffer register and the input shift register, and is adapted to control the input shift register to serially input the received data in a determined time period, and to control the input shift register to send the received data to the input buffer register.

9. A universal asynchronous receiver-transmitter, comprising: The data transmitter as claimed in any one of claims 1 to 4; as well as A data receiver as claimed in any one of claims 5 to 8.

10. A universal asynchronous receiver-transmitter, comprising: a transmitter, the transmitter comprising an output shift register adapted to store transmit data to be output serially at a baud rate; a receiver including an input shift register adapted to store received data to be input serially at a baud rate; a control unit, coupled to the transmitter and the receiver, comprising a transmission frequency register and a reception frequency register, adapted to determine a first time period suitable for outputting the transmission data according to the operating frequency of the transmitter and the baud rate, and instruct the output shift register to serially output the transmission data in the determined first time period, wherein the first time period is closest to a time point for outputting data at the baud rate; and further adapted to determine a second time period suitable for serially inputting the reception data according to the operating frequency of the receiver and the baud rate, and instruct the input shift register to serially input the reception data in the determined second time period, wherein the second time period is closest to a time point for inputting data at the baud rate; Wherein, before the data is to be serially output, the value of the transmission frequency register is initialized to the operating frequency; each time a time period is entered, the baud rate is subtracted from the value in the transmission frequency register, and the remaining value is compared with the baud rate; if the value in the transmission frequency register is lower than half of the baud rate, the time period is determined to be the first time period for serially outputting the transmission data, and the value in the frequency register is increased by the operating frequency; and if the value in the transmission frequency register is not lower than half of the baud rate and is lower than the baud rate, the next time period of the time period is determined to be the first time period for serially outputting the transmission data, and the value in the frequency register is increased by the operating frequency; Before serially inputting data, the value of the receiving frequency register is initialized to half of the operating frequency; each time a time period is entered, the baud rate is subtracted from the value in the receiving frequency register, and the remaining value is compared with the baud rate; if the value in the receiving frequency register is lower than half of the baud rate, the time period is determined to be a second time period for serially inputting the received data, and the value in the receiving frequency register is increased by the operating frequency; and if the value in the receiving frequency register is not lower than half of the baud rate and is lower than the baud rate, the next time period of the time period is determined to be a second time period for serially inputting the received data, and the value in the receiving frequency register is increased by the operating frequency.

11. The universal asynchronous receiver-transmitter as claimed in claim 10, wherein the time period is a time period defined by a periodic signal, the periodic signal sequentially comprising a rising edge, a high level phase, a falling edge and a low level phase, and The control unit is suitable for respectively determining the first and second time points corresponding to the rising edge in the determined first and second time periods, and instructing the output shift register to serially output the transmitted data at the determined first time point, and the input shift register to serially input the received data at the determined second time point.

12. A processor, comprising: Instruction processing means adapted to perform instruction processing in order to send data to a peripheral device or to receive data from said peripheral device; as well as The universal asynchronous receiver-transmitter as described in any one of claims 9 to 11 is coupled to the instruction processing device and the peripheral device, and is suitable for asynchronously transmitting data from the instruction processing device to the peripheral device, and asynchronously receiving data from the peripheral device and sending it to the instruction processing device.

13. A system on chip comprising the processor according to claim 12.

14. An intelligent device comprising the system on chip according to claim 13.

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