Display device

Abstract

The display device includes pixels. The pixel is electrically connected to the first power line, the second power line, and the data line. The pixel includes a first transistor and a capacitor electrically connected between a gate electrode of the first transistor and one electrode of the first transistor. In a plan view, the data lines extend in the second direction. The first power line extends in a first direction crossing the second direction and overlaps the data line and a gate electrode of the first transistor. The second power line extends in the second direction, overlaps the data line, and overlaps the gate electrode of the first transistor.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] The display device includes pixels, and each of the pixels emits light based on a corresponding data signal among data signals supplied through the data lines. Summary of the invention

[0003] Technical issues

[0004] There may be parasitic capacitance between components in the pixel (e.g., gate and source electrodes of a driving transistor) and the data line, and due to the parasitic capacitance, the pixel may emit light having a brightness different from the desired brightness. Accordingly, defects such as stains may appear in the image displayed on the display device, and the display quality may be deteriorated.

[0005] An aspect of the present disclosure is to provide a display device with improved display quality.

[0006] Aspects of the present disclosure are not limited to the above-described aspects, and other technical aspects that are not described will be clearly understood by those skilled in the art from the following description.

[0007] Technical Solution

[0008] According to an embodiment, a display device may include a pixel that may be electrically connected to a first power line, a second power line, and a data line. The pixel may include a first transistor and a capacitor electrically connected between a gate electrode of the first transistor and an electrode of the first transistor. In a plan view, the data line may extend in a second direction, the first power line may extend in a first direction intersecting the second direction and overlap with the data line and the gate electrode of the first transistor, and the second power line may extend in the second direction, overlap with the data line, and overlap with the gate electrode of the first transistor.

[0009] Each of the first power line and the second power line may overlap a channel region of the first transistor in a plan view.

[0010] The first power supply line may extend in the second direction in a region adjacent to the first transistor in a plan view.

[0011] The second power supply line may extend in the first direction in a region adjacent to the first transistor in a plan view.

[0012] The first power line and the second power line may be electrically connected to each other, and a constant voltage may be applied to the first power line and the second power line.

[0013] The first power line and the second power line may be electrically separated from each other, and different constant voltages may be applied to the first power line and the second power line.

[0014] The pixel may further include a second transistor electrically connected between the data line and a gate electrode of the first transistor, and each of the first power line and the second power line may not overlap the second transistor in a plan view.

[0015] The capacitor may include: a first electrode, which is arranged on the same layer as the first power line; a second electrode arranged on the first electrode; a third electrode, which is arranged on the same layer as the gate electrode of the first transistor; and a fourth electrode arranged on the third electrode and electrically connected to the electrode of the first transistor.

[0016] A first capacitor may be arranged between the first electrode and the second electrode, a second capacitor may be arranged between the second electrode and the third electrode, a third capacitor may be arranged between the third electrode and the fourth electrode, and the first capacitor, the second capacitor and the third capacitor may be electrically connected in parallel to each other to configure a capacitor.

[0017] The third electrode may be electrically connected to the first electrode through a first opening disposed in the second electrode, and the fourth electrode may be electrically connected to the second electrode through a second opening disposed in the third electrode.

[0018] The second electrode of the capacitor may overlap the semiconductor layer of the first transistor in a plan view, and the second electrode of the capacitor may configure a lower electrode of the first transistor.

[0019] The pixel may further include a holding capacitor disposed between the first power supply line and the second electrode of the capacitor.

[0020] The data line and the fourth electrode may be disposed at the same layer, and the second power line may be disposed on the fourth electrode.

[0021] The pixel may further include a light emitting element, and the second power supply line may be arranged between the capacitor and an anode electrode of the light emitting element and shield the capacitor.

[0022] According to an embodiment, a display device may include a pixel electrically connected to a first power line, a second power line, a third power line, and a data line. The pixel may include a first transistor and a capacitor arranged between a gate electrode of the first transistor and an electrode of the first transistor. In a plan view, the first power line may extend in a first direction, and the data line, the second power line, and the third power line may extend in a second direction intersecting the first direction. In a plan view, the data line and the capacitor may be covered by the first power line, the second power line, and the third power line.

[0023] The second power line and the third power line may be arranged in the same layer, and in a plan view, the second power line may overlap a portion of the capacitor and the third power line may overlap a remaining portion of the capacitor.

[0024] The first power line and the second power line may be electrically connected to each other, and a constant voltage may be applied to the first power line and the second power line.

[0025] The capacitor may include: a first electrode, which is arranged on the same layer as the first power line; a second electrode arranged on the first electrode; a third electrode, which is arranged on the same layer as the gate electrode of the first transistor; and a fourth electrode arranged on the third electrode and electrically connected to the electrode of the first transistor.

[0026] The third electrode may be electrically connected to the first electrode through a first opening disposed in the second electrode, and the fourth electrode may be electrically connected to the second electrode through a second opening disposed in the third electrode.

[0027] The data line and the fourth electrode may be disposed at the same layer, and the second power line may be disposed on the fourth electrode.

[0028] Details of other embodiments are included in the detailed description and accompanying drawings.

[0029] Beneficial Effects

[0030] In a display device according to an embodiment of the present disclosure, a first power line may be arranged below a data line and a first transistor (or a source node) to shield the first transistor and a data line adjacent thereto. A second power line may be arranged on the data line and the first transistor (or a source node) and may shield the data line and the first transistor. For example, the data line and the first transistor (or the source node) may be shielded in an upward direction and a downward direction by the first power line and the second power line. Therefore, an accurate data signal may be maintained in the first transistor (or between the gate electrode and the source electrode of the first transistor), the sub-pixel may accurately emit light having a target brightness, and the display quality of the display device may be improved.

[0031] The effects according to the embodiments are not limited to the contents provided above as examples, and additional various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become more apparent by further describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0034] Figure 2 It is shown that the Figure 1 A schematic circuit diagram of an embodiment of a sub-pixel in a display device;

[0035] Figure 3 It is shown that the Figure 1A schematic circuit diagram of an embodiment of a sub-pixel in a display device;

[0036] Figure 4 It is shown Figure 1 A schematic plan view of an embodiment of a sub-pixel;

[0037] Figure 5 It is shown that the Figure 4 A schematic plan view of an embodiment of a semiconductor layer in a first sub-pixel;

[0038] Figure 6 yes Figure 4 an enlarged schematic plan view of a first region of

[0039] Figure 7 is shown along Figure 6 A schematic cross-sectional view of an embodiment of a first sub-pixel along line II';

[0040] Figure 8 is shown along Figure 6 A schematic cross-sectional view of an example of a first sub-pixel taken along line II-II';

[0041] Fig. 9 It is shown Figure 1 A schematic plan view of an embodiment of a sub-pixel of ; and

[0042] Fig.10 is a schematic cross-sectional view showing a comparative example of a sub-pixel. DETAILED DESCRIPTION

[0043] Since various changes may be applied to the present disclosure and the present disclosure may have various forms, only certain specific embodiments will be shown in the drawings and described in detail herein.In the following description, unless the context clearly dictates otherwise, the singular form also includes the plural form.

[0044] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean any combination including "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0045] For the purpose of the present disclosure, the phrase "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. Moreover, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0046] The term "connection" may include electrical connection and / or physical connection. As just one example, "connection" used based on a circuit diagram may mean electrical connection.

[0047] Although the terms "first", "second" and similar terms are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component described below may be the second component and still be within the technical spirit of the present disclosure. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0048] The term "overlap" or "overlapping" means that a first object may be located above or below a second object or to the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term appreciated and understood by a person of ordinary skill in the art.

[0049] When an element is described as “non-overlapping” or “non-overlapping” with another element, this may include the elements being spaced apart, offset or separated from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0050] The present disclosure is not limited to the embodiments disclosed below and may be modified in various forms. In addition, each of the embodiments disclosed below may be implemented alone or in combination with at least one of the other embodiments.

[0051] In the accompanying drawings, some components that are not directly related to the characteristics of the present disclosure may be omitted to clearly represent the present disclosure. In addition, some components in the accompanying drawings may be shown with slightly exaggerated sizes, proportions, etc. Throughout the accompanying drawings, the same or similar components will be given the same reference numerals and symbols as much as possible, although they are shown in different drawings, and repeated descriptions will be omitted.

[0052] As used herein, "about" or "approximately" or "substantially" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0053] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly dogmatic sense unless expressly so defined herein.

[0054] Figure 1 is a schematic plan view showing a display device according to an embodiment. Figure 1 , a display device, particularly a display panel PNL provided in the display device, is shown as an example of an electronic device.

[0055] For convenience, in Figure 1 , the structure of the display panel PNL is briefly shown based on the display area DA. However, according to embodiments, at least one driving circuit unit (eg, at least one of a scan driver and a data driver), lines and / or pads not shown may be further arranged on the display panel PNL.

[0056] The display device may be an electronic device in which a display surface is applied to at least one surface, such as a smart phone, a television, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a PDA, a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device.

[0057] Reference Figure 1 , the display panel PNL may include a substrate SUB and pixels PXL arranged on the substrate SUB.

[0058] The substrate SUB may configure the base component of the display panel PNL, and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate formed of glass or tempered glass, a flexible substrate (or film) of a plastic or metal material, and / or at least one insulating layer. The material and / or material properties of the substrate SUB are not particularly limited. The substrate SUB may be transparent or opaque. According to an embodiment, the substrate SUB may include a reflective material.

[0059] The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA except the display area DA.

[0060] The pixels PXL may be arranged in the display area DA. Various lines, pads, and / or built-in circuit units connected to the pixels PXL in the display area DA may be arranged in the non-display area NDA.

[0061] The pixel PXL may include sub-pixels SPXL1 to SPXL3. For example, the pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0062] Each of the sub-pixels SPXL1 to SPXL3 may emit light of a predetermined or selectable color. According to an embodiment, the sub-pixels SPXL1 to SPXL3 may emit light of different colors. For example, the first sub-pixel SPXL1 may emit light of a first color, the second sub-pixel SPXL2 may emit light of a second color, and the third sub-pixel SPXL3 may emit light of a third color. For example, the first sub-pixel SPXL1 may be a red pixel emitting red light, the second sub-pixel SPXL2 may be a green pixel emitting green light, and the third sub-pixel SPXL3 may be a blue pixel emitting blue light, but the present disclosure is not limited thereto.

[0063] In an embodiment, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include a light-emitting element of a first color, a light-emitting element of a second color, and a light-emitting element of a third color as light sources to emit light of a first color, light of a second color, and light of a third color, respectively. In another embodiment, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include light-emitting elements that emit light of the same color, and may include a color conversion layer and / or a color filter of different colors arranged on each light-emitting element to emit light of a first color, light of a second color, and light of a third color, respectively. However, the color, type, quantity, etc. of the sub-pixels SPXL1 to SPXL3 configuring each pixel PXL are not particularly limited. For example, the color of the light emitted by each pixel PXL may be changed differently.

[0064] Sub-pixels SPXL1 to SPXL3 can be based on stripes or PENTILE TM The sub-pixels SPXL1 to SPXL3 are regularly arranged in a layout structure, etc. For example, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may be sequentially and repeatedly arranged along the first direction DR1, and may be repeatedly arranged along the second direction DR2. At least one of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 arranged adjacent to each other may configure a pixel PXL capable of emitting light of various colors. However, the layout structure of the sub-pixels SPXL1 to SPXL3 is not limited thereto, and the sub-pixels SPXL1 to SPXL3 may be arranged in the display area DA in various structures and / or methods.

[0065] In an embodiment, each of the sub-pixels SPXL1 to SPXL3 may be configured as an active pixel. For example, each of the sub-pixels SPXL1 to SPXL3 may include at least one light source (e.g., a light-emitting element) driven by a control signal (e.g., a scan signal and a data signal) and / or a predetermined or optional power source (e.g., a first power source and a second power source). However, the type, structure and / or driving method of the sub-pixels SPXL1 to SPXL3 applicable to the display device are not particularly limited.

[0066] Figure 2 It is shown that the Figure 1 Schematic circuit diagram of an embodiment of a sub-pixel in a display device. Figure 1 The sub-pixels SPXL1 to SPXL3 in the display device of FIG. 1 may be substantially the same as or similar to each other, and thus the sub-pixel SPXL is described below by including the sub-pixels SPXL1 to SPXL3.

[0067] Reference Figure 1 and Figure 2 , the subpixel SPXL may be connected to a scan line SL (or a gate line), an emission control line ECL (or a first emission control line), and a data line DL. The scan line SL may include a first scan line SL1, a second scan line SL2, and a third scan line SL3. A drive signal DRS may be applied to the scan line SL, the emission control line ECL, and the data line DL. A first scan signal GW may be applied to the first scan line SL1, a second scan signal GR may be applied to the second scan line SL2, and a third scan signal GI may be applied to the third scan line SL3. An emission control signal EM (or a first emission control signal) may be applied to the emission control line ECL, and a data signal Vdata (or a data voltage) may be applied to the data line DL.

[0068] The pixel PXL may also be connected to a first power line PL1, a second power line PL2, a reference power line RFL, and an initialization power line INL (or a first initialization power line). A first power supply voltage VDD may be applied to the first power line PL1, a second power supply voltage VSS may be applied to the second power line PL2, a reference power supply voltage VREF may be applied to the reference power line RFL, and an initialization power supply voltage VINT (or a first initialization power supply voltage) may be applied to the initialization power line INL. Each of the first power supply voltage VDD, the second power supply voltage VSS, and the initialization power supply voltage VINT may be a constant voltage. The voltage levels of the first power supply voltage VDD, the second power supply voltage VSS, and the initialization power supply voltage VINT may be different from each other.

[0069] The pixel PXL may include a pixel circuit PXC and a light emitting element LD.

[0070] The pixel circuit PXC may include a first transistor T1 (or driving transistor), a second transistor T2 and a first capacitor Cst (or storage capacitor). In an embodiment, the pixel circuit PXC may also include a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a second capacitor Chold (or holding capacitor).

[0071] The first transistor T1 may be connected between the first power line PL1 and the second node N2 (or source node). For example, the first electrode (e.g., drain electrode) of the first transistor T1 may be connected to the first power line PL1 via the fifth transistor T5, and the second electrode (e.g., source electrode) of the first transistor T1 may be connected to the second node N2. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may further include a lower electrode, and the lower electrode may be connected to the second node N2. The first transistor T1 may supply a driving current to the light emitting element LD. For example, the first transistor T1 may supply a driving current corresponding to the voltage of the first node N1 to the light emitting element LD.

[0072] The second transistor T2 may be connected between the data line DL and the first node N1. The gate electrode of the second transistor T2 may be connected to the first scan line SL1. The second transistor T2 may be turned on in response to the first scan signal GW of the first scan line SL1. When the second transistor T2 is turned on, the data signal Vdata of the data line DL may be transmitted to the first node N1.

[0073] The third transistor T3 may be connected between the reference power line RFL and the first node N1. The gate electrode of the third transistor T3 may be connected to the second scan line SL2. The third transistor T3 may be turned on in response to the second scan signal GR of the second scan line SL2. When the third transistor T3 is turned on, the reference power voltage VREF may be transmitted to the first node N1. The first node N1 may be initialized by the reference power voltage VREF.

[0074] The fourth transistor T4 may be connected between the second node N2 and the initialization power line INL. The gate electrode of the fourth transistor T4 may be connected to the third scan line SL3. The fourth transistor T4 may be turned on in response to the third scan signal GI of the third scan line SL3. When the fourth transistor T4 is turned on, the initialization power voltage VINT may be transmitted to the second node N2. The second node N2 may be initialized by the initialization power voltage VINT.

[0075] The fifth transistor T5 may be connected between the first power line PL1 and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the emission control line ECL. The fifth transistor T5 may be turned on in response to the emission control signal EM of the emission control line ECL. When the fifth transistor T5 is turned on, a current path through which a driving current may flow from the first power line PL1 to the second power line PL2 via the pixel circuit PXC and the light emitting element LD may be formed.

[0076] The first capacitor Cst may be formed or connected between the first node N1 and the second node N2. A voltage corresponding to the data voltage Vdata may be stored in the first capacitor Cst.

[0077] The second capacitor Chold may be formed or connected between the first power line PL1 and the second node N2. The second capacitor Chold may stabilize the voltage of the second node N2.

[0078] The light emitting element LD may be connected between the second node N2 and the second power line PL2. For example, the light emitting element LD may be connected between the second node N2 and the second power line PL2 in a forward direction. When a driving current is supplied from the first transistor T1, the light emitting element LD may emit light having a brightness corresponding to the driving current.

[0079] In an embodiment, the light emitting element LD may include an organic light emitting diode. In another embodiment, the light emitting element LD may include at least one inorganic light emitting diode. The type, size and / or number of the light emitting element LD may vary according to the embodiment.

[0080] The first to fifth transistors T1 to T5 may be n-type transistors, but are not limited thereto. For example, at least one of the first to fifth transistors T1 to T5 may be changed to a p-type transistor. The voltage level of the driving signal DRS for controlling the operation of the transistor may be set according to the type of each transistor.

[0081] In an embodiment, at least one of the first to fifth transistors T1 to T5 may include an oxide semiconductor. For example, at least one transistor including the first transistor T1 may be an oxide semiconductor transistor including an oxide semiconductor.

[0082] The structure and driving method of the sub-pixel SPXL may be changed variously. For example, in addition to Figure 2 In addition to the embodiment shown in FIG. 1 , the pixel circuit PXC may be configured with pixel circuits and / or driving methods of various structures.

[0083] Figure 3 It is shown that the Figure 1 Schematic circuit diagram of an embodiment of a sub-pixel in a display device.

[0084] Reference Figure 2 and Figure 3 , the sub-pixel SPXL may also be connected to the second emission control line ECL2 and the second initialization power line INL2. The second emission control signal EMB may be applied to the second emission control line ECL2, and the second initialization power voltage VAINT may be applied to the second initialization power line INL2. The second initialization power voltage VAINT may be a constant voltage. The second initialization power voltage VAINT may be different from the initialization power voltage VINT of the initialization power line INL, but is not limited thereto.

[0085] The pixel circuit PXC may further include a sixth transistor T6 and a seventh transistor T7 .

[0086] The sixth transistor T6 may be connected between the second node N2 and the anode electrode of the light emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the second emission control line ECL2. The sixth transistor T6 may be turned on in response to the second emission control signal EMB of the second emission control line ECL2. When the sixth transistor T6 is turned on, a current path through which a driving current can flow from the first power line PL1 to the second power line PL2 via the pixel circuit PXC and the light emitting element LD may be formed.

[0087] The seventh transistor T7 may be connected between the anode electrode of the light emitting element LD and the second initialization power line INL2. The gate electrode of the seventh transistor T7 may be connected to the third scan line SL3. The seventh transistor T7 may be turned on in response to the third scan signal GI of the third scan line SL3. When the seventh transistor T7 is turned on, the second initialization power voltage VAINT may be transmitted to the anode electrode of the light emitting element LD.

[0088] The light emitting element LD may have capacitance, and the capacitance of the light emitting element LD may appear as the third capacitor CLD. Figure 2 In the pixel circuit PXC, the second node N2 can be initialized by the initialization voltage VINT, and when the driving current is supplied to the light emitting element LD, the third capacitor CLD can be fully charged. Accordingly, Figure 2 The light emitting element LD may emit light having a brightness slightly different from the desired brightness. Figure 3 In the pixel circuit PXC of FIG. 1 , the second node N2 may be initialized by the initialization voltage VINT, and the light emitting element LD (for example, the light emitting element LD separated from the second node N2 by the sixth transistor T6) may be initialized by the second initialization power supply voltage VAINT. For example, the third capacitor CLD of the light emitting element LD may be charged by the second initialization power supply voltage VAINT, and the driving current may not be used to charge the third capacitor CLD. Therefore, the light emitting element LD may accurately emit light with a desired brightness.

[0089] Figure 4 It is shown Figure 1 A schematic plan view of an embodiment of a sub-pixel. Figure 4 In, based on Figure 3 The pixel circuit PXC of FIG. 1 shows the sub-pixels SPXL1 to SPXL3. For convenience of description, the sub-pixels SPXL1 to SPXL3 (or the sub-pixel regions in which the sub-pixels SPXL1 to SPXL3 are arranged) are divided based on the pixel circuit in a plan view. Figure 5 It is shown that the Figure 4 Schematic plan view of an embodiment of a semiconductor layer in a first sub-pixel. Figure 6 yes Figure 4 An enlarged schematic plan view of a first region of FIG. Figure 7 is shown along Figure 6 A cross-sectional view of an embodiment of a first sub-pixel taken along line II'. Figure 8 is shown along Figure 6 A schematic cross-sectional view of an example of a first sub-pixel taken along line II-II'. Figure 7 compared to, Figure 8 A first light emitting element LD1 is also shown.

[0090] exist Figures 4 to 8 In the figure, the sub-pixels are simplified, such as each electrode is shown as a single-layer electrode, and each insulating layer is shown as a single-layer insulating layer, but the present disclosure is not limited thereto.

[0091] In describing the embodiments of the present disclosure, “formed and / or provided in the same layer” may mean formed in the same process, and “formed and / or provided in different layers” may mean formed in different processes.

[0092] exist Figures 4 to 8 , a width direction (or lateral direction) in the plan view is indicated as a first direction DR1, a height direction (or longitudinal direction) in the plan view is indicated as a second direction DR2, and a thickness direction of the substrate SUB is indicated as a third direction DR3.

[0093] Reference Figures 4 to 8 Since the first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 have pixel circuits (or circuit structures) that are substantially the same as or similar to each other, the common configuration of the first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 is described based on the first sub-pixel SPXL1, and the overlapping descriptions are not repeated.

[0094] In the following, reference is made to Figure 8 , the components are described according to the stacking order on the substrate SUB.

[0095] An eleventh conductive pattern BML11 (or a first transverse power line), a twelfth conductive pattern BML12 , and a repair line DML may be arranged on the substrate SUB.

[0096] In a central region of the first subpixel SPXL1 based on the second direction DR2, the eleventh conductive pattern BML11 may extend in the first direction DR1. The eleventh conductive pattern BML11 may cross or intersect the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3. In a region where the eleventh conductive pattern BML11 overlaps with the first power line PL1, the eleventh conductive pattern BML11 may be electrically connected to the first power line PL1 through the first bridge pattern BRP1 and the fifth bridge pattern BRP5. The eleventh conductive pattern BML11 may not be connected to the initialization power line INL and the second power line PL2.

[0097] The width of the second direction DR2 of the eleventh conductive pattern BML11 may vary depending on the position. The eleventh conductive pattern BML11 may extend in a direction opposite to the second direction DR2 in a region adjacent to the data line DL and the first transistor T1. As will be described later, the eleventh conductive pattern BML11 may overlap with the gate electrode (and channel region) and source electrode (second electrode or source node) of the first transistor T1 and the data line DL, and may shield the gate electrode and second electrode of the first transistor T1 and the data line DL. For example, the eleventh conductive pattern BML11 may prevent the gate electrode and source electrode (or source node) of the first transistor T1 from being affected (or coupled) by signal transmission of the data line DL adjacent to the gate electrode and source electrode (or source node) of the first transistor T1 (refer to Figure 7 and Figure 8 ). Therefore, an accurate data signal can be maintained between the gate electrode and the source electrode of the first transistor T1, and the sub-pixel can accurately emit light with target brightness.

[0098] The twelfth conductive pattern BML12 may be arranged to correspond to a section in which the width of the eleventh conductive pattern BML11 is relatively small. The twelfth conductive pattern BML12 may be arranged in an island shape.

[0099] The repair line DML may be positioned adjacent to the lower side of the first sub-pixel SPXL1 and may extend in the first direction DR1. In the case where the pixel circuit of the first sub-pixel SPXL1 is defective, the repair line DML may be a configuration for connecting the first sub-pixel SPXL1 (or the light-emitting element of the first sub-pixel SPXL1) to a dummy pixel (or a dummy pixel circuit). According to an embodiment, the repair line DML may be omitted.

[0100] The eleventh conductive pattern BML11, the twelfth conductive pattern BML12, and the repair line DML may include a conductive material. For example, the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and / or alloys thereof. The eleventh conductive pattern BML11, the twelfth conductive pattern BML12, and the repair line DML may have a single-layer, double-layer, or multi-layer structure.

[0101] The buffer layer BFL may be provided on the substrate SUB to cover the eleventh conductive pattern BML11, the twelfth conductive pattern BML12, and the repair line DML. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). The buffer layer BFL may be provided as a single layer, but may be provided as a multilayer of at least two layers. In the case where the buffer layer BFL is provided as a multilayer, each layer may be formed of the same material or different materials.

[0102] The second conductive pattern BML2 may be disposed on the buffer layer BFL and may overlap the eleventh conductive pattern BML11 and the twelfth conductive pattern BML12. The second conductive pattern BML2 may be disposed in an island shape. The second conductive pattern BML2 may include a conductive material.

[0103] like Figure 7 and Figure 8 As shown in , the second conductive pattern BML2 may overlap with the eleventh conductive pattern BML11 and configure the second capacitor Chold. For example, the second capacitor Chold may be formed between the second conductive pattern BML2 and the eleventh conductive pattern BML11. The second conductive pattern BML2 may overlap with the first semiconductor pattern SCL1 and may configure the lower electrode of the first transistor T1. The second conductive pattern BML2 may overlap with the twelfth conductive pattern BML12 and configure the first sub-capacitor Cst1. The first sub-capacitor Cst1 may configure the first capacitor Cst together with the second sub-capacitor Cst2 and the third sub-capacitor Cst3. The capacitance (or capacity) of the first capacitor Cst may be increased or maximized.

[0104] The first gate insulating layer GI1 may be disposed on the second conductive pattern BML2. The first gate insulating layer GI1 may include an inorganic material. Various materials that impart insulating properties to the first gate insulating layer GI1 may be applied. For example, the first gate insulating layer GI1 may include an organic material. The first gate insulating layer GI1 may be provided as a single layer, but may also be provided as a multilayer of at least a double layer.

[0105] The semiconductor patterns SCL1 to SCL4 may be disposed on the first gate insulating layer GI1. The semiconductor patterns SCL1 to SCL4 may be semiconductor patterns formed of amorphous silicon, polycrystalline silicon, low temperature polycrystalline silicon, an oxide semiconductor, an organic semiconductor, and / or the like.

[0106] The first semiconductor pattern SCL1 may extend in the second direction DR2. The first semiconductor pattern SCL1 overlapping the first capacitor electrode CE1 may configure a channel region of the first transistor T1, and the first semiconductor pattern SCL1 overlapping the emission control line ECL may configure a channel region of the fifth transistor T5. The channel region may be, for example, a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. A region other than the channel region (for example, a remaining region of the first semiconductor pattern SCL1) may be a semiconductor pattern doped with impurities.

[0107] The second semiconductor pattern SCL2 may be positioned on an upper side of the first semiconductor pattern SCL1. The second semiconductor pattern SCL2 overlapping the second gate electrode GE2 may configure a channel region of the second transistor T2, and the second semiconductor pattern SCL2 overlapping the second scan line SL2 may configure a channel region of the third transistor T3.

[0108] The third semiconductor pattern SCL3 and the fourth semiconductor pattern SCL4 may be positioned on the lower side of the first semiconductor pattern SCL1. The third semiconductor pattern SCL3 overlapping the third scan line SL3 may configure a channel region of the fourth transistor T4. The fourth semiconductor pattern SCL4 overlapping the second emission control line ECL2 may configure a channel region of the sixth transistor T6, and the fourth semiconductor pattern SCL4 overlapping the third scan line SL3 may configure a channel region of the seventh transistor T7. According to an embodiment, for example, in Figure 2 In the sub-pixel SPXL, the fourth semiconductor pattern SCL4 may be omitted.

[0109] The second gate insulating layer GI2 may be disposed on the semiconductor patterns SCL1 to SCL4. The second gate insulating layer GI2 may include an inorganic material or an organic material, and may be provided as a single layer or a multi-layer.

[0110] The first capacitor electrode CE1 (or the first gate electrode GE1), the second gate electrode GE2, the first scan line SL1, the transverse reference power line RFL_H, the second scan line SL2, the emission control line ECL, the first bridge pattern BRP1, the second emission control line ECL2, the third scan line SL3, the transverse initialization power line INL_H and the second initialization power line INL2 may be arranged on the second gate insulating layer GI2 (or the first gate insulating layer GI1). The first capacitor electrode CE1, the second gate electrode GE2, the first scan line SL1, the transverse reference power line RFL_H, the second scan line SL2, the emission control line ECL, the first bridge pattern BRP1, the second emission control line ECL2, the third scan line SL3, the transverse initialization power line INL_H and the second initialization power line INL2 may include a conductive material.

[0111] The first capacitor electrode CE1 may overlap the second conductive pattern BML2. Most of the first capacitor electrode CE1 may overlap the second conductive pattern BML2. The first capacitor electrode CE1 overlapping the first semiconductor pattern SCL1 may configure a gate electrode of the first transistor T1.

[0112] like Figure 7 and Figure 8 As shown in FIG. 1 , the first capacitor electrode CE1 may overlap the second conductive pattern BML2 and form a second sub-capacitor Cst2. The first capacitor electrode CE1 may be connected to the twelfth conductive pattern BML12 through the first opening OP1 passing through the second conductive pattern BML2. Accordingly, the second sub-capacitor Cst2 and the first sub-capacitor Cst1 may be connected to each other in parallel.

[0113] The second gate electrode GE2 may overlap the second semiconductor pattern SCL2 and configure a gate electrode of the second transistor T2 .

[0114] The first bridge pattern BRP1 may overlap the eleventh conductive pattern BML11 and may be connected to the eleventh conductive pattern BML11 through a contact hole.

[0115] The first scan line SL1, the transverse reference power line RFL_H, the second scan line SL2, the emission control line ECL, the second emission control line ECL2, the third scan line SL3, the transverse initialization power line INL_H and the second initialization power line INL2 may extend in the first direction DR1 and may be arranged along the second direction DR2.

[0116] The first scan line SL1 may be electrically connected to the second gate electrode GE2 through the second bridge pattern BRP2.

[0117] The transverse reference power line RFL_H may be connected to the upper end of the second semiconductor pattern SCL2 through the third bridge pattern BRP3. For example, the transverse reference power line RFL_H may be electrically connected to the electrode of the third transistor T3.

[0118] The second scan line SL2 may overlap the second semiconductor pattern SCL2 and configure a gate electrode of the third transistor T3 .

[0119] The emission control line ECL may overlap the first semiconductor pattern SCL1 and configure a gate electrode of the fifth transistor T5 .

[0120] The emission control line ECL may overlap the first semiconductor pattern SCL1 and configure a gate electrode of the fifth transistor T5 .

[0121] The second emission control line ECL2 may overlap the fourth semiconductor pattern SCL4 and configure a gate electrode of the sixth transistor T6 .

[0122] The third scan line SL3 may overlap the fourth semiconductor pattern SCL4 and may configure a gate electrode of the seventh transistor T7. The third scan line SL3 may overlap the third semiconductor pattern SCL3 and configure a gate electrode of the fourth transistor T4.

[0123] The transverse initialization power line INL_H may be connected to the lower end of the third semiconductor pattern SCL3 through the fourth bridge pattern BRP4. For example, the transverse initialization power line INL_H may be electrically connected to the electrode of the fourth transistor T4.

[0124] The second initialization power line INL2 may be connected to the lower end of the fourth semiconductor pattern SCL4 through the seventh bridge pattern BRP7. For example, the second initialization power line INL2 may be electrically connected to the electrode of the seventh transistor T7.

[0125] The first interlayer insulating layer ILD1 may be disposed on the first capacitor electrode CE1, the second gate electrode GE2, the first scan line SL1, the transverse reference power line RFL_H, the second scan line SL2, the emission control line ECL, the first bridge pattern BRP1, the second emission control line ECL2, the third scan line SL3, the transverse initialization power line INL_H, and the second initialization power line INL2. The first interlayer insulating layer ILD1 may include an inorganic material or an organic material and may be provided as a single layer or a multilayer.

[0126] The second capacitor electrode CE2, the data line DL, the second bridge pattern BRP2, the third bridge pattern BRP3, the fourth bridge pattern BRP4, the fifth bridge pattern BRP5, the sixth bridge pattern BRP6, the seventh bridge pattern BRP7, and the dummy bridge pattern BRPD may be arranged on the first interlayer insulating layer ILD1. The second capacitor electrode CE2, the data line DL, the second bridge pattern BRP2, the third bridge pattern BRP3, the fourth bridge pattern BRP4, the fifth bridge pattern BRP5, the sixth bridge pattern BRP6, the seventh bridge pattern BRP7, and the dummy bridge pattern BRPD may include a conductive material.

[0127] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1. Most of the first capacitor electrode CE1 may overlap the second capacitor electrode CE2. The second capacitor electrode CE2 may extend in the second direction DR2 and may be connected to the upper end of the third semiconductor pattern SCL3 and the upper end of the fourth semiconductor pattern SCL4 through the contact hole. For example, the second capacitor electrode CE2 may be electrically connected to the electrode of the fourth transistor T4 and the electrode of the sixth transistor T6.

[0128] like Figure 7 and Figure 8 As shown in , the second capacitor electrode CE2 may overlap with the first capacitor electrode CE1 and form a third sub-capacitor Cst3. The second capacitor electrode CE2 may be connected to the first semiconductor pattern SCL1 (or the source region of the first semiconductor pattern SCL1) through the second opening OP2 passing through the first capacitor electrode CE1. For example, the second capacitor electrode CE2 may be electrically connected to an electrode (e.g., a source electrode) of the first transistor T1.

[0129] The second capacitor electrode CE2 may be connected to the second conductive pattern BML2 through the second opening OP2. Accordingly, the third sub-capacitor Cst3 and the second sub-capacitor Cst2 may be connected to each other in parallel.

[0130] The data line DL may extend in the second direction DR2 and may be repeatedly arranged along the first direction DR1. The data line DL may be connected to the left end of the second semiconductor pattern SCL2 through a contact hole. For example, the data line DL may be electrically connected to an electrode of the second transistor T2.

[0131] In an embodiment, the data line DL may not include a bent portion and may have a constant line width along the second direction DR2. In order to prevent the data line DL from affecting adjacent components, the data line DL may have a partially bent shape, but in this case, the resistance of the data line DL may increase. In an embodiment of the present disclosure, since the data line DL and the adjacent component (e.g., the first transistor T1) are shielded by the eleventh conductive pattern BML11 and the power line (e.g., the first power line PL1 or the like), the data line DL may not include a bent portion.

[0132] The second bridge pattern BRP2 may overlap the first scan line SL1 and the second gate electrode GE2 , and electrically connect the first scan line SL1 and the second gate electrode GE2 through a contact hole.

[0133] The third bridge pattern BRP3 may electrically connect the electrode of the third transistor T3 and the transverse reference power line RFL_H through the contact hole.

[0134] The fourth bridge pattern BRP4 may overlap the lateral initialization power line INL_H and the lower end of the third semiconductor pattern SCL3 and electrically connect the lateral initialization power line INL_H to the lower end of the third semiconductor pattern SCL3 (eg, the electrode of the fourth transistor T4 ) through the contact hole.

[0135] The fifth bridge pattern BRP5 may overlap the lower end of the first semiconductor pattern SCL1 and the first bridge pattern BRP1, and may be connected to the lower end of the first bridge pattern BRP1 and the first semiconductor pattern SCL1 (for example, the electrode of the fifth transistor T5). The fifth bridge pattern BRP5 may be connected to the first power line PL1 to be described later. The first power line PL1 may be electrically connected to the electrode of the fifth transistor T5 through the fifth bridge pattern BRP5, and the first power line PL1 may be electrically connected to the eleventh conductive pattern BML11 through the fifth bridge pattern BRP5 and the first bridge pattern BRP1.

[0136] The sixth bridge pattern BRP6 may overlap the second semiconductor pattern SCL2 and the first capacitor electrode CE1 , and electrically connect the second semiconductor pattern SCL2 (eg, a node between the second transistor T2 and the third transistor T3 ) and the first capacitor electrode CE1 .

[0137] The seventh bridge pattern BRP7 may overlap the lower end of the third semiconductor pattern SCL3 and the transverse initialization power line INL_H, and electrically connect the lower end of the third semiconductor pattern SCL3 (e.g., the electrode of the fourth transistor T4) to the transverse initialization power line INL_H. The seventh bridge pattern BRP7 may be connected to the initialization power line INL to be described later. The initialization power line INL may be electrically connected to the transverse initialization power line INL_H through the seventh bridge pattern BRP7.

[0138] The dummy bridge pattern BRPD may overlap with the fourth semiconductor pattern SCL4 and the repair line DML. The dummy bridge pattern BRPD may be connected to the fourth semiconductor pattern SCL4 (e.g., a node between the sixth transistor T6 and the seventh transistor T7). The dummy bridge pattern BRPD may not be connected to the repair line DML. In other embodiments, in the case where the dummy bridge pattern BRPD is connected to the repair line DML, the dummy bridge pattern BRPD may electrically connect the dummy line to the node between the sixth transistor T6 and the seventh transistor T7.

[0139] The second interlayer insulating layer ILD2 may be disposed on the second capacitor electrode CE2, the data line DL, the second bridge pattern BRP2, the third bridge pattern BRP3, the fourth bridge pattern BRP4, the fifth bridge pattern BRP5, the sixth bridge pattern BRP6, the seventh bridge pattern BRP7, and the dummy bridge pattern BRPD. The second interlayer insulating layer ILD2 may include an inorganic material or an organic material and may be provided as a single layer or a multilayer.

[0140] The first power line PL1, the initialization power line INL, the second power line PL2, the reference power line RFL and the eighth bridge pattern BRP8 may be disposed on the second interlayer insulating layer ILD2. The first power line PL1, the initialization power line INL, the second power line PL2, the reference power line RFL and the eighth bridge pattern BRP8 may include a conductive material.

[0141] The first power line PL1, the initialization power line INL, the second power line PL2, and the reference power line RFL may extend substantially in the second direction DR2, and the first power line PL1, the initialization power line INL, the second power line PL2, and the reference power line RFL may be arranged along the first direction DR1. The first power line PL1 may be arranged adjacent to the left side of the first sub-pixel SPXL1, the initialization power line INL may be arranged corresponding to the boundary between the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the second power line PL2 may be arranged corresponding to the boundary between the second sub-pixel SPXL2 and the third sub-pixel SPXL3, and the reference power line RFL may be arranged adjacent to the right side of the first sub-pixel SPXL1.

[0142] Each of the first power line PL1, the initialization power line INL, and the second power line PL2 may overlap with the data line DL and may shield the data line DL. The reference power line RFL may not overlap with the data line DL. This is because in the case where the reference power line RFL overlaps with the data line DL, the reference power voltage VREF of the reference power line RFL (and the voltage at the gate electrode of the first transistor T1 controlling the driving current) may fluctuate due to the data signal of the data line DL.

[0143] The first power line PL1 may overlap the fifth bridge pattern BRP5 and may be connected to the fifth bridge pattern BRP5 through a contact hole. The first power line PL1 may be electrically connected to the eleventh conductive pattern BML11 through the fifth bridge pattern BRP5 and the first bridge pattern BRP1. The eleventh conductive pattern BML11 and the first power line PL1 may form a mesh structure in the entire display device.

[0144] The first power line PL1 may partially overlap with the second capacitor electrode CE2. The first power line PL1 may overlap with the gate electrode (and the channel region) of the first transistor T1, shielding the gate electrode and the source electrode of the first transistor T1 (the second capacitor electrode CE2 connected to the source electrode or the source node), and preventing the gate electrode and the source electrode (or the source node) of the first transistor T1 from being affected by the signal transmission of the data line DL (refer to Figure 7 and Figure 8 ). To this end, the first power line PL1 may extend in the first direction DR1 in a region adjacent to the first transistor T1. The first power line PL1 may not overlap with the second to seventh transistors T2 to T7, but is not limited thereto.

[0145] In the region where the initialization power line INL intersects the transverse initialization power line INL_H, the initialization power line INL may be electrically connected to the transverse initialization power line INL_H through the fourth bridge pattern BRP4. The initialization power line INL and the transverse initialization power line INL_H may form a mesh structure in the entire display device.

[0146] The initialization power line INL may extend in the first direction DR1 in an area adjacent to the first transistor T1 (or the first transistor T1 of the second sub-pixel SPXL2) and partially overlap with the second capacitor electrode CE2. For example, the initialization power line INL may partially overlap with the second capacitor electrode CE2 of the first sub-pixel SPXL1 (for example, the remaining portion of the second capacitor electrode CE2 not covered by the first power line PL1). For example, the second capacitor electrode CE2 of the first sub-pixel SPXL1 may be substantially shielded by the initialization power line INL and the first power line PL1. Similar to the first power line PL1, the initialization power line INL may partially overlap with the second capacitor electrode CE2 of the second sub-pixel SPXL2.

[0147] Similar to the first power line PL1 and the initialization power line INL, the second power line PL2 may partially overlap with the second capacitor electrode CE2. For example, the second power line PL2 may overlap with the second capacitor electrode CE2 of the second sub-pixel SPXL2 (e.g., the remaining portion of the second capacitor electrode CE2 not covered by the initialization power line INL). For example, the second capacitor electrode CE2 of the second sub-pixel SPXL2 may be substantially shielded by the second power line PL2 and the initialization power line INL. The second power line PL2 may partially overlap with the second capacitor electrode CE2 of the third sub-pixel SPXL3.

[0148] In the area where the reference power line RFL intersects with the transverse reference power line RFL_H, the reference power line RFL may be electrically connected to the transverse reference power line RFL_H by a bridge pattern (e.g., a bridge pattern corresponding to the third bridge pattern BRP3). The reference power line RFL and the transverse reference power line RFL_H may form a mesh structure in the entire display device. The reference power line RFL may overlap with the second capacitor electrode CE2 of the third sub-pixel SPXL3 (e.g., the remaining portion of the second capacitor electrode CE2 not covered by the second power line PL2). For example, the second capacitor electrode CE2 of the third sub-pixel SPXL3 may be substantially shielded by the reference power line RFL and the second power line PL2.

[0149] The eighth bridge pattern BRP8 may overlap with the dummy bridge pattern BRPD. The eighth bridge pattern BRP8 may be electrically connected to the fourth semiconductor pattern SCL4 (eg, a node between the sixth transistor T6 and the seventh transistor T7) through the dummy bridge pattern BRPD. The eighth bridge pattern BRP8 may be connected to the light emitting element (refer to Figure 8 and Fig. 9 For example, the eighth bridge pattern BRP8 may electrically connect the light emitting element to a node between the sixth transistor T6 and the seventh transistor T7.

[0150] The protective layer PSV may be disposed on the first power line PL1, the initialization power line INL, the second power line PL2, the reference power line RFL, and the eighth bridge pattern BRP8. The protective layer PSV may include an organic material and / or an inorganic material. For example, the organic material may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and / or benzocyclobutene resin.

[0151] The light emitting element may be arranged on the protective layer PSV.

[0152] In the embodiment, in the first subpixel SPXL1, the first light emitting element LD1 may be disposed on the protective layer PSV and may be an organic light emitting diode. The first light emitting element LD1 may include a first pixel electrode AND (or anode electrode), an emission layer EML and a second pixel electrode CAD (or cathode electrode).

[0153] The first pixel electrode AND may be disposed on the protective layer PSV. The first pixel electrode AND may be electrically connected to the eighth bridge pattern BRP8 (refer to Fig. 9 ).

[0154] The pixel defining layer PDL may include an opening, and at least a portion of the first pixel electrode AND may be exposed through the opening. The pixel defining layer PDL may include an organic material.

[0155] The emission layer EML may be disposed on the first pixel electrode AND, and the second pixel electrode CAD may be disposed on the emission layer EML.

[0156] At least one of the first pixel electrode AND and the second pixel electrode CAD may be a transmissive electrode. For example, when the display device is a front surface emission type display device, the first pixel electrode AND may be a reflective electrode, and the second pixel electrode CAD may be a transmissive electrode.

[0157] The emission layer EML may be arranged on the exposed surface of the first pixel electrode AND. The emission layer EML may have a multilayer thin film structure including at least a light generating layer. For example, the emission layer EML may include a hole injection layer for injecting holes, a hole transport layer having excellent hole transport properties and for increasing the chance of recombination of holes and electrons by suppressing the movement of unbound electrons in the light generating layer, a light generating layer for emitting light by recombination of injected electrons and holes, a hole blocking layer for suppressing the movement of unbound holes in the light generating layer, an electron transport layer for smoothly transporting electrons to the light generating layer, and an electron injection layer for injecting electrons.

[0158] The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may each be a common layer connected in sub-pixels (or sub-pixel regions) adjacent to each other.

[0159] The second pixel electrode CAD may be arranged on the emission layer EML. The second pixel electrode CAD may be a transflective layer. For example, the second pixel electrode CAD may be a thin metal layer having a thickness sufficient to transmit light. The second pixel electrode CAD may transmit a portion of the light generated in the light generation layer and reflect the rest of the light generated in the light generation layer.

[0160] A portion of the light emitted from the emission layer EML may not pass through the second pixel electrode CAD, and the light reflected from the second pixel electrode CAD may be reflected again from the first pixel electrode AND. For example, the light emitted from the emission layer EML may resonate between the first pixel electrode AND and the second pixel electrode CAD. The light extraction efficiency of the first light emitting element LD1 may be improved by the resonance of the light.

[0161] A thin film encapsulation layer TFE may be disposed on the first light emitting element LD1 .

[0162] The thin film encapsulation layer TFE may be disposed on the second pixel electrode CAD. The thin film encapsulation layer TFE may be commonly disposed in the sub-pixel SPXL. The thin film encapsulation layer TFE may directly cover the second pixel electrode CAD.

[0163] The thin film encapsulation layer TFE may include a first inorganic layer, an organic layer, and a second inorganic layer stacked on one another on the second pixel electrode CAD.

[0164] As described above, the eleventh conductive pattern BML11 may be arranged under the data line DL and the second conductive pattern BML2, and the eleventh conductive pattern BML11 may shield the data line DL and the second conductive pattern BML2 (or the source node). The first power line PL1, the initialization power line INL, and the second power line PL2 may be arranged on the second capacitor electrode CE2, and may shield the data line DL and the second capacitor electrode CE2 (or the source node). Therefore, an accurate data signal may be maintained between the gate electrode and the source electrode of the first transistor T1, the sub-pixel may accurately emit light having a target brightness, and the display quality of the display device may be improved.

[0165] Figures 4 to 8 The embodiments can also be applied to Figure 2 For example, in Figures 4 to 8 In the embodiment of the present invention, by removing the sixth transistor T6 and the seventh transistor T7 (as well as the second initialization power line VAINT and the second control line EMB), it is possible to achieve Figure 3 Sub-pixel SPXL.

[0166] Fig. 9 It is shown Figure 1 Schematic plan view of an embodiment of a sub-pixel.

[0167] Reference Figure 4 , Figure 8 and Fig. 9 , except for the light emitting elements LD1 to LD3, Fig. 9 The sub-pixels SPXL1 to SPXL3 can be connected with Figure 4 The sub-pixels SPXL1 to SPXL3 are substantially the same, and therefore overlapping descriptions will not be repeated.

[0168] The first light emitting element LD1 may overlap with the second capacitor electrode CE2 of the first sub-pixel SPXL1. Figure 8 ) may be connected to the eighth bridge pattern BRP8 of the first sub-pixel SPXL1.

[0169] In the area where the first light emitting element LD1 and the second capacitor electrode CE2 of the first sub-pixel SPXL2 overlap, most of the second capacitor electrode CE2 may be covered or shielded by the first power line PL1 and the initialization power line INL. The first power line PL1 and the initialization power line INL may shield the first light emitting element LD1 (or the anode electrode of the first light emitting element LD1) based on the data line DL.

[0170] The second light emitting element LD2 may be disposed on the lower side of the first light emitting element LD1. The second light emitting element LD2 (or the first pixel electrode AND of the second light emitting element LD2, refer to Figure 8 ) may be connected to a bridge pattern of the second sub-pixel SPXL2 (eg, a bridge pattern corresponding to the eighth bridge pattern BRP8).

[0171] The third light emitting element LD3 may partially overlap with the pixel circuit of the second sub-pixel SPXL2 and the pixel circuit of the third sub-pixel SPXL3. The second power line PL2 may be arranged under the third light emitting element LD3, and the second power line PL2 may cover or shield the configuration (e.g., the first transistor and the storage capacitor) under the third light emitting element LD3. Based on the data line DL, the second power line PL2 may shield the third light emitting element LD3 (or the anode electrode of the third light emitting element LD3).

[0172] Fig. 9 The arrangement of the light emitting elements LD1 to LD3 shown in FIG. 1 is an example and is not limited to Fig. 9 , and the arrangement of the light emitting elements LD1 to LD3 may be variously changed. For example, each of the light emitting elements LD1 to LD3 may be arranged on a pixel circuit of a corresponding sub-pixel.

[0173] Fig.10 is a schematic cross-sectional view showing a comparative example of a sub-pixel. Fig.10 Corresponds to Figure 7 .and Figure 4 Like components are assigned like reference numerals, and overlapping descriptions are not repeated.

[0174] Reference Figure 7 and Fig.10 , Fig.10The sub-pixel SPXL_C may include a first conductive pattern BML1_C, a second conductive pattern BML2_C, a second capacitor electrode CE2, a data line DL, and a first power line PL1_C.

[0175] The second conductive pattern BML2_C and the first capacitor electrode CE1 spaced apart via the buffer layer BFL and the second gate insulating layer GI2 may configure a second capacitor Cst2_C. The first capacitor electrode CE1 and the second capacitor electrode CE2 may configure a third capacitor Cst3_C. The second capacitor electrode CE2 and the second conductive pattern BML2 may be electrically connected, and the second capacitor Cst2_C and the third capacitor Cst3_C may be connected in parallel.

[0176] The first conductive pattern BML1_C may be arranged at the same layer as the second conductive pattern BML2_C. The second conductive pattern BML2_C may not be shielded by the first conductive pattern BML1_C. Therefore, the second conductive pattern BML2_C (or source node) may be connected to the data line DL or be affected by signal transmission of the data line DL.

[0177] The first power line PL1_C may be arranged on the data line DL, but may not overlap with the second capacitor electrode CE2. The second capacitor electrode CE2 may not be shielded by the first power line PL1_C. Therefore, the second capacitor electrode CE2 (or source node) of the subpixel SPXL_C may be connected to the data line DL or be affected by the signal transmission of the data line DL.

[0178] and Fig.10 Compared with the sub-pixel SPXL_C, in the first sub-pixel SPXL1 (refer to Figure 7 and Figure 8 ), the eleventh conductive pattern BML11 may be arranged under the second conductive pattern BML2, and the second conductive pattern BML2 (e.g., the source node) may be shielded by the eleventh conductive pattern BML11. Since the twelfth conductive pattern BML12 arranged on the same layer as the eleventh conductive pattern BML11 configures the first sub-capacitor Cst1, the capacitance of the first capacitor Cst may be increased or maximized. In addition, the first power line PL1 and the initialization power line INL (the second power line PL2 and the reference power line RFL) may also be arranged on the second capacitor electrode CE2, and the second capacitor electrode CE2 (or the source node) may be shielded. Therefore, the first transistor (or the source node) may be prevented from being affected (or coupled) by the signal transmission of the data line DL adjacent to the first transistor (or the source node), and an accurate data signal may be written and maintained between the gate electrode and the source electrode of the first transistor, and the sub-pixel may accurately emit light with a target brightness.

[0179] Embodiments have been disclosed herein, and although terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Accordingly, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: A pixel, the pixel being electrically connected to a first power line, a second power line and a data line, the pixel comprising: a first transistor; and a capacitor electrically connected between a gate electrode of the first transistor and an electrode of the first transistor, Among them, in the plan view: The data line extends in a second direction, The first power supply line extends in a first direction intersecting the second direction and overlaps the data line and the gate electrode of the first transistor, and The second power line extends in the second direction, overlaps the data line, and overlaps the gate electrode of the first transistor.

2. The display device according to claim 1, wherein: In a plan view, each of the first power line and the second power line overlaps a channel region of the first transistor.

3. The display device according to claim 2, wherein: The first power supply line extends in the second direction in a region adjacent to the first transistor in a plan view.

4. The display device according to claim 2, wherein: The second power supply line extends in the first direction in a region adjacent to the first transistor in a plan view.

5. The display device according to claim 1, wherein: The first power line and the second power line are electrically connected to each other, and A constant voltage is applied to the first power line and the second power line.

6. The display device according to claim 1, wherein: The first power line and the second power line are electrically separated from each other, and Different constant voltages are applied to the first power line and the second power line.

7. The display device according to claim 1, wherein: The pixel further includes a second transistor electrically connected between the data line and the gate electrode of the first transistor, and In a plan view, each of the first power supply line and the second power supply line does not overlap with the second transistor.

8. The display device according to claim 1, wherein: The capacitor comprises: a first electrode, wherein the first electrode and the first power line are arranged in the same layer; a second electrode, the second electrode being arranged on the first electrode; a third electrode, the third electrode and the gate electrode of the first transistor being arranged at the same layer; and A fourth electrode is disposed on the third electrode and is electrically connected to the electrode of the first transistor.

9. The display device according to claim 8, wherein: A first capacitor is arranged between the first electrode and the second electrode, A second capacitor is arranged between the second electrode and the third electrode, A third capacitor is arranged between the third electrode and the fourth electrode, and The first capacitor, the second capacitor, and the third capacitor are electrically connected in parallel with each other to configure the capacitor.

10. The display device according to claim 8, wherein: The third electrode is electrically connected to the first electrode through a first opening arranged in the second electrode, and The fourth electrode is electrically connected to the second electrode through a second opening disposed in the third electrode.

11. The display device according to claim 8, wherein: In a plan view, the second electrode of the capacitor overlaps with the semiconductor layer of the first transistor, and The second electrode of the capacitor configures a lower electrode of the first transistor.

12. The display device according to claim 11, wherein: The pixel further includes a holding capacitor disposed between the first power supply line and the second electrode of the capacitor.

13. The display device according to claim 8, wherein: The data line and the fourth electrode are arranged on the same layer, and The second power line is arranged on the fourth electrode.

14. The display device according to claim 13, wherein: The pixel also includes a light emitting element, and The second power supply line is arranged between the capacitor and the anode electrode of the light emitting element and shields the capacitor.

15. A display device, comprising: a pixel, wherein the pixel is electrically connected to a first power line, a second power line, a third power line and a data line, Wherein, the pixels include: a first transistor; and a capacitor disposed between a gate electrode of the first transistor and an electrode of the first transistor, In a plan view, the first power line extends in a first direction, and the data line, the second power line, and the third power line extend in a second direction intersecting the first direction, and In a plan view, the data line and the capacitor are covered by the first power line, the second power line, and the third power line.

16. The display device according to claim 15, wherein: The second power line and the third power line are arranged on the same layer, In a plan view, the second power line overlaps a portion of the capacitor, and the third power line overlaps a remaining portion of the capacitor.

17. The display device according to claim 16, wherein: The first power line and the second power line are electrically connected to each other, and A constant voltage is applied to the first power line and the second power line.

18. The display device according to claim 15, wherein: The capacitor comprises: a first electrode, wherein the first electrode and the first power line are arranged in the same layer; a second electrode, the second electrode being arranged on the first electrode; a third electrode, the third electrode and the gate electrode of the first transistor being arranged at the same layer; and A fourth electrode is disposed on the third electrode and is electrically connected to the electrode of the first transistor.

19. The display device according to claim 18, wherein: The third electrode is electrically connected to the first electrode through a first opening arranged in the second electrode, and The fourth electrode is electrically connected to the second electrode through a second opening disposed in the third electrode.

20. The display device according to claim 18, wherein: The data line and the fourth electrode are arranged on the same layer, and The second power line is arranged on the fourth electrode.

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