Methods and operations for writing and reading data in memory devices

Abstract

In a method for writing data to a memory device, a plurality of copied bit rows are generated by performing a first copy operation, in which multiple bits included in the data to be written are copied bit by bit. A plurality of copied bit groups are generated by performing a second copy operation, in which the plurality of copied bit rows are copied row by row. The plurality of copied bit groups are respectively stored in a plurality of memory regions included in the memory device. Each of the plurality of memory regions is a region that is sensed simultaneously during a data read operation.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0168037, filed on December 16, 2019, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to methods for writing data to a memory device, methods for reading data from a memory device, and methods for operating a memory device including the methods of writing and reading data. Background Technology

[0004] Semiconductor memory devices are generally classified into two categories based on whether they retain stored data when power is off. These categories include volatile memory devices, which lose stored data when power is off, and non-volatile memory devices, which retain stored data when power is off. Data write and / or read operations on volatile memory devices can differ from those on non-volatile memory devices.

[0005] Recently, error-correcting code (ECC) encoding and / or decoding have been performed in both volatile and non-volatile memory devices to ensure or guarantee data integrity. However, ECC encoding and / or decoding increase the time required for data write and / or read operations, and when using ECC processing located outside the memory device (e.g., typically in the memory controller), there is a burden on data input / output (I / O), reduced performance efficiency, and increased cost. Summary of the Invention

[0006] At least one example embodiment of this disclosure provides a method for writing data to a memory device and a method for reading data from a memory device, which can ensure data integrity without reducing response speed or increasing cost.

[0007] At least one example embodiment of this disclosure provides a method for operating a memory device, including a method for writing data and a method for reading data.

[0008] According to an example embodiment, in a method of writing data to a memory device, a plurality of copied bit rows are generated by performing a first copy operation, in which a plurality of bits included in the data to be written are copied bit by bit. A plurality of copied bit groups are generated by performing a second copy operation, in which the plurality of copied bit rows are copied row by row. The plurality of copied bit groups are respectively stored in a plurality of memory regions included in the memory device. Each of the plurality of memory regions is a region that is sensed simultaneously during a data read operation.

[0009] According to an example embodiment, in a method for reading data from a memory device, when read data comprising a plurality of bits is written according to a scheme in which the plurality of bits are copied bit by bit to generate a plurality of copy bit rows, the plurality of copy bit rows are copied row by row to generate a plurality of copy bit groups, and the plurality of copy bit groups are respectively stored in a plurality of memory regions included in the memory device, each of the plurality of copy bit groups is simultaneously sensed. A first error correction based on majority sensing is performed on the sensing results of the plurality of copy bit groups to obtain a plurality of copy bit rows.

[0010] According to an example embodiment, in a method of operating a memory device, a data write operation is performed, in which first data is double-copied and the double-copied first data is stored. A data read operation is performed, in which the double-copied first data is retrieved. When the data write operation is performed, a first copy bit row is generated by performing a first copy operation, in which the first bit included in the first data is copied bit by bit. A first copy bit group is generated by performing a second copy operation, in which the first copy bit row is copied row by row. The first copy bit group is stored in a first memory region. The first memory region is connected to the same bit line and is a region that is simultaneously sensed during the data read operation. When the data read operation is performed, the first copy bit group is simultaneously sensed. A first copy bit row is obtained by performing a first error correction based on majority sensing on the sensing result of the first copy bit group. When the first copy bit row is obtained, a bit of the first copy bit row is obtained as a first value when the first sensing voltage is higher than a first reference voltage. The first sensing voltage is obtained by simultaneously sensing the memory cell included in the first memory region that is connected to the first bit line and stores the first bit. When the first sensing voltage is lower than or equal to the first reference voltage, a bit of the first copy bit row is obtained as the second value.

[0011] In the methods for writing data to a memory device, reading data from a memory device, and operating a memory device according to the example embodiments, data can be written by performing a double copy operation, and data can be read based on multi-step error correction by performing majority sensing and / or additional majority voting. Therefore, data integrity can be ensured or guaranteed without external ECC, for example, without reducing response speed or increasing costs. Attached Figure Description

[0012] The illustrative, non-limiting exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a flowchart illustrating a method for writing data into a memory device according to an example embodiment.

[0014] Figure 2 This is a block diagram illustrating a memory system including a memory device according to an example embodiment.

[0015] Figure 3 This is a block diagram illustrating a memory device according to an example embodiment.

[0016] Figure 4A and Figure 4B It is shown Figure 3 A diagram illustrating an example of memory blocks included in a memory cell array in a memory device.

[0017] Figure 5 It is shown Figure 1 A flowchart illustrating a detailed example of a method for writing data to a memory device.

[0018] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B It is used to describe Figure 5 A diagram illustrating the data writing operation.

[0019] Figure 9 It is shown Figure 1 A flowchart of another detailed example of a method for writing data to a memory device.

[0020] Figure 10 This is a flowchart illustrating a method for writing data into a memory device according to an example embodiment.

[0021] Figure 11 , Figure 12A and Figure 12B It is used to describe Figure 1 and Figure 10 A diagram illustrating the method of writing data into a memory device.

[0022] Figure 13 This is a flowchart illustrating a method for reading data from a memory device according to an example embodiment.

[0023] Figure 14 It is shown Figure 13 A flowchart illustrating a detailed example of a method for reading data from a memory device.

[0024] Figure 15 It is shown Figure 14 A flowchart of an example of step S1210.

[0025] Figure 16 It is used to describe Figure 15 The diagram shows the operation.

[0026] Figure 17 It is shown Figure 14 The flowchart shows another example of step S1210.

[0027] Figure 18 It is used to describe Figure 17 The diagram shows the operation.

[0028] Figure 19 This is a diagram illustrating a method for reading data from a memory device according to an example embodiment.

[0029] Figure 20 , Figure 21 and Figure 22 This is a flowchart illustrating a method for reading data from a memory device according to an example embodiment.

[0030] Figure 23 It is shown Figure 22 The flowchart is an example of step S1300.

[0031] Figure 24 and Figure 25 It is shown Figure 23 The flowchart is an example of step S1310.

[0032] Figure 26 It is used to describe Figure 24 and Figure 25 The diagram shows the operation.

[0033] Figure 27 , Figure 28 and Figure 29 This is a flowchart illustrating a method for reading data from a memory device according to an example embodiment.

[0034] Figure 30This is a flowchart illustrating a method of operating a memory device according to an example embodiment.

[0035] Figure 31 It is used to describe Figure 30 The diagram shows the operation.

[0036] Figure 32 , Figure 33 and Figure 34 This is a diagram illustrating a matrix multiplication method using a memory device, based on an example embodiment.

[0037] Figure 35 This is a block diagram illustrating a mobile system including a memory device according to an example embodiment. Detailed Implementation

[0038] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, similar reference numerals refer to similar elements.

[0039] Figure 1 This is a flowchart illustrating a method for writing data into a memory device according to an example embodiment.

[0040] refer to Figure 1 A memory device performing a method for writing data according to an example embodiment may include a memory cell array for storing data, and data copying and rearranging circuitry for copying (e.g., duplicating or replicated) and rearranging the written data to be stored. (Refer to...) Figure 2 and Figure 3 Describe the configuration of memory devices and memory systems that include memory devices.

[0041] In a method for writing data to a memory device according to an example embodiment, a plurality of copied bit rows are generated by performing a first copy (or recopy) operation, in which a plurality of bits included in the write data are copied bit by bit (e.g., bit-by-bit, per-bit, or on a per-bit basis) (step S100). The write data may be provided along with a write command and a write address. A plurality of copied bit groups are generated by performing a second copy operation, in which a plurality of copied bit rows are copied row by row (e.g., row-by-row, per-row, or on a per-row basis) (step S200). The plurality of copied bit groups are stored respectively into a plurality of memory regions included in the memory device (step S300). Each of the plurality of memory regions is a region sensed substantially simultaneously or concurrently during a data read operation.

[0042] In the method for writing data to a memory device according to the example embodiment, a first copy operation for copying the data to be written bit by bit can be performed, a second copy operation for copying the result of the first copy operation row by row can be performed, and then multiple copied bit groups can be finally stored. By performing the above-described double-duplication operation, data integrity can be ensured or guaranteed by applying a majority-sensing and / or majority-voting error correction scheme in subsequent data read operations without the need for external error correction codes (ECC) (or by minimizing the use of external ECC). Therefore, response speed can be improved or enhanced, and processing-in-memory (PIM) or computing-in-memory (CIM) can be performed efficiently.

[0043] Figure 2 This is a block diagram illustrating a memory system including a memory device according to an example embodiment.

[0044] refer to Figure 2 The memory system 10 may include a memory controller 20 and at least one memory device 30.

[0045] In some example embodiments, such as reference Figure 3 As described, memory device 30 may be a non-volatile memory device, and memory system 10 may include flash memory-based data storage media, such as memory cards, solid-state drives (SSDs), etc. In other example embodiments, memory device 30 may be a volatile memory device.

[0046] The memory device 30 can perform read, erase, program, and / or write operations under the control of the memory controller 20. The memory device 30 can receive commands (CMD), addresses (ADDR), and data (DAT) from the memory controller 20 via input / output lines to perform such operations. Furthermore, the memory device 30 can receive control signals (CTRL) from the memory controller 20 via control lines. Additionally, the memory device 30 can receive power (PWR) from the memory controller 20 via power lines.

[0047] The memory controller 20 may include an ECC block 25. The ECC block 25 for error correction may be encoded and modulated using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc., or may use the aforementioned codes or other error-correcting codes to perform ECC encoding and decoding. In some example embodiments, ECC encoding and / or decoding may not be performed, such as... Figure 1 Methods for writing data Figure 13 Methods for reading data, etc. In other example embodiments, ECC encoding and / or decoding may be selectively performed, such as... Figure 10 Methods for writing data Figure 20 Methods for reading data, etc.

[0048] The memory device 30 may include a data copy and arrangement circuit (DDAC) 50 for performing the data writing method described above, and may include a majority sensing circuit (MSENC) 70 and a majority voting circuit (MVOTC) 80 for performing the data reading method described later. Furthermore, the memory device 30 may also include a read-write circuit (RWC) 40 and an arithmetic (or computation) circuit (OPER) 60 for performing the matrix multiplication method described later.

[0049] Figure 3 This is a block diagram illustrating a memory device according to an example embodiment.

[0050] refer to Figure 3 The memory device 500 includes a memory cell array 510, an address decoder 520, a page buffer circuit 530, a data input / output (I / O) circuit 540, a voltage generator 550, and a control circuit 560. Figure 3 The memory devices will be described using examples of non-volatile memory devices in the following figures.

[0051] Memory cell array 510 is connected to address decoder 520 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). Memory cell array 510 is also connected to page buffer circuitry 530 via multiple bit lines (BL). Memory cell array 510 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and multiple bit lines (BL). Memory cell array 510 may be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, each memory block comprising memory cells. Furthermore, each of the multiple memory blocks BLK1, BLK2, ..., BLKz may be divided into multiple pages. See reference... Figure 4A and Figure 4B As described herein, the multiple memory cells in the memory cell array 510 can be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure.

[0052] The control circuit 560 is controlled from the outside (e.g., Figure 2 The memory controller 20 receives the command CMD and the address ADDR, and controls the operation of the memory device 500 (e.g., erase, program, and read operations) based on the command CMD and the address ADDR. For example, the control circuit 560 can generate a control signal CON for controlling the voltage generator 550 and a control signal PBC for controlling the page buffer circuit 530 based on the command CMD, and can generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 560 can provide the row address R_ADDR to the address decoder 520 and the column address C_ADDR to the data I / O circuit 540.

[0053] Address decoder 520 can be connected to memory cell array 510 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0054] Voltage generator 550 can generate the voltage VS required for the operation of memory device 500 based on power PWR and control signal CON. Voltage VS can be applied to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL via address decoder 520. Furthermore, voltage generator 550 can generate the erase voltage VERS required for data erase operations based on power PWR and control signal CON. Erasing voltage VERS can be applied directly to memory cell array 510 or via bit line BL.

[0055] Page buffer circuit 530 can be connected to memory cell array 510 via multiple bit lines BL. Page buffer circuit 530 may include multiple page buffers. Page buffer circuit 530 can store data DAT to be programmed into memory cell array 510, or can read data DAT sensed from memory cell array 510.

[0056] Data I / O circuit 540 can be connected to page buffer circuit 530 via data line DL. Based on column address C_ADDR, data I / O circuit 540 can provide data DAT from outside the memory device 500 to memory cell array 510 via page buffer circuit 530, or it can provide data DAT from memory cell array 510 to outside the memory device 500 via page buffer circuit 530.

[0057] Figure 3 The data copying and placement circuit DDAC, the majority sensing circuit MSENC, the majority voting circuit MVOTC, and the arithmetic circuit OPER can respectively correspond to Figure 2 The data copying and arrangement circuit 50, the majority sensing circuit 70, the majority voting circuit 80, and the arithmetic circuit 60 are included. Figure 3 The page buffer circuit 530 in the middle can correspond to Figure 2 The read / write circuit 40 is included. In some example embodiments, such as... Figure 3 As shown, the majority sensing circuit MSENC, the data copying and placement circuit DDAC, the majority voting circuit MVOTC, and the arithmetic circuit OPER can be included in the page buffer circuit 530 and the data I / O circuit 540. In other example embodiments, although not shown in Figure 3 As shown, however, at least one of the majority sensing circuit MSENC, the data copying and placement circuit DDAC, the majority voting circuit MVOTC, and the arithmetic circuit OPER can be implemented as a separate, distinct, or differentiated component (or element) from the page buffer circuit 530 and the data I / O circuit 540.

[0058] Figure 4A and Figure 4B It is shown Figure 3 A diagram illustrating an example of memory blocks included in a memory cell array in a memory device. Figure 4A This is a circuit diagram illustrating an example of a memory block included in a NAND flash memory device. Figure 4B This is a circuit diagram illustrating an example of a memory block included in a vertical NAND flash memory device.

[0059] refer to Figure 4AThe memory block BLKi may include a string select transistor SST, a ground select transistor GST, and memory cells MC. The string select transistor SST may be connected to bit lines BL1, ..., BLm, and the ground select transistor GST may be connected to the common source line CSL. Memory cells arranged in the same row may be connected in series between one of the bit lines BL1 to BLm and the common source line CSL, and memory cells arranged in the same column may be connected together to one of the word lines WL1, WL2, ..., WL(n-1), WLn.

[0060] The serial select transistor SST can be connected to the serial select line SSL, so that the serial select transistor SST is controlled according to the level of the voltage applied from the serial select line SSL. The ground select transistor GST can be connected to the ground select line GSL, so that the ground select transistor GST is controlled according to the level of the voltage applied from the ground select line GSL. The memory cell MC can be controlled according to the level of the voltage applied to word lines WL1 to WLn.

[0061] Figure 4B The memory block BLKj can be a three-dimensional memory block formed on a substrate in a three-dimensional (or vertical) structure. For example, the memory block BLKj can include multiple vertical cell strings (e.g., NAND strings) that are vertically oriented such that at least one memory cell is located above another memory cell. The multiple vertical cell strings included in the memory block BLKj can be formed in a direction perpendicular to the substrate.

[0062] refer to Figure 4B The memory block BLKj may include multiple NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST.

[0063] Each string select transistor (SST) can be connected to a corresponding string select line (one of SSL1, SSL2, and SSL3). Multiple memory cells MC1 through MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground select transistor (GST) can be connected to a corresponding ground select line (one of GSL1, GSL2, and GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1 through BL3), and each ground select transistor (GST) can be connected to the common source line CSL.

[0064] NAND strings connected to a single bit line can form a column, and NAND strings connected to a single string select line can form a row. For example, NAND strings NS11, NS21, and NS31 connected to the first bit line BL1 can correspond to the first column, and NAND strings NS11, NS12, and NS13 connected to the first string select line SSL1 can form the first row.

[0065] A three-dimensional vertical array structure may include vertical NAND strings that are vertically oriented such that at least one memory cell is situated above another memory cell. The at least one memory cell may include a charge trapping layer. Suitable configurations of memory cell arrays including 3D vertical array structures are described in their entirety by reference to the following patent documents incorporated herein by reference: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0066] Although the memory cell array and memory block included in the memory device according to the example embodiment are described based on a NAND flash memory device, the memory device according to the example embodiment can be any non-volatile memory device, such as phase random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc., or any volatile memory device, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0067] Figure 5 It is shown Figure 1 A flowchart illustrating a detailed example of a method for writing data to a memory device. Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B It is used to describe Figure 5 A diagram illustrating the data writing operation.

[0068] refer to Figure 1 and Figure 5The write data stored in the memory device by the write data method according to the example embodiment may include the first to the nth bits, where n is a natural number greater than or equal to two. Each of the first to the nth bits may be copied m times by a first copy operation to generate a corresponding one of the first to the nth copy bit rows, where m is a natural number greater than or equal to two. Each of the first to the nth copy bit rows may be copied k times by a second copy operation to generate a corresponding one of the first to the nth copy bit groups, where k is a natural number greater than or equal to two. Each of the first to the nth copy bit groups may be stored in a corresponding one of the first to the nth memory regions included in the memory device.

[0069] For example, when multiple copy bit rows are generated by performing a first copy operation (step S100), the first copy bit row can be generated by copying the first bit m times (step S110), and the nth copy bit row can be generated by copying the nth bit m times (step S120).

[0070] When multiple copy bit groups are generated by performing the second copy operation (step S200), the first copy bit group can be generated by copying the first copy bit row k times (step S210), and the nth copy bit group can be generated by copying the nth copy bit row k times (step S220).

[0071] When multiple copied bit groups are stored in multiple memory regions respectively (step S300), the first copied bit group can be stored in the first memory region (step S310), and the nth copied bit group can be stored in the nth memory region (step S320). Therefore, each of the multiple bits included in the written data can be double-copied (or double-copyed) m*k times, and each double-copied bit can be stored in the memory device.

[0072] In some example embodiments, such as reference Figure 9 The order of the first copy operation, the second copy operation, and the storage operation can be changed, as described.

[0073] refer to Figure 6A and Figure 6B , showed Figure 5 A detailed example of data write operations.

[0074] The data DAT1 can be written from the first to the nth bit, b1, b2, ..., bn.

[0075] The first copied data DRDAT1 generated by performing a first copy operation DPO1 on the write data DAT1 may include the first copied bit row to the nth copied bit row DBR1, DBR2, ..., DBRn. The first copied bit row DBR1 may include m first bits b1, the second copied bit row DBR2 may include m second bits b2, and the nth copied bit row DBRn may include m nth bits bn. The first copy operation DPO1 may represent copying in a first direction D1. For example, the first direction D1 may be the row direction or the word line direction. The first copied data DRDAT1 may form a data unit for a data write operation.

[0076] The second copy data DGDAT1 generated by performing a second copy operation DPO2 on the first copy data DRDAT1 may include first copy bit groups to nth copy bit groups DBG1, DBG2, ..., DBGn. The first copy bit group DBG1 may include k first copy bit rows DBR1, the second copy bit group DBG2 may include k second copy bit rows DBR2, and the nth copy bit group DBGn may include k nth copy bit rows DBRn. The second copy operation DPO2 may represent copying in a second direction D2 that intersects (e.g., is perpendicular to) the first direction D1. For example, the second direction D2 may be a column direction or a bit line direction.

[0077] The first copy bit group DBG1 can be stored in a first memory region MR1, which includes memory cells connected to k word lines WL1, WL2, ..., WLk and m bit lines BL11, BL12, ..., BL1m. Similarly, the second copy bit group DBG2 can be stored in a second memory region MR2, which includes memory cells connected to k word lines WL1 to WLk and m bit lines BL21, BL22, ..., BL2m. The nth copy bit group DBGn can be stored in an nth memory region MRn, which includes memory cells connected to k word lines WL1 to WLk and m bit lines BLn1, BLn2, ..., BLnm.

[0078] In some example embodiments, each of the memory regions MR1 ​​to MRn may be a region that is sensed simultaneously during a data read operation, and may include memory cells connected to the same bit line, such as... Figure 6B As shown. When a bit is copied and stored in a memory cell connected to the same bit line, it can be efficiently executed in the reference. Figure 13 Most of the sensing will be performed in the described method of reading data.

[0079] refer to Figure 7A and Figure 7B, showed Figure 5 Another detailed example of a data write operation. (The text will omit the likely repetition.) Figure 6A and Figure 6B Repeated description.

[0080] A first copy data DRDAT1' can be generated by performing a first copy operation DPO1' on the written data DAT1. A second copy data DGDAT1' can be generated by performing a second copy operation DPO2' on the first copy data DRDAT1'. The second copy data DGDAT1' can be stored in the memory cell array.

[0081] exist Figure 6A and Figure 6B In the example, in each of the first copy data DRDAT1 and the second copy data DGDAT1, all identical bits can be arranged to be adjacent to each other. On the other hand, in Figure 7A and Figure 7B In the example, in the first copy data DRDAT1', the same bits may not be adjacent to each other, while in the second copy data DGDAT1', the same bits may be arranged to be partially adjacent to each other.

[0082] Although not shown in detail, Figure 7A The combination of the first bit b1, the combination of the second bit b2, and the combination of the nth bit bn in the first copied data DRDAT1' can represent the first copied bit row, the second copied bit row, and the nth copied bit row, respectively. Similarly, Figure 7A The combination of the first bit b1, the combination of the second bit b2, and the combination of the nth bit bn in the second copy data DGDAT1' can represent the first copy bit group, the second copy bit group, and the nth copy bit group, respectively. Figure 7B The memory cells in the memory that store the first bit b1 and are connected to bit lines BL11, BL21, ..., BLm1, the memory cells that store the second bit b2 and are connected to bit lines BL12, BL22, ..., BLm2, and the memory cells that store the nth bit bn and are connected to bit lines BL1n, BL2n, ..., BLmn can respectively represent the first memory region, the second memory region, and the nth memory region.

[0083] although Figure 6A , Figure 6B , Figure 7A and Figure 7B Multiple bits are shown being copied to have a specific arrangement, but the example embodiment is not limited to this, and the arrangement of the copied bits can be changed according to the example embodiment. Furthermore, although Figure 6B and Figure 7BThe example illustrates storing copied bits into a memory region connected to word lines and bit lines arranged sequentially or consecutively. However, the example embodiment is not limited to this, and a memory region may be connected to word lines and / or bit lines that are not arranged sequentially or consecutively (e.g., spaced apart from each other).

[0084] Furthermore, despite Figure 6A , Figure 6B , Figure 7A and Figure 7B The example illustrates performing a first copy operation in the row direction and a second copy operation in the column direction, but the example embodiment is not limited thereto. For example, multiple copied bit columns can be generated by copying multiple bits in the column direction bit by bit, and multiple copied bit groups can be generated by copying multiple copied bit columns in the row direction column by column.

[0085] refer to Figure 8A The memory cell array may include four memory blocks BLK1, BLK2, BLK3, and BLK4. Memory blocks BLK1 through BLK4 can be connected to a page buffer PGBUF via the same bit line BLa. Memory blocks BLK1 through BLK4 can be... Figure 4A memory block BLKi or Figure 4B The memory block BLKj.

[0086] Each of the multiple memory regions storing multiple replicated bit groups may include memory blocks BLK1 to BLK4 connected to the same bit line BLa, and may correspond to a portion of memory blocks BLK1 to BLK4.

[0087] For example, DUP1, DUP2, DUP3, and DUP4 can represent four copy bit rows containing the same bits. DUP1 can represent a copy bit row generated by performing a first copy operation, and DUP2, DUP3, and DUP4 can represent copy bit rows generated by performing a second copy operation based on DUP1. Copy bit row DUP1 can be stored in a memory cell connected to word line WL1a of memory block BLK1, copy bit row DUP2 can be stored in a memory cell connected to word line WL2a of memory block BLK2, copy bit row DUP3 can be stored in a memory cell connected to word line WL3a of memory block BLK3, and copy bit row DUP4 can be stored in a memory cell connected to word line WL4a of memory block BLK4. In other words, the memory cells included in memory blocks BLK1 to BLK4, connected to word lines WL1a to WL4a, and storing copy bit rows DUP1 to DUP4 can correspond to a memory region.

[0088] refer to Figure 8BThe memory block BLK0 in the memory cell array can include four subgroups (or string select groups) SG0, SG1, SG2, and SG3. Subgroup SG0 can be connected to the string select line SSL0, subgroup SG1 can be connected to the string select line SSL1, subgroup SG2 can be connected to the string select line SSL2, and subgroup SG3 can be connected to the string select line SSL3. Subgroups SG0 to SG3 can be connected to a page buffer PGBUF via the same bit line BLB. Memory block BLK0 can be Figure 4B The memory block BLKj.

[0089] Each of the multiple memory regions storing multiple replicated bit groups may include subgroups SG0 to SG3 connected to the same bit line BLb, and may correspond to a portion of subgroups SG0 to SG3.

[0090] For example, copy bit row DUP1 can be stored in a memory cell connected to word line WL1b of subgroup SG0, copy bit row DUP2 can be stored in a memory cell connected to word line WL2b of subgroup SG1, copy bit row DUP3 can be stored in a memory cell connected to word line WL3b of subgroup SG2, and copy bit row DUP4 can be stored in a memory cell connected to word line WL4b of subgroup SG3. In other words, the memory cells included in subgroups SG0 to SG3 of memory block BLK0, connected to word lines WL1b to WL4b, and storing copy bit rows DUP1 to DUP4, can correspond to a memory region.

[0091] although Figure 8A and Figure 8B A certain number of memory blocks and subgroups are shown, but the example embodiment is not limited thereto, and the number of memory blocks and / or subgroups included in a memory region can be varied according to the example embodiment.

[0092] Figure 9 It is shown Figure 1 A flowchart of another detailed example of a method for writing data to a memory device. (The remaining text is omitted.) Figure 5 Repeated description.

[0093] refer to Figure 9 In addition to Figure 9 Apart from changing the order of operations in the example, Figure 9 Examples can be compared with Figure 5 The examples are basically the same. Figure 9 Steps S110, S120, S210, S220, S310, and S320 can be respectively connected with... Figure 5 Steps S110, S120, S210, S220, S310, and S320 are basically the same.

[0094] In Figure 5 examples, the first copy operation may be performed sequentially on all bits of the written data, the second copy operation may be performed sequentially on all copied bit rows after the first copy operation is completed, and all copied bit groups may be stored sequentially after the second copy operation is completed. On the other hand, in Figure 9 examples, the first copy operation, the second copy operation, and the storage operation are performed sequentially on the first bit of the written data, and then the first copy operation, the second copy operation, and the storage operation may be performed sequentially on the second bit of the written data. Finally, the first copy operation, the second copy operation, and the storage operation may be performed sequentially on the nth bit of the written data.

[0095] Figure 10 is a flowchart showing a method of writing data in a memory device according to an exemplary embodiment. Descriptions that are repeated with Figure 1 will be omitted.

[0096] Referring to Figure 10 , except that step S500 is added to Figure 10 examples, Figure 10 examples may be substantially the same as Figure 1 examples.

[0097] Before performing the first copy operation and the second copy operation, ECC bits may be generated by performing ECC encoding on the written data (e.g., raw data) (step S500). When the error correction scheme of majority sensing and / or majority voting fails in the method of reading data to be described with reference to Figure 20 etc., the ECC bits may be used to recover the data. For example, the ECC encoding may be performed by a memory controller (e.g., Figure 2 memory controller 20 in).

[0098] Figure 10 Steps S100 and S200 after step S500 in Figure 1 may be substantially the same as steps S100 and S200 in Figure 10 . Except that the ECC bits are stored together with multiple copied bit groups, Figure 1 step S300a in

[0099] Figure 11 , Figure 12A and Figure 12B are diagrams for describing Figure 1 and Figure 10 methods of writing data in a memory device.

[0100] Referring to Figure 11 , when performing Figure 10In this method, the first copy data DRDAT1 generated by performing a first copy operation on the write data DAT1 and the ECC bit EB1 generated by performing ECC encoding on the write data DAT1 can form a data unit (e.g., a sector SEC1) for the data write operation.

[0101] refer to Figure 12A When executing Figure 1 In this method, multiple write data can be provided. Each of the multiple first copy data DRDAT1, DRDAT2, DRDAT3, and DRDAT4 generated by performing a first copy operation on the multiple write data can form a data unit for the data write operation.

[0102] refer to Figure 12B When executing Figure 10 In this method, multiple write data can be provided. One of the multiple first copy data DRDAT1, DRDAT2, DRDAT3, and DRDAT4 generated by performing a first copy operation on the multiple write data, and a corresponding one of the ECC bits EB1, EB2, EB3, and EB4 generated by performing ECC encoding on the multiple write data, can form a corresponding one of the multiple sectors SEC1, SEC2, SEC3, and SEC4.

[0103] Figure 13 This is a flowchart illustrating a method for reading data from a memory device according to an example embodiment.

[0104] refer to Figure 13 A memory device performing a method for reading data according to an example embodiment may include a memory cell array for storing data, and majority sensing circuitry for performing majority sensing on the read data to be read or retrieved. The configuration of the memory device and the memory system including the memory device may be consistent with reference to... Figure 2 and Figure 3 The descriptions are basically the same.

[0105] In the method for reading data from a memory device according to an example embodiment, when based on Figure 1 The method for writing data can be executed when writing or storing / reading data. Figure 13 The method for reading data. In other words, when read data comprising multiple bits is written according to a scheme in which multiple bits are copied bit by bit to generate multiple rows of duplicate bits, multiple rows of duplicate bits are copied row by row to generate multiple groups of duplicate bits, and multiple groups of duplicate bits are stored respectively in multiple memory regions included in the memory device, the following can be performed. Figure 13 The method for reading data.

[0106] Simultaneously sense each of the multiple replicated bit groups (step S110). Obtain multiple replicated bit rows by performing a first error correction based on majority sensing on the sensing results of the multiple replicated bit groups (step S1200). Steps S1100 and S1200 can be performed when a read command and read address are provided or received. For example, when the same bit is copied (or duplicated) and stored in multiple memory cells connected to the same bit line, the above-described simultaneous sensing and majority sensing can be performed on a bit line basis (e.g., bit line by bit or bit line by bit line). (Refer to...) Figures 14 to 19 Describe in detail simultaneous sensing and multiple sensing.

[0107] In the method for reading data from a memory device according to the example embodiment, each bit of the copied bit row can be obtained by performing majority sensing on the read data written via a double copy operation. By performing the aforementioned majority sensing, data integrity can be ensured or guaranteed without external ECC. Therefore, response speed can be improved or enhanced, and in-memory processing or in-memory computation can be performed efficiently.

[0108] Figure 14 It is shown Figure 13 A flowchart illustrating a detailed example of a method for reading data from a memory device. (The remaining text is omitted.) Figure 5 and Figure 9 Repeated description.

[0109] refer to Figure 6A , Figure 6B , Figure 13 and Figure 14 The read data read from or retrieved from the memory device by the method of reading data according to the example embodiment can be referred to Figures 5 to 9 The described method of writing or storing data. For example, reading data may include the first to the nth bit, the first copy bit row may be generated by copying the first bit m times, the first copy bit group may be generated by copying the first copy bit row k times, and the first copy bit group may be stored in a first memory area. Figure 14 This illustrates the operation of obtaining the first copy row by performing majority sensing on the first copy bit group.

[0110] For example, when sensing each of multiple replica bit groups simultaneously (step S1100), the first bit b1 stored in the memory cell connected to the first bit line BL11 among the multiple first bit b1 included in the first replica bit group DBG1 stored in the first memory region MR1 can be sensed simultaneously or concurrently (step S1110). When multiple replica bit rows are obtained by performing first error correction based on majority sensing (step S1200), a bit (e.g., the foremost bit or the first bit) of the first replica bit row DBR1 can be obtained (e.g., read) based on the first sensing voltage (step S1210). The first sensing voltage can be obtained by simultaneously sensing the memory cell connected to the first bit line BL11 and storing the first bit b1.

[0111] Similarly, the first bit b1 stored in the memory cell connected to the m-th bit line BL1m can be sensed simultaneously (step S1120), and another bit (e.g., the last bit or the m-th bit) of the first copy bit row DBR1 can be obtained based on the m-th sensed voltage (step S1220). The m-th sensed voltage can be obtained by simultaneously sensing the memory cell connected to the m-th bit line BL1m and storing the first bit b1.

[0112] although Figure 14 Only the operation of obtaining the first copy bit row DBR1 by performing majority sensing on the first copy bit group DBG1 is shown, but each of the operations of obtaining the second copy bit row DBR2 by performing majority sensing on the second copy bit group DBG2 and obtaining the nth copy bit row DBRn by performing majority sensing on the nth copy bit group DBGn can be substantially the same as the operation of obtaining the first copy bit row DBR1.

[0113] Figure 15 It is shown Figure 14 A flowchart of an example of step S1210. Figure 16 It is used to describe Figure 15 The diagram shows the operation.

[0114] refer to Figure 14 , Figure 15 and Figure 16 When a bit (e.g., the first bit) of the first copy bit row DBR1 is obtained based on the first sensing voltage (step S1210), the first sensing voltage VSN1 can represent the voltage at the sensing node included in the page buffer connected to the first bit line BL1.

[0115] The first sensing voltage VSN1 can be compared with the first reference voltage VREF1 (step S1212). When the first sensing voltage VSN1 is higher than the first reference voltage VREF1 (step S1212: Yes), a bit of the first copy bit row DBR1 can be obtained as a first value (e.g., "0") (step S1214). When the first sensing voltage VSN1 is lower than or equal to the first reference voltage VREF1 (step S1212: No), a bit of the first copy bit row DBR1 can be obtained as a second value (e.g., "1") (step S1216).

[0116] Typically, in a memory device, memory cells can be classified or identified as on-cell and off-cell based on the level of a sensed voltage (e.g., the voltage level at a sensed node), and thus can be classified as binary bit "0" or binary bit "1". In the following, for convenience, example embodiments will be described where off-cells are mapped to "0" (e.g., a first value), and on-cells are mapped to "1" (e.g., a second value).

[0117] When a memory cell is sensed, the level change of the sensed voltage can be limited or constrained. For example, during the initial sensing time, when the sensed node is pre-charged to the supply voltage, the sensed voltage can have the supply voltage level. Subsequently, when a sensing operation is performed, cell current can flow through the turn-on cell, causing the sensed voltage to decrease from the supply voltage level and become lower than the supply voltage level, and cell current can not flow through the turn-off cell, so that the sensed voltage maintains the supply voltage level.

[0118] On the other hand, when multiple memory cells are sensed simultaneously according to the example embodiment, the level changes of the sensed voltage can be more diverse than described above. Figure 16 This illustrates an example where four memory cells connected to one bit line BL1 and four word lines WL1, WL2, WL3, and WL4 are simultaneously sensed. As the number of on-line cells sensed simultaneously on the same bit line increases, the amount of cell current can increase, and the sensed voltage can decrease further. Conversely, as the number of off-line cells sensed simultaneously on the same bit line increases, the amount of cell current can decrease, and the sensed voltage can decrease even less, approaching the level of the supply voltage.

[0119] For example, Case 1 where the first sense voltage VSN1 has the highest level (Case 1) may represent the case where all four memory cells are off cells (e.g., "0"). In Case 1, it can be determined that no bit error has occurred, and one bit (e.g., the leading bit) of the first replicated bit row DBR1 can be sensed as "0". Case 2 where the level of the first sense voltage VSN1 is higher than the level of the first reference voltage VREF1 but lower than that of Case 1 may represent the case where three memory cells are off cells (e.g., "0") and one memory cell is an on cell (e.g., "1"). In Case 2, it can be determined that a bit error has occurred in one on cell, and by correcting the bit error based on majority sensing, one bit of the first replicated bit row DBR1 can be sensed as "0".

[0120] Similarly, Case 4 may represent the case where all four memory cells are on cells (e.g., "1"). In Case 4, one bit of the first replicated bit row DBR1 can be sensed as "1". Case 3 may represent the case where three memory cells are on cells (e.g., "1") and one memory cell is an off cell (e.g., "0"). In Case 3, by correcting the bit error based on majority sensing, one bit of the first replicated bit row DBR1 can be sensed as "1".

[0121] In this way, error correction can be performed based on majority sensing, in which the value with a relatively large quantity is selected as the bit value.

[0122] Figure 17 is a flowchart showing another example of step S1210 in Figure 14 . Figure 18 is a diagram for describing the operation of Figure 17 . Descriptions that are repetitive with Figure 15 and Figure 16 will be omitted.

[0123] Referring to Figure 14 , Figure 17 and Figure 18 , when obtaining one bit (e.g., the leading bit) of the first replicated bit row DBR1 based on the first sense voltage (step S1210), Figure 17 the step S' in Figure 15 can be substantially the same as the step S1212 in

[0124] When the first sensing voltage VSN1 is higher than the first reference voltage VREF1 (step S1212: Yes), the first sensing voltage VSN1 can be compared with the second reference voltage VREF2, which is higher than the first reference voltage VREF1 (step S1213). When the first sensing voltage VSN1 is higher than the second reference voltage VREF2 (step S1213: Yes), a bit of the first copy bit row DBR1 can be obtained as "STRONG 0" (step S1214a). When the first sensing voltage VSN1 is lower than or equal to the second reference voltage VREF2 (step S1213: No), a bit of the first copy bit row DBR1 can be obtained as "WEAK 0" (step S1214b).

[0125] When the first sensing voltage VSN1 is lower than or equal to the first reference voltage VREF1 (step S1212: No), the first sensing voltage VSN1 can be compared with the third reference voltage VREF3, which is lower than the first reference voltage VREF1 (step S1215). When the first sensing voltage VSN1 is higher than the third reference voltage VREF3 (step S1215: Yes), a bit of the first copy bit row DBR1 can be obtained as "WEAK" (step S1216b). When the first sensing voltage VSN1 is lower than or equal to the third reference voltage VREF3 (step S1215: No), a bit of the first copy bit row DBR1 can be obtained as "STRONG" (step S1216b).

[0126] Figure 18 Cases A, B, C, and D can be respectively compared with... Figure 16 Cases 1, 2, 3, and 4 are essentially the same. In Case A ("STRONG 0") and Case D ("STRONG 1"), it can be determined that no bit error has occurred, so additional error correction may not be necessary, and therefore a bit may ultimately be sensed as "0" in Case A and "1" in Case D. However, in Case B ("WEAK 0") and Case C ("WEAK 1"), since a bit error has been determined to have occurred, additional error correction may be necessary, and therefore a bit may primarily be sensed as "0" in Case B and "1" in Case C, and reference correction may also be performed. Figure 20 Additional error corrections will be provided in the description.

[0127] Although reference Figures 15 to 18 Only described Figure 14 Step S1210 in the text, but Figure 14 Step S1220 in the reference can be used with reference to Figures 15 to 18 The steps described are basically the same.

[0128] Figure 19 This is a diagram illustrating a method for reading data from a memory device according to an example embodiment.

[0129] refer to Figure 19 DUP1, DUP2, DUP3, and DUP4 can represent four duplicate bit rows stored in memory cells connected to eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8, and include the same bits. SR indicates the result of performing majority sensing on DUP1, DUP2, DUP3, and DUP4.

[0130] The sensing results of bit lines BL1, BL2, BL4, BL5, BL6, and BL8 can correspond to Figure 16 Case 3 or Figure 18 In case C, the value "1" can be obtained by performing error correction based on majority sensing. The results of sensing bit lines BL3 and BL7 can correspond to Figure 16 Case 4 or Figure 18 In case D, the value "1" can be obtained without error correction.

[0131] Figure 20 , Figure 21 and Figure 22 This is a flowchart illustrating a method for reading data from a memory device according to an example embodiment. (The remaining text is omitted.) Figure 13 Repeated description.

[0132] refer to Figure 20 Except for steps S1410 and S1420 being added Figure 20 In addition to the examples, Figure 20 Examples can be compared with Figure 13 The examples are basically the same.

[0133] After performing step S1200, when it is determined that additional error correction is needed for at least one of the multiple copy bit rows (e.g., the first copy bit row) (step S1410: Yes), additional error correction can be performed on at least one of the multiple copy bit rows based on ECC decoding (step S1420). For example, additional error correction can be performed in "weak (WEAK) 0" in case B and "weak (WEAK) 1" in case C (e.g., when the accuracy of error correction based on majority sensing is reduced). For example, ECC decoding can be performed by a memory controller (e.g., Figure 2 The memory controller 20 in the memory is used to execute this.

[0134] Figure 20 The ECC decoding in step S1420 can be based on Figure 10 Generate and in step S500 Figure 10The process is executed based on the ECC bits stored in step S300a. In other words, when based on... Figure 10 The method for writing and reading data, for example when multiple copy bit groups and ECC bits are stored together, can be executed. Figure 20 The method for reading data.

[0135] refer to Figure 21 Except for step S1430 being added Figure 21 In addition to the examples, Figure 21 Examples can be compared with Figure 20 The examples are basically the same.

[0136] After step S1420, at least one of the multiple copied bit rows for which additional error correction was performed (e.g., the first copied bit row) can be stored in another memory region (e.g., a memory region other than the first memory region) (step S1430). In other words, the data recovered using ECC can enter the reclaim stage through the memory controller and can be stored in a new memory region as error-corrected data. By performing this write-back operation, repeated ECC operations can be prevented when reading the same data later.

[0137] refer to Figure 22 Except for step S1300 being added Figure 22 In addition to the examples, Figure 22 Examples can be compared with Figure 13 The examples are basically the same.

[0138] A memory device performing a method for reading data according to an example embodiment may include a memory cell array for storing data, majority sensing circuitry for performing majority sensing on the read data to be read or retrieved, and majority voting circuitry for performing majority voting on the read data. The configuration of the memory device and the memory system including the memory device may be consistent with reference to... Figure 2 and Figure 3 The descriptions are basically the same.

[0139] Multiple replicated bit rows are re-obtained by performing a second error correction based on majority voting on the multiple replicated bit rows obtained in step S1200 (step S1300). (Refer to...) Figures 23 to 26 Describe the majority vote in detail.

[0140] In the method for reading data from a memory device according to the example embodiment, each bit of the copied bit row can be obtained by performing majority sensing and majority voting on the read data written via a double copy operation. By performing multi-step error correction including the aforementioned majority sensing and majority voting, data integrity can be ensured or guaranteed without external ECC.

[0141] Figure 23 It is shown Figure 22 The flowchart is an example of step S1300.

[0142] refer to Figure 22 and Figure 23 When multiple replicated bit rows are reacquired by performing second error correction based on majority voting (step S1300), all of the multiple first bits included in the first replicated bit row can be reacquired (or reacquired) based on the number of first bits with a value of "1" (e.g., a second value) among the multiple first bits included in the first replicated bit row (step S1310). For example, all bits included in the first replicated bit row obtained by step S1300 can have the same value.

[0143] Similarly, all of the nth bits included in the nth copy row can be obtained again based on the number of nth bits with the value "1" among the multiple nth bits included in the nth copy row (step S1320).

[0144] Figure 24 and Figure 25 It is shown Figure 23 The flowchart is an example of step S1310. Figure 26 It is used to describe Figure 24 and Figure 25 The diagram shows the operation.

[0145] refer to Figure 23 and Figure 24 When all the first bits included in the first copy bit row are obtained again (step S1310), if the number of first bits with the value "1" in the first copy bit row is greater than the first reference number (step S1312: Yes), all the first bits included in the first copy bit row can be obtained as "1" (step S1314). If the number of first bits with the value "1" in the first copy bit row is less than or equal to the first reference number (step S1312: No), all the first bits included in the first copy bit row can be obtained as "0" (step S1316).

[0146] exist Figure 24 In the example, when the first copy bit row includes eight bits, the first reference number can be four. When the number of bits with "1" is 5, 6, 7, or 8, all eight bits can be restored or reverted to "1". When the number of bits with "1" is 0, 1, 2, 3, or 4, all eight bits can be restored or reverted to "0".

[0147] refer to Figure 23 and Figure 25When all the first bits included in the first copy bit row are obtained again (step S1310), if the number of first bits with the value "1" in the first copy bit row is greater than the first reference number (step S1312: Yes), all the first bits included in the first copy bit row can be obtained as "STRONG 1" (step S1314a). If the number of first bits with the value "1" in the first copy bit row is less than or equal to the first reference number (step S1312: No) and less than the second reference number (step S1313: Yes), all the first bits included in the first copy bit row can be obtained as "STRONG 0" (step S1316a). If the number of first bits with the value "1" in the first copy bit row is less than or equal to the first reference number (step S1312: No) and greater than or equal to the second reference number (step S1313: No), all the first bits included in the first copy bit row can be obtained as "WEAK 0" or "WEAK 1" (step S1317).

[0148] exist Figure 25 In the example, when the first copy bit row includes eight bits, the first reference number can be five, and the second reference number can be four. When the number of bits with "1" is 6, 7, or 8, all eight bits can be restored to "STRONG 1". When the number of bits with "1" is 0, 1, 2, or 3, all eight bits can be restored to "STRONG 0". When the number of bits with "1" is 4 or 5, all eight bits can be restored to "WEAK 0" or "WEAK 1". (See reference...) Figure 18 As mentioned above, additional error correction may be required in the cases of "weak (WEAK) 0" and "weak (WEAK) 1".

[0149] Although reference Figure 24 and Figure 25 Only described Figure 23 Step S1310 in the text, but Figure 23 Step S1320 in the reference can be compared with the reference. Figure 24 and Figure 25 The steps described are basically the same.

[0150] refer to Figure 26 Even though an error has occurred in data A where the second and sixth bits changed from '1' to '0' (e.g., a duplicate bit row), data A can be restored to data A', where the second and sixth bits are corrected through the aforementioned majority vote. Similarly, data B can be restored to data B'.

[0151] Figure 27 , Figure 28 and Figure 29This is a flowchart illustrating a method for reading data from a memory device according to an example embodiment. (The remaining text is omitted.) Figure 13 , Figure 20 , Figure 21 and Figure 22 Repeated description.

[0152] refer to Figure 27 Except for steps S1410 and S1420 being added Figure 27 In addition to the examples, Figure 27 Examples can be compared with Figure 22 The examples are basically the same. Figure 27 Steps S1410 and S1420 can be respectively connected with Figure 20 Steps S1410 and S1420 are essentially the same. In some example embodiments, Figure 21 Step S1430 in the process can also be added Figure 27 In the example.

[0153] refer to Figure 28 and Figure 29 Except for steps S1510 and S1520 being added Figure 28 Examples and steps S1515 and S1520 are added Figure 29 In addition to the examples, Figure 28 and Figure 29 Examples can be compared with Figure 13 The examples are basically the same. Figure 28 and Figure 29 In the example, additional error correction based on ECC decoding can be performed when predetermined conditions are met (e.g., when the probability of an error occurring increases relatively).

[0154] exist Figure 28 In the example, the predetermined condition may include data retention time. When the data retention time is greater than a reference time, for example, when more than a reference time has elapsed since the point in time when multiple replicate bit groups were stored (step S1510: Yes), additional error correction based on ECC decoding can be performed (step S1520). For example, the data retention time can be detected based on a timestamp.

[0155] exist Figure 29 In the example, the predetermined condition may include the number of times data is read. When the number of times data is read is greater than a reference number, for example, when the number of times multiple copy bit groups are read is greater than a reference number (step S1515: Yes), additional error correction based on ECC decoding can be performed (step S1520).

[0156] In some example embodiments, Figure 28 Steps S1510 and S1520 and / or Figure 29 Steps S1515 and S1520 in the above can also be applied to Figure 13 , Figure 20 , Figure 21 , Figure 22 and Figure 27 Examples.

[0157] Figure 30 This is a flowchart illustrating a method of operating a memory device according to an example embodiment. Figure 31 It is used to describe Figure 30 The diagram shows the operation.

[0158] refer to Figure 30 In the method of operating a memory device according to an example embodiment, a data write operation is performed in which first data is double-copied and the double-copied first data is stored (step S2100), and a data read operation is performed in which the double-copied first data is retrieved (step S2200). Step S2100 can be referenced from... Figures 1 to 1 The method for writing data described in section 2 is executed, and step S2200 can be performed by referring to... Figures 13 to 29 The described method for reading data is executed. Therefore, as... Figure 31 As shown, it can process, treat, or handle data.

[0159] As those skilled in the art will understand, this disclosure can be implemented as a system, method, computer program product, and / or a computer program product implemented on one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in conjunction with an instruction execution system, apparatus, or device. For example, a computer-readable medium can be a non-transitory computer-readable medium.

[0160] Figure 32 , Figure 33 and Figure 34 This is a diagram illustrating a matrix multiplication method using a memory device, based on an example embodiment.

[0161] refer to Figure 32 A neural network driven by a memory device according to an example embodiment may include an input layer IL, multiple hidden layers HL1, HL2, ..., HLn and an output layer OL.

[0162] The input layer (IL) can include i input nodes x1, x2, ..., x3. iWhere i is a natural number. Input data of length i (e.g., vector input data) IDAT can be input to input nodes x1, x2, ..., x... i This ensures that each element of the input data IDAT is input into the input nodes x1, x2, ..., x... i The corresponding one in the middle. Multiple hidden layers HL1, HL2, ..., HLn can include n hidden layers, where n is a natural number, and can include multiple hidden nodes h. 1 1. h 1 2. h 1 3、...、h 1 m h 2 1. h 2 2. h 2 3、...、h 2 m h n 1. h n 2. h n 3、...、h n m The output layer OL can include j output nodes y1, y2, ..., y3. j , where j is a natural number and can indicate, for example, the probability that the input data IDAT corresponds to a car. Figure 32 The structure of the neural network shown can be represented by information about the branches (or connections) between nodes shown as lines and the weights (not shown) assigned to each branch.

[0163] refer to Figure 33 The multiplication matrix MY can be calculated by multiplying the multiplicand matrix MW and the multiplier matrix MX. The multiplicand values ​​W11 to Wpr of the multiplicand matrix MW, the multiplier values ​​X11 to Xrq of the multiplier matrix MX, and the component values ​​Y11 to Ypq of the multiplication matrix MY can correspond to the values ​​obtained from the reference matrix MY. Figure 32 The description describes the weights, inputs, and outputs of the multiplication and accumulation (MAC) operations performed by the neural network.

[0164] refer to Figure 34The multiplicand values ​​W11 to Wpr of the multiplicand matrix MW can be stored in the memory cells of the memory device (step S10). The multiplier values ​​X11 to Xrq of the multiplier matrix MX can be stored in the read / write circuit of the memory device (step S20). Bitwise multiplication of the multiplicand values ​​W11 to Wpr and the multiplier values ​​X11 to Xrq can be performed (step S30). The multiplication values ​​of the multiplicand values ​​W11 to Wpr and the multiplier values ​​X11 to Xrq can be calculated by performing a weighted addition operation (step S40). The component values ​​Y11 to Ypq of the multiplication matrix MY can be provided by summing the multiplication values ​​(step S50). To perform the above operations, the following can be used: Figure 2 The memory device includes a read / write circuit 40, a data copying and placement circuit 50, and an arithmetic circuit 60. It can also utilize methods for writing data, reading data, and operating the memory device according to the example embodiment. By using the read / write circuit and arithmetic circuit included in the memory device to perform data-intensive processing, the amount of data transferred between the memory device and external devices can be reduced, thereby reducing data processing time and power consumption.

[0165] Figure 35 This is a block diagram illustrating a mobile system including a memory device according to an example embodiment.

[0166] refer to Figure 35 The mobile system 3000 includes an application processor (AP) 3100, a connectivity unit 3200, a volatile memory device (VM) 3300, a non-volatile memory device (NVM) 3400, a user interface 3500, and a power supply 3600, all connected via a bus.

[0167] Application processor 3100 can run applications such as web browsers, game applications, video players, etc. Connection unit 3200 can perform wired or wireless communication with external devices. Volatile memory device 3300 and non-volatile memory device 3400 can store data processed by mobile system 3000. User interface 3500 may include at least one input device and at least one output device. Power supply 3600 can provide power voltage to mobile system 3000. Volatile memory device 3300 and / or non-volatile memory device 3400 can operate based on methods for writing data, reading data, and operating memory devices according to exemplary embodiments.

[0168] This disclosure can be applied to a variety of electronic devices and / or systems, including memory devices. For example, this disclosure can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, portable camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0169] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible to the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims. It will thus be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting oneself to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A method for writing data into a memory device, the method comprising: Multiple rows of copied bits are generated by performing a first copy operation, in which multiple bits included in the written data are copied bit by bit. A plurality of copy bit groups are generated by performing a second copy operation, in which the plurality of copy bit rows are copied row by row; as well as The plurality of copied bit groups are respectively stored in a plurality of memory regions included in the memory device, wherein each of the plurality of memory regions includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, and Each of the plurality of memory regions is a region that is sensed simultaneously during a data read operation.

2. The method according to claim 1, wherein: The plurality of bits includes the first to the nth bit. The plurality of copy bit rows include a first copy bit row to an nth copy bit row, each copy bit row being generated by copying the corresponding bit from the first to the nth bit m times. The plurality of copy bit groups include a first copy bit group to an nth copy bit group, each copy bit group being generated by making k copies of a corresponding copy from the first copy bit row to the nth copy bit row. The plurality of memory regions include a first memory region to an nth memory region. The first to the nth copy bit groups are stored in the first to the nth memory regions, respectively. Each of n, m, and k is a natural number greater than or equal to two.

3. The method according to claim 2, wherein: A first copy bit group, comprising k first copy bit rows, is stored in a first memory region, each of the k first copy bit rows comprising m bits. The nth copy bit group, comprising k nth copy bit rows, is stored in the nth memory region, each of the k nth copy bit rows comprising m nth bits.

4. The method according to claim 1, wherein: The memory device includes a memory cell array, the memory cell array comprising multiple memory cells connected to multiple bit lines and multiple word lines, and Each of the plurality of memory regions is connected to the same bit line.

5. The method according to claim 4, wherein: The memory cell array is divided into multiple memory blocks, and Each of the plurality of memory regions includes two or more memory blocks among the plurality of memory blocks that are connected to the same bit line.

6. The method according to claim 4, wherein: The memory cell array is divided into multiple memory blocks. Each of the plurality of memory blocks is divided into multiple subgroups connected to multiple string select lines, and Each of the plurality of memory regions includes two or more subgroups connected to the same bit line from among the multiple subgroups included in a memory block.

7. The method of claim 1 further comprises generating ECC bits by performing error correction code (ECC) encoding on the written data.

8. The method according to claim 7, wherein, The ECC bit is stored together with the plurality of copy bit groups.

9. A method for reading data from a memory device, the method comprising: When read data comprising multiple bits is written in a manner that causes the multiple bits to be copied bit by bit to generate multiple rows of copied bits, the multiple rows of copied bits to be copied row by row to generate multiple groups of copied bits, and the multiple groups of copied bits to be stored respectively in multiple memory regions included in a memory device, each of the multiple groups of copied bits is sensed simultaneously. as well as The plurality of replicated bit rows are obtained by performing a first error correction based on majority sensing on the sensing results of the plurality of replicated bit groups.

10. The method according to claim 9, wherein: The plurality of bits includes the first bit. The plurality of copied bit rows includes a first copied bit row generated by copying the first bit m times, where m is a natural number greater than or equal to two. The plurality of copy bit groups includes a first copy bit group generated by copying the first copy bit row k times, where k is a natural number greater than or equal to two. The first copy bit group is stored in a first memory region included in the plurality of memory regions, and Simultaneous sensing of each of the plurality of replicate bit groups includes simultaneously sensing the first bit among the plurality of first bits included in the first replicate bit group, stored in a memory cell connected to the first bit line.

11. The method according to claim 10, wherein, Obtaining the plurality of copy bit rows includes: When the first sensed voltage is higher than the first reference voltage, a bit of the first copied bit row is obtained as a first value. The first sensed voltage is obtained by simultaneously sensing a memory cell connected to the first bit line and storing the first bit. When the first sensing voltage is lower than or equal to the first reference voltage, a bit of the first copied bit row is obtained as the second value.

12. The method of claim 11, further comprising: When the first sensed voltage is between a second reference voltage higher than the first reference voltage and a third reference voltage lower than the first reference voltage, additional error correction is performed on the first copy bit row based on error correction code (ECC) decoding.

13. The method of claim 12, further comprising: After performing additional error correction on the first copied bit row based on ECC decoding, the first copied bit row with additional error correction is stored in a memory area other than the first memory area.

14. The method of claim 9, further comprising: The multiple replicated bit rows are reacquired by performing a second error correction based on majority voting on the multiple replicated bit rows.

15. The method of claim 14, wherein: The plurality of bits includes the first bit. The plurality of copied bit rows includes a first copied bit row generated by copying the first bit m times, where m is a natural number greater than or equal to two, and Retrieving the plurality of copied bit rows includes: When the number of bits with a first value among the multiple bits included in the first copied bit row is greater than the first reference number, all bits of the first copied bit row are obtained as the first value; and When the number of bits with the first value among the multiple bits included in the first copy bit row is less than or equal to the first reference number, all bits of the first copy bit row are obtained as the second value.

16. The method of claim 15, wherein: Retrieving the plurality of copied bit rows further includes: when the number of bits with a first value among the plurality of bits included in the first copied bit row is less than the second reference number, obtaining all bits of the first copied bit row as the second value; and The method further includes performing additional error correction on the first copy bit row based on ECC decoding when the number of first bits with a first value among the plurality of first bits included in the first copy bit row is between the first reference number and the second reference number.

17. The method of claim 9, further comprising: When predetermined conditions are met, additional error correction based on ECC decoding is performed after obtaining the plurality of copied bit rows.

18. The method of claim 17, wherein: The predetermined conditions include data retention time, and When more than a reference time has elapsed since the point in time when the plurality of replicated bit groups were stored, additional error correction based on ECC decoding is performed.

19. The method of claim 17, wherein: The predetermined conditions include the number of times data is read, and When the number of reads of multiple copy bit groups exceeds the reference number, additional error correction based on ECC decoding is performed.

20. A method of operating a memory device, the method comprising: A data write operation is performed, in which first data is copied twice and the copied first data is stored. as well as Perform a data read operation, in which the first data of the double copy is retrieved, wherein: Performing data write operations includes: A first copy row is generated by performing a first copy operation, in which the first bit included in the first data is copied bit by bit; A first copy bit group is generated by performing a second copy operation, in which the first copy bit rows are copied row by row; and Store the first copy bit group into the first memory region. The first memory region is connected to the same bit line and is the region that is sensed simultaneously during the data read operation. Performing the data read operation includes: Simultaneously sensing the first copy bit group; and The first copy bit row is obtained by performing a first error correction based on majority sensing on the sensing results of the first copy bit group, and Obtaining the first copy bit row includes: When the first sensed voltage is higher than the first reference voltage, a bit of the first copied bit row is obtained as a first value. The first sensed voltage is obtained by simultaneously sensing a memory cell in the memory cells included in the first memory region that is connected to the first bit line and stores the first bit. When the first sensing voltage is lower than or equal to the first reference voltage, a bit of the first copied bit row is obtained as the second value.

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