Write operations that mitigate write disturb

Abstract

The present application relates to write operations that mitigate write disturb. A request to write a set of host data is received. A first plurality of write operations are performed to write a first portion of the set of host data to a first set of memory cells of a memory device arranged in a first pattern. The first set of memory cells arranged in the first pattern includes alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells. A second plurality of write operations are performed to write a second portion of the set of host data to the second set of memory cells arranged in a second pattern. The second set of memory cells arranged in the second pattern includes other alternating memory cells adjacent to the first set of memory cells on each word line of the memory device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to performing write operations that mitigate write disturb in memory subsystems. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present application provides a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: receiving a request to write a set of host data; performing a first plurality of write operations to write a first portion of the set of host data to a first set of memory cells of the memory device arranged in a first pattern, wherein the first set of memory cells arranged in the first pattern includes alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells; and performing a second plurality of write operations to write a second portion of the set of host data to the second set of memory cells arranged in a second pattern, wherein the second set of memory cells arranged in the second pattern includes other alternating memory cells adjacent to the first set of memory cells on each word line of the memory device.

[0004] In another aspect, the present application provides a method comprising: performing a first write operation to write a first portion of a host data set to a first location of a memory device; monitoring the time elapsed from the time the first write operation is performed to determine whether the elapsed time satisfies a time condition; in response to determining that the elapsed time does not satisfy the time condition: performing a second write operation by a processing device to write a second portion of the host data set to a second location of the memory device, wherein the second location is not adjacent to the first location; and continuing to monitor the elapsed time to determine whether the elapsed time satisfies the time condition; and in response to determining that the elapsed time satisfies the time condition, performing a third write operation to write a third portion of the host data set to a third location of the memory device, wherein the third location is adjacent to the first location.

[0005] In another aspect, the present application provides a non-temporary computer-readable storage medium comprising instructions, which, when executed by a processing device, causes the processing device to perform the following operations: perform a first write operation to write a first portion of a host data set to a first location of the memory device; monitor the time elapsed from the time the first write operation is performed to determine whether the elapsed time satisfies a time condition; in response to determining that the elapsed time does not satisfy the time condition: perform a second write operation to write a second portion of the host data set to a second location of the memory device, wherein the second location is not adjacent to the first location; and continue to monitor the elapsed time to determine whether the elapsed time satisfies the time condition; and in response to determining that the elapsed time satisfies the time condition, perform a third write operation to write a third portion of the host data set to a third location of the memory device, wherein the third location is adjacent to the first location. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem is illustrated in accordance with some embodiments of the present disclosure.

[0008] Figure 2A-2B Depicted is an example of performing write operations in adjacent cells with delay in response to a host request according to some embodiments of the present disclosure.

[0009] Figure 3A-3B An example of performing write operations from multiple host requests with delay according to some embodiments of the present disclosure is depicted.

[0010] Figure 4 is a flow chart of an example method for performing write operations in adjacent cells with delay according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of performing a write operation using a time condition according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure are directed to performing write operations that mitigate write disturb in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (e.g., a memory device that stores data). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0014] The memory device may be a non-volatile memory device, which is a package of one or more dies. The dies in the package may be assigned one or more channels for communicating with a memory subsystem controller. The non-volatile memory device includes cells (i.e., electronic circuits that store information) that are grouped into pages to store data bits. The non-volatile memory device may include, for example, a three-dimensional cross-point ("3D cross-point") memory device that is a cross-point array of non-volatile memory cells that may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. Another example of a non-volatile memory device is a NAND memory device. hereinafter combined with Figure 1 Other examples of non-volatile memory devices are described.

[0015] Each of the memory devices may include one or more memory cell arrays. Depending on the cell type, a cell may store one or more bits of binary information and have various logic states associated with the number of bits stored. The logic states may be represented by binary values, such as "0" and "1," or a combination of these values. For example, a single-level cell (SLC) may store one bit of information and have two logic states.

[0016] When data is conventionally written to a memory cell of a memory device for storage, a neighboring (e.g., adjacent, neighboring, nearby, close by, etc.) memory cell may experience a condition known as "write disturbance". Write disturbance is the result of continuously writing data to a particular memory cell without writing and / or refreshing the data stored at the nearby memory cell, causing the nearby memory cell to change state (e.g., programmed state change) over time. If too many write operations are performed on a particular memory cell (hereinafter also referred to as an "aggressor cell"), data stored at a neighboring or proximate memory cell of the memory device (hereinafter also referred to as a "victim cell" or "target cell") may become corrupted or incorrectly stored. The heat generated from the aggressor cell during the write operation may cause the memory alloy of the victim cell to crystallize, thereby degrading its quality. Therefore, in a conventional memory subsystem, a higher error rate may result when reading data stored at a neighboring or proximate memory cell. A higher error rate (e.g., a raw bit error rate or RBER) may increase the use of error detection and correction operations (e.g., error control operations) for subsequent operations (e.g., reading and / or writing) performed on the memory cell. Increased use of error control operations can result in reduced performance of conventional memory subsystems. As more resources of the memory subsystem are used to perform error control operations, fewer resources are available to perform other read operations or write operations. Therefore, the performance of the memory subsystem may be reduced because fewer read operations and write operations can be performed in a particular amount of time.

[0017] In order to mitigate the effects of write disturbance on data stored at the memory subsystem, conventional memory subsystems typically utilize various write refresh processes. For example, a conventional memory subsystem may perform a write refresh based on the number of write operations performed on a managed unit. A managed unit may be defined as a unit of user data that is managed and / or operated by a memory device. A managed unit may be defined by the size of the data (e.g., bytes). Typically, the memory subsystem stores the number of write operations performed on a managed unit of a memory device as metadata on a memory device. The number of write operations performed on a managed unit may be read from metadata stored at the memory device and used to determine a disturbance count for one or more of a portion of the memory device (e.g., close to a memory unit). The disturbance count may correspond to the number of write operations performed on a particular managed unit without an intervening write or refresh operation for the particular managed unit. Once the disturbance count exceeds a threshold number of write operations, the data of the managed unit of the memory device may be refreshed (i.e., copied and written to another managed unit of the same or different memory device). In addition, some conventional memory subsystems may utilize a single count of write operations performed on a memory device instead of a separate count for each managed unit. Once the number of write operations satisfies a threshold condition (eg, meets or exceeds a threshold), memory cells of the memory device are identified for refresh operations.

[0018] In some examples, refreshing data stored at one or more memory cells may include reading data from the one or more memory cells and subsequently writing the data back to the one or more memory cells. Since the data was recently written back to the memory cells, the effects of write disturbances (e.g., read errors resulting from changes in cell states due to write disturbances) may be mitigated as further time passes. In some examples, refreshing the data may include clearing an existing logical to physical address data mapping and setting the logical to physical address mapping again. Since the operations involved in the write refresh process are performed in addition to the actual host data operations (e.g., read, write, etc.), the process of write refresh may reduce device life and increase read time. Additionally, in a cross-point array type memory, the managed cells of the memory device may be relatively small, and the number of write counts may be in the millions due to the high endurance of the cross-point array type memory. The storage of disturbance counts may result in a large amount of overhead of the memory subsystem dedicated to storing the number of write operations performed on the managed cells of the memory device. Furthermore, in conventional memory subsystems, each time a write operation is performed on a particular managed unit, metadata associated with the number of write operations for the particular managed unit is read from the memory device, incremented to reflect the most recently performed write operation, and then the updated metadata is written back to the memory device. The process of maintaining write count metadata is performed for each managed unit of the memory device. The execution of these operations each time a write operation is performed consumes a significant amount of the resources of the memory subsystem. Furthermore, the memory device may include hundreds of thousands of managed units. Maintaining write count metadata for this large number of managed units consumes a significant amount of the computing resources of the memory subsystem. This results in a reduction in memory subsystem performance and a lesser capacity memory subsystem to store user data.

[0019] Aspects of the present disclosure address the above and other deficiencies by performing write operations to store data in a particular cell to produce a minimum amount of delay (e.g., lag time, wait time, etc.) without causing a delay between two consecutive write operations to write host data to mitigate or avoid write interference. The minimum delay may correspond to a threshold time based on various factors, such as experiments, system specifications, etc. The minimum delay between write operations in adjacent cells allows the adjacent cells to dissipate heat and reduce the temperature. As a result, the memory cell can recover before the next write operation occurs and can be prevented from crystallizing. As the delay between write operations in adjacent cells increases, the RBER continues to decrease to a point where the error rate can be completely mitigated. The present disclosure provides for implementing delays in write operations of adjacent cells by utilizing various write operation modes that cause host data to be written to memory cells that are not adjacent to each other for consecutive write operations until sufficient delays have occurred. For example, a first mode may be used, which may include performing a write operation to write a set of host data to a plurality of cells, wherein a portion of the data is written to a first cell for a first write operation, then the next cell in the array is skipped, and the next portion of the data is written to a second cell not adjacent to the first cell for a consecutive next write operation. The first mode may continue until a time condition is met. For example, the time condition may be met when the time elapsed from the first write operation is above a threshold time. Once the time condition is met, a second mode may be used, wherein the next consecutive write operation is performed to write the next portion of the host data to a cell adjacent to the first cell, and the remainder of the host data continues to be written to the cell skipped using the first mode. Using an alternating mode, the total time to write host data may remain unchanged while designing a minimum delay between write operations that introduce adjacent cells. Various other modes may be used to achieve sufficient delay between two adjacent cells that minimize the effects of write interference, as described throughout this disclosure.

[0020] Advantages of the present disclosure include, but are not limited to, increased reliability of data stored at the memory subsystem. Since the effect of write disturb stress on data stored in nearby cells is mitigated, the number of errors found in the data stored at the memory subsystem is reduced. The reduced error rate associated with data stored at nearby memory cells can reduce the number of error correction operations performed by the memory subsystem and improve the performance of the memory subsystem. In addition, delays between writes to adjacent cells are implemented without any increase in the total time to perform write operations requested by the host system. In addition, by introducing an inherent delay rather than performing a write refresh to compensate for the effects of write disturbance, the amount of computing resources dedicated to performing clearing and rewriting data for write refresh is reduced. Since fewer computing resources are dedicated to performing error correction and write refresh operations, computing resources can be used to perform other operations for the host system (e.g., reading and writing data), and the capacity of the memory subsystem used to store data from the host system is increased. This brings about an improvement in the performance of the memory subsystem.

[0021] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, and the like.

[0025] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access components (e.g., memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. With respect to some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory, such as 3D crosspoints, may group pages across dies and channels.

[0030] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 may be a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a delay handling component 113 that can cause delays between write operations of adjacent memory cells. In some embodiments, the memory subsystem controller 115 includes at least a portion of the delay handling component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 to perform the operations described herein. In some embodiments, the delay handling component 113 is part of the host system 110, an application, or an operating system.

[0038] The delay handling component 113 may be used to perform write operations in adjacent cells with a delay. The write operation may be performed so that data is written to the adjacent memory cell with at least a minimum delay. In one example, the controller 115 may perform a first write operation to write a first portion of a host data set on a first cell of a data block. The delay handling component 113 may monitor the time elapsed from the time the first write operation is performed to determine whether the elapsed time satisfies a time condition. For example, if the elapsed time is greater than a threshold time, the time condition may be satisfied. If it is determined that the time condition is not satisfied (e.g., the elapsed time is less than or equal to the threshold time), the controller may perform a second write operation to write a second portion of the host data set on a second cell of the data block that is not adjacent to the first cell. The delay handling component 113 may continue to monitor the time elapsed from the time of the first write operation, and until the time condition is satisfied, the controller 115 may continue to write to cells that are not adjacent to the first cell. When it is determined that the time condition is satisfied (e.g., the elapsed time is greater than the threshold time), the controller 115 may write the date to a cell adjacent to the first cell. Thus, the delay handling component 113 causes the write operation between adjacent first and second cells to have a delay. Additional details regarding the operation of the delay handling component 113 are described below.

[0039] Figure 2A-2B An example of performing write operations in adjacent cells of a memory device 200 with a delay in response to a host request according to some embodiments of the present disclosure is depicted. The memory device 200 includes word lines 205a-f and bit lines 210a-f. Memory cells such as memory cells at positions 220a-220z and 230a-230z are located at the intersection of each of the word lines 205a-f and the bit lines 210a-f.

[0040] When a write operation is performed on a particular memory cell (e.g., an aggressor cell), write disturb stress may affect data stored at memory cells (e.g., victim cells) adjacent to the memory cell on which the write operation is performed. Adjacent cells may include cells that are close to, near, adjacent to, abutting, and the like. The farther a memory cell is from another memory cell, the less impact the write disturb stress has on each other. In one example, if a write operation is performed on a memory cell at position 220d, then the write disturb may have the highest impact on data stored at memory cells at positions 230a, 230e, 230g, and 230d that are all adjacent to position 220d. As the distance between cells increases, the impact of the write disturb becomes reduced. Therefore, the write disturb impact from position 220d is minimized at positions that are not adjacent to position 220d, such as positions 220a, 220b, 230b, 220g, 220h, 220e, 220j, 230b, and the like. In addition, although in some examples, neighboring cells may include cells that are in close proximity to the aggressor cell, in other examples, neighboring cells may include cells that are not in close proximity to the aggressor cell. Whether a cell is considered a neighboring cell may depend on the specific technical implementation of the memory subsystem and the size of the array layout. For example, if the cells are placed relatively close to each other, the range of cells that are considered as victim cells of the write operation in the aggressor cell may become wider and will include more devices. For example, in some configurations of the memory subsystem, cells 220a, 220b, 220g, 220h, which are diagonal cells of 220d, may be affected by the write operation in cell 220d because the placement of the cells is extremely close to cell 220d. In this case, the diagonal cells may be considered neighboring cells of the aggressor cell. In addition, as time passes after a write operation is performed on a particular memory cell, the heat generated from the write operation is dissipated and after a certain amount of time has passed since the write operation was performed, the effect of the write disturbance on the cells adjacent to the particular cell is minimized. For example, if a write operation is performed on a memory cell at location 220d at time t1, then after a certain amount of time delay after time t1, the effect of write disturbance from the data written at location 220d on neighboring locations 230a, 230e, 230g, and 230d is minimized. The delay may be a lag, gap, or wait time between two operations. The time sufficient to minimize the effect of write disturbance on neighboring cells may vary based on the specifications of the memory subsystem.

[0041] In an embodiment of the present disclosure, a memory subsystem may receive a request to write a host data set and may perform a write operation to write the host data set to a memory cell of the memory device 200. In order to mitigate the effect of a write disturbance caused by a write operation performed on a specific memory cell on its neighboring cells, the memory subsystem performs the write operation so that the time elapsed between writes to the neighboring cells satisfies a threshold time sufficient to overcome the write disturbance effect of the write operation performed on the neighboring cells without increasing the total time for the host request to write data. For example, if a write operation is performed on a memory cell at position 220d, the memory subsystem performs a subsequent write operation on a position that is not adjacent to position 220d. That is, the memory subsystem skips performing a subsequent write operation at any one of the memory cells located at 230a, 230e, 230g, and 230d, and performs a write operation on another memory cell position other than positions 230a, 230e, 230g, and 230d. The memory subsystem then performs a write operation on one of the cells located at 230a, 230e, 230g, and 230d after a minimum time delay (e.g., a threshold time defined within the memory subsystem) has elapsed from when the write operation was performed at memory cell location 220d. In this way, no waiting time is experienced between consecutive write operations performed by the memory subsystem, while delays are inherently introduced for write operations between adjacent cells, and the overall time to perform a write operation by the host system is not increased compared to performing consecutive write operations in adjacent cells.

[0042] In some implementations, the memory subsystem may use a particular pattern of write operations to cause data to be written to a location where the write disturb effects of performing write operations on a particular cell are minimized during the time that the write disturb effects still exist. The memory subsystem may use another pattern of write operations to write remaining data to remaining cells in the memory device 200 that are adjacent to the particular cell at a time after a sufficient time delay has elapsed to minimize the write disturb effects.

[0043] In one embodiment, the memory subsystem may receive a request to write a set of host data and may perform multiple write operations to write the set of host data to the memory cells of the memory device 200. For example, in one implementation, the memory subsystem may use a pattern similar to a checkerboard pattern, where alternating locations are used for writing portions of the host data in consecutive write operations. Figure 2AAs shown, the memory subsystem performs the plurality of write operations using alternating memory cells following a first pattern. According to the first pattern, the memory subsystem begins a write operation using word line 205a, and performs a first write operation of the plurality of write operations to write a first portion of the host data set to a first memory cell located at a first location 220a (e.g., at word line 205a and bit line 210a). The memory subsystem then continues on word line 205a, but bypasses the next bit line 210b to skip writing on memory cell 230a, and performs a second write operation of the plurality of write operations to write a second portion of the host data set to a second memory cell located at location 220b (e.g., at word line 205a and bit line 210c). The memory subsystem continues to perform write operations on word line 205a, skipping memory cells at every other bit line (e.g., 230b, 230c), until no bit lines on word line 205a remain to be written. In this way, the memory subsystem performs a write operation in one cell and skips performing a subsequent write operation at an adjacent cell that is affected by a write disturbance of the previous write operation to the previous cell. The memory subsystem then continues writing to the next word line 205b. The memory subsystem skips writing to the memory cell 230d on the bit line 210a because the cell 230d is located adjacent to the cell 220a on which the write operation has been performed. The memory subsystem performs subsequent write operations in the plurality of write operations on the memory cell 220d and so on, thereby skipping each alternating memory cell (e.g., 230e, 230f, etc.) on the word line 205b. The first mode of write operations can continue for each word line on the memory device 200, thereby avoiding writing in adjacent memory cells for consecutive write operations to complete writing the host data set, thereby minimizing write disturbance.

[0044] In one embodiment, the memory subsystem may monitor the time that has elapsed ("elapsed time") since a first write operation was performed to write a first portion of a set of host data at memory cell 220a. The memory subsystem may determine whether the elapsed time satisfies a time condition. For example, if the elapsed time is greater than a threshold time, then the elapsed time may satisfy the time condition. The memory subsystem may define a threshold time (e.g., a minimum delay time) based on a specification of the memory subsystem such that the threshold time is sufficient to minimize the write disturbance effects of the aggressor cell on the victim cell. If it is determined that the elapsed time does not satisfy the time condition (e.g., the elapsed time is equal to or less than the threshold time), then the memory subsystem continues to perform the remainder of the plurality of write operations using the first mode, writing portions of the host data in memory cells 220b, 220c, 220d, and so on, as described above with reference to Figure 2AThe memory subsystem also continues to monitor the elapsed time to determine whether the elapsed time after performing each of the plurality of write operations satisfies the time condition.

[0045] In one embodiment, if it is determined that the elapsed time satisfies the time condition (e.g., the elapsed time is greater than a threshold time), the memory subsystem may stop performing the remainder of the write operation using the first mode. Figure 2A , after writing to memory cell 220m of word line 205e, the memory subsystem determines that the elapsed time is greater than the threshold time and stops using the first mode to perform subsequent write operations in word line 205e. In practice, upon determining that the time condition is satisfied, the memory subsystem may switch to using the second mode (e.g., reverse checkerboard mode) in which the memory subsystem writes the remainder of the host data at a location adjacent to the previously skipped aggressor cell. For example, if Figure 2B , the memory subsystem performs a write operation to write a portion of a set of host data on memory cell 230a, which is adjacent to the first location 220a where the first write operation is performed. The time elapsed between the write operation on location 220a and the write operation on the adjacent cell at location 230a satisfies the time condition because the elapsed time is greater than a threshold time (e.g., a minimum delay time). Therefore, by the time the data is written on the adjacent cell at 130a, the effect of the write disturbance from the write operation on the aggressor cell at 220a is minimized on the adjacent cell at 230a. The memory subsystem continues to write the remainder of the set of host data in the remaining memory cells 230b, 230c, 230d, etc. (e.g., cells skipped during the execution of the write operation using the first mode) until the remaining portion of the host data is written in the memory device 200, thereby completing the write operation at memory cell 230g.

[0046] In one embodiment, even if it is determined that the elapsed time satisfies the time condition (e.g., the elapsed time is greater than a threshold time), the memory subsystem may still stop using the first mode to perform write operations. For example, the memory subsystem may continue to write data at memory cell 220n after skipping the memory cell at the intersection of bit line 210b on word line 205d. The memory subsystem may continue to write data until the data is written at the last memory cell 220z on the last word line 205f. In a certain embodiment, due to the specifications of the memory subsystem, continuing to write data until the end of the word line can guarantee that the elapsed time is greater than the threshold time. In these cases, the memory subsystem can use the first mode to perform write operations until the end of the word line is reached without monitoring the elapsed time to determine whether the time condition is met, because by the time the end of the word line is reached, the elapsed time is known by default to be greater than the threshold time in such memory subsystems. At that time, the memory subsystem can switch to using a first mode such as Figure 2B The second mode shown performs a write operation, in which the memory subsystem writes data in a memory cell 230a adjacent to the first memory cell 220a, and the time elapsed between the write operations in the two adjacent cells is greater than a designed threshold time.

[0047] In an embodiment, if the elapsed time is not met when a word line ends due to the specific specifications of the memory subsystem, the memory subsystem does not switch to using Figure 2B The second mode shown is used to write data because the effects of write disturb on neighboring cells have not yet been minimized. In these cases, the memory subsystem may perform subsequent write operations on different units of data, such as to different blocks, planes, or memory devices. In an embodiment, when the memory subsystem performs a write operation using the second mode and reaches the end of the last word line before completely completing writing the host data (e.g., all memory cells have been used), the memory subsystem may follow Figure 2A and 2B The mode described in writes host data to another data unit (e.g., a different block, plane, or memory device, etc.).

[0048] In some implementations, the memory subsystem tracks an individual elapsed time for each of the write operations for the aggressor cell in the plurality of write operations and determines whether each of the individual elapsed times satisfies a time condition, and then writes data to each of the neighboring cells of the aggressor cell based on the determination that each of the corresponding individual elapsed times satisfies the time condition.

[0049] In some implementations, the pattern used by the memory subsystem is predefined within the memory subsystem. The memory subsystem can identify available locations corresponding to memory cells to which data will be written following a particular pattern. Figure 2A In the first mode described in the foregoing, the memory subsystem may identify memory cells 220a, 220b, 220c to 220z as available memory cells for use with the first mode. That is, after the memory subsystem completes writing data to cell 220a, it identifies the next memory cell available for performing a subsequent write operation as 220b, and so on. Similarly, for Figure 2B In the second mode shown in FIG. 1 , the memory subsystem may identify memory cells 230a, 230b, 230c to 230z as available memory cells for use with the second mode. The order of the memory cells may be identified in a predefined list of memory cells available for use by the memory subsystem. The predefined list may be stored in metadata.

[0050] In some embodiments, the memory subsystem performs a write operation by tracking memory cells that have been written and memory cells that are still to be written. For example, the memory subsystem may track the use of memory cell 220a to perform a write operation. The memory subsystem may dynamically determine to skip adjacent memory cell 230a by skipping to write data in the next bit line 210b. The memory subsystem may detect which cells are adjacent to cell 220a and track the adjacent cells. For subsequent write operations, the memory subsystem skips writing data in the identified adjacent cells. The skip decision of the memory subsystem may be made based on previously defined and loaded information and / or logic in the system (e.g., including but not limited to a portion of the delay handling component 113). If the time elapsed between writes is equal to or lower than a predefined threshold, the memory subsystem skips writing to the adjacent cells. The predefined threshold may also be stored as part of the delay handling component 113. This information is defined per technology node and is preprogrammed in the system.

[0051] Figure 3A-3B An example of requesting from multiple hosts to perform write operations in memory cells of the memory device 300 according to some embodiments of the present disclosure is depicted. A host system (e.g., Figure 1 The host system 120 in FIG. 1 may be configured to perform operations on the memory subsystem (e.g., Figure 1The host system may initiate a data operation (e.g., write, read, erase, etc.) to the memory subsystem 110 in the host system. The host system may send an access request (e.g., a write command, a read command) to the memory subsystem to store data on a memory device at the memory subsystem and read data from a memory device on the memory subsystem. As specified by the host request, the data to be read or written is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), name space) for the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, name space) may be part of the metadata of the host data.

[0052] In one embodiment, the memory subsystem may receive a first request to write a first set of host data ("first data set") and a second request to write a second set of host data ("second data set"). The memory subsystem may perform a write operation to write the first set of host data and the second set of host data on the memory device 300 such that a time elapsed between the write operations to an aggressor cell and a victim cell adjacent to the aggressor cell satisfies a time condition (e.g., is greater than a threshold time).

[0053] In one embodiment, it is determined that the time elapsed between performing a first write operation for a first data set and a first write operation for a second data set satisfies the time condition. In one example, the time condition may be satisfied because the first data set includes a large amount of data that has a write time longer than a threshold time. In another example, the time condition may be satisfied because the second request is received after the threshold time has elapsed from the time of the first write operation for the first data set. When the elapsed time satisfies the time condition, the memory subsystem may continue to use the memory subsystem as described above. Figure 2A Alternatively, the memory subsystem may switch to using the first mode described in Figure 2B The second mode described in is written into the second data set.

[0054] In one example, if Figure 3A As shown, the memory subsystem receives a first data set and performs write operations to write the first data set using the first pattern in memory cells 320a to 320n. After the last portion of the first data set is written to cell 320n, it is determined that the elapsed time has satisfied the time condition. The memory subsystem then receives a second data set and continues to perform write operations to write the second data set using the first pattern in memory cells 320o, 320p, etc. (e.g., continuing to skip alternate cells). When the end of word line 305f is reached (e.g., data written in cell 320z), the memory subsystem may switch to using the first pattern as shown. Figure 2BThe remaining write operations are performed in the second mode described in . In doing so, the time elapsed between the write operations to the adjacent cells 320a and 330a satisfies the time condition.

[0055] In another example, instead of continuing to perform write operations for the second data set using the first mode and writing in cell 320o, upon determining that the elapsed time satisfies the time condition, the memory subsystem may immediately switch to the second mode (e.g., reverse mode) and begin writing the second data set in cell 330a, and continue writing in cells 330b, 330c, etc., as shown in FIG. Figure 3B In doing so, the time elapsed between the write operations to adjacent cells 320a and 330a satisfies the time condition.

[0056] In one embodiment, it is determined that the time elapsed between performing a first write operation for a first data set and a first write operation for a second data set does not satisfy a time condition (e.g., the elapsed time is equal to or less than a threshold time). For example, a first data set received at time t1 may include a small amount of data that can be completely written in memory cell 320a at time t2. A second data set may be received at time t3, where the time elapsed between time t2 and time t3 is less than the threshold time. Therefore, the memory subsystem continues to perform write operations for the second data set in memory cells 320b, 320c, etc. using the first mode, so that write operations for the second data set are not performed on adjacent data cells. Once it is determined that the time elapsed from the write operation to cell 320a satisfies the threshold time, the memory subsystem may continue to write the remaining data in memory cells 320o, 320p, etc. using the first mode. Alternatively, the memory subsystem may switch to the second mode after the elapsed time satisfies the time condition, writing the remaining portion of the second data set to memory cells 330a, 330b, 330c, etc. In doing so, the time elapsed between the write operations to the adjacent cells 320a and 330a satisfies the time condition.

[0057] In a certain implementation, a different pattern other than the checkerboard and anti-checkerboard patterns is used to perform write operations. For example, instead of skipping a memory cell adjacent to an aggressor cell, the memory subsystem may skip two or more memory cells after writing data in the aggressor cell and continue the pattern. Various other patterns may be used that may cause the memory subsystem to perform consecutive write operations in cells that are not adjacent to each other while performing write operations in adjacent cells that have elapsed times that satisfy the time condition. Even though a particular pattern has been described, Figure 2A-2B and Figure 3A-3B Although the concepts in FIG. 1 are not limited to a specific pattern, a memory subsystem can use the described pattern to implement write operations in adjacent cells with a delay that is not limited to a specific pattern.

[0058] Figure 4 4 is a flow chart of an example method 400 for performing write operations in adjacent cells with delay according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The delay handling component 113 is executed. Although shown in a specific order or sequence, the order of the processing procedures can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0059] At operation 410, processing logic receives a request to write a set of host data. In some examples, processing logic may receive a first request to write a first set of host data and a second request to write a second set of host data. At operation 420, processing logic performs a write operation to write a first portion of the set of host data to a first set of memory cells of a memory device arranged in a first pattern. The first set of memory cells arranged in the first pattern includes alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells. In an example, the write operation is a continuous write operation.

[0060] At operation 430, processing logic performs a second plurality of write operations to write a second portion of the host data set to a second set of memory cells arranged in a second pattern. The second set of memory cells arranged in the second pattern includes other alternating memory cells adjacent to the first set of memory cells on each word line of the memory device. In one example, each of the second set of memory cells may be adjacent to each of the first set of memory cells. In some examples, performing the first plurality of write operations on the first set of memory cells arranged in the first pattern and performing the second plurality of write operations on the second set of memory cells arranged in the second pattern causes the time elapsed between writes to adjacent cells of the memory device to satisfy a time condition. In one example, the time elapsed satisfies the time condition when the time elapsed is greater than a threshold time. In one example, the previous logic performs the second plurality of write operations on the second set of memory cells arranged in the second pattern causing one of the alternating memory cells in the first set of memory cells arranged in the first pattern to be adjacent to a corresponding one of the other alternating memory cells in the second set of memory cells arranged in the second pattern. In some examples, the first pattern and the second pattern are predefined patterns that identify available memory cells for performing the first plurality of write operations and the second plurality of write operations, respectively.

[0061] Figure 5 is a flow chart of an example method 500 for performing a write operation using a time condition according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The delay handling component 113 is executed. Although shown in a specific order or sequence, the order of the processing procedures can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0062] At operation 510, processing logic performs a first write operation to write a first portion of a host data set at a first location of a memory device. In one example, the first location corresponds to a first memory cell of the memory device. The memory cell may be located at an intersection of a word line and a bit line.

[0063] At operation 520, processing logic monitors the time elapsed from when the first write operation was performed to determine whether the elapsed time satisfies the time condition. In one example, the elapsed time satisfies the time condition when the elapsed time is greater than a threshold time, and the elapsed time does not satisfy the time condition when the elapsed time is equal to or less than the threshold time.

[0064] At operation 530, processing logic performs a second write operation to write a second portion of the host data set at a second location of the memory device in response to determining that the elapsed time does not satisfy the time condition, wherein the second location is not adjacent to the first location. In one example, the first write operation and the second write operation are performed according to a first pattern that causes the first location to be non-adjacent to the second location. In some examples, the first pattern is a predefined pattern that identifies available locations for performing write operations. Additionally, processing logic continues to monitor the elapsed time to determine whether the elapsed time satisfies the time condition.

[0065] At operation 540, processing logic performs a third write operation to write a third portion of the set of host data at a third location of the memory device in response to determining that the elapsed time satisfies the time condition, wherein the third location is adjacent to the first location. Additionally, after performing the third write operation, processing logic performs a fourth write operation to write a fourth portion of the set of host data at a fourth location of the memory device, wherein the fourth location is adjacent to the second location. In one example, the second write operation and the fourth write operation are performed according to a second pattern that causes the third location to be adjacent to the first location and the fourth location to be adjacent to the second location.

[0066] Additionally, in response to determining that the elapsed time satisfies the time condition and before performing the third write operation, processing logic performs a fifth write operation to write a fifth portion of the host data set at a fifth location of the memory device, wherein the fifth location is not adjacent to the first location or the second location.

[0067] Figure 6 An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 The host system 120 may be used to execute the operation of the controller (for example, to execute an operating system to execute the corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0068] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0069] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0070] Processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 to communicate on a network 620.

[0071] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0072] In one embodiment, the instructions 626 include implementing a command corresponding to a delay handling component (e.g., Figure 1 The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0073] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical control of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0074] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0075] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as but not limited to any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present invention described herein may be implemented using a variety of programming languages.

[0077] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0078] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory device; as well as a processing device operatively coupled to the memory device to perform operations including: receiving a request to write a host data set; performing a first plurality of write operations to write a first portion of the set of host data to a first set of memory cells of the memory device arranged in a first pattern, wherein the first set of memory cells arranged in the first pattern includes alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells; as well as performing a second plurality of write operations to write a second portion of the set of host data to the second set of memory cells arranged in a second pattern, wherein the second set of memory cells arranged in the second pattern includes other alternating memory cells adjacent to the first set of memory cells on each word line of the memory device, Wherein performing the first plurality of write operations on the first set of memory cells arranged in the first pattern and performing the second plurality of write operations on the second set of memory cells arranged in the second pattern causes a time elapsed between writes to adjacent cells of the memory device to satisfy a time condition. 2 . The system of claim 1 , wherein the first plurality of write operations comprises consecutive write operations. 3 . The system of claim 1 , wherein the first pattern and the second pattern are predefined patterns that identify available memory for performing the first plurality of write operations and the second plurality of write operations, respectively. The system of claim 1 , wherein the elapsed time satisfies the time condition when the elapsed time is greater than a threshold time.

5. The system of claim 1 , wherein performing the second plurality of write operations on the second set of memory cells arranged in the second pattern causes one of the alternating memory cells in the first set of memory cells arranged in the first pattern to be adjacent to a corresponding one of the other alternating memory cells in the second set of memory cells arranged in the second pattern.

6. A method comprising: performing a first write operation to write a first portion of a set of host data to a first location of a memory device; monitoring a time elapsed from when the first write operation is performed to determine whether the elapsed time satisfies a time condition; In response to determining that the elapsed time does not satisfy the time condition: performing, by a processing device, a second write operation to write a second portion of the host data set to a second location of the memory device, wherein the second location is not adjacent to the first location; as well as continuing to monitor the elapsed time to determine whether the elapsed time satisfies the time condition; as well as In response to determining that the elapsed time satisfies the time condition, a third write operation is performed to write a third portion of the set of host data to a third location of the memory device, wherein the third location is adjacent to the first location. 7 . The method of claim 6 , wherein the elapsed time satisfies the time condition when the elapsed time is greater than a threshold time, and wherein the elapsed time does not satisfy the time condition when the elapsed time is equal to or less than the threshold time.

8. The method according to claim 6, further comprising: After performing the third write operation, a fourth write operation is performed to write a fourth portion of the host data set at a fourth location of the memory device, wherein the fourth location is adjacent to the second location.

9. The method of claim 6, wherein the first write operation and the second write operation are performed according to a first pattern that causes the first location to be non-adjacent to the second location.

10. The method of claim 9, wherein the first pattern is a predefined pattern that identifies available locations for performing write operations.

11. The method of claim 8, wherein the second and fourth write operations are performed according to a second pattern causing the third position to be adjacent to the first position and the fourth position to be adjacent to the second position.

12. The method according to claim 6, further comprising: In response to determining that the elapsed time satisfies the time condition and before performing the third write operation, performing a fifth write operation to write a fifth portion of the host data set at a fifth location of the memory device, wherein the fifth location is not adjacent to the first location or the second location.

13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: performing a first write operation to write a first portion of a set of host data to a first location of a memory device; monitoring a time elapsed from when the first write operation is performed to determine whether the elapsed time satisfies a time condition; In response to determining that the elapsed time does not satisfy the time condition: performing a second write operation to write a second portion of the host data set to a second location of the memory device, wherein the second location is not adjacent to the first location; as well as continuing to monitor the elapsed time to determine whether the elapsed time satisfies the time condition; as well as In response to determining that the elapsed time satisfies the time condition, a third write operation is performed to write a third portion of the set of host data at a third location of the memory device, wherein the third location is adjacent to the first location.

14. The non-transitory computer-readable storage medium of claim 13, wherein the elapsed time satisfies the time condition when the elapsed time is greater than a threshold time, and wherein the elapsed time does not satisfy the time condition when the elapsed time is equal to or less than the threshold time.

15. The non-transitory computer-readable storage medium of claim 13, wherein the processing device further: After performing the third write operation, a fourth write operation is performed to write a fourth portion of the host data set at a fourth location of the memory device, wherein the fourth location is adjacent to the second location. 16 . The non-transitory computer-readable storage medium of claim 13 , wherein the first write operation and the second write operation are performed according to a first pattern that causes the first location to be non-adjacent to the second location. 17 . The non-transitory computer-readable storage medium of claim 16 , wherein the first pattern is a predefined pattern that identifies available locations for performing a write operation.

18. The non-transitory computer-readable storage medium of claim 15, wherein the second write operation and the fourth write operation are performed according to a second pattern causing the third position to be adjacent to the first position and the fourth position to be adjacent to the second position.

19. The non-transitory computer-readable storage medium of claim 16, further comprising: In response to determining that the elapsed time satisfies the time condition and before performing the third write operation, performing a fifth write operation to write a fifth portion of the host data set at a fifth location of the memory device, wherein the fifth location is not adjacent to the first location or the second location.

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