Data Compression for Global Column Repair

Abstract

This application relates to data compression for global column repair. In some cases, a test device may perform a first internal read operation to identify errors associated with one or more column planes. Values (e.g., bits) indicating whether an error occurred when each column plane was tested may be stored. The test device may perform a second internal read operation on the same column surface or on column planes of different banks of memory cells. The values (e.g., bits) indicating whether an error occurred during the first internal read operation and the values indicating whether an error occurred during the second internal read operation may be combined and stored in a register. The stored values may be read out (e.g., as a burst) to repair defective column planes.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 716,366, filed Dec. 16, 2019, by Johnson, titled “DATA COMPRESSION FOR GLOBAL COLUMN REPAIR,” which is assigned to its assignee and the entire contents of which are hereby incorporated by reference in their entirety.

[0003] The technical field relates to data compression for global column repair. Background Art

[0004] The following generally relates to one or more memory systems and, more particularly, to data compression for global column repair.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states and any of the states can be stored. To access the stored information, a component can read or sense at least one of the stored states in the memory device. To store information, a component can write or program a state in the memory device.

[0006] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logical state for an extended period even in the absence of an external power source. Volatile memory devices (e.g., DRAM) lose their stored state when disconnected from an external power source. Summary of the Invention

[0007] A method is described. In some instances, the method includes generating first data using a first read operation to identify one or more errors associated with memory cells of a first plurality of column planes of a memory device, the first data including a first plurality of indicators regarding whether each column plane of the first plurality of column planes includes the one or more errors; generating second data using a second read operation to identify one or more errors associated with memory cells of a second plurality of column planes of the memory device, the second data including a second plurality of indicators regarding whether each column plane of the second plurality of column planes includes the one or more errors; combining the first data and the second data into third data including a third plurality of indicators regarding whether the first plurality of column planes and the second plurality of column planes include one or more errors; and communicating a message including the third data formed by combining the first data and the second data through the memory device.

[0008] An apparatus is described. In some instances, the apparatus may include a memory array including a first plurality of column planes and a second plurality of column planes; and a tester coupled to the memory array, and the tester is configured to cause the apparatus to: generate first data to identify one or more errors associated with memory cells of the first plurality of column planes; generate second data to identify one or more errors associated with memory cells of the second plurality of column planes of the storage device; combine the first data and the second data into third data including a third plurality of indicators regarding whether the first plurality of column planes and the second plurality of column planes include one or more errors; and communicate a message including the third data formed by combining the first data and the second data.

[0009] An apparatus is described. In some instances, the apparatus may include a memory array including a plurality of memory cells, the plurality of memory cells including a first plurality of column planes and a second plurality of column planes; a data generation component configured to generate first data to identify one or more errors associated with the first plurality of column planes and generate second data to identify one or more errors associated with the second plurality of column planes; a data combination component configured to combine the first data and the second data into third data including a plurality of indicators regarding whether the first plurality of column planes and the second plurality of column planes include one or more errors; and a transmission component configured to transmit a message including the third data formed by combining the first data and the second data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Illustrates an example of a system supporting data compression for global column repair in accordance with an example disclosed herein.

[0011] Figure 2 An example of a test setup that supports data compression for global column repair according to the examples disclosed herein.

[0012] Figure 3 An example of a repair area of a memory array that supports data compression for global column repair according to the examples disclosed herein.

[0013] Figure 4 An example register of a memory device that supports data compression for global column repair according to the examples disclosed herein.

[0014] Figure 5 An example of instance data stored in a register of a memory device that supports data compression for global column repair according to the examples disclosed herein.

[0015] Figure 6 A block diagram of a memory device that supports data compression for global column repair according to the examples disclosed herein.

[0016] Figure 7 A flowchart illustrating a method that supports data compression for global column repair according to the examples disclosed herein. DETAILED DESCRIPTION

[0017] Designers and manufacturers of memory devices may test aspects of a memory device for electrical defects, such as unexpected conductive paths (e.g., short circuits or leaks) or disconnections (e.g., open circuits), for example, for quality control purposes or as part of a design process. Testing for electrical defects can be used to verify or refine a device design or a device manufacturing process. Some techniques for testing electrical defects may use additional storage devices (e.g., additional memory arrays) to store test data.

[0018] As the size of a memory cell array increases, the amount of data generated by testing also increases. Data can then be read from the test cells to determine whether an error has occurred associated with the corresponding memory cells. In this test configuration, as the size and density of the memory array grow, the memory amount of the tester used to perform the test can also increase. Additionally, due to the relatively large amount of data stored in the test cells, the time to read data from the test cells (e.g., the time required to perform a test operation) may be undesirably long. Thus, it may be desirable to reduce the memory amount of the tester used during a test program for storing data.

[0019] This document describes a memory system configured to test aspects of a memory device using compressed data. The storage system may include a plurality of memory cells arranged in a bank. Each bank may include one or more column planes, and each column plane may include rows and columns of individual memory cells. A column plane may refer to a set of memory cells that can be tested during any one test operation. During a global column repair operation, data may be read from any column plane. Since a column plane includes a plurality of memory cells, typically a plurality of data bits may be read out from the column plane. However, as described herein, the data may be compressed (e.g., into a single data bit) which indicates whether an error has occurred when testing the associated memory cells. Based on the occurrence of an error, an individual column plane may be repaired.

[0020] Data read out from a column plane may be stored into a portion of the memory array (e.g., a register). When testing a subsequent column plane, the associated data (e.g., associated data bits) may be stored in the register. When testing a column plane, the associated data may be compressed using the data that has already been stored in the register. Thus, if the column plane subsequently fails (i.e., if an error occurs in the column plane during a subsequent test), then the data stored in the register may be updated. Thus, a single data bit indicating the most recent test result associated with each column plane may be stored in the register. Due to the compression of data from multiple tests, a relatively small amount of data associated with each column plane may be stored in the memory device. This data compression may reduce the amount of information communicated to and stored by the tester during a test operation. This reduction in information may reduce the time to perform the test operation and may reduce the amount of memory used by the tester (and thereby avoid a memory overflow at the tester).

[0021] First, the features of the present invention are described in the context of a memory system and test setup as described in reference Figure 1 and 2 The features of the present invention are described in the context of the repair area of the memory device and the data stored in an associated register as described in reference Figures 3 to 5 These and other features of the present invention are further illustrated and described with reference to device diagrams and flowcharts related to the data compression for global column repair as described in reference Figure 6 and 7 These and other features of the present invention are described with reference thereto.

[0022] Figure 1Describe an example of a system 100 that supports data compression for global column repair according to the examples disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 that couple the host device 105 to the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] The system 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. The memory device 110 may be a component of a system that is operable to store data for one or more other components of the system 100.

[0024] At least a portion of the system 100 may be an example of the host device 105. The host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, for example, within other examples such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or some other fixed or portable electronic device. In some examples, the host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 120. In some examples, the external memory controller 120 may be referred to as the host or host device 105.

[0025] The memory device 110 may be a stand-alone device or component that is operable to provide physical memory addresses / spaces that may be used or referenced by the system 100. In some examples, the memory device 110 may be configured to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

[0026] The memory device 110 is operable to store data for components of the host device 105. In some instances, the memory device 110 may act as a slave device of the host device 105 (e.g., in response to and executing commands provided by the host device 105 via the external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0027] The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). Components of the host device may be coupled to each other using a bus 135.

[0028] The processor 125 is operable to provide control or other functionality for at least part of the system 100 or at least part of the host device 105. The processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these components. In such instances, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system on a chip (SoC), among other examples. In some instances, the external memory controller 120 may be implemented by the processor 125 or be part of the processor 125.

[0029] The BIOS component 130 may be a software component that includes the BIOS operating as firmware, which may initialize and run various hardware components of the system 100 or the host device 105. The BIOS component 130 may also manage the data flow between the processor 125 and various components of the system 100 or the host device 105. The BIOS component 130 may include a program or software stored in one or more of a read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), where each memory cell is operable to store at least one data bit. In some instances, each memory array 170 may include one or more column planes for testing. When testing a column plane, data associated with the memory cells may be read and compressed (e.g., compressed into a single bit). The compressed data may indicate whether an error occurred during the test operation.

[0031] The external memory controller 120 may be operable to enable communication of one or more of information, data, or commands between the components of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may translate or transpose the communications exchanged between the components of the host device 105 and the memory device 110. In some instances, the external memory controller 120 or other components of the system 100 or host device 105, or its functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, software, or some combination thereof implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is described as being external to the memory device 110, in some instances, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), and vice versa.

[0032] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an instance of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. The signal path may be an instance of a conductive path operable to carry a signal. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an instance of a conductive input or output point of a device of the system 100, and the pin may be operable to act as part of the channel.

[0033] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some instances, communication may occur over the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal may be latched for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be latched for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0034] The memory device 110 may undergo a test operation to identify defective memory cells. In some cases, the test operation may occur as part of the manufacturing process of the memory device 110. During the test operation, the memory device 110 may be coupled to a tester (e.g., the tester 210 as described in reference Figure 2 The tester may test individual column planes of the memory array 170 during respective test operations. When testing a single column plane, data indicating whether an error has occurred associated with a corresponding memory cell may be compressed (e.g., compressed into a single bit). Thus, when testing a column plane, a single bit may be generated indicating whether any one of the memory cells within the column plane is defective. The bit (and bits associated with other column planes) may be stored in a designated portion of the memory device 110.

[0035] The tester can initiate an internal read operation to test one or more column planes at a time. The data from each internal read can be stored in a register. In some memory systems, the data from each internal read can be output by the memory device 110 to the tester. To reduce the amount of data communicated to or stored by the tester, the memory device 110 can compress the data from multiple internal read operations into a single register and output the compressed data to the tester. When compressing, some data may be lost. For example, both column plane 0 in the first internal read operation and column plane 0 in the second internal read operation have errors. That is, the bits stored in the register can reflect whether an error associated with the corresponding column plane index value occurred during any of the internal read operations. The stored bits can be read out to the tester as part of a command sequence that includes bits associated with test operations for other column planes. Due to the compression of data from subsequent tests, a relatively small amount of data associated with each column plane can be stored in the memory device 110. Such operations can reduce the amount of data communicated to and stored by the tester (which can reduce the likelihood of a memory overflow occurring at the tester). Such operations can also reduce the time used to read data from the test unit.

[0036] Figure 2 An example of a test setup 200 that supports data compression for global column repair as disclosed herein is described. The test setup 200 can involve a memory die 205 coupled to a tester 210. The memory die 205 can be an example of the memory die 160 as described with reference to Figure 1 In some cases, the methods described herein can be performed during a test operation of the memory die 205. The data generated during the test operation can be compressed and stored as a series of bits in a register 220, which can reduce the number of memory cells designated for storing test data and can also reduce the time used to read data from the test unit. In some instances, the memory die 205 can be replaced by more general logic circuitry without departing from the scope of the present invention.

[0037] The memory die 205 can include one or more memory arrays, which can be subdivided into memory banks that include memory banks 215. The memory banks 215 can contain one or more column planes, each of which contains a different subset of memory cells housed in one or more memory arrays. Additionally, each memory bank can include one or more access lines (e.g., word lines or bit lines), where each access line is coupled to at least one of the corresponding subset of memory cells.

[0038] In some instances, the memory bank 215 can be coupled to the register 220. The register 220 can be configured to store test data associated with the memory bank 215. For example, the tester 210 can initiate one or more internal read operations to test one or more column planes of the memory bank 215, and the resulting data can be compressed and / or stored in the register 220. In some instances, one or more column planes can be tested one or more times, and the resulting data can be stored in the register 220. The data can be stored as a series of bits indicating whether an error occurred during a test operation at a corresponding column plane index value. The data stored in the register 220 can be read out (e.g., as a burst) to the tester 210. Then, the tester 210 can determine how to correct any detected errors. In some instances, the tester 210 can be configured to use a global repair area to repair one or more portions of the memory bank 215.

[0039] As the size of the memory die or the density of memory cells increases, the amount of data generated during a test operation also increases. To analyze the test data, the tester 210 can include memory to store data received from the memory die 205. In some cases, the amount of data generated by testing the memory die can exceed the memory of the tester 210, such that a memory overflow can occur. In such an event, the test may fail, and the test operation may not produce usable data. Techniques for compressing data at the memory die 205 to reduce the amount of data communicated to the tester 210 and the amount of data stored by the tester 210 are described. Such techniques can reduce the latency of the test operation, can reduce the likelihood of a memory overflow at the tester 210, or can produce other advantages.

[0040] Figure 3 An example of a repair area 300 of a memory array that supports data compression for global column repair according to an example disclosed herein is illustrated. The repair area 300 can include one or more column planes 305, each of which includes one or more columns of memory cells and a repair column plane 310. For example, the repair area 300 can include column planes 305-a through 305-n, where column 305-n represents the Nth column plane of the repair area 300. The repair column plane 310 can include one or more columns that can be used to replace a faulty column in another column plane 305 of the repair area 300. For example, if it is determined that column 2 of column plane 3 (e.g., column plane 305-c) of the repair area 300 is faulty, then the address for this faulty column can be redirected to a column in the repair column plane 310.

[0041] In some instances, the column planes 305 may be repaired during a test process that uses identified memory (e.g., the failed memory of a tester) designated to store errors associated with the repair area 300. Errors associated with the repair area 300 may be identified using OR logic (e.g., one or more OR gates), which can reduce the amount of data output from the memory array and also reduce the amount of failed memory required to identify errors associated with each of the column planes 305 of the repair area 300.

[0042] The repair area 300 may include column planes 305-a through 305-n, and each column plane (CP) may include one or more rows and / or columns of memory cells. For example, the repair area 300 may include thirty-four (34) column planes 305, each of which includes one or more rows and / or columns of memory cells. That is, the memory array may include one or more banks that include one or more repair areas, such as the repair area 300. When an error associated with a column plane 305 is identified, an indication may be stored that allows the defective column plane 305 to be fixed or replaced by a column of the repair column plane 310 in the repair area 300. In some instances, each column plane 305 may be located on the same memory die as the failed memory.

[0043] In some instances, the repair area 300 may be one of several repair areas within a bank of the memory array. That is, the memory array may include multiple banks, and each bank may include one or more repair areas, such as the repair area 300. Techniques are described for performing internal read operations as part of a test operation over multiple repair areas. Data from each internal read operation may be compressed into a single set of data output to a test device. In some cases, similar errors may occur in similar regions of the memory die (e.g., more errors may occur in repair areas near the edge of the memory die). To reduce the likelihood of data loss due to data compression, the test operation may include an interleaved internal read operation pattern of the banks (i.e., alternating read operations between banks), which can result in errors local to a particular column plane 305 being more easily detected.

[0044] During the manufacturing test phase, an internal read operation can be applied to one or more column planes 305 to determine if an error has occurred. Error data for each column plane in the internal read can be stored in a register. For example, the internal read operation can test 34 column planes for errors, and the associated register can have at least 34 bit positions to store the error data for each column plane tested as part of the internal read operation. Each column plane 305 can include a plurality of memory cells, each of which can be associated with an error. Thus, a relatively large amount of data can be read from any one column plane 305. To minimize the amount of failed memory data stored to the tester, one or more compression schemes can be used to compress the data read from each column plane 305 to a single bit. For example, the compressed data can indicate if an error occurred when testing the column plane 305. For example, if an error occurred when testing the column plane 305, the compressed bit can be a logical value of "1", and if no error occurred when testing the column plane 305, the compressed bit is a logical value of "0". The logical value can be stored in a register of the memory device before being output to the tester.

[0045] Rather than sending the data after each internal read operation, multiple read operations can be performed and stored in a register before being output to the tester. Error data from a second internal read can be stored in the same register as the first internal read operation. For example, when storing the error data in the register, the value stored in the register (e.g., the error data associated with the first read operation) can be ORed with the data from the second internal read operation. In this way, the data from the first internal read operation and the second internal read operation can be compressed into a single register before being output to the tester.

[0046] After performing one or more internal read operations, the data stored in the register can be read out. This can be referred to as a readout or read operation. The data can be read out as a single command sequence (i.e., a single burst) and can be read into a device coupled to the memory array, such as a test device (e.g., a tester). The command sequence can include a plurality of bits that indicate, for example, if a particular column plane 305 experienced an error during a particular internal read and / or if any error associated with the column plane 305 occurred, etc. The read operation can facilitate the repair of one or more failed column planes 305. For example, the tester can use the data read from the memory device to determine which column of the repair column plane 310 to use to replace which failed column of one or more column planes 305 of the repair region 300.

[0047] Figure 4Describe example register 400 of a memory device that supports data compression for global column repair according to the examples disclosed herein. Register 400 may include combinational register 455 and serial output register 460. Each register 400 may include a storage device for storing logical values indicating whether a particular column plane (e.g., column plane 305 as referenced Figure 3 described) has experienced an error, whether any errors associated with the column plane occurred during a particular internal read, and whether the error is associated with an even and / or odd address. Logical values associated with an internal read operation of the memory array may be stored into combinational register 455 and may be shifted (e.g., transferred) to serial output register 460 to be read out as a single burst (e.g., read out to a test device).

[0048] Combinational register 455 may correspond to a portion of the memory array. Specifically, combinational register 455 may be associated with column planes 305 of repair region 300 as described with reference to Figure 3 . For example, CP0 405 may store a logical value indicating whether an error occurred during an internal read of column plane 305-a of an internal read operation. Similarly, CP1 410 and CP2 415 may store corresponding logical values indicating whether an error occurred during internal reads of column plane 305-b and column plane 305-c, respectively.

[0049] Combinational register 455 may include storage devices up to and including CPn 420 that store an indication of whether an error occurred during an internal read of the Nth column plane (column plane 320-n) as described with reference to Figure 3 . For example, if an internal read operation can test 34 column planes at a time, combinational register 455 may include 34 bit positions to store error data for each column plane tested as part of a single internal read operation. In some examples, the Nth column plane may represent the final column plane within repair region 300 (e.g., the 34th column plane of repair region 300). Error data from multiple internal read operations may be compressed into combinational register 455.

[0050] Combinational register 455 may also store a logical value indicating whether an error occurred during a particular internal read operation. For example, RD0 425 may store a logical value indicating whether an error occurred during a first internal read operation of the repair region. Similarly, RD1 may store a logical value indicating whether an error occurred during a second internal read operation of the repair region (a different repair region or the same repair region as the first internal read). Combinational register 455 may include storage devices up to and including RDn 435 that store whether an error occurred during an internal read as described with reference to Figure 3An indication of whether an error occurred during the Nth internal read of the repair region 300. In some instances, a number of internal read operations (e.g., up to eight (8) internal read operations) occur before transferring data to the serial output register 460. The number of internal read operations that can be compressed into a single readout command can be related to the number of bit positions in the register 455 configured to store whether a particular internal read operation contains an error. From the error data regarding the column planes and the error data regarding the internal read operations, the tester may be able to reconstruct which column planes have errors and can determine how to repair such column planes. In some cases, the bit positions in the register 455 may be referred to as bit indices.

[0051] Examples of how the compression scheme can work can include ORing the bits when inputting the bits into the combined register 455. The memory device may perform a first internal read operation of a first repair region. The error data for each column plane in the repair region may be stored in the column plane bit positions in the combined register region 455. For example, if no error occurred during the first internal read operation, then the bit positions for the column planes (e.g., CPn 405 to 420) may all be logic "0", and the bit position for the first internal read operation (e.g., RD0 425) may also be logic "0". The memory device may perform a second internal read operation of a second repair region. The error data for each column plane in the second repair region may be ORed with the data already stored in the combined register 455, and the resulting data may be stored in the combined register 455. For example, if no error occurred during the second internal read operation, then the bit positions for the column planes (e.g., CPn 405 to 420) may all be logic "0" after the OR, and the bit position for the second internal read operation (e.g., RD1 430) may also be logic "0". However, if an error did occur during the second internal read operation, then at least one of the column plane bit positions will contain a logic "1", and the internal read operation bit position (e.g., RD1 430) may also contain a logic "1".

[0052] The combined register 455 may store logical values indicating whether an error occurred associated with even and / or odd addresses. For example, if an error occurred associated with an even address (e.g., even gap) of the repair region 300, then E 440 may store a logical value "1". Similarly, if an error occurred associated with an odd address (e.g., odd gap) of the repair region 300, then O 445 may store a logical value "1". If no error occurred associated with even and / or odd addresses, then E 440 and / or O 445 may store a logical value "0". By storing an indication of whether an error occurred in even and / or odd gaps in the combined register 455, additional information regarding where the error occurred can be determined.

[0053] During a first internal read operation, a logical value indicating whether an error occurred during the internal read of each column plane can be stored in the combinational register 455. For example, no error is determined during the first internal read and read, and the logical value "0" can be stored in each of CP0 405, CP1 410, CP2 415, and CPn 420. Similarly, the logical value "0" can be stored in RD0 425 to indicate that no error was detected during the first internal read.

[0054] During subsequent internal read operations, the logical value associated with each of CP0 405, CP1 410, CP2 415, and CPn 420 can be compared with the value stored in the combinational register 455 before being stored. Specifically, when comparing logical values, OR logic (e.g., an OR gate) can be used. For example, during a second internal read operation, an error associated with the first column plane of the first repair area can be determined. The associated logical value "1" (indicating that an error occurred) can be compared with the logical value "0" of CP0 405 stored in the combinational register 455. Since OR logic can be used to compare the logical values, the logical value stored in CP0 405 can be updated to store the logical value "1". That is, due to the occurrence of an error associated with the corresponding column plane, the logical value "0" can be overwritten with the logical value "1". In this example, the logical value "1" can be stored in RD1 430 to indicate that an error was detected during the second internal read operation. Using OR logic when storing the logical value in the combinational register 455 can reduce the amount of failed memory required to identify errors associated with each of the column planes of the repair area at the tester.

[0055] In some instances, logical values may be stored in the combinational register 455 as part of a bank interleaving operation. Sometimes, errors on the memory device may occur in similar locations on the memory die. For example, more errors may occur near the edge of the die than in the middle of the die. With the data compression scheme described herein, data conflicts may occur when information is lost due to data compression. For example, if the column plane indexed as CP0 contains an error in multiple internal read operations, the tester may not be able to determine whether the CP0 associated with the first internal read operation has failed, or whether the CP0 of a different internal read operation has failed. To reduce the likelihood of the same column plane failing during the same data compression, the repair regions tested by successive internal read operations may be interleaved between banks or between different locations on the memory die. In other instances, when a memory cell within a column plane experiences an error, the likelihood of the error affecting surrounding memory cells increases. When the error affects surrounding memory cells, the column plane may be incorrectly indicated as faulty, which may result in the column plane being unnecessarily repaired (i.e., over-repaired). To minimize over-repair, the column planes may be tested by alternating (e.g., interleaving) the banks.

[0056] When interleaving the banks, a first bank may be selected for a first internal read operation, and a second bank (e.g., a different bank) may be selected for a second internal read operation. That is, the column plane of the first bank may be read during the first internal read operation, and the column plane of the second (e.g., subsequent) internal read operation may be read during the second internal read operation. Because similar errors associated with the same column plane of different banks (e.g., the first column plane of the first bank and the first column plane of the second bank) are less likely, local errors may be more clearly distinguishable in the compressed data by interleaving the banks. That is, the cases where the column plane is incorrectly identified as faulty may be isolated to a particular bank and / or a particular column plane, which may reduce the number of times any one column plane is unnecessarily repaired.

[0057] In some instances, the data stored in the combinational register 455 may be read out (e.g., transferred) to the serial output register 460 based on the occurrence of an event. For example, the data may be transferred after a predefined number of internal read operations, or the data may be transferred based on the associated memory device receiving a command (e.g., a readout command) from an external device such as a test device. The data may be transferred from the combinational register 455 to the serial output register 460 via one or more buses. Once the data is stored in the serial output register 460, the data may be serially read out (e.g., to an external device such as a test device).

[0058] When data is read from the serial output register 460, it can be read as a single command sequence (e.g., as a single burst). The command sequence can be, for example, forty-eight (48) data bits, which indicate whether an error has occurred associated with a particular column plane, whether an error has occurred associated with a particular internal read operation, etc. Thus, the size of the data read can depend on the number of several internal operations and / or the number of column planes checked in each read. In other instances, the sequence can be fifty-six (56) bits. The additional eight (8) bits can be associated with additional data compression. In any instance, the data can be read serially (from the serial output register 460).

[0059] In other instances, a read-modify-write (RMW) operation can occur. During the RMW operation, whenever a read command is received, a subset of the bits stored in the serial output register 460 can be read. For example, when a read command is received, eight (8) bits can be read from the serial output register 460. When an additional read command is received, additional bits stored in the serial output register 460 can be read. The RMW operation can be implemented according to a design choice to save time that would otherwise be dedicated to reading all the bits (e.g., all forty-eight (48) bits) from the serial output register 460.

[0060] By way of example, a first compression operation is described, in which up to twelve (12) internal read operations are compressed into a single read operation. In some instances, it may be desirable to use DDR to internally read eight (8) banks of memory cells respectively. Each internal read operation can include thirty-four (34) column planes (or seventeen (17) column planes, each of which is read twice for redundancy purposes). In some instances, the compression scheme for reading the banks of memory cells can allow data to be read from the banks in an eight (8)-bit burst. Thus, the command sequence saved to the combined register 455 and transferred to the serial output register 460 can be forty-eight (48) bits (e.g., bits <0:33> can be used for error data of individual column planes, bits <34:45> can be used for error data associated with internal read operations, and bits <46:47> can be used for even / odd error data).

[0061] Out of the forty-eight (48) bits, the first thirty-four (34) bits can be reserved for storing an indication of whether an error has occurred during the internal read of the corresponding column plane, and two (2) bits can be reserved for storing an indication of whether an error has occurred associated with even and / or odd addresses. Thus, twelve (12) bits are left and can be used to indicate whether an error has occurred in a particular internal read operation. That is, the eight (8) banks of memory cells can be read up to twelve (12) times in total. The forty-eight (48) bits can be transferred from the combined register 455 to the serial output register 460, where it can be read out (e.g., to a test device).

[0062] Describing the second compression operation by way of example, where up to twenty (20) internal read operations are compressed into a single read operation. In some examples, it may be desirable to internally read each of the sixteen (16) banks of memory cells seven (7) times using DDR. Each internal read operation may include thirty-four (34) column planes (or seventeen (17) column planes each read twice for redundancy purposes). In some examples, the compression scheme for reading the banks of memory cells may allow data to be read from the banks in an eight (8)-bit burst. Thus, the command sequence saved to the combined register 455 and transferred to the serial output register 460 may be fifty-six (56) bits (e.g., bits <0:33> may be used for error data of individual column planes, bits <34:53> may be used for error data associated with the internal read operation, and bits <54:55> may be used for even / odd error data).

[0063] Of the fifty-six (56) bits, the first thirty-four (34) bits may be reserved for an indication of whether an error occurred during the internal read of the corresponding column plane, and two (2) bits may be reserved for an indication of whether an error occurred associated with an even and / or odd address. Thus, twenty (20) bits remain and may be used to indicate whether an error occurred during a particular internal read operation. That is, the sixteen (16) banks of memory cells may be read up to twenty (20) times in total. The fifty-six (56) bits may be transferred from the combined register 455 to the serial output register 460, where they may be read out (e.g., to a test device).

[0064] Describing the third compression operation by way of example, where up to twenty (20) internal read operations are compressed into a single read operation. In some examples, it may be desirable to internally read each of the sixteen (16) banks of memory cells fourteen (14) times using SDR. Each internal read operation may include thirty-four (34) column planes (or seventeen (17) column planes each read twice for redundancy purposes). In some examples, the compression scheme for reading the banks of memory cells may allow data to be read from the banks in a two (2)-bit burst (i.e., a four (4)-bit burst when converted to DDR). Thus, the command sequence saved to the combined register 455 and transferred to the serial output register 460 may be fifty-six (56) bits (e.g., bits <0:33> may be used for error data of individual column planes, bits <34:53> may be used for error data associated with the internal read operation, and bits <54:55> may be used for even / odd error data).

[0065] Out of the fifty-six (56) bits, the first thirty-four (34) bits may be reserved to store an indication of whether an error occurred during an internal read in the corresponding column plane, and two (2) bits may be reserved to store an indication of whether an error associated with an even and / or odd address occurred. Thus, twenty (20) bits are left and available to indicate whether an error occurred during a particular internal read operation. That is, a total of twenty (20) reads may be performed on the banks of memory cells (e.g., the fourteen (14) banks of memory cells). The fifty-six (56) bits may be transferred from the combinational register 455 to the serial output register 460, where they may be read out (e.g., to a test device) at the combinational register 455.

[0066] Figure 5 Illustrative data 500 for a register storing to a memory device in support of data compression for global column repair according to an example disclosed herein. The register may be an example of the combinational register 455 or the serial output register 460 as described with reference to Figure 4 The register may include a storage device for storing logical values indicating whether a particular column plane (e.g., column plane 305 as described with reference to Figure 3 experienced an error, whether any error associated with the column plane occurred during a particular internal read, and whether the error is associated with an even and / or odd address. The stored logical values may be stored into a combinational register (e.g., the combinational register 455 as described with reference to Figure 4 and may be moved (e.g., transferred) to a serial output register (e.g., the serial output register 460 as described with reference to Figure 4 for a single burst readout (e.g., read out to a test device).

[0067] In some examples, the data 500 may illustrate the various results of a compression operation that includes multiple internal read operations. The register storing the data 500 may be associated with the column plane 305 of a repair region 300 as described with reference to Figure 3 For example, CP0 505 may store a logical value indicating whether an error occurred during an internal read of column plane 305-a. Similarly, CP1 510 and CP2 515 may store corresponding logical values indicating whether an error occurred during internal reads of column plane 305-b and column plane 305-c, respectively. The register may include a storage device up to and including CPn 520 that stores an indication of whether an error occurred during an internal read of the Nth column plane (column plane 320-n) as described with reference to Figure 3

[0068] ​The register may also store a logical value indicating whether an error occurred during a particular internal read operation. For example, RD0 525 may store a logical value indicating whether an error occurred during a first internal read of the repair area 300. Similarly, RD1 530 may store a logical value indicating whether an error occurred during an internal read of the column plane 305-b. The combined register 455 may include a storage device up to and including RDn 535 that stores an indication of whether an error occurred during the Nth internal read of the repair area 300 as described in reference Figure 3 The register may also store a logical value indicating whether an error associated with an even and / or odd address occurred. For example, if an error associated with an even address (e.g., an even gap) of the repair area 300 occurs, then E 540 may store the logical value “1”. Similarly, if an error associated with an odd address (e.g., an odd gap) of the repair area 300 occurs, then O 545 may store the logical value “1”. If no error associated with an even and / or odd address occurs, then E 540 and / or O 545 may store the logical value “0”.

[0069] In some instances, multiple internal read operations of the column plane may result in a pass 555. That is, no error may be identified when performing each internal read of each column plane. Accordingly, each of CP0 505 to CPn 520 may store the logical value “0”, each of RD0 525 to RDn 535 may store the logical value “0”, and each of E 540 and O 545 may store the logical value “0”. These values may be read out as a single command sequence (e.g., read out to a test device). The tester may be configured to determine that the column plane in the compressed data should not be repaired based on the pass 555.

[0070] In some instances, multiple internal read operations of the column plane may result in a single failure 560. That is, a single error may be identified during a single internal read operation of multiple internal read operations that are compressed into a single set of data. For example, the error may be associated with the first column plane and may occur during the first internal read operation. Accordingly, CP0 505 may store the logical value “1”, RD0 525 may store the logical value “1”, and E 540 may store the logical value “1”. All other values stored in the register may be logical “0”. These values may be read out as a single command sequence (e.g., read out to a test device). The tester may be configured to determine which column plane needs to be repaired based on which CPn bit is set to the logical “1” and which RDn bit is set to the logical “1”. In some cases, the tester may use prior information about the mapping of the internal read operations to determine which column plane failed.

[0071] In some instances, multiple internal read operations of a column plane can result in two failures 565. That is, two errors can be identified during a single internal read operation of compressed data. For example, the errors can be associated with the second and third column planes and can occur during the second internal read operation. Thus, CP1 510 can store a logical value of "1", CP2 515 can store a logical value of "1", RD1 525 can store a logical value of "1", and E 540 can store a logical value of "1". All other values stored in the registers can be logical "0". These values can be read out as a single command sequence (e.g., read out to a test device). The tester can be configured to determine which column plane needs to be repaired based on which CPn bits are set to logical "1" and which RDn bits are set to logical "1". In some cases, the tester can use prior information about the mapping of internal read operations to determine which column plane has failed.

[0072] In some instances, multiple internal read operations of a column plane can result in multiple failures and data conflicts 570. Data conflicts can occur when multiple failures occur during different internal reads (or during internal reads of different banks), and can cause one or more column planes to be over-repaired. A data conflict refers to a situation where data compression from multiple internal read operations causes information loss and the tester cannot reliably determine which column plane should be repaired. To minimize conflicts, column and / or row failures of a specific column plane can be identified. Circuitry such as the repair analyzer (RA) described herein can be used to identify column and / or row failures.

[0073] Internal read operations that result in multiple data failures and data conflicts 570 can be identified during internal read operations of two different banks. For example, the errors can be associated with the second and third column planes and can occur during the first internal read operation of the first bank and the second internal read operation of the second bank. Thus, without knowing which columns and / or rows of the column plane have failed, it may not be possible to determine which internal reads have caused which errors. For example, CP1 510 can store a logical value of "1", CP2 515 can store a logical value of "1", RD0 525 can store a logical value of "1", RD1 530 can store a logical value of "1", E 540 can store a logical value of "1", and O 545 can store a logical value of "1". Thus, the RA can identify potential data conflicts based on the data 500 stored in the registers and can identify specific columns and / or rows to be repaired to avoid over-repair of any one column plane. The tester can be configured to determine that a conflict has occurred based on which CPn bits are set to logical "1" and which RDn bits are set to logical "1".

[0074] In some instances, multiple internal read operations of a column plane can cause two banks 575 to fail at the same bit index value. That is, an error associated with the same column plane bit index can be identified during a first internal read operation of a first bank or repair area, and the error can be identified during a second internal read operation of a second bank or repair area. For example, the error may be associated with a second column plane and can occur during a first internal read operation of a first bank and a second internal read operation of a second bank. Accordingly, CP1 510 may store a logical value of “1”, RD0 525 may store a logical value of “1”, RD1 530 may store a logical value of “1”, and E 540 may store a logical value of “1”. All other values stored in the registers may be logical “0”. These values can be read out as a single command sequence (e.g., read out to a test device). The tester can be configured to determine which column planes need to be repaired based on which CPn bits are set to a logical “1” and which RDn bits are set to a logical “1”. In some cases, the tester can use prior information about the mapping of internal read operations to determine which column planes have failed.

[0075] Figure 6 FIG. 600 is a block diagram showing a memory device 605 that supports data compression for global column repair in accordance with examples disclosed herein. The memory device 605 can be an example of aspects of a memory device as described with reference to Figures 3 to 5 The memory device 605 can include a generation component 610, a combination component 615, a communication component 620, an identification component 625, a setting component 630, a repair analyzer 635, a determination component 640, a storage component 645, a transfer component 650, and a receiving component 655. Each of these modules can communicate directly or indirectly with each other (e.g., via one or more buses).

[0076] The generation component 610 can generate first data using a first read operation to identify one or more errors associated with memory cells of a first set of column planes of the memory device, the first data including a first set of indicators regarding whether each column plane in the first set of column planes includes one or more errors. In some instances, the generation component 610 can generate second data using a second read operation to identify one or more errors associated with memory cells of a second set of column planes of the memory device, the second data including a second set of indicators regarding whether each column plane in the second set of column planes includes one or more errors.

[0077] In some instances, for each read operation performed, the generation component 610 may generate an indicator regarding whether one or more errors are identified during the corresponding read operation, where the message includes an indicator for each read operation. In some instances, the generation component 610 may generate the value of the first bit index of the third data based on the first bit of the first data being a first value or the second bit of the second data being a first value.

[0078] The combination component 615 may combine the first data and the second data into third data that includes a third set of indicators regarding whether the first set of column planes and the second set of column planes include one or more errors.

[0079] The communication component 620 may communicate a message that includes the third data formed by combining the first data and the second data through the memory device.

[0080] The identification component 625 may identify that the first column plane in the first set of column planes or the second set of column planes includes an error at least in part based on the third data formed by combining the first data and the second data and an indicator regarding whether one or more errors are associated with the corresponding read operation. In some instances, the identification component 625 may identify that the first bit of the first data at the first bit index is the first value. In some instances, the identification component 625 may identify that the second bit of the second data at the first bit index is the first value.

[0081] In some instances, the identification component 625 may identify a conflict associated with the first data and the second data based on the values of the first bit, the second bit, the third bit, and the fourth bit. In some instances, the identification component 625 may identify one or more banks for the first read operation and one or more banks for the second read operation according to a bank interleaving pattern that is operable to reduce the likelihood of errors occurring for similar bit index values for the first data and the second data, where the generation of the first data and the second data is based on the identification of one or more banks for the first read operation and the second read operation.

[0082] The setting component 630 may set the value of the third bit to indicate whether one or more errors are associated with the first read operation. In some instances, the setting component 630 may set the value of the fourth bit to indicate whether one or more errors are associated with the second read operation.

[0083] The repair analyzer 635 may perform a single repair operation on the first set of column planes, the second set of column planes, or both based on identifying a conflict associated with the first data and the second data. In some instances, the repair analyzer 635 may repair the column plane at the address based on a determined address. In some instances, the repair analyzer 635 may be located external to the memory device 605. For example, the repair analyzer 635 may be included in a tester (e.g., as referenced Figure 2on the described tester 210) and communicable with the memory device 605.

[0084] The determination component 640 can determine the addresses of the column planes associated with one or more errors based on the communicated message.

[0085] The storage component 645 can store the first data and the second data into the first register, where the combination of the first data and the second data occurs at the first register.

[0086] The transfer component 650 can transfer the third data to a second register different from the first register, where the third data is communicated from the second register.

[0087] The receiving component 655 can receive a read command, where the communicated message is based on the received read command.

[0088] Figure 7 A flowchart showing a method 700 that supports data compression for global column repair according to an example disclosed herein is presented. The operations of method 700 can be implemented by a memory device or its components as described herein. For example, the operations of method 700 can be performed by the memory device Figure 6 described. In some instances, the memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can use dedicated hardware (such as a tester coupled to the memory device) to perform aspects of the described functions.

[0089] At step 705, the memory device can generate first data using a first read operation to identify one or more errors associated with the memory cells of a first set of column planes of the memory device, the first data including a first set of indicators regarding whether each column plane in the first set of column planes contains one or more errors. The operation of 705 can be performed according to the method described herein. In some instances, aspects of the operation of 705 can be performed by a generation component Figure 6 described.

[0090] At step 710, the memory device can generate second data using a second read operation to identify one or more errors associated with the memory cells of a second set of column planes of the memory device, the second data including a second set of indicators regarding whether each column plane in the second set of column planes contains one or more errors. The operation of 710 can be performed according to the method described herein. In some instances, aspects of the operation of 710 can be performed by a generation component Figure 6 described.

[0091] At step 715, the memory device may combine the first data and the second data into third data that includes a third set of indicators regarding whether the first set of column planes and the second set of column planes include one or more errors. The operation of 715 may be performed according to the methods described herein. In some instances, aspects of the operation of 715 may be performed by a combining component as described with reference to Figure 6 described.

[0092] At step 720, the memory device may communicate a message that includes the third data formed by combining the first data and the second data through the memory device. The operation 720 may be performed according to the methods described herein. In some instances, aspects of the operation 720 may be performed by a communication component as described with reference to Figure 6 described.

[0093] In some instances, the devices described herein may perform a method such as method 700. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for generating first data using a first read operation to identify one or more errors associated with memory cells of a first set of column planes of a memory device, the first data including a first set of indicators regarding whether each column plane in the first set of column planes includes the one or more errors; generating second data using a second read operation to identify one or more errors associated with memory cells of a second set of column planes of the memory device, the second data including a second set of indicators regarding whether each column plane in the second set of column planes includes the one or more errors; combining the first data and the second data into third data that includes a third set of indicators regarding whether the first set of column planes and the second set of column planes include one or more errors; and communicating, through the memory device, a message that includes the third data formed by combining the first data and the second data.

[0094] Some instances of the method 700 and the device described herein may further include operations, features, components, or instructions for generating, for each read operation performed, an indicator regarding whether one or more errors are identified during the corresponding read operation, where the message includes the indicator for each read operation. Some instances of the method 700 and the device described herein may further include operations, features, components, or instructions for identifying that a first column plane in the first set of column planes or the second set of column planes includes an error based at least in part on the third data formed by combining the first data and the second data and the indicator regarding whether the one or more errors may be associated with the corresponding read operation.

[0095] In some examples of the method 700 and apparatus described herein, combining the first data and the second data may include operations, features, components, or instructions for identifying that a first bit of the first data at a first bit index may be a first value, identifying that a second bit of the second data at the first bit index may be the first value, and generating a value for the first bit index of the third data based at least in part on the first bit of the first data being the first value or the second bit of the second data being the first value. In some examples of the method 700 and apparatus described herein, generating the indicator may further include operations, features, components, or instructions for setting a value of a third bit to indicate whether the one or more errors may be associated with the first read operation, and setting a value of a fourth bit to indicate whether the one or more errors may be associated with the second read operation.

[0096] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for identifying a conflict associated with the first data and the second data based on the values of the first bit, the second bit, the third bit, and the fourth bit, and performing a single repair operation on the first set of column planes, the second set of column planes, or both based on identifying the conflict associated with the first data and the second data. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for determining an address of a column plane associated with the one or more errors based on communicating the message, and repairing the column plane at the address based on determining the address.

[0097] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for storing the first data and the second data in a first register, wherein combining the first data and the second data occurs at the first register, and transferring the third data to a second register different from the first register, wherein the third data is communicated from the second register. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for receiving a read command, wherein communicating the message may be based on receiving the read command.

[0098] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for identifying one or more memory banks for the first read operation and one or more memory banks for the second read operation according to a memory bank interleaving pattern, the memory bank interleaving pattern being operable to reduce the likelihood of errors occurring for similar bit index values for the first data and the second data, wherein generating the first data and the second data may be at least partially based on identifying the one or more memory banks for the first read operation and the second read operation. In some examples of the method 700 and apparatus described herein, the first data read from a first column of memory cells and the second data read from a second column of memory cells include compressed data.

[0099] Note that the method descriptions above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0100] An apparatus is described. The apparatus may include a memory array including a first set of column planes and a second set of column planes; and a tester coupled to the memory array, and the tester is configured to cause the apparatus to: generate second data to identify one or more errors associated with memory cells of the second set of column planes; combine the first data and the second data into third data including a set of indicators regarding whether the first set of column planes and the second set of column planes include one or more errors; and convey a message including the third data formed by combining the first data and the second data.

[0101] Some examples may further include, for each read operation performed, generating an indicator regarding whether one or more errors are identified during the corresponding read operation, and identifying a first column plane in the first set of column planes or the second set of column planes that includes an error based on the indicator. Some examples may further include generating a value for a first bit index of the third data based on whether a first bit of the first data is a first value or a second bit of the second data is the first value.

[0102] Some examples may further include identifying a conflict associated with the first data and the second data based on a value of a bit associated with the corresponding data, and performing a single repair operation on the first set of column planes, the second set of column planes, or both based on identifying the conflict associated with the first data and the second data. In some examples, the first data includes a first set of indicators regarding whether each column plane in the first set of column planes includes the one or more errors, and the second data includes a second set of indicators regarding whether each column plane in the second set of column planes includes the one or more errors.

[0103] A device is described. The device may include a memory array including a set of memory cells, the set of memory cells including a first set of column planes and a second set of column planes; a data generation component configured to generate first data to identify one or more errors associated with the first set of column planes and generate second data to identify one or more errors associated with the second set of column planes; a data combination component configured to combine the first data and the second data into third data including a set of indicators regarding whether the first set of column planes and the second set of column planes include one or more errors; and a transmission component configured to transmit a message including the third data formed by combining the first data and the second data.

[0104] Some examples of the device may include an error identification component configured to generate an indicator regarding whether one or more errors are identified during a corresponding read operation for a performed read operation. In some examples, the error identification component may be configured to identify that a first column plane in the first set of column planes or the second set of column planes includes an error based on the indicator. Some examples of the device may include a repair analyzer configured to perform a single repair operation on the first set of column planes, the second set of column planes, or both based at least in part on identifying a conflict associated with the first data and the second data.

[0105] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, those of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have various bit widths.

[0106] The terms "electronically communicate", "electrically contact", "connect", and "couple" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in electrical contact with each other, connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between components that are in electronic communication with each other (or in electrical contact with each other or connected to each other or coupled to each other) can be an open circuit or a closed circuit. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that can include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components can be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0107] The term "couple" refers to the condition of transitioning from an open-circuit relationship between components (where signals cannot currently be conveyed between the components through a conductive path) to a closed-circuit relationship between components (where signals can be conveyed between the components through a conductive path). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0108] The term "isolate" refers to a relationship between components where signals cannot currently flow between the components. If there is an open circuit between the components, the components are isolated from each other. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components through a conductive path that previously allowed signal flow.

[0109] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species (including but not limited to: phosphorus, boron, or arsenic). The doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0110] The switching components or transistors discussed in this document may represent field effect transistors (FETs) and include three-terminal devices that contain a source, a drain, and a gate. The terminals may be connected to other electronic components through a conductive material (e.g., metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated".

[0111] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples within the scope of what may be implemented or of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "advantageous over other examples". However, these techniques may be practiced without these specific details. However, these techniques may be practiced without having these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0112] In the figures, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that differentiates among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0113] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0114] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0115] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software, hardware, firmware, hardwiring, or any combination thereof executed by a processor. The features implementing the functions may also be physically located in various positions, including being distributed such that portions of the functions are implemented at different physical locations. Further, as used herein, including in the claims, the "or" as used in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of") indicates an inclusive list such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present invention. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0116] The description herein is provided to enable a person skilled in the art to make or use the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Thus, the invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, which includes: generating first data using a first read operation to identify one or more errors associated with memory cells in a first plurality of column planes of a memory device, the first data including a first plurality of indicators regarding whether each of the first plurality of column planes contains the one or more errors; generating second data using a second read operation to identify one or more errors associated with memory cells in a second plurality of column planes of the memory device, the second data including a second plurality of indicators regarding whether each of the second plurality of column planes contains the one or more errors; combining the first data and the second data by performing a bitwise OR operation on bits of the first data and bits of the second data to form third data including a third plurality of indicators regarding whether the first plurality of column planes and the second plurality of column planes contain one or more errors; and communicating, via the memory device, a message including the third data formed by combining the first data and the second data.

2. The method according to claim 1, which further includes: generating, for each read operation performed, an indicator regarding whether one or more errors are identified during the corresponding read operation, wherein the message includes the indicator for each read operation.

3. The method according to claim 2, which further includes: identifying that a first column plane in the first plurality of column planes or the second plurality of column planes contains an error, at least in part based on the third data formed by combining the first data and the second data and the indicator regarding whether the one or more errors are associated with the corresponding read operation.

4. The method according to claim 2, wherein combining the first data and the second data includes: identifying that a first bit of the first data at a first bit index is a first value; identifying that a second bit of the second data at the first bit index is the first value; and generating a value for the first bit index of the third data, at least in part based on the first bit of the first data being the first value or the second bit of the second data being the first value.

5. The method according to claim 4, wherein generating the indicator further includes: setting a value of a third bit to indicate whether the one or more errors are associated with the first read operation; and setting a value of a fourth bit to indicate whether the one or more errors are associated with the second read operation.

6. The method according to claim 5, which further includes: identifying a conflict associated with the first data and the second data, at least in part based on the values of the first bit, the second bit, the third bit, and the fourth bit; and performing a single repair operation on the first plurality of column planes, the second plurality of column planes, or both, at least in part based on identifying the conflict associated with the first data and the second data.

7. The method according to claim 1, which further includes: determining an address of a column plane associated with the one or more errors, at least in part based on communicating the message; and Fix the column plane at the address at least in part based on determining the address.

8. The method according to claim 1, further comprising: Storing the first data and the second data in a first register, wherein combining the first data and the second data occurs at the first register; and Transferring the third data to a second register different from the first register, wherein the third data is communicated from the second register.

9. The method according to claim 1, further comprising: Receiving a read command, wherein communicating the message is at least in part based on receiving the read command.

10. The method according to claim 1, further comprising: Identifying one or more memory banks for the first read operation and one or more memory banks for the second read operation according to a bank interleaving pattern, the bank interleaving pattern being operable to reduce the likelihood of errors occurring for similar bit index values for the first data and the second data, wherein generating the first data and the second data is at least in part based on identifying the one or more memory banks for the first read operation and the second read operation.

11. The method according to claim 1, wherein the first data read from a first column of memory cells and the second data read from a second column of memory cells comprise compressed data.

12. An apparatus, which comprises: A memory array, which includes a first plurality of column planes and a second plurality of column planes; and A tester, which is coupled to the memory array, and the tester is configured to cause the apparatus to: Generate first data to identify one or more errors associated with memory cells of the first plurality of column planes; Generate second data to identify one or more errors associated with memory cells of the second plurality of column planes; Combine the first data and the second data into third data including a third plurality of indicators regarding whether the first plurality of column planes and the second plurality of column planes contain one or more errors by performing a bitwise OR operation on the bits of the first data and the bits of the second data; and Communicate a message including the third data formed by combining the first data and the second data.

13. The apparatus according to claim 12, wherein the tester is operable to cause the apparatus to: For each read operation performed, generate an indicator regarding whether one or more errors are identified during the corresponding read operation; and Identify that a first column plane in the first plurality of column planes or the second plurality of column planes contains an error at least in part based on the indicator.

14. The apparatus according to claim 12, wherein the tester is operable to cause the apparatus to: Generate a value for a first bit index of the third data at least in part based on the first bit of the first data being a first value or the second bit of the second data being the first value.

15. The apparatus according to claim 12, wherein the tester is operable to cause the apparatus to: Identify a conflict associated with the first data and the second data at least in part based on the value of the bits associated with the corresponding data; Perform a single repair operation on the first plurality of column planes, the second plurality of column planes, or both, at least in part based on identifying the conflict associated with the first data and the second data.

16. The apparatus according to claim 12, wherein: the first data includes a first plurality of indicators regarding whether each column plane in the first plurality of column planes contains the one or more errors; and the second data includes a second plurality of indicators regarding whether each column plane in the second plurality of column planes contains the one or more errors.

17. An apparatus, comprising: a memory array including a plurality of memory cells, the plurality of memory cells including a first plurality of column planes and a second plurality of column planes; a data generation component configured to generate first data to identify one or more errors associated with the first plurality of column planes, and generate second data to identify one or more errors associated with the second plurality of column planes; a data combination component configured to combine the first data and the second data into third data including a plurality of indicators regarding whether the first plurality of column planes and the second plurality of column planes contain one or more errors by performing a bitwise OR operation on bits of the first data and bits of the second data; and a transmission component configured to transmit a message including the third data formed by combining the first data and the second data.

18. The apparatus according to claim 17, further comprising: an error identification component configured to generate an indicator regarding whether one or more errors are identified during a corresponding read operation for a performed read operation.

19. The apparatus according to claim 18, wherein the error identification component is configured to identify that a first column plane in the first plurality of column planes or the second plurality of column planes contains an error at least in part based on the indicator.

20. The apparatus according to claim 17, further comprising: a repair analyzer configured to perform a single repair operation on the first plurality of column planes, the second plurality of column planes, or both, at least in part based on identifying a conflict associated with the first data and the second data.

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