Method for patterning silicon oxide-silicon nitride-silicon oxide stack and structure thereof

Abstract

A layer stack is formed over a conductive material portion located on a substrate. The layer stack comprises a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A through-hole cavity extending through the layer stack and downwardly to the conductive material portion is formed by isotropically etching the portion of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etching process. A buffered oxide etch process may be used in which the etch rate of the silicon nitride layer is less than the etch rate of the first silicon oxide layer but is significant enough to provide a tapered straight sidewall on the silicon nitride layer. An optical device including the patterned layer stack may be provided.

Description

Technical Field

[0001] The present disclosure relates to microfabrication methods, and in particular to methods of patterning silicon oxide-silicon nitride-silicon oxide stacks and the resulting structures thereof. Background Art

[0002] Microdevices are used in a wide variety of applications such as personal computers, cell phones, digital cameras, and other electronic devices. In many cases, such microdevices may include optical devices. Such microdevices are typically fabricated by sequentially depositing various material layers on a substrate and then patterning the material layers using photolithography and etching processes. Microfabrication processes can be used to increase the integration density of various components by continually reducing the minimum feature size, which allows more components to be integrated into a given area.

[0003] Silicon oxide-silicon nitride-silicon oxide stacks can be used as optical filters that exploit the difference in refractive index of the layers. In addition, silicon oxide-silicon nitride-silicon oxide stacks can be used, for example, to provide passivation over conductive structures by blocking the diffusion of moisture, ionic impurities, and hydrogen atoms, and to enhance the reliability and lifetime of conductive structures. Summary of the invention

[0004] According to an embodiment of the present disclosure, a microfabrication method is provided, the microfabrication method comprising: providing a structure including a layer stack (30, 40, 50) and a conductive material portion 20 underlying the layer stack (30, 40, 50) and overlying a substrate 10, the layer stack including, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50; forming a patterned etch mask layer 50 including an opening passing therethrough on the layer stack (30, 40, 50); 7; and isotropically etching the second silicon oxide layer 50, the silicon nitride layer 40 and a portion of the first silicon oxide layer 30 by using an isotropic etching process to form a through hole cavity 59 extending through the layer stack (30, 40, 50) and extending downward to the top surface of the conductive material portion 20, wherein the etching rate of the silicon nitride layer 40 in the isotropic etching process is in the range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide layer 30.

[0005] According to an embodiment of the present disclosure, a method for patterning a structure is provided, the method comprising: forming a layer stack (30, 40, 50) including a first silicon oxide layer 30, a silicon nitride layer 40 and a second silicon oxide layer 50 on a conductive material portion 20 on a substrate 10; forming a patterned etching mask layer 57 including an opening passing therethrough on the layer stack (30, 40, 50); and forming a through-hole cavity 59 extending through the layer stack (30, 40, 50) and downward to the top surface of the conductive material portion 20 by isotropically etching the second silicon oxide layer 50, the silicon nitride layer 40 and a portion of the first silicon oxide layer 30 during a single wet etching process using a buffered oxide etching solution, the buffered oxide etching solution comprising an n:1 volume ratio mixture of 40% NH4F in water to 49% HF in water, where n is in the range of 3 to 12.

[0006] According to an embodiment of the present disclosure, a structure is provided, the structure comprising: a conductive material portion 20 formed on a substrate 10; a layer stack (30, 40, 50) comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50, located above the conductive material portion 20; and a via cavity 59 extending through the layer stack (30, 40, 50) and extending downward to a top surface of the conductive material portion 20, wherein a sidewall of the via cavity 59 comprises a first concave sidewall of the first silicon oxide layer 30 adjacent to the top surface of the conductive material portion 20, a straight tapered sidewall of the silicon nitride layer 40 adjacent to a corresponding top end of the first concave sidewall, and a second concave sidewall of the second silicon oxide layer 50 adjacent to a corresponding top end of the straight tapered sidewall, such that a width of the via cavity 59 strictly increases with a vertical distance from a horizontal top surface of the conductive material portion 20. The silicon nitride layer 40 may have a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a conductive material portion and a layer stack including, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer over a substrate according to an embodiment of the present disclosure.

[0009] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a patterned etch mask layer according to an embodiment of the present disclosure.

[0010] Figure 3is a vertical cross-sectional view of an exemplary structure after a first step of an isotropic etching process to etch through the second silicon oxide layer according to an embodiment of the present disclosure.

[0011] Figure 4A is a vertical cross-sectional view of an exemplary structure after a second step of an isotropic etching process for etching a silicon nitride layer according to an embodiment of the present disclosure.

[0012] Figure 4B Yes Figure 4A An enlarged view of region B is shown.

[0013] Figure 5 is a graph comparing the etch rates and refractive indices of chemical vapor deposition (CVD) tetraethylorthosilicate (TEOS) oxide, CVD silicon nitride, and physical vapor deposition (PVD) silicon nitride according to an embodiment of the present disclosure.

[0014] Figure 6 is a vertical cross-sectional view of an exemplary structure after a third step of an isotropic etching process to etch through the first silicon oxide layer according to an embodiment of the present disclosure.

[0015] Figure 7 is a vertical cross-sectional view of an exemplary structure after removal of a patterned etch mask layer according to an embodiment of the present disclosure.

[0016] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming a metal contact structure in a via cavity according to an embodiment of the present disclosure.

[0017] Fig. 9 is a vertical cross-sectional view of an exemplary structure after mounting a semiconductor die according to an embodiment of the present disclosure.

[0018] Fig.10 is a flow chart illustrating an exemplary microfabrication method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] refer to Figure 1 , an exemplary structure according to an embodiment of the present disclosure is shown, which may include a substrate 10, a conductive material portion 20 located on the front surface of the substrate 10, and a layer stack, the layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 from bottom to top. The substrate 10 may include a dielectric material, a conductive material, and / or a semiconductor material. In one embodiment, the substrate 10 may include and / or may be composed of a transparent dielectric material such as fused silica, quartz, and glass. In one embodiment, the substrate 10 may have a thermal conductivity of less than 10×W / (m+K). For example, fused silica, quartz, and glass have a thermal conductivity of 1.3×W / (m+K). The substrate 10 may include a material having a thermal conductivity of less than 0.1×W / (m+K). The substrate 10 may have sufficient thickness to provide mechanical support for the conductive material portion 20 and the layer stack (30, 40, 50). In one embodiment, substrate 10 may have a thickness ranging from 10 microns to 3 mm, although lesser thicknesses or greater thicknesses may also be used.

[0022] At least one conductive material portion 20 may be formed over the front surface of the substrate 10. Each conductive material portion 20 includes at least one conductive material, which may include at least one metallic material or at least one transparent conductive material (e.g., a conductive metal oxide material). In one embodiment, each conductive material portion 20 may include an elemental metal, such as copper, tungsten, tantalum, titanium, ruthenium, or cobalt; an intermetallic alloy of at least two elemental metals; and / or a conductive metal nitride material, such as tungsten nitride, tantalum nitride, or titanium nitride. Alternatively or in addition, each conductive material portion 20 may include and / or consist essentially of a conductive metal oxide material, such as doped zinc oxide, indium tin oxide, cadmium tin oxide (Cd2SnO4), zinc stannate (Zn2SnO4), and doped titanium dioxide (TiO2). Exemplary doped zinc oxide materials include boron doped zinc oxide, fluorine doped zinc oxide, gallium doped zinc oxide, and aluminum doped zinc oxide. Other suitable materials are within the contemplated scope of the present disclosure. The conductive material of the at least one conductive material portion 20 may be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, electroplating, electroless plating, or a combination thereof. Each conductive material portion 20 may be formed by patterning the conductive material, for example, by applying a photoresist layer on the conductive material and photolithographically patterning it, and transferring the pattern in the photoresist layer through the deposited conductive material portion by using an etching process, the etching process using the patterned photoresist layer as an etching mask. The etching process may include an anisotropic etching process (e.g., a reactive ion etching process) and / or an isotropic etching process (e.g., a wet etching process). The thickness of each conductive material portion 20 may be in the range of 50nm to 3,000nm, for example, 100nm to 1,000nm, but smaller thicknesses or larger thicknesses may also be used. The conductive material portion 20 may include transparent conductive films (TCFs), such as transparent conductive oxides (TCOs), transparent conductive polymers, ultra-thin metal films, etc. Other suitable materials for use as the conductive material portion are within the contemplated scope of the present disclosure.

[0023] Subsequently, a layer stack of a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 may be formed on the at least one conductive material portion 20. The first silicon oxide layer 30 may be formed by depositing a first silicon oxide material using a first chemical vapor deposition process. In a wet etching process using a buffered oxide etching solution, the first silicon oxide material may have an etching rate of the same order of magnitude as the etching rate of thermal silicon oxide, the buffered oxide etching solution comprising a 6:1 volume ratio mixture of 40% NH4F in water to 49% HF in water at room temperature (hereinafter, the mixture is referred to as "6:1 BOE solution"). In general, the etching rate of all deposited silicon oxide materials in a hydrofluoric acid-based etchant is not less than the etching rate of thermal silicon oxide in the same etchant. Thermal silicon oxide refers to silicon oxide formed by thermal oxidation of silicon. Unless otherwise specified, all etching rates used herein are measured at room temperature (20 degrees Celsius). In one embodiment, the etching rate provided by the first silicon oxide material in a 6:1 BOE solution may be less than 3.0 times the etching rate of the thermal silicon oxide in a 6:1 BOE solution. In one embodiment, the etching rate of the first silicon oxide material in a 6:1 BOE solution may be less than 2.0 times the etching rate of the thermal silicon oxide in a 6:1 BOE solution, and may be less than 1.25 times. All etching rates are measured at room temperature, i.e., at 20 degrees Celsius.

[0024] In one embodiment, the first chemical vapor deposition process decomposes a silicon oxide precursor gas to deposit a first silicon oxide material of the first silicon oxide layer 30. The first chemical vapor deposition process may be a thermal chemical vapor deposition process in which the silicon oxide precursor gas is thermally decomposed, or may be a plasma enhanced chemical vapor deposition process in which the silicon oxide precursor gas is decomposed in a plasma environment. In one embodiment, the first silicon oxide layer includes a first silicon oxide material formed by thermal decomposition or plasma decomposition of tetraethoxysilane (TEOS). In one embodiment, the first silicon oxide material may be an undoped silicate glass material, i.e., a silicate glass material that does not include a p-type dopant (e.g., boron) or an n-type dopant (e.g., phosphorus or arsenic). In one embodiment, the undoped silicate glass material of the first silicon oxide layer 30 may consist essentially of silicon atoms, oxygen atoms, carbon atoms having an atomic concentration ranging from 0.005% (i.e., 50 parts per million (ppm)) to 0.1% (i.e., 1,000 parts per million), and hydrogen atoms having an atomic concentration ranging from 0.01% (100 parts per million) to 1.0% (10,000 parts per million), such as 0.05% (500 parts per million) to 0.5% (5,000 parts per million). In one embodiment, the undoped silicate glass material of the first silicon oxide layer 30 may be annealed before or after the deposition of the second silicon oxide layer 30 to remove moisture and hydrogen, thereby reducing the etching rate in the 6:1 BOE solution.

[0025] As another option, the first silicon oxide material may be a doped silicate glass material, such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, arsenosilicate glass, or borophosphosilicate glass. The concentration of the dopant in the doped silicate glass material may be selected so that the etching rate of the first silicon oxide material in a 6:1 BOE solution is no greater than 3.0 times the etching rate of thermal silicon oxide in a 6:1 BOE solution. The thickness of the first silicon oxide layer 30 may be between 100 nm and 1,000 nm (e.g., in the range of 200 nm to 500 nm), but a smaller thickness or a larger thickness may also be used. Hereinafter, the thickness of the first silicon oxide layer 30 is referred to as the first thickness t1. In one embodiment, the doped silicate glass material of the first silicon oxide layer 30 may consist essentially of silicon atoms, oxygen atoms, dopant atoms (e.g., boron atoms, phosphorus atoms, arsenic atoms, and / or fluorine atoms), carbon atoms in an atomic concentration ranging from 0.005% (i.e., 50 parts per million (ppm)) to 0.1% (i.e., 1,000 parts per million), and hydrogen atoms in an atomic concentration ranging from 0.01% (100 parts per million) to 1.0% (10,000 parts per million), such as 0.05% (500 parts per million) to 0.5% (5,000 parts per million). If the first silicon oxide layer 30 includes undoped silicate glass or doped silicate glass formed by a plasma enhanced chemical vapor deposition process using TEOS as a precursor gas, the first silicon oxide layer 30 may have a refractive index ranging from 1.40 to 1.55 (e.g., in a range of 1.43 to 1.50).

[0026] The silicon nitride layer 40 may be formed by depositing a silicon nitride material directly on the top surface of the first silicon oxide layer 30 using a second chemical vapor deposition process. The silicon nitride material of the silicon nitride layer 40 may be a stoichiometric silicon nitride material in which the atomic ratio of silicon atoms to nitrogen atoms is 3:4 or close to 3:4, i.e., the silicon nitride material has a chemical composition of Si3N4. In other words, the silicon nitride material of the silicon nitride layer 40 is not silicon-rich, but a sufficient amount of nitrogen-containing gas (e.g., ammonia or nitrogen) is provided during the second chemical vapor deposition process to ensure the stoichiometric composition of the silicon nitride material of the silicon nitride layer 40.

[0027] In addition, the silicon nitride material of the silicon nitride layer 40 can be formed at a relatively low temperature (e.g., less than 300 degrees Celsius) by a plasma enhanced chemical vapor deposition process. Compared with silicon nitride materials formed by thermal chemical vapor deposition at a temperature greater than 700 degrees Celsius or used as sputtering targets, silicon nitride materials deposited in a plasma enhanced chemical vapor deposition process can have a lower refractive index. For example, thermal silicon nitride materials or silicon nitride materials used as sputtering targets (physical vapor deposition targets) can have a refractive index in the range of 1.99 to 2.22 at a wavelength of 632.8 nm, which is the laser wavelength of a typical thickness measurement tool. In contrast, silicon nitride materials deposited in a plasma enhanced chemical vapor deposition process can have a refractive index in the range of 1.88 to 1.95 at a wavelength of 632.8 nm. The reduction in the refractive index of the silicon nitride material deposited in the plasma enhanced chemical vapor deposition process may be due to the lower density of the silicon nitride material, which may be caused by the presence of a higher volume fraction occupied by voids within the silicon nitride material deposited in the plasma enhanced chemical vapor deposition process and / or the inclusion of process gases (e.g., nitrogen or argon).

[0028] In one embodiment, the etching rate of the silicon nitride material of the silicon nitride layer 40 in an n:1 BOE solution (n is in the range of 3 to 12) may be in the range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide material of the first silicon oxide layer 30 in the n:1 BOE solution. In one embodiment, the etching rate of the silicon nitride material of the silicon nitride layer 40 in a 6:1 BOE solution may be in the range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide material of the first silicon oxide layer 30 in a 6:1 BOE solution.

[0029] In general, the silicon to nitrogen ratio in the silicon nitride material can have a significant effect on the etching rate of the silicon nitride material in dilute or buffered hydrofluoric acid. The etching rate of the silicon nitride material in dilute or buffered hydrofluoric acid increases as the silicon to nitrogen ratio decreases. Therefore, the etching rate of the stoichiometric silicon nitride material with a silicon to nitrogen ratio of 3:4, i.e., 0.75, has a greater etching rate than the silicon-rich silicon nitride material. The etching rate of the silicon nitride material in the silicon nitride layer 40 in the 6:1 BOE solution can be increased by adjusting the process parameters. For example, an increase in the deposition rate of the silicon nitride material can increase the etching rate of the silicon nitride material in the hydrofluoric acid solution.

[0030] In the second chemical vapor deposition process, the silicon precursor gas and the nitrogen precursor gas are combined to form a stoichiometric silicon nitride material. In one embodiment, the second chemical vapor deposition process may use silane or dichlorosilane as the silicon-containing precursor gas, and use ammonia or nitrogen as the nitrogen-containing precursor gas. In one embodiment, the second chemical vapor deposition process may include a plasma enhanced chemical vapor deposition process using a silicon-containing precursor gas (e.g., silane or dichlorosilane) and a nitrogen-containing precursor gas (e.g., ammonia or nitrogen). In one embodiment, the second chemical vapor deposition process may include a thermal chemical vapor deposition process using a silicon-containing precursor gas (e.g., silane or dichlorosilane) and a nitrogen-containing precursor gas (e.g., ammonia). The thickness of the silicon nitride layer 40 may be between 50nm and 500nm, for example, in the range of 100nm to 250nm, but a smaller thickness or a larger thickness may also be used. Hereinafter, the thickness of the silicon nitride layer 40 is referred to as the second thickness t2.

[0031] The second silicon oxide layer 50 may be formed by depositing a second silicon oxide material using a third chemical vapor deposition process. In a wet etching process using 100:1 diluted hydrofluoric acid at room temperature, the second silicon oxide material may have an etching rate comparable to that of thermal silicon oxide. In one embodiment, the etching rate provided by the second silicon oxide material in a 6:1 BOE solution may be less than 3.0 times the etching rate of thermal silicon oxide in a 6:1 BOE solution.

[0032] In one embodiment, the second chemical vapor deposition process decomposes the silicon oxide precursor gas to deposit the second silicon oxide material of the second silicon oxide layer 50. The second chemical vapor deposition process may be a thermal chemical vapor deposition process in which the silicon oxide precursor gas is thermally decomposed, or may be a plasma enhanced chemical vapor deposition process in which the silicon oxide precursor gas is decomposed in a plasma environment. In one embodiment, the second silicon oxide layer includes a second silicon oxide material formed by thermal decomposition or plasma decomposition of tetraethoxysilane. In one embodiment, the second silicon oxide material may be an undoped silicate glass material. In one embodiment, the undoped silicate glass material of the second silicon oxide layer 50 may consist essentially of silicon atoms, oxygen atoms, carbon atoms in an atomic concentration ranging from 0.005% (i.e., 50 parts per million (ppm)) to 0.1% (i.e., 1,000 parts per million), and hydrogen atoms in an atomic concentration ranging from 0.01% (100 parts per million) to 1.0% (10,000 parts per million), such as 0.05% (500 parts per million) to 0.5% (5,000 parts per million). In one embodiment, the undoped silicate glass material of the second silicon oxide layer 50 may be subsequently annealed to remove moisture and hydrogen, thereby reducing the etching rate in a 6:1 BOE solution. Alternatively, the second silicon oxide material may be a doped silicate glass material, such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, arsenosilicate glass, or borophosphosilicate glass. The concentration of the dopant in the doped silicate glass material can be selected so that the etching rate of the second silicon oxide material in the 6:1 BOE solution is no greater than 3.0 times the etching rate of the thermal silicon oxide in the 6:1 BOE solution. The thickness of the second silicon oxide layer 50 can be in the range of 50nm to 500nm, for example, 100nm to 250nm, but a smaller thickness or a larger thickness can also be used. Hereinafter, the thickness of the second silicon oxide layer 50 is referred to as the third thickness t3. In one embodiment, the doped silicate glass material of the second silicon oxide layer 50 may consist essentially of silicon atoms, oxygen atoms, dopant atoms (e.g., boron atoms, phosphorus atoms, arsenic atoms, and / or fluorine atoms), carbon atoms in an atomic concentration ranging from 0.005% (i.e., 50 parts per million (ppm)) to 0.1% (i.e., 1,000 parts per million), and hydrogen atoms in an atomic concentration ranging from 0.01% (100 parts per million) to 1.0% (10,000 parts per million), such as 0.05% (500 parts per million) to 0.5% (5,000 parts per million). If the second silicon oxide layer 50 includes undoped silicate glass or doped silicate glass formed by a plasma enhanced chemical vapor deposition process using TEOS as a precursor gas, the second silicon oxide layer 50 may have a refractive index ranging from 1.40 to 1.55, such as 1.43 to 1.50.

[0033] In one embodiment, the first silicon oxide material and the second silicon oxide material may be undoped silicate glass materials. In one embodiment, the etching rate of the second silicon oxide material is in the range of 0.80 times the etching rate of the first silicon oxide layer in a 6:1 BOE solution to 1.25 times the etching rate of the first silicon oxide layer in a 6:1 BOE solution. In one embodiment, the etching rate of the second silicon oxide material in a 6:1 BOE solution may be the same as that of the first silicon oxide material. In one embodiment, the second silicon oxide material may be the same as the first silicon oxide material.

[0034] refer to Figure 2 , a patterned etch mask layer 57 may be formed on the top surface of the second silicon oxide layer 50. In one embodiment, the patterned etch mask layer 57 may include a patterned photoresist material layer. In one embodiment, the patterned photoresist material layer may include a mid-ultraviolet (MUV) photoresist material or a deep ultraviolet (DUV) photoresist material, and may include a positive photoresist material or a negative photoresist material. A positive photoresist material is a photoresist material in which crosslinks within polymer molecules are removed by exposure, and thus can be patterned by removing the photolithographically exposed portion while retaining the unexposed portion. A negative photoresist material is a photoresist material in which crosslinks between monomer molecules are induced by exposure, and thus can be patterned by removing the unlithographically exposed portion.

[0035] In an embodiment in which the patterned etch mask layer 57 includes a patterned photoresist material layer, the patterned etch mask layer 57 can be formed by applying a photoresist material, photolithographically exposing the photoresist material, and developing the photoresist material. The photoresist material can be developed by removing the photolithographically exposed portion (in the case of a positive photoresist material) or the unphotolithographically exposed portion (in the case of a negative photoresist material). At least one opening can be formed in the photoresist material to provide the patterned etch mask layer 57. The opening through the patterned etch mask layer 57 can have a horizontal cross-sectional shape of a rectangle, a circle, an ellipse or an oval, a rounded rectangle or another polygon or another polygon with rounded corners. In one embodiment, the opening through the patterned etch mask layer 57 can have a pair of parallel straight sidewalls extending laterally in the horizontal direction (see, for example, Figure 2 ). In another embodiment, the openings through the patterned etch mask layer 57 may have a circular or elliptical horizontal cross-sectional shape. Each opening through the patterned etch mask layer 57 may extend vertically to the top surface of the underlying conductive material portion 20. The top surface of the conductive material portion 20 may be physically exposed below the opening in the patterned etch mask layer 57.

[0036] refer to Figure 3, an isotropic etching process may be performed to etch the portion of the layer stack (30, 40, 50) below each opening through the patterned etch mask layer 57. In an embodiment, a single isotropic etching process may be used to etch the entire thickness (i.e., t1+t2+t3) of the through layer stack (30, 40, 50) and physically expose the corresponding underlying portion of the conductive material portion 20. In one embodiment, the chemical mechanism of the single isotropic etching process may be selected to etch each material of the through layer stack (30, 40, 50) at a comparable etching rate that differs from each other by no more than a factor of 6.0. In one embodiment, the isotropic etching process may include a wet etching process that sequentially etches the second silicon oxide layer 50, the silicon nitride layer 40, and a portion of the first silicon oxide layer 30.

[0037] In one embodiment, the isotropic etching process may include a single wet etching process using a buffered oxide etching solution including a n:1 volume ratio mixture of 40% NH4F in water to 49% HF in water. The number n may range from 3 to 12, such as 4 to 10 and / or 5 to 7.5. In an illustrative example, the number n may be 6. The wet etching process may be performed at room temperature, i.e., at 20 degrees Celsius. Reference Figures 3 to 6 , a single wet etching process may sequentially etch through a portion of the second silicon oxide layer 50 underlying the opening through the patterned etching mask layer 57, a portion of the silicon nitride layer 40 underlying the opening through the patterned etching mask layer 57, and a portion of the first silicon oxide layer 30 underlying the opening through the patterned etching mask layer 57 to form a via cavity 59. Different time periods of the single isotropic etching process may be labeled as different steps of the single isotropic etching process, which are sequential sections of continuous duration during the single isotropic etching process. For example, the duration during which the bottommost surface of the via cavity 59 is the surface of the second silicon oxide layer 50 is referred to herein as the first step of the isotropic etching process, the duration during which the bottommost surface of the via cavity 59 is the surface of the silicon nitride layer 40 is referred to herein as the second step of the isotropic etching process, and the duration during which the bottommost surface of the via cavity 59 is the surface of the first silicon oxide layer 30 is referred to herein as the third step of the isotropic etching process.

[0038] Figure 3The time of the vertical cross-sectional profile of the exemplary structure shown corresponds to the time point at which the first step of a single isotropic etching process (e.g., a wet etching process using an n:1 BOE solution) is terminated and the second step of the single isotropic etching process is started. During the first step of the isotropic etching process, the material of the second silicon oxide layer 50 (i.e., the second silicon oxide material) is isotropically etched through the bottom cut below the patterned etching mask layer 57, while the remaining portion of the second silicon oxide layer 50 covers the silicon nitride layer 40 below the patterned etching mask layer 57. Due to the isotropic nature of the etching process, such as a wet etching process using an n:1 BOE solution, i.e., a buffered oxide etching solution including an n:1 volume ratio mixture of 40% NH4F in water and 49% HF in water, the sidewalls of the second silicon oxide layer 50 can be concave surfaces. At the end of the first step of the isotropic etching process, the radius of curvature Rc_O of the concave sidewall of the second silicon oxide layer 50 may be the same as the third thickness t3 , which is the thickness of the second silicon oxide layer 50 .

[0039] refer to Figure 4A and Figure 4B , the single isotropic etching process can continue to a second step, in which the portion of the silicon nitride layer 40 underlying the opening in the patterned etch mask layer 57 can be isotropically etched by an isotropic etchant, and the portion of the second silicon oxide layer 50 located below the proximal portion around each opening passing through the patterned etch mask layer 57 can be etched in parallel.

[0040] In one embodiment, the etching rate of the silicon nitride material of the silicon nitride layer 40 in an n:1 BOE solution (n is in the range of 3 to 12) may be in the range of 1 / 10 times to 1 / 2 times the etching rate of the second silicon oxide material of the second silicon oxide layer 50 in the n:1 BOE solution. In one embodiment, the etching rate of the silicon nitride material of the silicon nitride layer 40 in a 6:1 BOE solution may be in the range of 1 / 10 times to 1 / 2 times the etching rate of the second silicon oxide material of the second silicon oxide layer 50 in the 6:1 BOE solution.

[0041] Generally speaking, the silicon nitride material of the silicon nitride layer 40 can be etched at a lower etch rate than the etch rate of the second silicon oxide layer 50. The ratio of the etch rate of the silicon nitride material of the silicon nitride layer 40 to the etch rate of the second silicon oxide material of the second silicon oxide layer 50 can be kept as high as possible by using stoichiometric silicon nitride formed by chemical vapor deposition of the silicon nitride layer 40.

[0042] refer to Figure 5, providing a graph showing a comparison of the etching rates and refractive indices of CVD TEOS oxide, CVD silicon nitride, and PVD silicon nitride observed under laboratory conditions. CVD TEOS oxide is formed by a plasma enhanced chemical vapor deposition process at 280 degrees Celsius using tetraethoxysilane (TEOS) as a silicon oxide precursor gas. CVD silicon nitride is formed by a plasma enhanced chemical vapor deposition process at 275 degrees Celsius using silane as a silicon-containing precursor gas and nitrogen as a nitrogen-containing precursor gas. PVD silicon nitride is deposited by sputtering a silicon nitrogen material from a sputtering target at 25 degrees Celsius. The ratio of the etching rate of CVD silicon nitride in a 6:1 BOE solution to the etching rate of CVD silicon oxide in a 6:1 BOE solution is about 0.28, while the ratio of the etching rate of PVD silicon nitride in a 6:1 BOE solution to the etching rate of CVD silicon oxide in a 6:1 BOE solution is about 0.03. Therefore, the etch rate difference between CVD silicon nitride and CVD silicon oxide is smaller than the etch rate difference between PVD silicon nitride and CVD silicon oxide.

[0043] In one embodiment, during a single wet etching process, the etching rate of the silicon nitride layer 40 in an n:1 BOE solution (n is in a range of 3 to 12) may be in a range of 1 / 10 times to 1 / 2 times the etching rate of the second silicon oxide layer 50 in an n:1 BOE solution. Similarly, during a single wet etching process, the etching rate of the silicon nitride layer 40 in an n:1 BOE solution may be in a range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide layer 30 in an n:1 BOE solution.

[0044] In one embodiment, the silicon nitride material of the silicon nitride layer 40 may be formed by a plasma enhanced chemical vapor deposition process and may have a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm. In contrast, a thermal silicon nitride material deposited in a thermal chemical vapor deposition process at a temperature above 700 degrees Celsius or a sputtered silicon nitride material deposited from a sputtering target in a physical vapor deposition (PVD) process has a refractive index ranging from 1.99 to 2.02. The microstructure of the silicon nitride material deposited in the plasma enhanced chemical vapor deposition process results in a reduced refractive index relative to the refractive index of the thermal silicon nitride material or the sputtered silicon nitride material. In one embodiment, the silicon nitride material of the silicon nitride layer 40 has a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm.

[0045] Return to reference Figure 4A and Figure 4BDuring the isotropic etching process, the etching rate of the first silicon oxide layer 30 in the n:1 BOE solution may be at least three times (3x) the etching rate of the silicon nitride layer 40. Since all physically exposed surfaces of the silicon nitride layer 40 are physically exposed to the isotropic etchant (e.g., the n:1 BOE solution), the vertical etching distance of the silicon nitride layer 40 at the sidewalls of the silicon nitride layer 40 is determined by the lateral offset distance of each point on the sidewalls of the silicon nitride layer 40 from the vertical plane including the sidewalls of the patterned etching mask layer 57. Therefore, at the end of the second step of the single isotropic etching process, the sidewalls of the silicon nitride layer 40 may be straight tapered sidewalls extending from the bottom periphery of the corresponding concave sidewalls of the second silicon oxide layer 50 to the top surface of the first silicon oxide layer 30.

[0046] The second silicon oxide material of the second silicon oxide layer 50 may be laterally recessed to have a concave etched surface having a continuously increasing radius of curvature throughout the etching step of etching the silicon nitride layer 40. An isotropic etchant may be continuously supplied to the bottom edge of the concave sidewall of the silicon nitride layer 40 to provide a new concentric etching front for etching the material of the silicon nitride layer 40. The lower etching rate of the silicon nitride material of the silicon nitride layer 40 relative to the etching rate of the second silicon oxide material of the second silicon oxide layer 50 may result in the formation of a series of spherical etching fronts (ef_0, ef_1, ef_2) whose radii grow over time and provide overlapping surfaces in the form of conical two-dimensional planes having a cone angle α relative to the vertical direction. It is understood that the etching surface in the isotropic etching process recedes along a surface formed by the overlap of an infinite number of etching fronts. Furthermore, it is understood that the etching process is performed only at the sections of the surface that overlap with the etched material formed by the overlap of the etching fronts.

[0047] Each spherical etching front (ef_0, ef_1, ef_2) has a respective geometric center in a horizontal plane including the interface between the silicon nitride layer 40 and the second silicon oxide layer 50. Points (P_0, P_1, P_2) correspond to the geometric centers of the spherical etching fronts (ef_0, ef_1, ef_2). When the silicon nitride layer 40 is etched through and the top surface of the first silicon oxide layer 30 is physically exposed, the frontmost etching front ef_0 centered at the etching starting point P_0 at the bottom edge of the concave surface of the second silicon oxide layer 50 becomes the origin of the frontmost etching front ef_0. When the frontmost etching front ef_0 grows from a point into a sphere with a finite radius, the isotropic etchant begins to etch the silicon nitride material of the silicon nitride layer 40. The etching distance d_0 of the frontmost etching front ef_0 increases as the isotropic etching step proceeds, and reaches the value of the second thickness t2 when the silicon nitride layer 40 is etched through. As the bottom edge of the concave surface of the second silicon oxide layer 50 recedes laterally, other etching fronts are generated, and the newly exposed top surface segment of the silicon nitride layer 40 begins to be etched by the isotropic etchant. Although an infinite number of etching fronts can be generated during the isotropic etching step, only two other etching fronts (ef_1, ef_2) are shown. Once the first etching front center point P_1 becomes physically exposed to the isotropic etchant, the first etching front ef_1 can grow isotropically as the bottom edge of the concave etched surface of the second silicon oxide layer 50 passes through the first etching front center point P_1. As the first etching distance d_1 between the first etching front ef_1 and the first etching front center point P_1 increases over time, the first etching front ef_1 can grow isotropically in a spherical form. Likewise, once the second etch front center point P_2 is physically exposed to the isotropic etchant, the second etch front ef_2 may grow isotropically when the bottom edge of the concave etched surface of the second silicon oxide layer 50 passes through the second etch front center point P_2. As the second etch distance d_2 between the second etch front ef_2 and the second etch front center point P_2 increases over time, the second etch front ef_2 grows isotropically in a spherical form.

[0048] The taper angle α of the straight tapered sidewall of the silicon nitride layer 40 measured from the vertical direction perpendicular to the top surface of the conductive material portion 20 may be the arctangent of the ratio of the etching rate of the second silicon oxide layer 50 in the isotropic etchant to the etching rate of the silicon nitride layer 40 in the isotropic etchant. The straight tapered sidewall of the silicon nitride layer 40 may be in a corresponding two-dimensional (Euclidean) plane. In addition, even after the over-etching process, the straight tapered sidewall of the silicon nitride layer 40 may remain in the corresponding two-dimensional (Euclidean) plane because the etching rate of the silicon nitride material during the over-etching step is isotropic. In an illustrative example, if the isotropic etchant is a 6:1 BOE solution, if the second silicon oxide layer 50 has an etch rate of 8.2 nm / sec in the 6:1 BOE solution, and if the silicon nitride layer 40 has an etch rate of 2.3 nm / sec in the 6:1 BOE solution, the taper angle α of the straight tapered sidewall of the silicon nitride layer 40 may be approximately inverse tangent {(8.2 nm / sec) / (2.3 nm / sec)}≈1.30 radians≈74.3 degrees. The top surface of the first silicon oxide layer 30 is physically exposed at the end of the second step of the single isotropic etching process, which coincides with the start of the third step of the single isotropic etching process. The remaining portion of the silicon nitride layer 40 at this time covers the first silicon oxide layer 30 below the patterned etching mask layer 57.

[0049] refer to Figure 6 , when the second step of the isotropic etching is terminated, the third step of the isotropic etching process begins. The material of the first silicon oxide layer 30 and the second silicon oxide layer 50 can be etched while forming a concave surface, and the material of the silicon nitride layer 40 can be etched while the straight tapered sidewalls of the silicon nitride layer 40 move laterally outward without forming a concave surface. As described above, during the isotropic etching process, the etching rate of the first silicon oxide layer 30 and the second silicon oxide layer 50 is at least three times the etching rate of the silicon nitride layer 40. Therefore, the straight tapered sidewalls of the silicon nitride layer 40 move laterally outward during the third step of the isotropic etching process. Figure 6 As shown, at the time point when the top surface of the conductive material portion 20 becomes physically exposed, the radius of curvature Rc_f of the concave surface of the first silicon oxide layer 30 may be the same as the first thickness t1, that is, the thickness of the first silicon oxide layer 30. The third step of the isotropic etching process may include an extension portion after the top surface of the conductive material portion 20 is physically exposed, and the extension portion is an over-etched section of the third step of the isotropic etching process. Figure 6 During the over-etching process at the time point captured in FIG. 1 , the radius of curvature of the concave surface of the first silicon oxide layer 30 may increase to exceed the thickness of the first silicon oxide layer 30 .

[0050] A via cavity 59 is formed below each opening in the patterned etch mask layer 57, extending through the layer stack (30, 40, 50) and extending downward to the top surface of the conductive material portion 20. The via cavity 59 may include an undercut region UC at each layer of the layer stack (30, 40, 50). The undercut region UC corresponds to a volume underlying the patterned etch mask layer 57, i.e., a volume having an area overlap with the patterned etch mask layer 57 in a top-down view along a downward vertical direction. Each sidewall of the layer stack (30, 40, 50) may be located outside a vertical plane including a sidewall of the patterned etch mask layer 57 that defines a corresponding opening through the patterned etch mask layer 57. The width w of the via cavity 59 strictly increases with a vertical distance vd from the horizontal top surface of the conductive material portion 20.

[0051] refer to Figure 7 , the patterned etch mask layer 57 can be selectively removed to reach the conductive material portion 20 and the material of the layer stack (30, 40, 50). For example, if the patterned etch mask layer 57 includes a photoresist material, the patterned etch mask layer 57 can be removed by ashing or by dissolving in an organic solvent.

[0052] The sidewalls of the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50 may extend laterally (eg, along a plane parallel to the plane of the silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50) with a uniform vertical profile. Figure 7 ). Alternatively, the sidewalls of the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50 may be located around a substantially circular opening having a circular horizontal cross-sectional shape. In general, an exemplary structure of an embodiment of the present disclosure may have a first concave sidewall of the first silicon oxide layer 30, the first concave sidewall having a first radius of curvature Rc_1 of at least the first thickness t1. In addition, an exemplary structure of an embodiment of the present disclosure may have a second concave sidewall of the second silicon oxide layer 50, the second concave sidewall having a second radius of curvature Rc_2, the second radius of curvature Rc_2 being at least the sum of the product of the third thickness t3, the first thickness t1, and the second thickness t2 and the ratio of the etching rate of the material of the second silicon oxide layer 50 during the isotropic etching process to the etching rate of the material of the silicon nitride layer 40 during the isotropic etching process. Furthermore, the exemplary structure of the disclosed embodiment may include a straight tapered sidewall having a tapered angle α extending from a bottom edge of the second concave sidewall of the second silicon oxide layer 50 to a top edge of the first silicon oxide layer 30 , and the tapered angle α may be in a range of 62 to 84 degrees.

[0053] refer to Figure 8, a metal contact structure (60, 80) may be formed directly in the via cavity 59 on the top surface of the conductive material portion 20. The metal contact structure (60, 80) may include a combination of a bonding pad 60 and a solder material portion 80. In one embodiment, a plurality of via cavities 59 may be formed through the layer stack (30, 40, 50), and a plurality of metal contact structures (60, 80) may be formed. In an illustrative example, the bonding pad 60 may be formed by depositing and patterning a metal layer, such as an Al / Ni / Au stack, an Al / Ni / Cu stack, a Cu / Ni / Au stack, a Cu / Ni / Pd stack, a Ti / Ni / Au stack, a Ti / Cu / Ni / Au stack, a Ti-W / Cu stack, a Cr / Cu stack, a Cr / Cu / Ni stack, or another underbump metallurgy (UBM) stack known in the art. The solder material portion 80 includes a solder material, such as a Sn-Ag alloy or another tin-based alloy. The solder material portion 80 may have a lateral dimension (e.g., diameter) ranging from 5 microns to 100 microns, although smaller lateral dimensions or larger lateral dimensions may also be employed. One of ordinary skill in the art will appreciate that additional and / or alternative metal contact structures (60, 80) may be formed in conjunction with a silicon oxide-silicon nitride-silicon oxide stack that may be formed using the novel methods disclosed herein.

[0054] refer to Fig. 9 , an exemplary structure is shown after an optical structure 800 including a substrate 10, a conductive material portion 20, and a layer stack (30, 40, 50) is bonded to a semiconductor chip 900 including an optical semiconductor device 920. The optical semiconductor device 920 may include any semiconductor device that can capture or process an impinging optical signal or optical image transmitted through the optical structure 800. The semiconductor chip 900 may be provided with a front bonding pad 890 to which the solder material portion 80 is bonded. Optionally, an optically transparent filling material portion 880 may be provided between the optical structure 800 and the semiconductor chip 900 to prevent condensation and / or contamination.

[0055] In an illustrative example, optical semiconductor device 920 may include a complementary metal-oxide-semiconductor (CMOS) image sensor, a charge-coupled device (CCD), an optical sensor array for light detection and ranging (LIDAR) applications, or any suitable semiconductor-based optical signal detection device. In one embodiment, optical structure 800 may include an optical filter that allows or prohibits transmission of light within a specific wavelength range. The thickness of each layer in the layer stack (30, 40, 50) may be selected to provide a suitable transmission wavelength range for light to pass through while suppressing the transmission of light outside the transmission wavelength range.

[0056] In another example, the optical structure 800 may include a beam splitter that partially reflects and partially transmits an incident light beam. In yet another example, the optical structure 800 may include an optical mirror for a wide wavelength range or a specific wavelength range. Optionally, the semiconductor chip 900 may be connected to a printed circuit board 999 via a bonding structure (970, 980, 990), which may include, for example, a chip side bonding pad 970, a solder ball 980, and a board side bonding pad 990.

[0057] In general, the optical structure 800 of the present disclosure may be attached to a semiconductor chip 900 or any other optical device (e.g., a camera, an optical signal transmission device, or an optical sensor) using solder material portions, conductive pastes, and / or adhesive materials (e.g., epoxy resins). Fig. 9 The semiconductor chip 900 in FIG. 8 is replaced with an embodiment of another optical component that forms an optical module when integrated with the optical structure 800 .

[0058] refer to Fig.10 , a microfabrication method according to an embodiment of the present disclosure is shown in flowchart 1000. In step 1010, a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 may be formed on a conductive material portion 20 on a substrate 10 using the above method. A structure may be provided, the structure including a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 from bottom to top, and a conductive material portion underlying the layer stack (30, 40, 50) and overlying the substrate 10. In step 1020, a patterned etch mask layer 57 (e.g., a patterned photoresist layer) including an opening therethrough may be formed on the layer stack (30, 40, 50).

[0059] In step 1030, a via cavity 59 extending through the layer stack (30, 40, 50) and extending down to the top surface of the conductive material portion 20 may be formed by isotropically etching the second silicon oxide layer 50, the silicon nitride layer 40, and a portion of the first silicon oxide layer 30 during a single wet etching process. In one embodiment, a single wet etching process using a buffered oxide etching solution may be employed, the buffered oxide etching solution comprising an n:1 volume ratio mixture of NH4F in water to 49% HF in water, with n ranging from 3 to 12. The etching rate of the silicon nitride layer 40 may range from 1 / 10 times the etching rate of the first silicon oxide layer 30 to 1 / 2 times the etching rate of the first silicon oxide layer 30.

[0060] The microfabrication method disclosed herein (i.e., a method for forming a structure having at least one dimension less than 1 micron) enables the use of a single etching process to pattern a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a silicon oxide layer 50 to form a through-hole cavity 59, and the single etching process may be an isotropic etching process, such as a wet etching process. For example, the wet etching process may use an n:1 BOE solution. This wet etching process is a low-cost process using inexpensive wet etchant chemicals. In addition, this wet etching process utilizes common wet etching tools commonly used in other microfabrication processes, and therefore does not require the purchase of new process equipment. In addition, only a single patterned etching mask layer 57 (e.g., a patterned photoresist layer) is used for the microfabrication process disclosed herein. Therefore, a combination of a single photolithography patterning step and a single isotropic etching process can be used to pattern a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a silicon oxide layer 50 to form a through-hole cavity 59. Additionally, eliminating the dry etch process in favor of a wet etch process removes the possibility of photoresist mask burn concerns. Various advantages of the disclosed embodiments provide significant cost savings and increased yields during microfabrication processes.

[0061] In order to achieve a single isotropic etching process for etching a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a silicon oxide layer 50, the etching rates of the first silicon oxide layer 30 and the second silicon oxide layer 50 in an isotropic etchant (e.g., an n:1 BOE solution) can be suppressed to be as low as possible, and the etching rate of the silicon nitride layer 40 can be increased as high as possible. For example, the deposition method and material composition of the first silicon oxide material and the second silicon oxide material can be selected so that the etching rate of the first silicon oxide layer 30 and the second silicon oxide layer 50 is between 1.0 times the etching rate of thermal silicon oxide and 1.25 times the etching rate of thermal silicon oxide. The etching rate of the silicon nitride material in the silicon nitride layer 40 can be increased by forming a stoichiometric silicon nitride material using a plasma enhanced silicon nitride deposition process. A via cavity 59 can be formed through the layer stack (30, 40, 50) having the sidewall profile by maintaining a ratio of the etching rate of the silicon oxide material of the first silicon oxide layer and the second silicon oxide layer (30, 50) in an isotropic etchant to the etching rate of the silicon nitride material of the silicon nitride layer 40 in a range of 2 to 10. A metal contact structure 60 can be formed in the via cavity 59 on the conductive material portion 20.

[0062] Embodiments of the present disclosure provide a low-cost method for patterning a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 to form a through-hole cavity 59. In addition, embodiments of the present disclosure provide a patterned structure in which a high taper angle α at the straight tapered sidewall of the silicon nitride layer 40 limits the contact area between the metal contact structure 60 and the conductive material portion 20. The conductive material portion 20 may include a metal material (e.g., a metal pad or a metal wire), or may include a transparent conductive oxide material. The method of the present disclosure can be used for a substrate 10 having low thermal conductivity and high optical transparency, such as fused silica, quartz, or glass. Therefore, the various embodiment methods can be used for various optical components using a substrate 10 having low thermal conductivity.

[0063] The patterning methods of various embodiments use a single patterned etch mask layer 57 and a single isotropic etching process (which may be a wet etching process). In contrast, conventional processes for forming via cavities through an oxide-nitride-oxide (ONO) layer stack typically use multiple etching processes. For example, conventional processes may use at least three etching processes (wet-dry-wet) using at least two masks. A person of ordinary skill in the art may appreciate that the use of a single isotropic etching process as disclosed in various embodiments herein may produce multiple advantages over conventional methods using multiple etching processes. For example, by using a single isotropic etching process instead of multiple etching processes, the various embodiments disclosed herein may significantly reduce the total processing cost and total processing time. Such cost and time savings may be achieved because additional etching processes incur additional costs and take additional processing time. In addition, by reducing the processing steps to a single isotropic etching process using a single mask layer, the various embodiments disclosed herein further reduce the total processing cost and the total processing time, because each additional etching mask layer used in the conventional process requires the application and patterning of the photoresist layer in the photolithography tool. In addition, as described above, the conventional process may use three etching processes including wet etching, dry etching, and another wet etching process. The patterning method of the various embodiments disclosed herein may use a single wet etching process, thereby avoiding any possible damage to the second silicon oxide layer 50 that may occur during a dry etching process (e.g., a reactive ion etching process).

[0064] Therefore, an embodiment of the present disclosure may provide a micro device, the micro device comprising a substrate 10, a conductive material portion 20, and a layer stack (30, 40, 50), the layer stack comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 from bottom to top. In particular, in various embodiments, the micro device may be an optical device. In such an embodiment, the substrate 10 may include an optically transparent substrate, such as fused silica, quartz, or glass. The conductive material portion 20 may include a transparent conductive material (such as a transparent oxide material) or an optically opaque metal. In one embodiment, the first optical device formed on the substrate 10 may include a transparent conductive material as the corresponding conductive material portion 20, and the second optical device formed on the substrate 10 may include a metal (optically opaque material) as the corresponding conductive material portion 20. The optical device formed by the microfabrication process of the present disclosure may include an optical filter and / or an optical mirror and / or a beam splitter and / or other optical devices that can be obtained by adjusting the thickness of each layer in the layer stack of the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50. Furthermore, electrical contact may be provided to each conductive material portion 20 within an optical device formed on substrate 10 .

[0065] With reference to all the drawings and in accordance with various embodiments of the present disclosure, there is provided a structure comprising: a conductive material portion 20 located on a substrate 10; a layer stack (30, 40, 50) comprising, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40 having a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm, and a second silicon oxide layer 50 located above the conductive material portion 20; and a through-hole cavity 59 extending through the layer stack (30, 40, 50), wherein sidewalls of the through-hole cavity 59 comprise a first concave sidewall of the first silicon oxide layer 30 adjacent to a top surface of the conductive material portion 20, a right-conical sidewall of the silicon nitride layer 40 adjacent to a corresponding top end of the first concave sidewall, and a second concave sidewall of the second silicon oxide layer 50 adjacent to a corresponding top end of the straight-conical sidewall, such that a width w of the through-hole cavity 59 strictly increases with a vertical distance vd from a horizontal top surface of the conductive material portion 20. A quantity strictly increases with a parameter means that an increase in the value of the quantity follows any increase in the value of the parameter.

[0066] As described above, the taper angle α of the straight tapered sidewall of the silicon nitride layer may be determined by the ratio of the etching rate of the second silicon oxide material of the second silicon oxide layer 50 in an n:1 BOE solution (n is in the range of 3 to 12) to the etching rate of the silicon nitride layer 40 in the n:1 BOE solution. The ratio of the etching rates may be in the range of 2 to 10. In one embodiment, the straight tapered sidewall of the silicon nitride layer 40 may have a taper angle in the range of 62 degrees (which is approximately an angle corresponding to the inverse tangent of 2) to 84 degrees (which is approximately an angle corresponding to the inverse tangent of 10) relative to the vertical direction perpendicular to the top surface of the conductive material portion 20.

[0067] In one embodiment, substrate 10 comprises and / or consists essentially of a transparent dielectric material selected from fused silica, quartz, and glass; and conductive material portion 20 comprises and / or consists essentially of a material selected from a metal material and a transparent conductive oxide material.

[0068] In one embodiment, the substrate 10 has a thickness ranging from 10 microns to 3 mm; the first silicon oxide layer 30 has a first thickness t1 ranging from 100 nm to 1,000 nm; the silicon nitride layer 40 has a second thickness t2 ranging from 50 nm to 500 nm; and the second silicon oxide layer 50 has a third thickness t3 ranging from 50 nm to 500 nm.

[0069] In one embodiment, the structure includes a metal contact structure 60 in a via cavity 50 on a top surface of the conductive material portion 20 .

[0070] According to an embodiment of the present disclosure, a microfabrication method is provided, the microfabrication method comprising: providing a structure including a layer stack (30, 40, 50) and a conductive material portion 20 underlying the layer stack (30, 40, 50) and overlying a substrate 10, the layer stack including, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50; forming a patterned etch mask layer 50 including an opening passing therethrough on the layer stack (30, 40, 50); 7; and isotropically etching the second silicon oxide layer 50, the silicon nitride layer 40, and a portion of the first silicon oxide layer 30 by using an isotropic etching process to form a through hole cavity 59 extending through the layer stack (30, 40, 50) and extending downward to the top surface of the conductive material portion 20, wherein the etching rate of the silicon nitride layer 40 in the isotropic etching process is in the range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide layer 30. In one embodiment, the microfabrication method of the present disclosure can be used to form an optical structure, which may include an optical filter, an optical mirror, or a beam splitter. In one embodiment, the isotropic etching process includes a wet etching process using a buffered oxide etching solution, wherein the buffered oxide etching solution includes an n:1 volume ratio mixture of 40% NH4F in water to 49% HF in water, where n is in the range of 3 to 12. In one embodiment, the silicon nitride layer is formed by chemical vapor deposition, in which a silicon precursor gas and a nitrogen precursor gas are combined to form a silicon nitride material. In one embodiment, the silicon nitride layer has a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm. In one embodiment, the first silicon oxide layer comprises a first silicon oxide material formed by decomposition of tetraethoxysilane; and the second silicon oxide layer comprises a second silicon oxide material formed by decomposition of tetraethoxysilane. In one embodiment, the first silicon oxide material and the second silicon oxide material are undoped silicate glass materials; and the etching rate of the second silicon oxide material is in the range of 0.80 times the etching rate of the first silicon oxide layer to 1.25 times the etching rate of the first silicon oxide layer.In one embodiment, the isotropic etching process includes: a first step, in which the material of the second silicon oxide layer isotropically etched through the bottom cut below the patterned etching mask layer, while the remaining portion of the second silicon oxide layer covers the silicon nitride layer below the patterned etching mask layer; a second step, in which the material of the silicon nitride layer is etched at a lower etching rate than the etching rate of the second silicon oxide layer, while forming a straight tapered sidewall through the silicon nitride layer, and the remaining portion of the silicon nitride layer covers the first silicon oxide layer below the patterned etching mask layer; and a third step, in which the material of the first silicon oxide layer and the material of the second silicon oxide layer are etched to form a concave surface, and the material of the silicon nitride layer is etched while the straight tapered sidewall moves laterally outward without forming a concave surface. In one embodiment, the microfabrication method also includes forming a metal contact structure in the through-hole cavity on the top surface of the conductive material portion. In one embodiment, the substrate comprises a transparent dielectric material selected from fused silica, quartz, and glass, and has a thickness in the range of 10 micrometers to 3 mm. In one embodiment, the conductive material portion comprises a material selected from a metal material and a transparent conductive oxide material; the first silicon oxide layer has a first thickness in the range of 100 nm to 1,000 nm; the silicon nitride layer has a second thickness in the range of 50 nm to 500 nm; and the second silicon oxide layer has a third thickness in the range of 50 nm to 500 nm.

[0071] According to an embodiment of the present disclosure, a method for patterning a structure is provided, the method comprising: forming a layer stack (30, 40, 50) including a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 over a conductive material portion 20 on a substrate 10; forming a patterned etch mask layer 57 including an opening therethrough over the layer stack (30, 40, 50); and forming a through hole cavity 59 extending through the layer stack (30, 40, 50) and downwardly extending to a top surface of the conductive material portion 20 by isotropically etching the second silicon oxide layer 50, the silicon nitride layer 40, and a portion of the first silicon oxide layer 30 during a single wet etching process using a buffered oxide etching solution, the buffered oxide etching solution comprising an n:1 volume ratio mixture of 40% NH4F in water to 49% HF in water, n being in the range of 3 to 12. In one embodiment, the patterning method of the present disclosure can be used to form an optical structure, which can include an optical filter, an optical mirror, or a beam splitter. In one embodiment, the layer stack is formed by the following steps: forming the first silicon oxide layer by depositing a first silicon oxide material in a first chemical vapor deposition process; forming the silicon nitride layer by depositing a silicon nitride material in a second chemical vapor deposition process; and forming the second silicon oxide layer by depositing a second silicon oxide material in a third chemical vapor deposition process. In one embodiment, during the single wet etching process, the etching rate of the silicon nitride layer is in the range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide layer. In one embodiment, the substrate comprises a transparent dielectric material selected from fused silica, quartz, and glass; and the conductive material portion comprises a material selected from a metal material and a transparent conductive oxide material. In one embodiment, the method further comprises forming a metal contact structure in the through-hole cavity on the top surface of the conductive material portion by depositing and patterning a conductive material.

[0072] According to an embodiment of the present disclosure, a structure is provided, the structure comprising: a conductive material portion 20 formed on a substrate 10; a layer stack (30, 40, 50) comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50, located above the conductive material portion 20; and a via cavity 59 extending through the layer stack (30, 40, 50) and extending downward to a top surface of the conductive material portion 20, wherein a sidewall of the via cavity 59 comprises a first concave sidewall of the first silicon oxide layer 30 adjacent to the top surface of the conductive material portion 20, a straight tapered sidewall of the silicon nitride layer 40 adjacent to a corresponding top end of the first concave sidewall, and a second concave sidewall of the second silicon oxide layer 50 adjacent to a corresponding top end of the straight tapered sidewall, such that a width of the via cavity 59 strictly increases with a vertical distance from a horizontal top surface of the conductive material portion 20. The silicon nitride layer 40 may have a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm. In one embodiment, the structure of the present disclosure may include an optical structure, which may include an optical filter, an optical mirror, or a beam splitter. In one embodiment, the straight tapered sidewall of the silicon nitride layer has a taper angle in the range of 72 degrees to 85 degrees relative to a vertical direction perpendicular to the top surface of the conductive material portion. In one embodiment, the substrate comprises a transparent dielectric material selected from fused silica, quartz, and glass; and the conductive material portion comprises a material selected from a metal material and a transparent conductive oxide material. In one embodiment, the substrate has a thickness in the range of 10 microns to 3 mm; the first silicon oxide layer has a thickness in the range of 100 nm to 1,000 nm; the silicon nitride layer has a thickness in the range of 50 nm to 500 nm; and the second silicon oxide layer has a thickness in the range of 50 nm to 500 nm. In one embodiment, the structure also includes a metal contact structure in the through-hole cavity located on the top surface of the conductive material portion.

[0073] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and replacements herein without departing from the spirit and scope of the present disclosure.

[0074] [Explanation of Symbols]

[0075] 10: Substrate

[0076] 20: Conductive material part

[0077] 30: First silicon oxide layer / layer stack

[0078] 40: Silicon nitride layer / layer stack

[0079] 50: Second silicon oxide layer / layer stack

[0080] 57: Patterned etching mask layer

[0081] 59: Through hole cavity

[0082] 60: Metal contact structure / bonding pad

[0083] 80: Metal contact structure / solder material part

[0084] 800: Optical structure

[0085] 880: Optically clear filling material part

[0086] 890: Front binding pad

[0087] 900: Semiconductor chips

[0088] 920: Optical semiconductor devices

[0089] 970: Bonding structure / chip side bonding pad

[0090] 980: Bonding structure / solder balls

[0091] 990: Bonding structure / board side bonding pad

[0092] 999: Printed Circuit Board

[0093] 1000: Flowchart

[0094] 1010, 1020, 1030: Steps

[0095] α: cone angle

[0096] B: Area

[0097] d_0: Etching distance

[0098] d_1: first etching distance

[0099] d_2: Second etching distance

[0100] ef_0: Etching front / the frontmost etching front

[0101] ef_1: Etching front / first etching front

[0102] ef_2: Etching front

[0103] P_0: Etching starting point

[0104] P_1: The center point of the first etching front

[0105] P_2: center point before the second etching

[0106] Rc_0: radius of curvature

[0107] Rc_1: First radius of curvature

[0108] Rc_2: Second radius of curvature

[0109] Rc_f: radius of curvature

[0110] t1: first thickness

[0111] t2: second thickness

[0112] t3: third thickness

[0113] UC: Undercut area

[0114] vd: vertical distance

[0115] w: width

Claims

1. A method for making a patterned silicon oxide-silicon nitride-silicon oxide stack, comprising: Providing a structure including a layer stack and a conductive material portion underlying the layer stack and overlying a substrate, the layer stack including, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer; forming a patterned etch mask layer including openings therethrough over the layer stack; forming a via cavity extending through the layer stack and extending downward to a top surface of the conductive material portion by isotropically etching the second silicon oxide layer, the silicon nitride layer, and a portion of the first silicon oxide layer using an isotropic etching process, wherein an etching rate of the silicon nitride layer in the isotropic etching process is in a range of 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide layer; forming a solder material portion in the via cavity on the top surface of the conductive material portion; as well as A semiconductor chip is bonded to the solder material portion.

2. The method for manufacturing a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1, wherein the isotropic etching process comprises a wet etching process using a buffered oxide etching solution, wherein the buffered oxide etching solution comprises an n:1 volume ratio mixture of 40% NH4F in water and 49% HF in water, where n is in the range of 3 to 12.

3. The method for making a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1, wherein the silicon nitride layer is formed by chemical vapor deposition, in which a silicon precursor gas and a nitrogen precursor gas are combined to form a silicon nitride material. 4 . The method for fabricating a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 3 , wherein the silicon nitride layer has a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm.

5. The method for manufacturing a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1, wherein: The first silicon oxide layer includes a first silicon oxide material formed by decomposition of tetraethoxysilane; and The second silicon oxide layer includes a second silicon oxide material formed by decomposition of tetraethoxysilane.

6. The method for manufacturing a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 5, wherein: The first silicon oxide material and the second silicon oxide material are undoped silicate glass materials; and An etching rate of the second silicon oxide material is in a range from 0.80 times to 1.25 times of the etching rate of the first silicon oxide layer.

7. The method for manufacturing a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1, wherein the isotropic etching process comprises: A first step, in which the material of the second silicon oxide layer is isotropically etched through the bottom cut below the patterned etching mask layer, while the remaining portion of the second silicon oxide layer covers the silicon nitride layer below the patterned etching mask layer; A second step, in which the material of the silicon nitride layer is etched at a lower etching rate than the etching rate of the second silicon oxide layer, while forming a straight tapered sidewall through the silicon nitride layer, and the remaining portion of the silicon nitride layer covers the first silicon oxide layer below the patterned etching mask layer; as well as A third step is performed in which the material of the first silicon oxide layer and the material of the second silicon oxide layer are etched to form a concave surface, and the material of the silicon nitride layer is etched to move the straight tapered sidewall laterally outward without forming a concave surface.

8. The method for manufacturing a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1 further includes forming a metal contact structure including a bonding pad and the solder material portion in the through-hole cavity on the top surface of the conductive material portion, and the conductive material portion includes at least one of a metal material, a conductive metal nitride material, and a conductive metal oxide material.

9. The method for fabricating a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1, wherein the substrate comprises a transparent dielectric material selected from fused silica, quartz and glass, and has a thickness ranging from 10 microns to 3 mm.

10. The method for manufacturing a patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 1, wherein: The conductive material portion comprises a material selected from a metal material and a transparent conductive oxide material; The first silicon oxide layer has a first thickness ranging from 100 nm to 1,000 nm; The silicon nitride layer has a second thickness ranging from 50 nm to 500 nm; and The second silicon oxide layer has a third thickness ranging from 50 nm to 500 nm.

11. A method for patterning a silicon oxide-silicon nitride-silicon oxide stack, comprising: forming a layer stack including a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer over the conductive material portion on the substrate; forming a patterned etch mask layer including openings therethrough over the layer stack; forming a via cavity extending through the layer stack and down to a top surface of the conductive material portion by isotropically etching the second silicon oxide layer, the silicon nitride layer, and a portion of the first silicon oxide layer during a single wet etching process using a buffered oxide etch solution comprising an n:1 volume ratio mixture of 40% NH4F in water to 49% HF in water, n ranging from 3 to 12; forming a solder material portion in the via cavity on the top surface of the conductive material portion; and A semiconductor chip is bonded to the solder material portion.

12. The method according to claim 11, wherein the layer stack is formed by the following steps: forming the first silicon oxide layer by depositing a first silicon oxide material in a first chemical vapor deposition process; forming the silicon nitride layer by depositing a silicon nitride material in a second chemical vapor deposition process; and The second silicon oxide layer is formed by depositing a second silicon oxide material in a third chemical vapor deposition process. 13 . The method of claim 11 , wherein during the single wet etching process, an etching rate of the silicon nitride layer is in a range from 1 / 10 times to 1 / 2 times the etching rate of the first silicon oxide layer.

14. The method according to claim 11, wherein: The substrate comprises a transparent dielectric material selected from fused silica, quartz, and glass; and The conductive material portion includes a material selected from a metal material and a transparent conductive oxide material.

15. The method according to claim 14 also includes forming a metal contact structure including a bonding pad and the solder material portion in the through-hole cavity on the top surface of the conductive material portion by depositing and patterning a conductive material, and the conductive material portion includes at least one of a metal material, a conductive metal nitride material, and a conductive metal oxide material.

16. A patterned silicon oxide-silicon nitride-silicon oxide stack comprising: A conductive material portion, located on the substrate; a layer stack including, from bottom to top, a first silicon oxide layer, a silicon nitride layer having a refractive index ranging from 1.88 to 1.95 at a wavelength of 632.8 nm, and a second silicon oxide layer and located above the conductive material portion; as well as a via cavity extending through the layer stack, wherein sidewalls of the via cavity include a first concave sidewall of the first silicon oxide layer adjacent to a horizontal top surface of the conductive material portion, a straight tapered sidewall of the silicon nitride layer adjacent to a respective top end of the first concave sidewall, and a second concave sidewall of the second silicon oxide layer adjacent to a respective top end of the straight tapered sidewall, such that a width of the via cavity strictly increases with vertical distance from the horizontal top surface of the conductive material portion; a solder material portion located in the through-hole cavity on the horizontal top surface of the conductive material portion; as well as A semiconductor chip is bonded to the solder material portion.

17. The patterned silicon oxide-silicon nitride-silicon oxide stack of claim 16, wherein the straight tapered sidewalls of the silicon nitride layer have a taper angle ranging from 72 degrees to 85 degrees relative to a vertical direction perpendicular to the horizontal top surface of the conductive material portion.

18. The patterned silicon oxide-silicon nitride-silicon oxide stack of claim 16, wherein: The substrate comprises a transparent dielectric material selected from fused silica, quartz, and glass; and The conductive material portion includes a material selected from a metal material and a transparent conductive oxide material.

19. The patterned silicon oxide-silicon nitride-silicon oxide stack of claim 16, wherein: The substrate has a thickness ranging from 10 micrometers to 3 mm; The first silicon oxide layer has a thickness ranging from 100 nm to 1,000 nm; The silicon nitride layer has a thickness ranging from 50 nm to 500 nm; and The second silicon oxide layer has a thickness ranging from 50 nm to 500 nm.

20. The patterned silicon oxide-silicon nitride-silicon oxide stack according to claim 16 further includes a metal contact structure in the through-hole cavity located on the horizontal top surface of the conductive material portion, the metal contact structure includes a bonding pad and the solder material portion, and the conductive material portion includes at least one of a metal material, a conductive metal nitride material, and a conductive metal oxide material.

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