Semiconductor device and method of forming a semiconductor device

Abstract

The method includes: etching a dielectric layer to form a dielectric fin; depositing a transition metal dichalcogenide layer on the dielectric fin; and performing an anisotropic etching process on the transition metal dichalcogenide layer. A horizontal portion of the transition metal dichalcogenide layer is removed, while a vertical portion of the transition metal dichalcogenide layer located on the sidewalls of the dielectric fin is retained to form a vertical semiconductor ring. The method also includes: forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring; and forming source / drain contact plugs, wherein the source / drain contact plugs contact the sidewalls of a second portion of the vertical semiconductor ring. Embodiments of the present application also relate to semiconductor devices and methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that should be addressed. Summary of the Invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: etching a dielectric layer to form a dielectric fin; depositing a transition metal dichalcogenide layer on the dielectric fin; performing a first anisotropic etching process on the transition metal dichalcogenide layer, wherein a horizontal portion of the transition metal dichalcogenide layer is removed and a vertical portion of the transition metal dichalcogenide layer located on a sidewall of the dielectric fin is retained to form a vertical semiconductor ring; forming a gate stack on a first portion of the vertical semiconductor ring; and forming a source / drain contact plug, wherein the source / drain contact plug contacts the sidewall of a second portion of the vertical semiconductor ring.

[0005] Other embodiments of the present application provide a semiconductor device comprising: a dielectric fin; a transition metal dichalcogenide layer located on a sidewall of the dielectric fin; a gate stack located on the dielectric fin and the transition metal dichalcogenide layer, wherein the gate stack contacts a first portion of the sidewall of the transition metal dichalcogenide layer; a gate spacer contacting the gate stack; and a source / drain contact plug contacting a second portion of the sidewall of the transition metal dichalcogenide layer.

[0006] Still other embodiments of the present application provide a semiconductor device comprising: a dielectric layer; a dielectric fin located above the dielectric layer; a two-dimensional semiconductor material forming a ring surrounding and contacting the sidewalls of the dielectric fin; a gate dielectric contacting the dielectric fin and a top surface of the dielectric layer, and also contacting the two-dimensional semiconductor material; a gate electrode located above the gate dielectric, wherein the two-dimensional semiconductor material includes a source portion and a drain portion located on opposite sides of the gate electrode; and a source / drain contact plug contacting one of the source portion and the drain portion of the two-dimensional semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D Plan and cross-sectional views illustrate intermediate stages in the formation of a three-dimensional transistor including two-dimensional materials, according to some embodiments.

[0009] Figure 12 A cross-sectional view of a portion of a three-dimensional transistor is shown, according to some embodiments.

[0010] Figure 13 A single layer of a two-dimensional material is shown, according to some embodiments.

[0011] Figure 14 Minimum channel length and channel width dimensions for several types of transistors according to some embodiments are shown.

[0012] Figure 15 A process flow for forming a three-dimensional transistor including two-dimensional materials is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] According to some embodiments, a three-dimensional (3D) transistor formed of a two-dimensional (2D) semiconductor material and a method for forming the same are provided. According to some embodiments of the present invention, the 3D transistor includes a dielectric fin, and the 2D semiconductor material is formed on the sidewalls of the dielectric fin. The embodiments discussed herein will provide examples to enable the subject matter of the present invention to be performed or used, and those skilled in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although it may be discussed as implementing method embodiments in a specific order, other method embodiments may be implemented in any logical order.

[0016] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 2A 、 Figure 2B 、 Figure 2C、 Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D 1 shows a plan view and a cross-sectional view of an intermediate stage in the formation of a three-dimensional transistor using two-dimensional materials according to some embodiments. The corresponding process is also schematically shown in FIG. Figure 15 Throughout the present disclosure, the figure numbers may be followed by the letters "A", "B", or "C", where the letter "A" indicates that the corresponding view is a plan view (top view), the letter "B" indicates that the corresponding figure is taken from reference section BB in the corresponding plan view, and the letter "C" indicates that the corresponding figure is taken from reference section CC in the corresponding plan view. For example, Figure 1B Shown Figure 1A The reference cross section BB in Figure 1C Shown Figure 1A Reference section CC in.

[0017] refer to Figure 1A 、 Figure 1B and Figure 1C, a wafer 10 including a substrate 20 is provided. According to some embodiments of the present invention, the substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 20 may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, carbon-doped silicon, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0018] An isolation layer 22 is formed over the substrate 20. The corresponding process is shown as follows: Figure 15 Process 202 of process flow 200 is shown. According to some embodiments of the present invention, isolation layer 22 is in physical contact with substrate 20. According to alternative embodiments of the present invention, other layers and devices may be present between isolation layer 22 and substrate 20, including but not limited to dielectric layers, metal components, etc. For example, interlayer dielectrics, intermetallic dielectrics (which may include low-k dielectric layers), and / or the like may be present. Integrated circuit devices such as passive devices (capacitors, resistors, inductors, etc.) and / or active devices (transistors, diodes, etc.) may or may not be formed between isolation layer 22 and substrate 20.

[0019] According to some embodiments of the present invention, the isolation layer 22 includes or is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide), silicon oxide fluoride (SiOF), silicon oxide carbide (SiOC), etc. or a high-k dielectric material (such as aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, etc.). The isolation layer 22 can be a crystalline layer (single crystal or polycrystalline) or an amorphous layer. The isolation layer 22 can have a single-layer structure or a composite structure including multiple layers. For example, the isolation layer 22 can include a double-layer structure, a triple-layer structure, etc. The double-layer structure can include two layers formed of different materials, for example, a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer. According to some embodiments of the present invention, the thickness T1 ( Figure 1B and Figure 1C ) is in the range between about 5 nm and about 20 nm.

[0020] The formation process of the isolation layer 22 may include one or more deposition processes, including, for example, a plasma-enhanced chemical vapor deposition (PECVD) process, a plasma-enhanced atomic layer deposition (PEALD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, etc. According to some embodiments of the present invention, for example, when the isolation layer 22 includes silicon oxide and when the substrate 20 includes or is formed of silicon, the isolation layer 22 may also be formed by thermal oxidation, chemical oxidation, etc.

[0021] A dielectric layer 24 is formed over the isolation layer 22. The corresponding process is shown as Figure 15 Process 204 in the process flow 200 shown. The dielectric layer 24 is formed of a material different from the material of the isolation layer 22. According to some embodiments of the present invention, the dielectric layer 24 includes or is formed of an oxide (such as silicon oxide, silicon oxyfluoride (SiOF), silicon oxycarbide (SiOC), etc.). The dielectric layer 24 can be formed of a non-high-k material and can also be formed of a low-k dielectric layer having a k value of less than 3.8. The k value can also be less than about 3.5 or less than about 3.0. The use of a low-k dielectric layer has the advantageous feature of reducing the coupling of the drain region to the channel region in the resulting transistor, which will be discussed in subsequent paragraphs. The dielectric layer 24 can be porous, including small pores to have a reduced k value. According to some embodiments of the present invention, the dielectric layer 24 is formed using CVD, ALD, PEALD, PECVD, etc. According to some embodiments of the present invention, the thickness T1 of the dielectric layer 24 ( Figure 1C ) is in the range between about 20 nm and about 60 nm.

[0022] A patterned etch mask 26, which may be a patterned photoresist, is formed over dielectric layer 24. Figure 1A As shown, patterned etch mask 26 may include a plurality of elongated strips. It should be understood that while two elongated strips are shown from which transistors are formed, according to other embodiments, there may be a single strip, three strips, four strips, or more used to form transistors.

[0023] Then, the patterned etch mask 26 is used to etch the dielectric layer 24. The corresponding process is shown as Figure 15 The process 206 in the process flow 200 is shown. Figure 2A 、 Figure 2B and Figure 2C As shown, dielectric fins 24' are formed. Etching is performed using an anisotropic etching process. During the etching process, isolation layer 22 serves as an etching stop layer. According to some embodiments of the present invention, the width W1 ( Figure 2B ) is in a range between about 3 nm and about 10 nm. The height H1 of the dielectric fin 24 ′ may be in a range between about 20 nm and about 60 nm.

[0024] refer to Figure 3A 、 Figure 3B and Figure 3C , a semiconductor layer 28 is formed by deposition. The corresponding process is shown as Figure 15 Process 208 in process flow 200 is shown. According to some embodiments of the present invention, semiconductor layer 28 is formed of a 2D material, also known as a van der Waals material. The 2D material includes one or more monolayers. Strong bonds (such as covalent bonds) are formed within the monolayer to bind atoms in the same monolayer to each other. The binding force between adjacent monolayers is a van der Waals force, which is a weak force. Therefore, although semiconductor layer 28 may include more than one monolayer, the semiconductor may act as a van der Waals material. The thicknesses T3 and T4 of semiconductor layer 28 may be less than about 5 nm, and may be in a range between about 0.5 nm and about 5 nm, or in a range between about 0.7 nm and about 3 nm.

[0025] According to some embodiments of the present invention, semiconductor layer 28 includes or is formed of a transition metal dichalcogenide (TMD) material (compounds of transition metals and Group VIA elements). Transition metals may include W, Mo, Ti, V, Co, Ni, Zr, Tc, Rh, Pd, Hf, Ta, Re, Ir, Pt, etc. Group VIA elements may include sulfur (S), selenium (Se), tellurium (Te), etc. For example, semiconductor layer 28 may include or be formed of MoS2, MoSe2, WS2, WSe2, etc.

[0026] Figure 13 A portion of an exemplary semiconductor layer 28 is shown, with two monolayers 30 shown as an example, but the total number of monolayers may be greater or less. According to some embodiments of the present invention, transition metal atoms 32 form a layer in the middle, and Group VIA atoms 33 form a first layer below the layer of transition metal atoms 32 and a second layer above the layer of transition metal atoms 32. As described above, transition metal atoms 32 may be W atoms, Mo atoms, Ti atoms, etc., and Group VIA atoms 33 may be S atoms, Se atoms, Te atoms, etc., as described above. Each transition metal atom 32 is bonded to four Group VIA atoms 33, and each Group VIA atom 33 is bonded to two transition metal atoms 32. The combination of one layer of transition metal atoms 32 and two layers of Group VIA atoms 33 is referred to as a monolayer 30 of TMD material. The bond between transition metal atoms 32 and Group VIA atoms 33 is covalent, and the bond between monolayers 30 is via van der Waals forces.

[0027] Reference again Figure 3A 、 Figure 3B and Figure 3C According to some embodiments of the present invention, the semiconductor layer 28 is a conformal layer, and the thickness T3 of the vertical portion ( Figure 3Band Figure 3C ) and the thickness T4 of the horizontal portion are close to each other, for example, the difference is less than about 20% (or 10% or less) of either thickness T3 or T4. According to some embodiments of the present invention, semiconductor layer 28 is deposited using CVD, with MoO3 powder and sulfur (or Se) powder as precursors, and nitrogen (N2) as a carrier gas. The flow rate of each of the MoO3 powder and the Se powder can be in a range between about 5 sccm and about 100 sccm. According to alternative embodiments of the present invention, PECVD or another suitable method is used. According to some embodiments of the present invention, the deposition temperature can be between about 750°C and about 1,000°C, and higher or lower temperatures can be used. The deposition duration can be in a range between about 10 minutes and about 1 hour. The process tape is controlled to achieve the desired total number of monolayers. According to some embodiments of the present invention, semiconductor layer 28 includes between 1 (a single monolayer) and about 4 monolayers, although more monolayers can be formed simultaneously. Accordingly, thicknesses T3 and T4 can be in a range between about 0.7 nm (corresponding to a single monolayer) and about 3 nm (corresponding to four monolayers).

[0028] According to some embodiments, semiconductor layer 28 may be doped with a well dopant. For example, when the resulting transistor 62 is a p-type transistor, semiconductor layer 28 may be doped to an n-type by doping with, for example, potassium (K). When the resulting transistor 62 is an n-type transistor, semiconductor layer 28 may be doped to a p-type by doping with, for example, NO2.

[0029] Figure 4A 、 Figure 4B and Figure 4C 1 and 2 show a plan view and a cross-sectional view of the formation of a vertical semiconductor ring 28', which is formed by performing an anisotropic etching process on the semiconductor layer 28. The corresponding process is shown as Figure 15 According to some embodiments of the present invention, etching is performed using an etching gas including Ar, SF6, etc., and plasma is generated during etching. Due to the anisotropic etching process, the removal of Figure 3B and Figure 3C The horizontal portions of the semiconductor layer 28 are shown, while the vertical portions of the semiconductor layer 28 located on the sidewalls of the dielectric fins 24' still remain after the etching process. Due to the anisotropic etching, the top edges of the vertical semiconductor rings 28' may have a sloped top surface (edge) 24SW. In subsequent figures, the sloped top edges are not shown, while they may still exist as shown. Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D In the final transistor 62 shown, the topmost tip of the vertical semiconductor ring 28' can be lower than or at the same height as the top surface of the dielectric fin 24'. Figure 4A In the top view shown, the vertical semiconductor rings 28 ′ have the shape of full rings surrounding the corresponding dielectric fins 24 ′.

[0030] Subsequent figures illustrate the formation of additional components of a transistor according to some embodiments. The process shown is a gate-first process, in which the gate stack of the transistor is formed before the source / drain regions of the transistor are formed. According to alternative embodiments of the present invention, a gate-last process may be employed, in which a dummy gate stack is formed and subsequently replaced with a replacement gate stack.

[0031] refer to Figure 5A 、 Figure 5B and Figure 5C , depositing the gate dielectric layer 34. The corresponding process is shown as Figure 15 Process 212 of process flow 200 is shown. According to some embodiments of the present invention, the deposited gate dielectric layer 34 and gate electrode layer 36 are used to form a dummy gate stack. For example, gate dielectric layer 34 can be formed of silicon oxide. According to other embodiments, when gate dielectric layer 34 is a dummy gate dielectric, gate dielectric layer 34 is not formed. Gate electrode layer 36 can be formed, for example, using polysilicon, and other materials can also be used.

[0032] According to some embodiments of the present invention, the deposited gate dielectric layer 34 and gate electrode layer 36 are used to form the actual gate stack that is present in the final transistor 62 ( Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D ). Therefore, the gate dielectric layer 34 may include silicon oxide, high-k dielectric materials (such as HfO2, ZrO2, HfZrO x 、HfSiO x 、HfSiON、ZrSiO x 、HfZrSiO x 、Al2O3、HfAlO x 、HfAlN、ZrAlO x , La 2 O 3 , TiO 2 , Yb 2 O 3 , silicon nitride, etc.) or a composite layer thereof. For example, the gate dielectric layer 34 may include a silicon oxide layer and a high-k dielectric layer located above the silicon oxide layer.

[0033] A gate electrode layer 36 is formed over the gate dielectric layer 34. The corresponding process is shown as Figure 15Process 214 in the process flow 200 shown. The gate electrode layer 36 may include one or more layers. According to some embodiments of the present invention, the gate electrode layer 36 may have a diffusion barrier layer, a work function layer located above the diffusion barrier layer, a cap layer located above the work function layer, and may or may not include a fill metal region located above the cap layer. The diffusion barrier layer may include or be formed of TiN, TiSiN, etc. The work function layer may include or be formed of a material selected based on whether the corresponding transistor is an n-type transistor or a p-type transistor. A metal layer formed of a metal or a metal alloy (such as tungsten, cobalt, etc.) may be formed to form the fill metal region. According to other embodiments, the gate electrode layer 36 includes polysilicon.

[0034] Then, the gate dielectric layer 34 and the gate electrode layer 36 are patterned in a patterning process to form a gate electrode layer 36 as shown in FIG. Figure 6A 、 Figure 6B and Figure 6C The gate stack 38 is shown. The corresponding process is shown as Figure 15 The process 216 in the process flow 200 is shown. The remaining portion of the patterned gate dielectric layer 34 is referred to as the gate dielectric 34', and the remaining portion of the patterned gate electrode layer 36 is referred to as the gate electrode 36'. The gate dielectric 34' and the gate electrode 36' are collectively referred to as the gate stack 38. Figure 6A As shown, in the example, the gate stack 38 covers a portion of each of the vertical semiconductor rings 28' and leaves opposite ends of the vertical semiconductor rings 28' exposed. It should be understood that although a single gate stack 38 is shown, multiple gate stacks 38 may be formed on the dielectric fins 24' and the vertical semiconductor rings 28', with the multiple gate stacks 38 being parallel to each other. The multiple gate stacks 38 are spaced apart from each other, with each gate stack formed on a portion of each of the vertical semiconductor rings 28' and the dielectric fins 24' and leaving other portions of the vertical semiconductor rings 28' and the dielectric fins 24' exposed.

[0035] Figure 7A 、 Figure 7B and Figure 7C The formation of gate spacers 40 on the sidewalls of the gate stack 38 is shown. The corresponding process is shown as Figure 15Process 218 in the process flow 200 is shown. According to some embodiments of the present invention, the gate spacer 40 is formed of a dielectric material (such as silicon nitride, silicon oxide, silicon carbonitride, etc.) and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation of the gate spacer 40 may include depositing a blanket spacer layer and performing an anisotropic etching process to remove horizontal portions of the spacer layer. Since some portions of the spacer layer (schematically shown as 40') may remain on the sidewalls of the vertical semiconductor ring 28', an additional etching process may be performed to remove the undesired portions 40'. Removing the spacer portions 40' may include forming an etching mask 42 (such as a patterned photoresist) to cover the gate spacer 40 and the gate stack 38, and performing an isotropic etching process to remove the undesired spacers 40' on the sidewalls of the vertical semiconductor ring 28'. Due to the etching of the undesired spacers 40', the entire sidewall surface of the vertical semiconductor ring 28' (including the bottom near the isolation layer 22) is exposed. This will advantageously increase the contact area between subsequently formed source / drain contact plugs and the vertical semiconductor rings 28'. The etch mask 42, if formed, is then removed.

[0036] According to some embodiments of the present invention, the exposed portion of the vertical semiconductor ring 28' is doped to form the source / drain region 43. When the resulting transistor is an n-type transistor, the exposed portion of the vertical semiconductor ring 28' is doped to n-type by, for example, potassium. When the resulting transistor is a p-type transistor, the exposed portion of the vertical semiconductor ring 28' is doped to p-type by, for example, NO2.

[0037] Figure 8A 、 Figure 8B and Figure 8C The structure after the formation of the contact etch stop layer (CESL) 44 is shown. The corresponding process is shown as Figure 15 The process 220 in the process flow 200 is shown. The CESL 44 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. Figure 8C As shown, CESL 44 is formed as a conformal layer and can be in physical contact with the sidewalls of vertical semiconductor rings 28'. Additionally, CESL 44 can be in physical contact with the top surface of dielectric fins 24'.

[0038] Figure 8A 、 Figure 8B and Figure 8C Also shown is the formation of an interlayer dielectric (ILD) 46. The corresponding process is shown as Figure 15The process 222 in the process flow 200 is shown. ILD 46 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 46 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process (such as a CMP process or a mechanical grinding process) may be performed to level the top surface of ILD 46. According to some embodiments of the present invention, as Figure 8B and Figure 8C As shown, the planarization process stops before CESL 44 is exposed, and a layer of ILD 46 remains over CESL 44. According to alternative embodiments of the present invention, planarization may be performed until gate stack 38 and gate spacers 40 are exposed, and dashed line 48 is drawn to illustrate an exemplary location where the planarization process is stopped.

[0039] According to some embodiments where gate stack 38 is a dummy gate stack, the planarization process may be stopped at location 48 and dummy gate stack 38 may be replaced with replacement gate stack 38′. Figure 12 The replacement process may include: performing an etching process to remove the dummy gate stack 38, forming a trench between opposing gate spacers 40, depositing a dielectric layer and a gate electrode layer (which may include multiple layers) extending into the trench, and performing a planarization process to remove excess material. The resulting replacement gate dielectric 34" and gate electrode 36" Figure 12 ) can be found in the discussion of the gate dielectric layer 34 and the gate electrode layer 36 and will not be repeated here.

[0040] Figure 9A 、 Figure 9B and Figure 9C The formation of gate contact opening 50 and source / drain contact opening 52 is shown. The corresponding process is shown as Figure 15 The process 224 of the process flow 200 is shown. The formation process includes an anisotropic etching process. The etching is performed using the CESL 44 as an etch stop layer. As a result, the portion of the CESL 44 located on the sidewalls of the vertical semiconductor ring 28 ′ and the horizontal portion of the CESL 44 located on the top of the dielectric fin 24 ′ are exposed to the source / drain contact opening 52.

[0041] refer to Figure 10A 、 Figure 10B and Figure 10C , removing the exposed portion of CESL 44 so that the gate contact opening 50 and the source / drain contact opening 52 extend downward. The corresponding process is shown as Figure 15Process 226 of process flow 200 is shown. According to some embodiments of the present invention, etching is performed by an isotropic etching process (which can be a wet etching process or a dry etching process). As a result, the entire sidewall surface of vertical semiconductor ring 28' (including the bottom near isolation layer 22) is exposed.

[0042] Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D 1 and 2 show a plan view and a cross-sectional view of the formation of the gate contact plug 54 and the source / drain contact plug 56. The corresponding process is shown as follows: Figure 15 Process 228 in process flow 200 is shown. This formation may include depositing one or more conductive layers to fill gate contact opening 50 and source / drain contact openings 52, and performing a planarization process to remove excess material above ILD 46, leaving gate contact plug 54 and source / drain contact plug 56. According to some embodiments of the present invention, the entirety of gate contact plug 54 and source / drain contact plug 56 is formed from a homogeneous conductive material, which may be a metal or a metal alloy including tungsten, cobalt, aluminum, or alloys thereof. According to alternative embodiments of the present invention, each of gate contact plug 54 and source / drain contact plug 56 includes an adhesion layer 57A and a homogeneous conductive material 57B located above the adhesion layer. Adhesion layer 57A may include or be formed from titanium, titanium nitride, tantalum, tantalum nitride, or the like. The homogeneous conductive material may also be a metal or metal alloy including tungsten, cobalt, aluminum, or the like, or alloys thereof.

[0043] Figure 11D Also shown Figure 11A The reference cross section DD in Figure 11C and Figure 11D As shown, the source / drain contact plugs 56 contact the sidewalls of the vertical semiconductor rings 28' through edge contacts, and the contact area of ​​each of the vertical semiconductor rings 28' is equal to H1×(2L1+W1)( Figure 11A ), where height H1 is Figure 11C As shown in the figure, the length L1 and width W1 are Figure 11A Therefore, the contact area between the contact plug and the corresponding source / drain region is large, and the contact resistance is small.

[0044] refer to Figure 11C , according to some embodiments of the present invention, the source / drain contact plug 56 has a sidewall in contact with the sidewall of the gate spacer 40. Therefore, the value of L1 is maximized ( Figure 11A). This can maximize the contact area between the source / drain contact plugs 56 and the source / drain regions 43, and thus lead to a reduction in the source / drain contact resistance. According to an alternative embodiment of the present invention, the source / drain contact plugs 56 are spaced apart from the corresponding nearest gate spacers 40 to increase the process margin. For example, Figure 12 An embodiment is shown in which the source / drain contact plugs 56 are spaced apart from the gate spacers 40 .

[0045] Figure 12 According to an alternative embodiment, Figure 11A These embodiments are similar to Figure 11C In the illustrated embodiment, in addition to forming a replacement gate stack 38', when the gate stack 38 is a dummy gate stack, the replacement gate stack 38' replaces the gate stack 38'. Figure 5A 、 Figure 5B and Figure 5C The replacement gate stack 38 is shown. The replacement gate stack 38' includes a replacement gate dielectric 34" and a gate electrode 36". The replacement gate dielectric may include a silicon oxide layer and may include a high-k dielectric layer located above the silicon oxide layer. The high-k dielectric layer may include HfO2, ZrO2, HfZrO x 、HfSiO x 、HfSiON、ZrSiO x 、HfZrSiO x 、Al2O3、HfAlO x 、HfAlN、ZrAlO x , La2O3, TiO2, Yb2O3, silicon nitride, etc. or a composite layer thereof. The material of the replacement gate electrode 36" may include or be made of the same material as the reference Figure 5B and Figure 5C A similar metal-containing material as discussed with reference to gate electrode layer 36 is formed.

[0046] Figure 14 The figure shows simulation results for simulating the performance of several types of transistors. The Y-axis represents the minimum gate length, and the corresponding transistor with the minimum gate length can still have good gate control capability, for example, the subthreshold swing (SS) is less than about 70mV / dec. The X-axis represents the dimension of the channel in the direction perpendicular to the gate length direction (hereinafter referred to as the channel width dimension), which can be the channel thickness t CH , the diameter D of the nanowire and / or the width of the channel. The simulated transistors include single-gate transistors, FinFETs, nanowire (NW) transistors, and transistors according to embodiments of the present invention. Figure 14The functional relationship between the minimum channel length and the channel width size is shown. The simulation results show that when the channel width size increases, the minimum (required) channel length of the transistor may also increase. When the same channel width size is used for all types of transistors, the transistor according to the embodiment of the present invention has the smallest minimized channel length. This shows that the transistor formed according to the embodiment of the present invention can have a minimum channel length while still maintaining good channel control between the simulated transistors. In other words, when the channel width size is the same, the transistor formed according to the embodiment of the present invention has better scaling capabilities than other types of transistors. For example, when the channel width size is 6nm. The transistor according to the embodiment of the present invention has a minimum channel length of 6nm, while the nanowire transistor and FinFET have minimum channel lengths of about 9nm and about 14nm, respectively, which are much higher than the transistor according to the embodiment of the present invention. The single-gate transistor has even worse scaling capabilities than the nanowire transistor and the FinFET.

[0047] Embodiments of the present invention have several advantageous features. By forming a 2D (van der Waals) material as the transistor channel, short channel effects can be minimized, and the minimum channel length of the resulting transistor can be scaled down without increasing the subthreshold swing. By employing edge contacts with maximized area, the contact resistance of the source / drain contacts can be reduced.

[0048] According to some embodiments of the present invention, a method includes: etching a dielectric layer to form a dielectric fin; depositing a transition metal dichalcogenide layer on the dielectric fin; performing a first anisotropic etching process on the transition metal dichalcogenide layer, wherein a horizontal portion of the transition metal dichalcogenide layer is removed, while a vertical portion of the transition metal dichalcogenide layer located on a sidewall of the dielectric fin remains to form a vertical semiconductor ring; forming a gate stack on a first portion of the vertical semiconductor ring; and forming source / drain contact plugs, wherein the source / drain contact plugs contact sidewalls of a second portion of the vertical semiconductor ring. According to one embodiment, depositing the transition metal dichalcogenide layer includes depositing a MoS2 layer. According to an embodiment, the method further includes: after forming the gate stack, depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) covering the transition metal dichalcogenide layer, and forming source / drain contact plugs includes: performing a second anisotropic etching process to form contact openings penetrating the ILD, exposing the CESL layer in the contact openings; performing an isotropic etching process on the CESL to expose the transition metal dichalcogenide layer in the contact openings; and filling the contact openings with a conductive material. According to an embodiment, the method further includes: forming gate spacers on sidewalls of the gate stack, with the source / drain contact plugs contacting the sidewalls of the gate spacers. According to an embodiment, the method further includes: forming gate spacers, wherein the sidewalls of the gate stack and the gate spacers contact each other, and the source / drain contact plugs are spaced apart from the gate spacers. According to an embodiment, etching the dielectric layer using an additional dielectric layer as an etch stop layer to form dielectric fins, and the source / drain contact plugs form an interface with the vertical semiconductor rings, wherein the interface extends from the top of the vertical semiconductor rings to the top surface of the additional dielectric layer. According to an embodiment, the transition metal dichalcogenide layer is implemented using chemical vapor deposition of MoO 3 powder and sulfur powder as precursors.

[0049] According to some embodiments of the present invention, a device includes: a dielectric fin; a transition metal dichalcogenide layer located on sidewalls of the dielectric fin; a gate stack located on the dielectric fin and the transition metal dichalcogenide layer, wherein the gate stack contacts a first portion of the sidewalls of the transition metal dichalcogenide layer; a gate spacer contacting the gate stack; and source / drain contact plugs contacting a second portion of the sidewalls of the transition metal dichalcogenide layer. According to some embodiments, the device further includes: a dielectric layer, the dielectric fin located above and contacting the dielectric layer, wherein the transition metal dichalcogenide layer extends to a top surface of the dielectric layer. According to some embodiments, the source / drain contact plugs form an interface with the transition metal dichalcogenide layer, and the interface extends to the top surface of the dielectric layer. According to some embodiments, the dielectric fin and the dielectric layer are formed of different dielectric materials. According to some embodiments, the transition metal dichalcogenide layer is a single layer. According to some embodiments, the transition metal dichalcogenide layer includes multiple single layers. According to some embodiments, the transition metal dichalcogenide layer includes MoS2.

[0050] According to some embodiments of the present invention, a device includes: a dielectric layer; a dielectric fin located above the dielectric layer; a two-dimensional semiconductor material forming a ring surrounding and contacting the sidewalls of the dielectric fin; a gate dielectric contacting the dielectric fin and the top surfaces of the dielectric layer, and also contacting the two-dimensional semiconductor material; a gate electrode located above the gate dielectric, wherein the two-dimensional semiconductor material includes a source portion and a drain portion located on opposite sides of the gate electrode; and a source / drain contact plug contacting one of the source portion and the drain portion of the two-dimensional semiconductor material. In one embodiment, each of the source portion and the drain portion contacts three sidewalls of the dielectric fin to form a U-shaped structure. In one embodiment, the two-dimensional semiconductor material has no horizontal portion parallel to the interface between the dielectric layer and the dielectric fin. In one embodiment, the two-dimensional semiconductor material includes a transition metal dichalcogenide layer. In one embodiment, the source / drain contact plug and the two-dimensional semiconductor material form an interface extending to the top surface of the dielectric layer. In one embodiment, the dielectric layer and the dielectric fin are formed of different dielectric materials.

[0051] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: etching the dielectric layer to form dielectric fins; depositing a transition metal dichalcogenide layer on the dielectric fin; performing a first anisotropic etching process on the transition metal dichalcogenide layer, wherein a horizontal portion of the transition metal dichalcogenide layer is removed and a vertical portion of the transition metal dichalcogenide layer located on a sidewall of the dielectric fin is retained to form a vertical semiconductor ring; forming a gate stack on a first portion of the vertical semiconductor ring; and Source / drain contact plugs are formed, wherein the vertical semiconductor ring surrounds the peripheral sidewalls of the dielectric fin, and the source / drain contact plugs contact a first pair of opposite sidewalls and a second pair of opposite sidewalls of the vertical semiconductor ring.

2. The method according to claim 1, wherein Depositing a transition metal dichalcogenide layer includes depositing a MoS2 layer.

3. The method according to claim 1, further comprising: After forming the gate stack, depositing a contact etch stop layer and an interlayer dielectric covering the transition metal dichalcogenide layer, and forming the source / drain contact plugs includes: performing a second anisotropic etching process to form a contact opening penetrating the interlayer dielectric, so that the contact etch stop layer is exposed in the contact opening; performing an isotropic etching process on the contact etch stop layer to expose the transition metal dichalcogenide layer to the contact opening; and The contact opening is filled with a conductive material.

4. The method according to claim 1, further comprising: Gate spacers are formed on sidewalls of the gate stack, and the source / drain contact plugs contact the sidewalls of the gate spacers.

5. The method according to claim 1, further comprising: A gate spacer is formed, wherein sidewalls of the gate stack and the gate spacer are in contact with each other, and the source / drain contact plugs are spaced apart from the gate spacer.

6. The method according to claim 1, wherein The dielectric layer is etched using an additional dielectric layer as an etch stop layer to form the dielectric fin, and the source / drain contact plugs form an interface with the vertical semiconductor ring, and wherein the interface extends from the top of the vertical semiconductor ring to the top surface of the additional dielectric layer.

7. The method according to claim 1, wherein The transition metal dichalcogenide layer was implemented using chemical vapor deposition of MoO 3 powder and sulfur powder as precursors.

8. A semiconductor device comprising: dielectric fins; a transition metal dichalcogenide layer located on the sidewalls of the dielectric fin and forming a ring surrounding the peripheral sidewalls of the dielectric fin, wherein the transition metal dichalcogenide layer comprises a two-dimensional material; a gate stack on the dielectric fin and the transition metal dichalcogenide layer, wherein the gate stack contacts a top surface of the dielectric fin and a first portion of a sidewall of the transition metal dichalcogenide layer; a gate spacer contacting the gate stack; and First and second source / drain contact plugs contact a second portion and a third portion of the sidewall of the transition metal dichalcogenide layer, respectively, in one-to-one correspondence, wherein the second portion and the third portion are one of the source portion and the drain portion located on opposite sides of the gate stack, respectively. The first and second source / drain contact plugs contact a first pair of sidewalls and a second pair of sidewalls of the ring that are opposite to each other, and the first and second source / drain contact plugs do not include the two-dimensional material.

9. The semiconductor device according to claim 8, further comprising: A dielectric layer is provided, the dielectric fin being located above and contacting the dielectric layer, wherein the transition metal dichalcogenide layer extends to a top surface of the dielectric layer.

10. The semiconductor device according to claim 9, wherein The first and second source / drain contact plugs form interfaces with the transition metal dichalcogenide layer, and the interfaces extend to a top surface of the dielectric layer.

11. The semiconductor device according to claim 9, wherein The dielectric fin and the dielectric layer are formed of different dielectric materials.

12. The semiconductor device according to claim 8, wherein The transition metal dichalcogenide layer is a monolayer.

13. The semiconductor device according to claim 8, wherein The transition metal dichalcogenide layer includes a plurality of monolayers.

14. The semiconductor device according to claim 8, wherein The transition metal dichalcogenide layer includes MoS2.

15. A semiconductor device comprising: dielectric layer; a dielectric fin located above the dielectric layer; a two-dimensional semiconductor material forming a ring surrounding and contacting a peripheral sidewall of the dielectric fin; a gate dielectric contacting the dielectric fin and a top surface of the dielectric layer, and also contacting the two-dimensional semiconductor material; a gate electrode overlying the gate dielectric, wherein the two-dimensional semiconductor material includes a source portion and a drain portion on opposite sides of the gate electrode; and first and second source / drain contact plugs, contacting one of the source portion and the drain portion of the two-dimensional semiconductor material, respectively; The first and second source / drain contact plugs contact a first pair of sidewalls and a second pair of sidewalls of the ring that are opposite to each other.

16. The semiconductor device according to claim 15, wherein Each of the source portion and the drain portion contacts three sidewalls of the dielectric fin to form a U-shaped structure.

17. The semiconductor device according to claim 15, wherein The two-dimensional semiconductor material has no horizontal portion parallel to an interface between the dielectric layer and the dielectric fin.

18. The semiconductor device according to claim 15, wherein The two-dimensional semiconductor material includes a transition metal dichalcogenide layer.

19. The semiconductor device according to claim 15, wherein The first and second source / drain contact plugs and the two-dimensional semiconductor material form an interface extending to a top surface of the dielectric layer.

20. The semiconductor device according to claim 15, wherein The dielectric layer and the dielectric fin are formed of different dielectric materials.

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