Semiconductor package structure and method of manufacturing the same

Abstract

A semiconductor heat dissipation structure includes a first semiconductor device including a first active surface and a first back surface opposite the first active surface, a second semiconductor device including a second active surface and a second back surface opposite the second active surface, a first thermally conductive layer embedded in the first back surface of the first semiconductor device, a second thermally conductive layer embedded in the second back surface of the second semiconductor device, and a third thermally conductive layer disposed adjacent to the first thermally conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first thermally conductive layer is in contact with the second thermally conductive layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging structure. Specifically, the semiconductor packaging structure includes a semiconductor heat dissipation structure. Background Technology

[0002] In general, semiconductor packages encapsulate chips in a molding compound, and the heat generated by the chip can be transferred to the outside through the molding compound. The molding compound covers most (up to 99%, or even more) of the back side of the chip. Semiconductor packaging has historically been characterized by significant performance gains, but this has led to a substantial increase in the heat generated by the chip. Molding compounds have a low coefficient of thermal expansion (CTE). Therefore, heat dissipation has become a critical issue, especially for stacked chips. Summary of the Invention

[0003] In some embodiments, according to one aspect of this disclosure, a semiconductor heat dissipation structure includes: a first semiconductor device, the first semiconductor device including a first active surface and a first back surface opposite to the first active surface; a second semiconductor device, the second semiconductor device including a second active surface and a second back surface opposite to the second active surface; a first thermally conductive layer embedded in the first back surface of the first semiconductor device; a second thermally conductive layer embedded in the second back surface of the second semiconductor device; and a third thermally conductive layer disposed adjacent to the first thermally conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first thermally conductive layer is in contact with the second thermally conductive layer.

[0004] In some embodiments, according to one aspect of this disclosure, a semiconductor package structure includes: a semiconductor heat dissipation structure; a first redistribution layer (RDL) disposed on a first active surface of a first semiconductor device and including thermally connected elements extending through the first RDL; and a heat dissipation device disposed on the first RDL. A third thermally conductive layer of the semiconductor heat dissipation structure is connected to the heat dissipation device via the thermally connected elements of the first RDL.

[0005] In some embodiments, according to another aspect of this disclosure, a method for manufacturing a semiconductor package structure is disclosed. The method includes the following operations: providing a first semiconductor device, the first semiconductor device including a first active surface and a first back surface opposite to the first active surface; providing a second semiconductor device, the second semiconductor device including a second active surface and a second back surface opposite to the second active surface; forming a first thermally conductive layer embedded in the first back surface of the first semiconductor device; forming a third thermally conductive layer adjacent to the first thermally conductive layer and extending to the first active surface of the first semiconductor device; forming a second thermally conductive layer embedded in the second back surface of the second semiconductor device; aligning the first thermally conductive layer with the second thermally conductive layer; bonding the first back surface of the first semiconductor device to the second back surface of the second semiconductor device to form a semiconductor heat dissipation structure; encapsulating the semiconductor heat dissipation structure; and connecting a heat dissipation device to the third thermally conductive layer. Attached Figure Description

[0006] Various aspects of this disclosure can be readily understood from the following detailed description, which is read in conjunction with the accompanying drawings. It should be noted that the various features may not necessarily be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A A cross-sectional view of a semiconductor heat dissipation structure according to some embodiments of the present disclosure is shown.

[0008] Figure 1B This demonstrates the different paths of semiconductor devices. Figure 1A The top view is captured by lines a-a' and b-b'.

[0009] Figure 2 A cross-sectional view of a semiconductor heat dissipation structure according to some embodiments of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0012] Figures 5A to 5L Intermediate operations of a method for manufacturing a semiconductor heat dissipation structure according to some embodiments of the present disclosure are shown.

[0013] Figures 6A to 6G Intermediate operations of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure are shown.

[0014] Figures 7A to 7G Intermediate operations of a method for manufacturing a semiconductor heat dissipation structure according to some embodiments of the present disclosure are shown.

[0015] Figures 8A to 8J Intermediate operations of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure are shown.

[0016] Throughout the accompanying drawings and detailed description, common reference numerals are used to indicate the same or similar components. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0019] In embodiments of this disclosure, by placing a thermally conductive layer (e.g., copper or other metals or alloys, or other materials with a higher CTE than the molding material) on the back side of each of the two stacked chips and placing another thermally conductive layer to connect one of the thermally conductive layers to the outside, the heat generated by the chip can be rapidly transferred to the outside, thus significantly improving heat dissipation efficiency.

[0020] Figure 1A This is a cross-sectional view of a semiconductor heat dissipation structure 1 according to some embodiments of the present disclosure. The semiconductor heat dissipation structure 1 includes a semiconductor device 11, a semiconductor device 13, a thermally conductive layer 111, a thermally conductive layer 131, and a thermally conductive layer 112. Heat generated by the semiconductor device 11 or the semiconductor device 13 can be transferred to the outside through the thermally conductive layers 111, 112, and 131.

[0021] Semiconductor device 11 includes an active surface 11a and a back surface 11b opposite to the active surface 11a. Semiconductor device 11 includes conductive pillars 113 disposed on the active surface 11a. Semiconductor device 13 includes an active surface 13a and a back surface 13b opposite to the active surface 13a. Semiconductor device 11 is stacked on semiconductor device 13. In some embodiments, the dimensions (e.g., length or width) of semiconductor device 11 are substantially equal to or smaller than the dimensions of semiconductor device 13. In some embodiments, the dimensions (e.g., length or width) of semiconductor device 11 are larger than the dimensions of semiconductor device 13. The back surface 11b of semiconductor device 11 is in contact with the back surface 13b of semiconductor device 13.

[0022] In some embodiments, semiconductor device 11 may include application-specific integrated circuits (ASICs), controllers, processors, memory, or other electronic components or semiconductor devices. Semiconductor device 13 may be of the same or different type as semiconductor device 11.

[0023] The back surface 11b of semiconductor device 11 includes a recess, and a thermally conductive layer 111 is formed in the recess of semiconductor device 11. The back surface 13b of semiconductor device 13 includes a recess, and a thermally conductive layer 131 is formed in the recess of semiconductor device 13. Figure 1A As shown, the recess of semiconductor device 11 is filled by thermally conductive layer 111 or by thermally conductive layer 111 and thermally conductive layer 112. The recess of semiconductor device 13 is filled by thermally conductive layer 131.

[0024] A thermally conductive layer 111 is embedded in the back surface 11b of the semiconductor device 11. A thermally conductive layer 131 is embedded in the back surface 13b of the semiconductor device 13. At least a portion of the thermally conductive layer 111 is in contact with the thermally conductive layer 131. For example, (based on the surface area of ​​the thermally conductive layer 111 exposed from the back surface 11b of the semiconductor device 11) at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, or about 100% of the thermally conductive layer 111 exposed from the back surface 11b of the semiconductor device 11 is in contact with the thermally conductive layer 131.

[0025] A thermally conductive layer 112 is disposed adjacent to a thermally conductive layer 111 and extends to the active surface 11a of the semiconductor device 11. The thermally conductive layer 112 is in direct contact with the thermally conductive layer 111. The thermally conductive layer 112 may contact the distal end of the thermally conductive layer 111 or other portions of the thermally conductive layer 111. In some embodiments, the thermally conductive layer 112 extends outside the active surface 11a of the semiconductor device 11. The thermally conductive layer 112 may be disposed within the semiconductor device 11, such as... Figure 1AThe thermally conductive layer 112 may be disposed on or connected to the thermally conductive layer 131 (e.g., penetrating the semiconductor device 11 and contacting the thermally conductive layer 111) or disposed outside the semiconductor device 11 (e.g., attached to the outer surface of the semiconductor device 11). In some embodiments, the thermally conductive layer 112 may be disposed on or connected to (or electrically connected to) the thermally conductive layer 131. The thermally conductive layer 112 may contact the distal end of the thermally conductive layer 131 or other portions of the thermally conductive layer 131.

[0026] In some embodiments, the heat-conducting layer 112 may be a solid heat-conducting rod / pillar or a solid heat-conducting plate. Heat-conducting layers 111, 131, and 112 may be made of the same or different metals (e.g., copper or other metals or alloys). Heat-conducting layers 111 and 112 are formed as a single piece.

[0027] In some embodiments, the thermally conductive layer 112 is disposed around the semiconductor device 11. The thermally conductive layer 112 may be connected to or electrically connected to a heat dissipation device external to the semiconductor heat dissipation structure 1. Figure 1A , 1B (Not shown in the image). A heat dissipation device may be mounted on the active surface 11a of the semiconductor device 11.

[0028] In some embodiments, the thermally conductive layer 112 may be disposed on or in direct contact with the thermally conductive layer 131.

[0029] Figure 1B The respective edges of semiconductor devices 11 and 13 Figure 1A The top view is taken by lines a-a' and b-b'. Thermal conductive layer 111, thermal conductive layer 131, or both have a serpentine shape. In some embodiments, thermal conductive layer 111, thermal conductive layer 131, or both may have any shape suitable for dissipating heat generated by semiconductor device 11 or semiconductor device 13. Thermal conductive layer 111 may include 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, or 60% or more, or 70% or more of the surface area of ​​the back surface 11b of semiconductor device 11. In some embodiments, thermal conductive layer 111 may include 20% to 50% of the surface area of ​​the back surface 11b of semiconductor device 11. In some embodiments, thermal conductive layer 111 has a first shape, and thermal conductive layer 131 has a second shape corresponding to the first shape of thermal conductive layer 111.

[0030] The semiconductor heat dissipation structure 1 further includes alignment marks 15 and alignment marks 17. The shape of alignment mark 15 is different from that of alignment mark 17. After stacking semiconductor devices 11 and 13, thermal conductive layer 111 can be aligned with thermal conductive layer 131 by alignment marks 15 and 17.

[0031] Figure 2This is a cross-sectional view of a semiconductor heat dissipation structure 1' according to some embodiments of the present disclosure. The semiconductor heat dissipation structure 1' and... Figure 1A Similar to the semiconductor heat dissipation structure 1 in the example, except that the heat-conducting layers 111', 112' and 131' are not solid heat-conducting layers but are in the form of hollow heat-conducting pipes.

[0032] In some embodiments, thermally conductive layers 111' and 131' form a continuous hollow thermally conductive tube. The hollow thermally conductive tube formed by thermally conductive layers 111' and 131' can be a V-shaped or U-shaped thermally conductive tube or have any other suitable shape. Thermally conductive layer 112' is a hollow thermally conductive tube connected to the hollow thermally conductive tube formed by thermally conductive layers 111' and 131'. The hollow thermally conductive tube formed by thermally conductive layer 112 can, together with the hollow thermally conductive tube formed by thermally conductive layers 111' and 131', form a tubular channel for cooling liquids or cooling gases.

[0033] Figure 3 This is a cross-sectional view of a semiconductor package structure 2 according to some embodiments of the present disclosure. The semiconductor package structure 2 includes a semiconductor heat dissipation structure 1, a redistribution layer (RDL) 24, an encapsulant 26, and a heat dissipation device 28. In some embodiments, the semiconductor package structure 2 may further include a semiconductor device 25 disposed on and electrically connected to the RDL 24.

[0034] RDL 24 includes a thermally connected element 241 extending through RDL 24. The semiconductor package structure 2 further includes a thermally connected element 281 disposed on RDL 24 and connected to the thermally connected element 241 and the heat dissipation device 28. Heat generated by the semiconductor devices 11 and 13 of the semiconductor heat dissipation structure 1 can be transferred to the outside of the semiconductor heat dissipation structure 1 through thermally conductive layers 111, 112, and 131, and further transferred to the heat dissipation device 28 through the thermally connected elements 241 and 281.

[0035] RDL 24 is disposed on or above the active surface 11a of semiconductor device 11. A thermal connection element 241 extends through RDL 24. Conductive posts 113 of semiconductor device 11 electrically connect semiconductor device 11 to RDL 24. In some embodiments, semiconductor package structure 2 may further include RDL 22 disposed beneath semiconductor heat dissipation structure 1. RDL 22 may be disposed on the active surface 13a of semiconductor device 13 and electrically connected to semiconductor device 13. In some embodiments, RDL 22 is electrically connected to RDL 24 via interconnect element 21. Interconnect element 21 is disposed within and extends through encapsulation material 26. Encapsulation material 26 encapsulates semiconductor heat dissipation structure 1. In some embodiments, semiconductor package structure 2 may further include electrical connection element 23. Electrical connection element 23 may be disposed on RDL 22 or RDL 24 to electrically connect RDL 22 or RDL 24 to external circuitry or another semiconductor device (e.g., semiconductor device 25) or electronic device.

[0036] The heat dissipation device 28 is mounted on the RDL 24. The thermally conductive layer 112 of the semiconductor heat dissipation structure 1 is connected to the heat dissipation device 28 through the thermal connection element 241 of the RDL 24, and further through the combination of the thermal connection element 241 and the thermal connection element 281 of the RDL 24.

[0037] Semiconductor device 25 is disposed on or above RDL 24. In some embodiments, semiconductor device 25 is disposed below heat dissipation device 28. In some embodiments, thermal paste 27 may be disposed on semiconductor device 25. Thermal paste 27 may be disposed between semiconductor device 25 and heat dissipation device 28. Semiconductor device 25 may be connected to heat dissipation device 28 via thermal connection element 281 and / or thermal paste 27, such that heat generated by semiconductor device 25 can be transferred to heat dissipation device 28.

[0038] Figure 4 This is a cross-sectional view of a semiconductor package structure 2' according to some embodiments of the present disclosure. The semiconductor package structure 2' and... Figure 3 Similar to semiconductor package structure 2, except that semiconductor package structure 2' contains Figure 2 In addition to the semiconductor heat dissipation structure 1', hollow thermal connection element 241', and hollow thermal connection element 281', in some embodiments, the hollow heat pipe, hollow thermal connection element 241', and hollow thermal connection element 281' of the semiconductor heat dissipation structure 1' form a closed tubular channel for cooling liquid or cooling gas. By circulating the cooling liquid or cooling gas in the heat pipe, the heat generated by the semiconductor devices 11, 13, and 15 can be effectively transferred to the outside.

[0039] Figures 5A to 5LSome embodiments of a method for manufacturing a semiconductor heat dissipation structure 1 according to some embodiments of the present disclosure are shown. The various figures have been simplified to present aspects of the present disclosure more clearly.

[0040] refer to Figure 5A A method for manufacturing a semiconductor heat dissipation structure 1 includes providing a semiconductor device 11, the semiconductor device 11 including an active surface 11a and a back surface 11b opposite to the active surface 11a. Photoresist 51 is provided on the back surface 11b of the semiconductor device 11. Openings in the photoresist 51 are formed by a photolithography operation. Subsequently, an etching operation is performed to form grooves 52.

[0041] refer to Figure 5B A photoresist 51 is further provided on the back surface 11b of the semiconductor device 11. An opening is formed by a photolithography operation. Subsequently, an etching operation is performed to form a groove 54. The depth of the groove 54 is greater than the depth of the groove 52.

[0042] refer to Figure 5C A seed layer 53 is formed on the back side 11b of the semiconductor device 11 and in the grooves 52 and 54.

[0043] refer to Figure 5D A photoresist 51 is provided on the back side 11b of the semiconductor device 11. Thermally conductive layers 111 and 112 are formed, for example, by electroplating. Thermally conductive layers 111 and 112 are formed integrally. Thermally conductive layer 111 fills a groove 52. Thermally conductive layer 112 fills a groove 54. Thermally conductive layers 111 and 112 can be made of thermally conductive materials, such as metal.

[0044] refer to Figure 5E The seed layer 53 on the back side 11b of the semiconductor device 11 is removed by an etching operation.

[0045] refer to Figure 5F A semiconductor device 13 is provided. The semiconductor device 13 includes an active surface 13a and a back surface 13b opposite to the active surface 13a. Photoresist 51 is provided on the back surface 13b of the semiconductor device 13. Openings in the photoresist 51 are formed by a photolithography operation. Subsequently, an etching operation is performed to form a groove 52.

[0046] refer to Figure 5G A seed layer 53 is formed on the back side 13b of the semiconductor device 13 and in the groove 52.

[0047] refer to Figure 5H A photoresist 51 is provided on the back side 13b of the semiconductor device 13. A thermally conductive layer 131 is formed, for example, by an electroplating operation. The thermally conductive layer 131 fills the groove 52. The thermally conductive layer 131 can be a thermally conductive material, such as a metal.

[0048] refer to Figure 5I The seed layer 53 on the back side 13b of the semiconductor device 13 is removed by an etching operation.

[0049] refer to Figure 5J Semiconductor device 11 is aligned with semiconductor device 13. Semiconductor device 11 is bonded to semiconductor device 13 via wafer-to-wafer bonding operation. The back surface 11b of semiconductor device 11 is in direct contact with the back surface 13b of semiconductor device 13. Thermal conductive layer 111 is in direct contact with thermal conductive layer 131.

[0050] refer to Figure 5K A groove 59 is formed on the active surface 11a of the semiconductor device 11 to expose the thermally conductive layer 112. In some embodiments, a groove 58 may be formed to expose the electrical contacts of the semiconductor device 11.

[0051] refer to Figure 5L Conductive pillars are formed or disposed in the grooves 58 and 59, for example, by electroplating. The conductive pillars in the groove 59 form part of the heat-conducting layer 112, and the conductive pillars in the groove 58 (i.e., conductive pillars 113) are electrically connected to the semiconductor device 11. Thus, a semiconductor heat dissipation structure 1 is formed.

[0052] Figures 6A to 6G Some embodiments of a method for manufacturing a semiconductor package structure 2 according to some embodiments of the present disclosure are shown. The various figures have been simplified to present aspects of the present disclosure more clearly.

[0053] refer to Figure 6A A method for manufacturing a semiconductor package structure 2 includes providing a carrier 60. A semiconductor heat dissipation structure 1 is placed on the carrier 60.

[0054] refer to Figure 6B An encapsulating material 26 is formed on the carrier 60. The semiconductor heat dissipation structure 1 is encapsulated by the encapsulating material 26. Then, the carrier 60 is removed.

[0055] refer to Figure 6C The encapsulant 26 is ground to expose the upper surface of the conductive pillar 113 and the upper surface of the thermally conductive layer 112. Then, interconnecting elements 21 are formed in the encapsulant 26, penetrating the encapsulant 26.

[0056] refer to Figure 6D An RDL 24 is mounted on the semiconductor heat dissipation structure 1. The RDL 24 includes a thermal connection element 241. The thermal connection element 241 extends through the RDL 24 and contacts the thermally conductive layer 112. The thermal connection element 241 may contain Cu, Au, or other suitable materials. Then, a carrier 60 is mounted on the RDL 24.

[0057] refer to Figure 6EAn RDL 22, opposite to RDL 24, is disposed on the semiconductor heat dissipation structure 1. In some embodiments, an electrical connection element 23 is disposed on the RDL 22. The electrical connection element 23 may be a solder ball.

[0058] refer to Figure 6F Remove the carrier 60. Then, place the electrical connection element 23 on RDL 24.

[0059] refer to Figure 6G A semiconductor device 25 is mounted on RDL 24 and electrically connected to RDL 24 via an electrical connection element 23. A thermal connection element 281 is mounted on RDL 24 and connected to thermal connection element 241. Thermal connection element 281 may be made of metal or alloy or any suitable thermally conductive material and may have any suitable shape. In some embodiments, thermal connection element 281 is a metal cap.

[0060] A heat dissipation device 28 is mounted on RDL 24. In some embodiments, the heat dissipation device 28 is mounted on a thermal connection element 281. The thermal connection element 281 is aligned with and electrically connected to the thermal connection element 241. Thermal paste 27 can be applied to the upper surface (i.e., the back surface) of the semiconductor device 25. The thermal paste 27 can be disposed between the semiconductor device 25 and the heat dissipation device 28. Thus, a semiconductor package structure 2 is formed.

[0061] Figures 7A to 7G Some embodiments of a method for manufacturing a semiconductor heat dissipation structure 1' according to some embodiments of the present disclosure are shown. Figures 7A to 7G Operation and Figures 5A to 5J The operation is similar. The various figures have been simplified to present the aspects of this disclosure more clearly.

[0062] refer to Figure 7A A method for manufacturing a semiconductor heat dissipation structure 1' includes providing a semiconductor device 11, the semiconductor device 11 including an active surface 11a and a back surface 11b opposite to the active surface 11a. Photoresist 51 is provided on the back surface 11b of the semiconductor device 11. Openings in the photoresist 51 are formed by a photolithography operation. Subsequently, an etching operation is performed to form grooves 52.

[0063] refer to Figure 7B A photoresist 51 is further provided on the back surface 11b of the semiconductor device 11. An opening is formed by a photolithography operation. Subsequently, an etching operation is performed to form a groove 54. The depth of the groove 54 is greater than the depth of the groove 52.

[0064] refer to Figure 7C A seed layer 53 is formed on the back side 11b of the semiconductor device 11 and in the grooves 52 and 54.

[0065] refer to Figure 7D A semiconductor device 13 is provided. The semiconductor device 13 includes an active surface 13a and a back surface 13b opposite to the active surface 13a. Photoresist 51 is provided on the back surface 13b of the semiconductor device 13. Openings in the photoresist 51 are formed by a photolithography operation. Subsequently, an etching operation is performed to form a groove 52.

[0066] refer to Figure 7E A seed layer 53 is formed on the back side 13b of the semiconductor device 13 and in the groove 52.

[0067] refer to Figure 7F The seed layer 53 on the back surface 11b of the semiconductor device 11 is removed by etching to form thermally conductive layers 111' and 112'. Additionally, the seed layer 53 on the back surface 13b of the semiconductor device 13 is removed by etching to form thermally conductive layer 131'. The semiconductor device 11 and semiconductor device 13 are then aligned.

[0068] refer to Figure 7G Semiconductor device 11 is bonded to semiconductor device 13 via wafer-to-wafer bonding operations. The back surface 11b of semiconductor device 11 is in direct contact with the back surface 13b of semiconductor device 13. Thermal conductive layer 111' is in direct contact with thermal conductive layer 131. Thus, a semiconductor heat dissipation structure 1' is formed.

[0069] Figures 8A to 8J Some embodiments of a method for manufacturing a semiconductor package structure 2' according to some embodiments of the present disclosure are shown. The various figures have been simplified to present aspects of the present disclosure more clearly.

[0070] refer to Figure 8A A method for manufacturing a semiconductor package structure 2' includes providing a carrier 60. A semiconductor heat dissipation structure 1' is disposed on the carrier 60. Conductive pillars 113 are formed on a semiconductor device 11 and electrically connected to the semiconductor device.

[0071] refer to Figure 8B An encapsulating material 26 is formed on the carrier 60. The semiconductor heat dissipation structure 1' is completely encapsulated by the encapsulating material 26. Subsequently, the carrier 60 is removed.

[0072] refer to Figure 8C The encapsulant 26 is ground to expose the upper surface of the conductive pillars 113. Then, interconnecting elements 21 are formed in the encapsulant 26, penetrating the encapsulant 26.

[0073] refer to Figure 8DAn RDL 24 is disposed on the semiconductor heat dissipation structure 1. An opening O1 is formed to expose the traces or electrical contacts of the RDL 24. An opening O2 is formed to expose the recess 54 and the seed layer disposed in the recess 54. The opening O2 may be formed in multiple steps (e.g., by a first step of forming an opening through the encapsulant 26 before forming the RDL 24, and a second step of forming an opening through the RDL 24), or integrally formed in a single step (i.e., by forming an opening through the RDL 24 and the encapsulant 26).

[0074] refer to Figure 8E On RDL 24, a seed layer 53 is formed in opening O1 and opening O2. The seed layer 53 is formed in opening 62 of RDL 24.

[0075] refer to Figure 8F The seed layer 53 on the surface of RDL 24 is removed, and a conductive via is formed in the opening O1. A hollow thermal connection element 241' is formed in the opening O2 of RDL 24. The hollow thermal connection element 241' is in direct contact with the thermally conductive layer 112'. A thermally conductive element 243 can be formed and left on the periphery of the opening O2. The thermally conductive element 243 is connected to the hollow thermal connection element 241' and can be used to fasten the hollow thermal connection element 281', which will be discussed below.

[0076] refer to Figure 8G Carrier 60 is placed on RDL 24.

[0077] refer to Figure 8H An RDL 22, opposite to RDL 24, is disposed on the semiconductor heat dissipation structure 1'. In some embodiments, an electrical connection element 23 is disposed on the RDL 22. The electrical connection element 23 may be a solder ball.

[0078] refer to Figure 8I Remove the carrier 60. Then, install the electrical connection element 23 on RDL 24. In some embodiments, a cooling liquid (such as water, ethanol), refrigerant, or coolant can be added from the opening O2.

[0079] refer to Figure 8JA semiconductor device 25 is mounted on RDL 24 and electrically connected to RDL 24 via an electrical connection element 23. A hollow thermal connection element 281' is mounted on RDL 24 and connected to a hollow thermal connection element 241'. The hollow thermal connection element 281' can be made of metal or alloy or any suitable thermally conductive material and can have any suitable shape. The hollow thermal connection element 281' can be in direct contact with the thermally conductive element 243 (e.g., with the upper surface or side of the thermally conductive element 243). Fibers 282' are formed in the inner surface of the hollow thermal connection element 281'.

[0080] A heat dissipation device 28' is mounted on RDL 24. In some embodiments, the heat dissipation device 28' is mounted on a hollow thermal connector element 281'. The hollow thermal connector element 281' is aligned with and electrically connected to the hollow thermal connector element 241'. Thermal paste 27 can be applied to the upper surface (i.e., the back surface) of the semiconductor device 25. The thermal paste 27 can be disposed between the semiconductor device 25 and the heat dissipation device 28'. Thus, a semiconductor package structure 2 is formed.

[0081] As used herein, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “front,” “back,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” and “below” are used to specify the orientation of a component or group of components or a plane of a component or group of components with respect to the orientation of said one or more components, as shown in the associated figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that such arrangement does not depart from the advantages of the embodiments of this disclosure.

[0082] As used herein and unless otherwise defined, the terms “substantially,” “basically,” “approximately,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may cover instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. For example, when used in conjunction with a numerical value, the terms may cover variations less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may refer to two surfaces whose positional difference along the same plane is within a few micrometers, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.

[0083] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may include plural referents. In the description of some embodiments, the description of another component disposed “on” or “above” a component can cover the case where the preceding component is directly located on (e.g., in physical contact with) the following component, as well as the case where one or more intermediate components are positioned between the preceding and following components.

[0084] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limiting unless expressly indicated herein.

Claims

1. A semiconductor heat dissipation structure, comprising: A first semiconductor device, the first semiconductor device comprising a first active surface and a first back surface opposite to the first active surface; A second semiconductor device, the second semiconductor device comprising a second active surface and a second back surface opposite to the second active surface; A first thermally conductive layer is embedded in the first back surface of the first semiconductor device; A second thermally conductive layer is embedded in the second back side of the second semiconductor device; as well as A third thermally conductive layer is disposed adjacent to the first thermally conductive layer and extends perpendicularly to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other, and the first thermal conductive layer is aligned with the second thermal conductive layer, with at least a portion of the first thermal conductive layer in contact with the second thermal conductive layer.

2. The semiconductor heat dissipation structure according to claim 1, wherein the third thermal conductive layer penetrates the first semiconductor device, a first portion of the third thermal conductive layer contacts a first distal end of the first thermal conductive layer, and a second portion of the third thermal conductive layer contacts a second distal end of the first thermal conductive layer.

3. The semiconductor heat dissipation structure according to claim 1, wherein the third thermal conductive layer is connected to a heat dissipation device outside the semiconductor heat dissipation structure, the surface of the first thermal conductive layer is substantially coplanar with the first back surface of the first semiconductor device, and the surface of the second thermal conductive layer is substantially coplanar with the second back surface of the second semiconductor device.

4. The semiconductor heat dissipation structure according to claim 3, wherein the first back surface of the first semiconductor device includes a first groove, the second back surface of the second semiconductor device includes a second groove, the first thermally conductive layer is formed in the first groove, and the second thermally conductive layer is formed in the second groove, and wherein the semiconductor heat dissipation structure further includes a first alignment mark and a second alignment mark, wherein the first thermally conductive layer and the second thermally conductive layer are aligned by the first alignment mark and the second alignment mark.

5. The semiconductor heat dissipation structure according to claim 4, wherein the first groove is filled by the first thermally conductive layer, and the second groove is filled by the second thermally conductive layer, and wherein the shape of the first alignment mark is different from the shape of the second alignment mark.

6. The semiconductor heat dissipation structure according to claim 4, wherein the first thermally conductive layer and the second thermally conductive layer together form a hollow thermally conductive tube, the hollow thermally conductive tube having a closed tubular channel for cooling liquid or cooling gas, such that the cooling liquid or the cooling gas circulates in the hollow thermally conductive tube.

7. The semiconductor heat dissipation structure according to claim 1, wherein, according to the top view, the first thermal conductive layer, the second thermal conductive layer, or both have a serpentine shape, thereby increasing the contact surface area between the first thermal conductive layer and the second thermal conductive layer and the first back surface of the first semiconductor device and the second back surface of the second semiconductor device, the contact surface area occupying 20% ​​to 50% of the first back surface or the second back surface.

8. The semiconductor heat dissipation structure according to claim 7, wherein the first thermally conductive layer and the third thermally conductive layer are formed integrally.

9. The semiconductor heat dissipation structure according to claim 1, wherein the third thermally conductive layer is disposed outside the first semiconductor device and adjacent to the side of the second semiconductor device.

10. The semiconductor heat dissipation structure according to claim 6, wherein the first thermally conductive layer, the second thermally conductive layer and the third thermally conductive layer together form the hollow heat pipe.

11. A semiconductor package structure comprising: The semiconductor heat dissipation structure according to claim 1; A first redistribution layer RDL is disposed on the first active surface of the first semiconductor device and includes a thermal connection element extending through the first RDL; as well as A heat dissipation device is mounted on the first RDL. The third thermally conductive layer of the semiconductor heat dissipation structure is connected to the heat dissipation device via the thermal connection element of the first RDL.

12. The semiconductor package structure of claim 11, wherein the first semiconductor device includes a conductive pillar, and the conductive pillar electrically connects the first semiconductor device to the first RDL.

13. The semiconductor packaging structure of claim 11, further comprising a third semiconductor device disposed on the first RDL.

14. The semiconductor packaging structure of claim 13, wherein the third semiconductor device is disposed below the heat dissipation device.

15. The semiconductor package structure of claim 11, further comprising a second redistribution layer RDL disposed below the semiconductor heat dissipation structure.

16. The semiconductor packaging structure according to claim 15, further comprising an encapsulating material encapsulating the semiconductor heat dissipation structure.

17. The semiconductor package structure of claim 16, further comprising interconnect elements extending through the encapsulant and electrically connected to the first RDL and the second RDL.

18. A method for manufacturing a semiconductor package structure, the method comprising: A first semiconductor device is provided, the first semiconductor device comprising a first active surface and a first back surface opposite to the first active surface; A second semiconductor device is provided, the second semiconductor device comprising a second active surface and a second back surface opposite to the second active surface; A first thermally conductive layer is formed, and the first thermally conductive layer is embedded in the first back surface of the first semiconductor device; A third thermally conductive layer is formed, the third thermally conductive layer being adjacent to the first thermally conductive layer and extending to the first active surface of the first semiconductor device; A second thermally conductive layer is formed, and the second thermally conductive layer is embedded in the second back side of the second semiconductor device; Align the first thermally conductive layer with the second thermally conductive layer; The first back side of the first semiconductor device is bonded to the second back side of the second semiconductor device to form a semiconductor heat dissipation structure; Encapsulate the semiconductor heat dissipation structure; as well as Connect the heat dissipation device to the third heat-conducting layer.

19. The method of claim 18, wherein the heat dissipation device is disposed on the semiconductor heat dissipation structure, wherein the first thermally conductive layer and the second thermally conductive layer are aligned by a first alignment mark and a second alignment mark on the first semiconductor device and the second semiconductor device, respectively.

20. The method of claim 18, wherein the first thermally conductive layer and the third thermally conductive layer are formed by the following steps: A groove is formed on the first back surface of the first semiconductor device; A via is formed within the first semiconductor device, wherein the via is connected to the recess; and A metal layer is applied to the groove and the through hole to form the first thermally conductive layer and the third thermally conductive layer. The surface of the first thermally conductive layer is substantially coplanar with the first back surface of the first semiconductor device, and the surface of the second thermally conductive layer is substantially coplanar with the second back surface of the second semiconductor device.

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