semiconductor packages

Abstract

A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member located on the redistribution substrate, a second redistribution layer located on the first molding member and having redistribution pads, an electrical connection pad located on an upper surface of the second molding member and electrically connected to the second redistribution layer, and a passivation layer located on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer including a first metal and a contact layer located on the conductor layer and including a second metal. The redistribution pad includes a third metal different from the first and second metals. The width of the portion of the electrical connection pad exposed by the opening is greater than the width of the redistribution pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0168552 filed on December 17, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to semiconductor packages, and more particularly, to semiconductor packages including a redistribution layer for making electrical connections. Background Art

[0004] Although semiconductor devices may be required to process large amounts of data, their size has gradually decreased. Therefore, in a package-on-package (POP) structure including semiconductor chips coupled to each other, the number of electrical connection pads provided on the back side of the lower package and the number of back-side interconnects electrically connecting the electrical connection pads to the first redistribution layer (RDL) have increased. However, since the electrical connection pads are required to have an area of ​​a standard size, it may be difficult to reduce the area to a predetermined size or smaller, and there may be technical limitations in reducing the width and space of the back-side interconnects. Summary of the Invention

[0005] Example embodiments provide a semiconductor package having improved integration density and reliability by using a second redistribution layer.

[0006] According to example embodiments, a semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip located on the redistribution substrate and electrically connected to the first redistribution layer; a first molding member located on the redistribution substrate and the semiconductor chip; a second redistribution layer located on the first molding member and having redistribution pads; a vertical connection structure located between the redistribution substrate and the second redistribution layer and electrically connecting the first and second redistribution layers to each other; a second molding member located on the first molding member and on at least a portion of the second redistribution layer; an electrical connection pad located on an uppermost surface of the second molding member and electrically connected to the second redistribution layer; and a passivation layer located on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer including a first metal and a contact layer located on the conductor layer and including a second metal. The redistribution pad includes a third metal different from the first and second metals. The portion of the electrical connection pad exposed by the opening has a width greater than a width of the redistribution pad.

[0007] According to example embodiments, a semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip located on the redistribution substrate; a first molding member located on the redistribution substrate and the semiconductor chip; a second redistribution layer located on the first molding member and including a redistribution pad; a vertical connection structure located on the redistribution substrate and electrically connecting the first and second redistribution layers to each other; a second molding member located on the first molding member and covering at least a portion of the second redistribution layer; and an electrical connection structure located on the second molding member and electrically connected to the redistribution pad. The electrical connection structure includes a conductor layer including nickel (Ni) and a contact layer located on an upper surface of the conductor layer and including gold (Au). The redistribution pad includes copper (Cu).

[0008] According to example embodiments, a semiconductor package includes: a redistribution substrate including a first redistribution layer; a semiconductor chip located on the redistribution substrate and electrically connected to the first redistribution layer; a first molding member located on the redistribution substrate and the semiconductor chip; a plurality of vertical connection structures embedded in the first molding member and electrically connected to the first redistribution layer; and a second molding member including a base molding layer and a buildup molding layer, the base molding layer being located on an upper surface of the first molding member. On the surface, the buildup mold layer is located on the upper surface of the base mold layer; a second redistribution layer, the second redistribution layer is located on the upper surface of the base mold layer and includes a plurality of redistribution pads and a plurality of redistribution patterns that electrically connect the plurality of redistribution pads and the plurality of vertical connection structures to each other; and a plurality of electrical connection structures, each of the electrical connection structures is located on the second molding member and has a pad portion and a via portion, the pad portion protruding from the upper surface of the buildup mold layer, and the via portion passes through the buildup mold layer and is in physical contact with at least one of the plurality of redistribution pads. The plurality of electrical connection structures include a conductor layer containing nickel (Ni) and a contact layer located on the upper surface of the conductor layer and containing gold (Au). The plurality of redistribution pads include a first back redistribution pad and a second back redistribution pad adjacent to each other. The plurality of electrical connection structures include a first back electrical connection structure and a second back electrical connection structure corresponding to the first back redistribution pad and the second back redistribution pad, respectively. The plurality of redistribution patterns extend between the first back side redistribution pad and the second back side redistribution pad, and in a cross-sectional view of the semiconductor package with the redistribution substrate used as a base reference plane, one or more of the plurality of redistribution patterns vertically overlap with at least one of the first back side electrical connection structure and the second back side electrical connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 are cross-sectional views of semiconductor packages according to some example embodiments of the inventive concepts.

[0011] Figure 2 is shown with Figure 1 Schematic top view of components corresponding to area “A” in a semiconductor package.

[0012] Figure 3 are cross-sectional views of semiconductor packages according to other example embodiments of the inventive concepts.

[0013] Figures 4A to 6B It shows Figure 3 Schematic top views of various examples of components in a semiconductor package.

[0014] Figure 7 are cross-sectional views of semiconductor packages according to other example embodiments of the inventive concepts.

[0015] Figure 8 is shown with Figure 7 Schematic top view of components corresponding to area “B” in a semiconductor package.

[0016] Figure 9 are cross-sectional views of semiconductor packages according to other example embodiments of the inventive concepts.

[0017] Figure 10 is shown with Figure 9 Schematic top view of components corresponding to area “C” in a semiconductor package.

[0018] Figure 11A and Figure 11B are schematic cross-sectional views illustrating elements of a semiconductor package according to some embodiments of the inventive concept.

[0019] Figure 12 are cross-sectional views of semiconductor packages according to other example embodiments of the inventive concepts.

[0020] Figure 13 are cross-sectional views of semiconductor packages according to other example embodiments of the inventive concepts.

[0021] Figure 14 are cross-sectional views of package-on-package structures according to some example embodiments of the inventive concepts.

[0022] Figure 15 are cross-sectional views of package-on-package structures according to other example embodiments of the inventive concept.

[0023] Figure 16 are cross-sectional views of package-on-package structures according to other example embodiments of the inventive concept. DETAILED DESCRIPTION

[0024] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same elements, and their repeated description will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be understood that when an element is referred to as being "on" another element, "attached" to another element, "connected" to another element, "coupled" to another element, "contacting" another element, etc., it can be directly on another element, directly attached to another element, directly connected to another element, directly coupled to another element, or directly contacting another element, or there can also be an intermediate element. In contrast, when an element is referred to as being "directly" on another element, "directly attached" to another element, "directly connected" to another element, "directly" "coupled" to another element, "directly contacting" another element, then there is no intermediate element. It should be noted that the various aspects described for one embodiment can be incorporated into different embodiments, although not specifically described. That is, the features of all embodiments and / or any embodiment can be combined in any way and / or combination.

[0025] Figure 1 is a cross-sectional view of a semiconductor package 100A according to some example embodiments of the present inventive concepts, and Figure 2 is shown with Figure 1 Schematic top view of components corresponding to area “A” in the semiconductor package 100A. Figure 2 Shows the Figure 1 The semiconductor package 100A is a component corresponding to the area “A”.

[0026] Reference Figure 1 and Figure 2 The semiconductor package 100A may include a vertical connection structure 110, a semiconductor chip 120, a first molding member 130a, a second molding member 130b, a second redistribution layer 132 having a redistribution pad 132P, a redistribution substrate 140 having a first redistribution layer 142, an electrical connection structure 185 having an electrical connection pad 182 and an electrical connection path 183, and a second passivation layer 181 located on a portion of the electrical connection structure 185 and at least partially covering the portion.

[0027] In example embodiments, the semiconductor package 100A may further include a first passivation layer 150 disposed on the redistribution substrate 140 to protect the first redistribution layer 142 , an under bump metal 160 penetrating the first passivation layer 150 , and a connection bump 170 connected to the under bump metal 160 .

[0028] The vertical connection structure 110 may be disposed on a surface of the redistribution substrate 140 (eg, Figure 1 The conductive pillars are provided on the upper surface of the redistribution substrate in the semiconductor chip 120 and pass through at least a portion of the first molding member 130a to electrically connect the first redistribution layer 142 and the second redistribution layer 132 to each other. The vertical connection structure 110 may include a plurality of vertical connection structures 110 arranged around the semiconductor chip 120. The vertical connection structure 110 may form an electrical path that penetrates the first molding member 130a. The conductive pillars may include a conductive material. The conductive pillars may be completely filled with a conductive material and may have, for example, a cylindrical shape or a polygonal cylindrical shape. The shape of the conductive pillars is not necessarily limited; therefore, the conductive pillars may have various shapes. Figure 1 In the embodiment, the vertical connection structure 110 is connected to the second redistribution layer 132 through the backside via 133. Figure 1 Unlike the example shown, when the upper surface of the vertical connection structure 110 is disposed coplanar with the upper surface of the first molding member 130a by a planarization process such as a chemical mechanical polishing (CMP) process, the vertical connection structure 110 may be directly connected to the second redistribution layer 132 (see FIG. Figure 12 ).

[0029] The semiconductor chip 120 may have an active surface on which the connection electrode 120P is provided and a passive surface opposite to the active surface. The semiconductor chip 120 may be a logic chip or a memory chip. For example, the semiconductor chip 120 may include: a system large-scale integrated circuit (LSI), a logic circuit, a CMOS image sensor (CIS), a memory device such as DRAM, SRAM, flash memory, PRAM, ReRAM, FeRAM, MRAM, high-bandwidth memory (HBM), a hybrid memory cube (HMC), a micro-electromechanical system (MEMS) device, etc.

[0030] Additional connection members may be provided between the connection electrodes 120P and the first redistribution layer 142. The connection members may include solder balls or copper pillars. For example, the semiconductor chip 120 may be mounted on the redistribution substrate 140 in a flip-chip bonding manner. In such an embodiment, an underfill resin may be formed between the semiconductor chip 120 and the redistribution substrate 140 to surround and / or at least partially surround the connection members.

[0031] The first molding member 130a may be provided on the redistribution substrate 140 and may be located on the semiconductor chip 120 and at least partially cover the semiconductor chip 120. The first molding member 130a may include an insulating material, and the insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler in a thermosetting resin or a thermoplastic resin, specifically, Ajinomoto build-up film (ABF), FR-4 resin, bismaleimide triazine (BT) resin, etc. In addition, the insulating material may be an epoxy molding compound (EMC), a photoimageable encapsulant (PIE), etc.

[0032] The second molding member 130b may be an insulating layer disposed on the back side of the semiconductor package 100A (i.e., a side close to the surface (inactive surface) on which the connection electrodes 120P of the semiconductor chip 120 are not disposed). The second molding member 130b may be located on a portion of the second redistribution layer 132 and at least partially cover the portion. The second molding member 130b may include an insulating material, and the insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler in a thermosetting resin or a thermoplastic resin. Specifically, it may be Ajinomoto build-up film (ABF), FR-4 resin, bismaleimide triazine (BT) resin, or the like. Alternatively, the insulating material may be an epoxy molding compound (EMC), a photoimageable encapsulant (PIE), or the like. The second molding member 130b may be formed of the same material as the first molding member 130a, or may be formed of a material different from that of the first molding member 130a. Figure 1 A boundary line separating the second molding member 130b and the first molding member 130a is shown in FIG, but the boundary therebetween may not be very distinct depending on a process used for manufacturing.

[0033] The second molding member 130b may include a base molding layer (lower molding layer) 130b disposed in physical contact with the upper surface of the first molding member 130a, and a buildup molding layer (upper molding layer) 130b disposed in physical contact with the upper surface of the base molding layer (lower molding layer) 130b. The second redistribution layer 132 may be disposed on the upper surface of the base molding layer (lower molding layer) 130b, and the buildup molding layer (upper molding layer) 130b may be located on the second redistribution layer 132 and at least partially cover the second redistribution layer 132.

[0034] The second redistribution layer 132 may include redistribution pads (or "backside redistribution pads") 132P disposed on the upper surface of the base mold layer (lower mold layer) 130b, and redistribution patterns (or "backside redistribution patterns") 132L that electrically connect the redistribution pads 132P to the vertical connection structures 110. The second redistribution layer 132 may include a plurality of redistribution pads 132P and a plurality of redistribution patterns 132L that connect the plurality of redistribution pads 132P to the plurality of vertical connection structures 110. The second redistribution layer 132 may be disposed on the first molding member 130a to provide circuitry on the backside of the semiconductor package 100A. The second redistribution layer 132 may include a conductive material. For example, the conductive material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second redistribution layer 132 may perform various functions depending on its design. For example, the second redistribution layer 132 may have a ground (GND) pattern, a power (PWR) pattern, and / or a signal (S) pattern. The second redistribution layer 132 may be formed by a plating process and may include a seed layer and a conductor layer.

[0035] The redistribution pad 132P may be a portion directly connected to the electrical connection structure 185 and may have a circular pad having a diameter greater than the width of the redistribution pattern 132L. However, in other embodiments of the present inventive concept, the shape of the redistribution pad 132P is not necessarily limited to these examples.

[0036] The redistribution pattern 132L may be a circuit pattern formed to extend on the first molding member 130a and connected at one end to the redistribution pad 132P and at the other end to the vertical connection structure 110. The redistribution pattern 132L may extend from one side of the redistribution pad 132P along the upper surface of the base mold layer (lower mold layer 130b) and may be electrically connected to the vertical connection structure 110 through a backside via 133 penetrating the base mold layer (lower mold layer) 130b.

[0037] The redistribution substrate 140 may include an insulating layer 141, a first redistribution layer 142 disposed on the insulating layer 141, and redistribution vias 143 that pass through the insulating layer 141 and electrically connect the first redistribution layer 142 and the under-bump metallurgy 160 or the vertical connection structure 110. The redistribution substrate 140 may redistribute the connection electrodes 120P of the semiconductor chip 120 and may physically and / or electrically connect the connection electrodes 120P to an external entity through the connection bumps 170. The number of insulating layers 141, first redistribution layers 142, and redistribution vias 143 may be more or less than those shown in the figure.

[0038] Insulating layer 141 may include an insulating material. For example, a photoimageable dielectric (PID) may be used as the insulating material. In such an embodiment, fine pitch can be achieved through optical path. The boundaries between insulating layers 141 may be distinct or not distinct.

[0039] The first redistribution layer 142 can redistribute the connection pads 120P of the semiconductor chip 120 to electrically connect the vertical connection structure 110 and the connection bump 170 to each other. The first redistribution layer 142 can be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The redistribution layer 142 can perform various functions according to its design. For example, the first redistribution layer 142 can have a ground (GND) pattern, a power (PWR) pattern and / or a signal (S) pattern, etc. The ground (GND) pattern and the power (PWR) pattern can be the same. In addition, the first redistribution layer 142 may include redistribution path pads and connection bump pads. The first redistribution layer 142 can be formed by a plating process and may include a seed layer and a conductor layer.

[0040] The redistribution path 143 can electrically connect the first redistribution layers 142 formed on different layers to each other, and can also connect the connection electrodes 120P of the semiconductor chip 120 and the vertical connection structure 110 to the first redistribution layer 142. When the semiconductor chip 120 is a bare chip, the redistribution path 143 can be in physical contact with the connection electrode 120P. The redistribution path 143 is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The redistribution path 143 can have a path for signals, a path for power supply, a path for grounding, etc., and the path for power supply and the path for grounding can be the same. The redistribution path 143 can be a field type path filled with a metal material, or can be a conformal path in which a metal material is formed along the wall surface of the through hole. The redistribution path 143 can be formed by a plating process and can include a seed layer and a conductor layer.

[0041] The electrical connection structures 185 (or backside electrical connection structures) may include electrical connection pads 182 disposed on the upper surface of the second molding member 130b and electrically connected to the second redistribution layer 132, and electrical connection vias 183 formed below the electrical connection pads 182 and passing through the second molding member 130b to connect the electrical connection pads 182 and the redistribution pads 132P to each other. Tens to tens of thousands of electrical connection structures 185 may be provided. A plurality of vertical connection structures 110 may be spaced apart from the side surfaces of the semiconductor chip 120 on the redistribution substrate 140 to surround and / or enclose the semiconductor chip 120. The electrical connection structures 185 may be disposed in an area surrounded and / or enclosed by the plurality of vertical connection structures 110. In such an embodiment, the plurality of backside electrical connection structures 185 may not be disposed in the central portion of the area surrounded and / or enclosed by the plurality of vertical connection structures 110.

[0042] The electrical connection pads 182 and the electrical connection paths 183 may be integrated with each other and, in some embodiments, may comprise a monolithic structure. Thus, the electrical connection structure 185 may be disposed on the second molding member 130b and may include an electrical connection pad (also referred to herein as a pad portion) 182 protruding from the upper surface of the second molding member 130b and an electrical connection path (also referred to herein as a path portion) 183 disposed through the second molding member 130b and in physical contact with the redistribution pads 132P. The width D2 of the electrical connection pads 182 of the electrical connection structure 185 may be greater than the width D1 of the redistribution pads 132P.

[0043] The electrical connection structure 185 includes seed layers 182a and 183a formed along the surface of the second molding member 130b and the surface of the redistribution pads 132P, conductor layers 182b and 183b formed on the seed layers 182a and 183a, and a contact layer 182c formed on the conductor layers 182b and 183b. The conductor layers 182b and 183b may include a body layer 182b extending horizontally along the upper surface of the second molding member 130b and a via body layer 183b extending through the second molding member 130b toward the redistribution pads 132P. The seed layers 182a and 183a may include copper (Cu) and may be formed by electroless plating. The conductor layers 182b and 183b may include nickel (Ni) and may be formed by electroplating. The contact layer 182c may include gold (Au) and may be formed by electroplating. Seed layers 182a and 183a, conductor layers 182b and 183b, and contact layer 182c may have a thickness of approximately 0.8 μm, a thickness of approximately 5 μm, and a thickness of approximately 0.5 μm, respectively. In electrical connection structure 185, the Ni / Au layer formed on the surface of the Cu pad for soldering (the pad included in the second redistribution layer) as a barrier layer and a diffusion barrier layer may be separated into additional conductive structures to reduce the size of the Cu pad and increase the integration density of the Cu pattern on the back side of the package.

[0044] The second passivation layer 181 may have an opening 181h provided on the second molding member 130b to expose at least a portion of the electrical connection pad 182. The width D3 of the electrical connection pad 182 exposed through the second passivation layer 181 may meet a predetermined standard. The width D3 of the exposed surface of the electrical connection pad 182 exposed through the opening 181h of the second passivation layer 181 may be greater than the width D1 of the redistribution pad 132P. The second passivation layer 181 is configured to protect the electrical connection structure 185 from physical and chemical damage. The second passivation layer 181 may include a thermosetting resin. For example, the second passivation layer 189 may be ABF, but the embodiment is not limited thereto. Tens to tens of thousands of openings 181h may be provided.

[0045] In a typical POP, the back connection pads for the POP, which can be formed on the back side of the lower package, can be designed to have a predetermined size. A surface treatment layer (Ni / Au) for bonding with solder is formed on the surface of the back connection pads for the POP. In this case, when the number of back connection pads for the POP increases, the space for forming the back interconnection line is limited, and there may be technical limitations in reducing the width of the back interconnection line. Therefore, it may be difficult to implement multiple back connection pads for POP bonding of high-performance semiconductor chips.

[0046] In contrast, the semiconductor package 100A according to some example embodiments may include a backside electrical connection structure 185 for bonding to solder. The backside electrical connection structure 185 includes conductor layers 182b and 183b including nickel (Ni) and a contact layer 182c provided on the upper surfaces of the conductor layers 182b and 183b and including gold (Au). Figure 1 In the cross-sectional view of FIG, the second redistribution layer 132 or the redistribution pad 132P including copper (Cu) may be provided below the backside electrical connection structure 185. The width D2 of the electrical connection pad 182 of the backside electrical connection structure 185 may be greater than the width D1 of the redistribution pad 132P. Therefore, the redistribution pattern 132L electrically connected to the redistribution pad 132P may be formed more densely without causing space limitation due to an increase in the number of backside electrical connection structures 185 for POP bonding to which solder is bonded.

[0047] For example, the redistribution pads 132P may include a first backside redistribution pad 132P-1 and a second backside redistribution pad 132P-2 disposed adjacent to each other. The electrical connection pads 182 may include a first electrical connection pad 182-1 and a second electrical connection pad 182-2, the first electrical connection pad 182-1 being disposed above the first backside redistribution pad 132P-1, and the second electrical connection pad 182-2 being disposed above the second backside redistribution pad 132P-2. Figure 2 As shown in a top view of the semiconductor package 100A. The redistribution pattern 132L may include a redistribution pattern 132L that passes between the first backside redistribution pad 132P-1 and the second backside redistribution pad 132P-2 to connect the vertical connection structure 110 and the other redistribution pads 132P to each other. In the cross-sectional view of the semiconductor package 100A, one or more of the multiple redistribution patterns may vertically overlap with at least one of the first electrical connection pad 182-1 and the second electrical connection pad 182-2. The distance W1 between the first electrical connection pad 182-1 and the second electrical connection pad 182-2 may be less than the distance W2 between the first backside redistribution pad 132P-1 and the second backside redistribution pad 132P-2.

[0048] The first passivation layer 150 is configured to protect the redistribution substrate 140 from physical and chemical damage. The first passivation layer 150 may include a thermosetting resin. For example, the first passivation layer 150 may be ABF, but embodiments are not limited thereto. The first passivation layer 150 may have an opening formed to expose at least a portion of the lowermost first redistribution layer 142 among the first redistribution layers 142. Tens to tens of thousands of openings may be provided, or tens to thousands or more openings may be provided, or tens to thousands or fewer openings may be provided. Each opening may have a plurality of holes.

[0049] The under bump metal 160 can improve the connection reliability of the connection bump 170 and can improve the board-level reliability of the semiconductor package 100A. Tens or tens of thousands of under bump metals 160 can be provided, or tens to thousands or more under bump metals 160 can be provided, or tens to thousands or fewer under bump metals 160 can be provided. Each under bump metal 160 can be formed in an opening of the first passivation layer 150 to electrically connect to the exposed lowermost first redistribution layer 142. The under bump metal 160 can be formed by a metallization method using a metal, but embodiments of the method of forming the under bump metal 160 are not limited thereto.

[0050] The connection bumps 170 are configured to physically and / or electrically connect the semiconductor package 100A to an external entity. For example, the semiconductor package 100A can be mounted on a mainboard of an electronic device via the connection bumps 170. The connection bumps 170 can be disposed on the first passivation layer 150 and can be electrically connected to the under-bump metal 160, respectively. The connection bumps 170 can be formed of a metal having a low melting point (e.g., tin (Sn) or an alloy including tin (Sn)). The connection bumps 170 can include solder, but according to various embodiments of the present invention, their materials are not necessarily limited.

[0051] The connection bump 170 can be embodied as a land, a ball, a pin, etc. The connection bump 170 can be formed to have a multi-layer structure or a single-layer structure. When the connection bump 170 is formed to have a multi-layer structure, the connection bump 170 may include a copper column and a solder. When the connection bump 170 is formed to have a single-layer structure, the connection bump 170 may include a tin-silver solder or copper. However, its exemplary embodiments are not limited thereto. The number, spacing, arrangement form, etc. of the connection bump 170 are not necessarily limited, but can be fully modified by those skilled in the art based on the design details according to various embodiments of the present invention.

[0052] At least one connection bump 170 may be provided in a fan-out region. The fan-out region may refer to an area outside the region where the semiconductor chip 120 is provided. Compared to a fan-in package, a fan-out package may have improved reliability, may allow for implementation of multiple input / output (I / O) terminals, and may facilitate 3D interconnection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, and the like, a fan-out package may be manufactured to have a relatively small thickness and is economically advantageous.

[0053] Figure 3 is a cross-sectional view of a semiconductor package 100B according to other example embodiments of the present inventive concepts, and Figures 4A to 6B It shows Figure 3Schematic top views of various examples of components in a semiconductor package.

[0054] Reference Figure 3 and Figures 4A to 6B The semiconductor package 100B may have a first hole 182H1 and / or a second hole 182H2 that penetrates the electrical connection pad 182 of the backside electrical connection structure 185. The first hole 182H1 and the second hole 182H2 may be formed by patterning during a plating process of the electrical connection pad 182 or by removing a portion of the electrical connection pad 182.

[0055] Figure 4A and Figure 4B Electrical connection pads 182A and 182B are shown with first holes 182H1, each of which has an example configuration. The first holes 182H1 may be formed in the outer regions of the electrical connection pads 182A and 182B. The outer regions are covered with a second passivation layer 181. The first holes 182H1 penetrate at least one of the contact layer 182c, the conductor layer 182b, and the seed layer 182a that constitute the electrical connection pads 182. For example, the first holes 182H1 may extend through the contact layer 182c and the conductor layer 182b, in which case the first holes may also be referred to as first grooves. When viewed from above (i.e., a top view), each first hole 182H1 may have a hollow shape ( Figure 4A ), or may have a shape in which one side of the inner wall may be open ( Figure 4B ). The first hole 182H1 may be at least partially filled with the second passivation layer 181. Therefore, adhesion and bonding of the second passivation layer 181 may be improved, and reliability of the package may be enhanced.

[0056] Figure 5An electrical connection pad 182C is shown having second holes 182H2, each of which has an exemplary configuration. Second holes 182H2 may be formed in the inner region of electrical connection pad 182C. The inner region is the area not covered by second passivation layer 181 and exposed, and is the inner region of opening 181h. Second holes 182H2 may penetrate at least one of contact layer 182c, conductor layer 182b, and seed layer 182a that constitute electrical connection pad 182. For example, second holes 182H2 may extend through contact layer 182c and conductor layer 182b, in which case the second holes may also be referred to as second recesses. For example, second holes 182H2 may penetrate all of contact layer 182c, conductor layer 182b, and seed layer 182a to expose a portion of second molding member 130b. In such an embodiment, second holes 182H2 may serve as vents to increase the adhesive strength of second molding member 130b. When viewed from above (i.e., in a top view), second hole 182H2 may have a hollow shape with a continuously connected inner wall, or at least a portion of the hollow portion may be continuously connected. During POP bonding, second hole 182H2 may be at least partially filled with solder to improve solder bonding and enhance package reliability.

[0057] Figure 6A and Figure 6B The electrical connection pads 182D and 182F are shown with a first hole 182H1 and a second hole 182H2, each of which has an example configuration. The first hole 182H1 may be at least partially covered by the second passivation layer 181, and the second hole 182H2 may be exposed from the second passivation layer 181. When viewed from above (i.e., a top view), the second hole 182H2 may be formed at a position that does not overlap with the electrical connection path 183.

[0058] Figure 3 and Figures 4A to 6B The other elements shown are similar to Figure 1 , and therefore a detailed description thereof will be omitted.

[0059] Figure 7 is a cross-sectional view of a semiconductor package 100C according to other example embodiments of the present inventive concepts, and Figure 8 is shown with Figure 7 Schematic top view of components corresponding to area “B” in a semiconductor package. Figure 8 Shows the Figure 7 The semiconductor package 100C is a portion corresponding to the region “B”.

[0060] Reference Figure 7 and Figure 8, electrical connection pads 182 can be provided on the upper surface of the second molding member 130b and can further include electrical connection patterns 182L extending from the electrical connection pads 182P. The electrical connection patterns 182L can be connected to the redistribution pads 132P via electrical connection vias 183 penetrating the second molding member 130b. Thus, the electrical connection pads 182P can be provided offset from the redistribution pads 132P. Because the electrical connection patterns 182L can be used to extend and select the arrangement area of ​​the electrical connection pads 182P, design freedom can be increased, and a greater number of electrical connection pads 182P can be formed.

[0061] An electrical connection pattern 182L may be provided on the second molding member 130b to provide a circuit on the back side of the semiconductor package 100C. The electrical connection pattern 182L may include a conductive material. For example, the conductive material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The electrical connection pattern 182L may perform various functions depending on its design. For example, the electrical connection pattern 182L may include a ground (GND) pattern, a power (PWR) pattern, and / or a signal (S) pattern. The electrical connection pattern 182L may be formed by a plating process and may include a seed layer and a conductor layer. The electrical connection pattern 182L may be a circuit pattern that extends along the upper surface of the second molding member 130b and has one end connected to the electrical connection pad 182P and the other end connected to the electrical connection path 183 that penetrates the second molding member 130b. The electrical connection pattern 182L may extend from the upper surface of the second molding member 130b in a horizontal direction, as shown in FIG. Figure 7 and Figure 8 and when viewed from above (i.e., Figure 8 When viewed in a top view (e.g., FIG. 2 ), the electrical connection pattern 182L may be bent along first and second directions different from each other.

[0062] The electrical connection pad 182P has a portion exposed by the opening 181h of the second passivation layer 181 and provides a connection portion of the upper package of the POP structure. The electrical connection pad 182P may be a circular pad having a diameter greater than the line width of the electrical connection pattern 182L. However, according to various embodiments of the present inventive concept, the shape of the electrical connection pad 182P is not necessarily limited to Figure 8 The shape shown.

[0063] exist Figure 7 and Figure 8 Among the components shown, Figure 1 The same reference numerals as shown in FIG. Figure 1 The illustrated elements are similar, so their description will be omitted.

[0064] Figure 9 is a cross-sectional view of a semiconductor package 100D according to other example embodiments of the present inventive concepts, and Figure 10 is shown with Figure 9 Schematic top view of components corresponding to area “C” in a semiconductor package. Figure 10 Shows the Figure 9 The semiconductor package 100D is a portion corresponding to the region “C”.

[0065] Reference Figure 9 and Figure 10 The semiconductor package 100D may include a bypass wiring layer 184 disposed at the same level as the electrical connection pads 182 and electrically connecting the plurality of second redistribution layers 132 spaced apart from each other. The bypass wiring layer 184 may be physically spaced apart from the electrical connection pads 182. Unlike the electrical connection pads 182 having portions exposed by the openings 181h, in some embodiments, the bypass wiring layer 184 may be completely covered by the second passivation layer 181. The density issue of the second redistribution layers 132 may be addressed using the bypass wiring layer 184.

[0066] exist Figure 9 In the cross-sectional view of FIG, the bypass wiring layer 184 may overlap with the plurality of redistribution patterns 132L, and when viewed from above (ie, Figure 10 When viewed from above (a top view of the semiconductor package 100D), the bypass wiring layer 184 may extend across multiple redistribution pads 132P. The bypass wiring layer 184 may be provided on the second molding member 130b to provide a circuit on the back side of the semiconductor package 100D. The bypass wiring layer 184 may include a conductive material. For example, the conductive material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The bypass wiring layer 184 may perform various functions depending on its design. For example, the bypass wiring layer 184 may have a ground (GND) pattern, a power supply (PWR) pattern, and / or a signal (S) pattern. The bypass wiring layer 184 may be formed by a plating process and may include a seed layer and a conductor layer.

[0067] exist Figure 9 and Figure 10 Among the components shown, Figure 1 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1 The illustrated elements are similar, so their description will be omitted.

[0068] Figure 11A and Figure 11B is a schematic cross-sectional view showing elements of a semiconductor package. Figure 11A and Figure 11BA schematic configuration of an electrical connection structure 185 according to some example embodiments of the inventive concepts is shown.

[0069] Reference Figure 11A and Figure 11B , the electrical connection structure 185 may include seed layers 182 a and 183 a , a conductor layer CL, and a contact layer 182 c .

[0070] exist Figure 11A In the embodiment, the conductor layer CL may include body layers 182b-1 and 182b-2 and via body layers 183b-1 and 183b-2. The body layers 182b-1 and 182b-2 extend horizontally on the second molding member 130b, and the via body layers 183b-1 and 183b-2 extend toward the redistribution pads 132P. The conductor layer CL may include lower metal layers 182b-1 and 183b-1 and upper metal layers 182b-2 and 183b-2, each comprising different metal materials. For example, the lower metal layers 182b-1 and 183b-1 may comprise copper, while the upper metal layers 182b-2 and 183b-2 may comprise nickel. The conductor layer CL may be formed by electroplating. The lower metal layers 182b-1 and 183b-1 and the upper metal layers 182b-2 and 183b-2 may each have a thickness of approximately 5 μm.

[0071] exist Figure 11B , seed layers 182a and 183a may be continuously formed along the lower surface of the conductor layer CL. The seed layer 183a may include a lower seed layer 183a-1 and an upper seed layer 183a-2, which may include different metal materials from each other. For example, the lower seed layer 183a-1 may include titanium (Ti) or a titanium-tungsten (Ti-W) alloy, and the upper seed layer 183a-2 may include copper. The seed layer 183a may be formed by chemical plating or sputtering. The lower seed layer 183a-1 may have a thickness of approximately 0.1 μm, and the upper seed layer 183a-2 may have a thickness of approximately 0.3 μm.

[0072] Contact layer 182c may be formed on the upper surface of conductor layer CL. Contact layer 182c may include a metal material different from the metal material of conductor layer CL and seed layers 182a and 183a. For example, contact layer 182c may include gold (Au) and may be formed by electroplating. During POP bonding, contact layer 182c may be in direct physical contact with solder. Contact layer 182c may have a thickness of approximately 0.5 μm.

[0073] exist Figure 11A and Figure 11B Among the components shown, Figure 1 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1 The illustrated elements are similar, so their description will be omitted.

[0074] Figure 12 is a cross-sectional view of a semiconductor package 100E according to other example embodiments of the inventive concepts.

[0075] Reference Figure 12 In the semiconductor package 100E, the second redistribution layer 132 may be directly disposed on the upper surface of the first molding member 130a, and the vertical connection structure 110 exposed from the upper surface of the first molding member 130a may be directly connected to the second redistribution layer 132. The upper surface of the vertical connection structure 110 may be disposed on the second surface S2, and the second molding member 130b may be disposed on the upper surface of the first molding member 130a. The first surface S1, the upper surface of the semiconductor chip 120, and the second surface S2 may be spaced apart from each other. Figure 12 Unlike what is shown, in other example embodiments, the first surface S1 and the second surface S2 may be provided on the same surface.

[0076] The above-described structure according to some embodiments of the present inventive concept can be achieved by molding the vertical connection structure 110 and the semiconductor chip 120 using the first molding member 130a and removing the upper surface of the first molding member 130a using a polishing process to expose the upper surface of the vertical connection structure 110. During the polishing process, the upper surface of the semiconductor chip 120 can even be exposed to allow the first surface S1 and the second surface S2 to be coplanar with each other. In such an embodiment, a portion of the semiconductor chip 120 can be removed. As a result, the connection distance between the first redistribution layer 142 and the second redistribution layer 132 can be significantly reduced, thereby improving the electrical characteristics of the semiconductor package 100E.

[0077] exist Figure 12 Among the components shown, Figure 1 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1 The illustrated elements are similar, so their description will be omitted.

[0078] Figure 13 is a cross-sectional view of a semiconductor package 100F according to other example embodiments of the inventive concepts.

[0079] Reference Figure 13In the semiconductor package 100F, the vertical connection structure 110 may include a first insulating layer 111a disposed in physical contact with the redistribution substrate 140, a first wiring layer 112a disposed in physical contact with the redistribution substrate 140 and embedded in the first insulating layer 111a, a second wiring layer 112b disposed on a side of the first insulating layer 111a opposite to the side in which the first wiring layer 112a is embedded, a second insulating layer 111b disposed on the first insulating layer 111a and at least partially covering the second wiring layer 112b, and a third wiring layer 112c disposed on a side of the second insulating layer 111b opposite to the side in which the second wiring layer 112b is embedded. The first wiring layer 112a and the second wiring layer 112b may be electrically connected to each other via a first wiring via 113a penetrating the first insulating layer 111a, and the second wiring layer 112b and the third wiring layer 112c may be electrically connected to each other via a second wiring via 113b penetrating the second insulating layer 111b. In addition, the first to third wiring layers 112 a , 112 b , and 112 c may be electrically connected to the first redistribution layer 142 of the redistribution substrate 140 .

[0080] The vertical connection structure 110 can further improve the rigidity of the semiconductor package 100F based on the specific material of the insulating layers 111a and 111b, and can ensure the uniformity of the thickness of the first molding member 130a. The vertical connection structure 110 can have a through hole 110H that penetrates the insulating layers 111a and 111b. The semiconductor chip 120 can be disposed in the through hole 110H. The through hole 110H can have a shape in which the wall surface surrounds and / or surrounds the semiconductor chip 120, but the shape of the through hole 110H is not limited thereto according to various embodiments of the present inventive concept.

[0081] According to various embodiments of the present inventive concept, the material of the insulating layers 111a and 111b is not necessarily limited. For example, the material of the insulating layers 111a and 111b may be an insulating material. In this case, the insulating material may be a thermosetting resin such as an epoxy resin and / or a thermoplastic resin such as an Ajinomoto built-up film (ABF). In other embodiments, the insulating material may be an insulating material in which an inorganic filler and a core material (e.g., glass fiber (or glass cloth or glass fabric)) are impregnated in a thermosetting resin or a thermoplastic resin, such as a prepreg.

[0082] The wiring layers 112a, 112b, and 112c can provide upper / lower electrical connection paths for the package together with the wiring paths 113a and 113b, and can be used to redistribute the connection electrodes 120P. The wiring layers 112a, 112b, and 112c include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers 112a, 112b, and 112c can have a ground (GND) pattern, a power (PWR) pattern, and / or a signal (S) pattern depending on the design of the corresponding layer. The wiring layers 112a, 112b, and 112c can include various signals other than the ground (GND) pattern, the power (PWR) pattern, etc., such as data signals. The ground (GND) pattern and the power (PWR) pattern can be the same. In addition, the wiring layers 112a, 112b, and 112c can each include various types of via pads. The wiring layers 112 a , 112 b , and 112 c may be formed by a known plating process, and may each include a seed layer and a conductor layer.

[0083] The wiring paths 113a and 113b can electrically connect the wiring layers 112a, 112b, and 112c formed on different layers to each other. As a result, an electrical path can be formed in the vertical connection structure 110. The wiring paths 113a and 113b may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The wiring paths 113a and 113b may each have a path for a signal, a path for a power supply, and / or a path for grounding, and the path for the power supply and the path for grounding may be the same. The wiring paths 113a and 113b may each be a field-type path at least partially filled with a metal material, or may be a conformal path in which a metal material is formed along the wall surface of the through-hole. The wiring paths 113a and 113b may be formed by a plating process and may include a seed layer and a conductor layer.

[0084] exist Figure 13 Among the components shown, Figure 1 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1 The illustrated elements are similar, so their description will be omitted.

[0085] Figure 14 is a cross-sectional view of a package-on-package structure 300A according to other example embodiments of the inventive concepts.

[0086] Reference Figure 14 , the package-on-package structure 300A may include Figure 1The second package 200 is combined with the semiconductor package 100A. The second package 200 may include a second redistribution substrate 210, a second semiconductor chip 220, and an encapsulant 230.

[0087] The second redistribution substrate 210 may include redistribution pads 211 and 212 disposed on its upper and lower surfaces, respectively. Each of the redistribution pads 211 and 212 may be electrically connected to an external entity. Furthermore, the second redistribution substrate 210 may have a redistribution pattern disposed therein, the redistribution pattern being configured to connect to the redistribution pads 211 and 212. The redistribution pattern may redistribute the second connection electrodes 220P of the second semiconductor chip 220 to the fan-out region.

[0088] The second semiconductor chip 220 may include a second connection electrode 220P, and the second connection electrode 220P may be electrically connected to the second redistribution substrate 210 through a metal bump 222. As an example, the second package 200 may further include an underfill material 223 surrounding and / or surrounding the metal bump 222. The underfill material 223 may be an insulating material including epoxy resin, etc. The metal bump 222 may include a solder ball or a copper pillar.

[0089] In other example embodiments, the second connection electrodes 220P of the second semiconductor chip 220 may be in direct physical contact with the upper surface of the second redistribution substrate 210 and may be electrically connected to the redistribution pattern through vias in the second redistribution substrate 210 .

[0090] The encapsulant 230 may include a material that is the same as or similar to that of the first and second molding members 130 a and 130 b of the semiconductor package 100A.

[0091] The second package 200 can be physically / electrically connected to the semiconductor package 100A through the second connection bumps 240. The second connection bumps 240 can be electrically connected to the redistribution pattern in the second redistribution substrate 210 through the redistribution pads 211 on the lower surface of the second redistribution substrate 210. In other embodiments, the redistribution patterns can be electrically connected to each other through the under-bump metals on the redistribution pads 211 provided on the lower surface of the second redistribution substrate 210. Each second connection bump 240 can be formed of a metal having a relatively low melting point, for example, tin (Sn) or an alloy including tin (Sn). More specifically, each second connection bump 240 can be formed of solder (solder) or the like. However, according to various example embodiments of the present inventive concept, the material thereof is not necessarily limited thereto.

[0092] exist Figure 14 Among the components shown, Figure 1 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1The illustrated elements are similar, so their description will be omitted.

[0093] Figure 15 is a cross-sectional view of a package-on-package structure 300B according to other example embodiments of the inventive concepts.

[0094] Reference Figure 15 ,and Figure 14 Unlike the package-on-package structure 300A, the package-on-package structure 300B includes a redistribution substrate 140, on which the first semiconductor chip 120 of the semiconductor package 100A' can be mounted in a flip-chip manner. The first semiconductor chip 120 can be electrically connected to the redistribution layer 142 of the redistribution substrate 140 via metal bumps 122. An underfill material 123 can be disposed under the first semiconductor chip 120 to surround and / or enclose the metal bumps 122. The underfill material 123 can be an insulating material including epoxy resin, etc. The metal bumps 122 can include solder balls or copper pillars.

[0095] exist Figure 15 Among the components shown, Figure 1 and Figure 14 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1 and Figure 14 The illustrated elements are similar, so their description will be omitted.

[0096] Figure 16 is a cross-sectional view of a package-on-package structure 300C according to other example embodiments of the inventive concepts.

[0097] Reference Figure 16 , the package-on-package structure 300C may include Figure 13 The semiconductor package 100F is combined with the second package 200. Figure 16 Among the components shown, Figure 1 and Figure 14 The same reference numerals in FIG. 1 indicate elements corresponding to those in FIG. Figure 1 and Figure 14 The illustrated elements are similar, so their description will be omitted.

[0098] As described above, the electrical connection pads and the second redistribution layer may be separated from each other to provide a semiconductor package having an improved integration density of the second redistribution layer and improved reliability.

[0099] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a redistribution substrate, the redistribution substrate comprising a first redistribution layer; a semiconductor chip located on the redistribution substrate and electrically connected to the first redistribution layer; a first molding member on the redistribution substrate and directly on the semiconductor chip; a second redistribution layer located on the first molding member and having a redistribution pad; a vertical connection structure located between the redistribution substrate and the second redistribution layer and electrically connecting the first redistribution layer and the second redistribution layer to each other; a second molding member on the first molding member and on at least a portion of the second redistribution layer; an electrical connection pad located on an uppermost surface of the second molding member and electrically connected to the second redistribution layer; as well as a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad, The electrical connection pad includes: a conductor layer containing a first metal and a contact layer located on the conductor layer and containing a second metal. wherein the redistribution pad includes a third metal different from the first metal and the second metal, wherein the width of the portion of the electrical connection pad exposed by the opening is greater than the width of the redistribution pad, and Wherein, the vertical connection structure extends through the first molding member.

2. The semiconductor package according to claim 1, wherein The second molding member includes a base molding layer and a buildup molding layer, the base molding layer is located on an upper surface of the first molding member, and the buildup molding layer is located on an upper surface of the base molding layer. wherein the redistribution pad of the second redistribution layer is located on the upper surface of the base molding layer, and the buildup molding layer is located on a portion of the redistribution pad, wherein the electrical connection pad is located on the upper surface of the buildup molding layer, wherein the second redistribution layer extends from one side of the redistribution pad along the upper surface of the base mold layer and has a redistribution pattern electrically connected to the vertical connection structure through a backside via extending through the base mold layer, The redistribution pads include a first backside redistribution pad and a second backside redistribution pad adjacent to each other. wherein the electrical connection pads include: a first electrical connection pad located above the first backside redistribution pad and a second electrical connection pad located above the second backside redistribution pad in a cross-sectional view of the semiconductor package with the redistribution substrate serving as a base reference plane; wherein the redistribution pattern comprises a plurality of redistribution patterns extending between the first backside redistribution pad and the second backside redistribution pad, and Wherein, in the cross-sectional view of the semiconductor package, one or more redistribution patterns among the plurality of redistribution patterns vertically overlap with at least one of the first electrical connection pad and the second electrical connection pad.

3. The semiconductor package according to claim 2, wherein A distance between the first electrical connection pad and the second electrical connection pad is smaller than a distance between the first back side redistribution pad and the second back side redistribution pad.

4. The semiconductor package according to claim 1, wherein The electrical connection pad has an outer region having a plurality of first grooves formed therein, the plurality of first grooves extending through the contact layer and the conductor layer, Wherein, the passivation layer is located on the outer area of ​​the electrical connection pad.

5. The semiconductor package according to claim 4, wherein The electrical connection pad has an inner region having a plurality of second grooves formed therein, the plurality of second grooves extending through the contact layer and the conductor layer, Wherein, the inner area of ​​the electrical connection pad is free of the passivation layer.

6. The semiconductor package according to claim 1, further comprising: an electrical connection pattern located on the uppermost surface of the second molding member and extending from the electrical connection pad, wherein the electrical connection pattern is connected to the redistribution pad through an electrical connection path extending through the second molding member, and Wherein, the electrical connection pad deviates from the redistribution pad.

7. The semiconductor package according to claim 1, wherein The second redistribution layer includes a plurality of second redistribution layers spaced apart from each other, wherein the bypass wiring layer is located at the same level as the electrical connection pads and electrically connects the plurality of second redistribution layers to each other, and Wherein, the bypass wiring layer is separated from the electrical connection pad.

8. The semiconductor package according to claim 7, wherein The passivation layer is located on an upper surface of the bypass wiring layer.

9. The semiconductor package according to claim 1, further comprising: an electrical connection via which is formed under the electrical connection pad in a cross-sectional view of the semiconductor package with the redistribution substrate serving as a base reference plane and which passes through the second molding member to electrically connect the electrical connection pad and the redistribution pad to each other, Wherein, in the cross-sectional view, the conductor layer includes a body layer extending in a vertical direction on the second molding member, and a via body layer passing through the second molding member and extending toward the redistribution pad.

10. The semiconductor package according to claim 9, wherein The conductor layer includes a lower metal layer including copper and an upper metal layer located on the lower metal layer and including nickel.

11. The semiconductor package according to claim 9, further comprising: A seed layer continuously extends along the lower surface of the conductor layer.

12. The semiconductor package according to claim 11, wherein The seed layer includes a lower seed layer including titanium and an upper seed layer located on the lower seed layer and including copper.

13. The semiconductor package according to claim 1, wherein The vertical connection structure includes: a first insulating layer in physical contact with the redistribution substrate, a first wiring layer in physical contact with the redistribution substrate and embedded in the first insulating layer, a second wiring layer located on a side of the first insulating layer opposite to a side of the first wiring layer in which the first wiring layer is embedded, a second insulating layer located on the first insulating layer and the second wiring layer, and a third wiring layer located on a side of the second insulating layer opposite to a side of the second wiring layer in which the second wiring layer is embedded, and The first wiring layer, the second wiring layer, and the third wiring layer are electrically connected to the first redistribution layer.

14. A semiconductor package, comprising: a redistribution substrate, the redistribution substrate comprising a first redistribution layer; a semiconductor chip, wherein the semiconductor chip is located on the redistribution substrate; a first molding member located on the redistribution substrate and the semiconductor chip; a second redistribution layer on the first molding member and including a redistribution pad; a vertical connection structure located on the redistribution substrate and electrically connecting the first redistribution layer and the second redistribution layer to each other; a second molding member directly on the first molding member and on at least a portion of the second redistribution layer such that the at least a portion of the second redistribution layer is between the second molding member and the redistribution substrate; as well as an electrical connection structure located on the second molding member and electrically connected to the redistribution pad, The electrical connection structure includes a conductor layer containing nickel and a contact layer located on the upper surface of the conductor layer and containing gold, and Wherein, the redistribution pad comprises copper.

15. The semiconductor package according to claim 14, wherein The electrical connection structure has a pad portion protruding from an uppermost surface of the second molding member and a via portion passing through the second molding member to physically contact the redistribution pad.

16. The semiconductor package according to claim 15, wherein A width of the pad portion of the electrical connection structure is greater than a width of the redistribution pad.

17. A semiconductor package, comprising: a redistribution substrate, the redistribution substrate comprising a first redistribution layer; a semiconductor chip located on the redistribution substrate and electrically connected to the first redistribution layer; a first molding member located on the redistribution substrate and directly on at least an upper surface of the semiconductor chip such that the semiconductor chip is located between the first molding member and the redistribution substrate; a plurality of vertical connection structures embedded in the first molding member and electrically connected to the first redistribution layer; a second molding member including a base molding layer and a buildup molding layer, the base molding layer being located on an upper surface of the first molding member and the buildup molding layer being located on an upper surface of the base molding layer; a second redistribution layer located on an upper surface of the base mold layer and including a plurality of redistribution pads and a plurality of redistribution patterns electrically connecting the plurality of redistribution pads and the plurality of vertical connection structures to each other; as well as a plurality of electrical connection structures, each of the electrical connection structures being located on the second molding member and having a pad portion and a via portion, the pad portion protruding from an upper surface of the buildup molding layer, the via portion passing through the buildup molding layer in physical contact with at least one redistribution pad of the plurality of redistribution pads, The plurality of electrical connection structures include a conductor layer comprising nickel and a contact layer located on an upper surface of the conductor layer and comprising gold. The plurality of redistribution pads include a first backside redistribution pad and a second backside redistribution pad adjacent to each other. wherein the plurality of electrical connection structures include a first back side electrical connection structure and a second back side electrical connection structure corresponding to the first back side redistribution pad and the second back side redistribution pad, respectively; and wherein the plurality of redistribution patterns extend between the first back side redistribution pad and the second back side redistribution pad, and in a cross-sectional view of the semiconductor package with the redistribution substrate used as a base reference plane, one or more of the plurality of redistribution patterns vertically overlap with at least one of the first back side electrical connection structure and the second back side electrical connection structure.

18. The semiconductor package according to claim 17, wherein The plurality of vertical connection structures surround the semiconductor chip on the redistribution substrate, and The plurality of electrical connection structures are located in a region surrounded by the plurality of vertical connection structures.

19. The semiconductor package according to claim 18, wherein The plurality of electrical connection structures are located outside a central portion of the area surrounded by the plurality of vertical connection structures.

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