Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device is disclosed, comprising: a stacked structure comprising a plurality of layers vertically stacked on a substrate, each layer comprising a semiconductor pattern, a gate electrode extending along a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern; a plurality of vertical insulators penetrating the stacked structure, the vertical insulators being arranged along the first direction; and a bit line disposed at one side of the stacked structure and extending vertically. The bit line electrically connects the stacked semiconductor patterns. Each of the vertical insulators comprises a first vertical insulator and a second vertical insulator adjacent to each other. The gate electrode comprises a connecting portion disposed between the first vertical insulator and the second vertical insulator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0168208 filed on December 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] Example embodiments of the inventive concepts relate to a semiconductor device and / or a method for manufacturing the same, and more particularly, to a three-dimensional (3D) semiconductor memory device having improved electrical characteristics and / or a method for manufacturing the same.

[0004] Semiconductor devices have been highly integrated to provide improved / excellent performance and / or low manufacturing costs. The integration density of semiconductor devices, for example, directly affects the cost of semiconductor devices, resulting in a demand for highly integrated semiconductor devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be mainly determined by the area occupied by a unit memory cell. Therefore, the integration density of a typical 2D semiconductor device may be greatly affected by the technology for forming fine patterns. However, due to the use / requirement of extremely high-priced devices to form fine patterns, the integration density of 2D semiconductor devices continues to increase but remains limited. Therefore, three-dimensional (3D) semiconductor memory devices have been developed to overcome the above limitations. A 3D semiconductor memory device may include memory cells arranged in three dimensions. Summary of the Invention

[0005] Some example embodiments of the inventive concepts may provide a three-dimensional (3D) semiconductor memory device having improved electrical characteristics and reliability.

[0006] Some example embodiments of the inventive concepts may also provide a method for manufacturing / fabricating a 3D semiconductor memory device having improved electrical characteristics and reliability.

[0007] According to some example embodiments, a semiconductor memory device may include a stacked structure including a plurality of layers stacked vertically on a substrate, wherein each of the plurality of layers includes a semiconductor pattern, a gate electrode extending along a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern. The semiconductor memory device includes: a plurality of vertical insulators penetrating the stacked structure, at least one of the plurality of vertical insulators being arranged along the first direction; and a bit line extending vertically on one side of the stacked structure. The bit line is electrically connected to the semiconductor pattern. Each of the vertical insulators includes a first vertical insulator and a second vertical insulator adjacent to the first vertical insulator. The gate electrode includes a connecting portion between the first vertical insulator and the second vertical insulator.

[0008] According to some example embodiments, a semiconductor memory device may include a stacked structure comprising a plurality of layers stacked vertically on a substrate, wherein each of the plurality of layers comprises a semiconductor pattern, a gate electrode extending along a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern. The semiconductor memory device includes: a vertical insulator penetrating the stacked structure, the vertical insulator extending along a second direction intersecting the first direction; and a bit line extending vertically on one side of the stacked structure. The semiconductor pattern includes a first semiconductor sub-pattern and a second semiconductor sub-pattern spaced apart from each other along the first direction, wherein the vertical insulator is interposed between the first semiconductor sub-pattern and the second semiconductor sub-pattern. The vertical insulator includes a first vertical insulator and a second vertical insulator adjacent to the first vertical insulator. The gate electrode includes a connecting portion between the first vertical insulator and the second vertical insulator. The gate electrode on the first semiconductor pattern is connected to the gate electrode on the second semiconductor pattern through the connecting portion.

[0009] According to some example embodiments, a semiconductor memory device may include: a bit line extending along a first direction on a substrate, the first direction being perpendicular to a top surface of the substrate; a semiconductor pattern extending from the bit line along a second direction, the second direction being parallel to the top surface of the substrate, the semiconductor pattern having a first surface and a second surface opposite to each other along the first direction; a first gate electrode and a second gate electrode respectively on the first surface and the second surface of the semiconductor pattern, the first gate electrode and the second gate electrode extending along a third direction, the first gate electrode and the second gate electrode being parallel to each other, the third direction being parallel to the top surface of the substrate and intersecting the second direction; and a data storage element electrically connected to the semiconductor pattern.

[0010] According to some example embodiments, a method for manufacturing a semiconductor memory device may include: forming a stack structure, the stack structure including a plurality of layers vertically stacked on a substrate, wherein each of the plurality of layers includes a first insulating layer, a semiconductor layer, and a second insulating layer, the first insulating layer and the second insulating layer being stacked sequentially; forming a first hole and a second hole, the first hole and the second hole penetrating the stack structure, partially etching the semiconductor layer exposed through the first hole and the second hole to divide each of the semiconductor layers into a pair of semiconductor patterns; forming a vertical insulator, filling the first hole and the second hole, replacing a portion of each of the second insulating layers with a gate electrode; forming a bit line on one side of the stack structure, the bit line extending vertically, replacing a portion of each of the semiconductor patterns with the first electrode, and replacing a remaining portion of each of the second insulating layers with the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The inventive concept will become more apparent in view of the accompanying drawings and the following detailed description.

[0012] Figure 1is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some example embodiments of the inventive concept.

[0013] Figures 2 to 6 are perspective views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts.

[0014] Figure 7 are plan views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts.

[0015] Figure 8A 、 8B and 8C are respectively along Figure 7 Cross-sectional views taken along lines AA′, BB′ and CC′.

[0016] Figure 9 、 11 , 13 , 15 , 17 , and 19 are plan views illustrating methods for fabricating a 3D semiconductor memory device according to some example embodiments of the inventive concept.

[0017] Figure 10 、 12 , 14A, 16A, 18A and 20A are respectively along Figure 9 、 11 , 13, 15, 17 and 19 are cross-sectional views taken along line AA′.

[0018] Figure 14B 、 16B , 18B and 20B are respectively along Figure 13 、 15 , 17 and 19 are cross-sectional views taken along line BB′.

[0019] Figure 21 It is along Figure 7 8 is a cross-sectional view taken along line BB′ to illustrate a 3D semiconductor memory device according to some example embodiments of the inventive concept.

[0020] Figure 22 and Figure 23 It is along Figure 7 1 is a cross-sectional view taken along line AA′ to illustrate a 3D semiconductor memory device according to some example embodiments of the inventive concept.

[0021] Figure 24 are plan views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts.

[0022] Figure 25A and Figure 25B are along Figure 24 A cross-sectional view taken along lines BB' and DD'.

[0023] Figure 26 are plan views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts.

[0024] Figure 27A 、 27B and 27C are respectively along Figure 26 Cross-sectional views taken along lines AA', BB' and DD'.

[0025] Figure 28 、 30 , 32 and 34 are plan views illustrating methods for fabricating a 3D semiconductor memory device according to some example embodiments of the inventive concept.

[0026] Figure 29 、 31 , 33A and 35A are respectively along Figure 28 、 30 , 32 and 34 are cross-sectional views taken along line AA′.

[0027] Figure 33B and Figure 35B are along Figure 32 and Figure 34 A cross-sectional view taken along line BB′. DETAILED DESCRIPTION

[0028] When an element is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element, the element may be directly on, directly connected to, coupled to, or adjacent to the other element, or one or more other intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element, there are no intervening elements present.

[0029] Figure 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some example embodiments of the inventive concept.

[0030] refer to Figure 1 , a cell array CA of a 3D semiconductor memory device according to some example embodiments of the inventive concepts may include a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged along a second direction D2.

[0031] Each of the subcell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One of the memory cell transistors MCT may be disposed between one of the word lines WL and one of the bit lines BL. The memory cell transistor MCT may be an N-type metal oxide semiconductor field effect transistor (MOSFET); however, example embodiments are not limited thereto.

[0032] The bit lines BL may be or include conductive patterns (e.g., metal lines) extending from the substrate in a vertical direction (i.e., a third direction D3). The bit lines BL in each of the subcell arrays SCA may be arranged along a first direction D1. The bit lines BL in each of the subcell arrays SCA may be spaced apart from each other along the first direction D1.

[0033] The word lines WL may be or include conductive patterns (e.g., metal lines and / or polysilicon lines) stacked on the substrate along the third direction D3. Each of the word lines WL may extend along the first direction D1. The word lines WL in each of the subcell arrays SCA may be spaced apart from each other along the third direction D3.

[0034] The gate of the memory cell transistor MCT may be connected to the word line WL, and the first source / drain of the memory cell transistor MCT may be connected to the bit line BL. The second source / drain of the memory cell transistor MCT may be connected to the data storage element DS. For example, the data storage element DS may be a capacitor. The second source / drain of the memory cell transistor MCT may be connected to the first electrode of the capacitor. Other passive components may be present between the second source / drain of the memory cell transistor MCT and the data storage element DS; however, example embodiments are not limited thereto.

[0035] Figures 2 to 6 are perspective views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts.

[0036] refer to Figures 1 to 2 The peripheral circuit region PER may be disposed on the substrate SUB. The substrate SUB may be or include a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The peripheral circuit region PER may include peripheral transistors disposed on the substrate SUB. The peripheral circuit region PER may include circuits for operating a memory cell array (or cell array) according to some example embodiments of the present inventive concepts. For example, the peripheral circuit region PER may include an address decoder circuit. The peripheral circuit region PER may include, for example, planar transistors formed within the substrate SUB.

[0037] refer to Figure 1One of the plurality of subcell arrays SCA may be disposed, for example, above or on the peripheral circuit region PER. For example, a stacked structure SS including first to third layers L1, L2, and L3 may be disposed on the peripheral circuit region PER. The first to third layers L1, L2, and L3 of the stacked structure SS may be stacked in a vertical direction (i.e., a third direction D3) and may be spaced apart from each other in the vertical direction (i.e., the third direction D3). Each of the first to third layers L1, L2, and L3 may include a plurality of semiconductor patterns SP, a plurality of data storage elements DS, and a gate electrode GE. Although Figure 2 Three layers L1 , L2 , L3 are shown, but example embodiments are not limited thereto and there may be more or fewer layers in the stack structure SS.

[0038] Each of the semiconductor patterns SP may have a line shape or a bar shape extending along the second direction D2. The semiconductor pattern SP may include a semiconductor material such as silicon, germanium, and / or silicon germanium. For example, the semiconductor pattern SP may include polycrystalline silicon and / or single crystal silicon.

[0039] Each of the semiconductor patterns SP may include a channel region CH, a first dopant region SD1, and a second dopant region SD2. The channel region CH may be disposed between the first dopant region SD1 and the second dopant region SD2. The channel region CH may be aligned with the reference Figure 1 The first dopant region SD1 and the second dopant region SD2 may correspond to the channel of the memory cell transistor MCT. Figure 1 The first source / drain and the second source / drain of the memory cell transistor MCT correspond to each other.

[0040] The first and second dopant regions SD1 and SD2 may be regions of the semiconductor pattern SP doped with dopants such as boron, phosphorus, and / or arsenic. Thus, the first and second dopant regions SD1 and SD2 may have N-type or P-type conductivity. The first and second dopant regions SD1 and SD2 may include other dopants, such as carbon; however, example embodiments are not limited thereto. The first dopant region SD1 may be formed adjacent to a first end of the semiconductor pattern SP, and the second dopant region SD2 may be formed adjacent to a second end of the semiconductor pattern SP. The second end may be opposite the first end along a second direction D2.

[0041] The data storage elements DS may be connected to (e.g., directly connected to) the second end of the semiconductor pattern SP, respectively, or to a passive element between the second end of the semiconductor pattern SP and the second end of the semiconductor pattern SP. The data storage elements DS may be connected to or directly connected to the second dopant region D2 of the semiconductor pattern SP, respectively. The data storage elements DS may be memory elements capable of storing data. Each of the data storage elements DS may be or include or correspond to a memory element using a capacitor, a memory element using a magnetic tunnel junction (MTJ) pattern, or a memory element using a variable resistor including a phase change material. For example, each of the data storage elements DS may be or include a capacitor, and may be connected to Figure 1 The capacitors shown correspond to the

[0042] Each of the gate electrodes GE may have a line shape or a bar shape extending along the first direction D1. The gate electrodes GE may be stacked along the third direction D3 and may be spaced apart from each other along the third direction D3. Each of the gate electrodes GE may intersect the semiconductor pattern SP in each of the layers L1, L2, and L3 and may extend along the first direction D1. In other words / for example, the gate electrode GE may be a reference Figure 1 The horizontal word line WL.

[0043] The gate electrode GE may include a conductive material. For example, the conductive material may include at least one of a doped semiconductor material (e.g., doped silicon or doped germanium, such as doped polysilicon), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, and / or titanium silicide).

[0044] A plurality of bit lines BL extending in a vertical direction (e.g., a third direction D3) may be provided on the substrate SUB. Each of the bit lines BL may have a line shape or a pillar shape extending in the third direction D3. The bit lines BL may be arranged in the first direction D1. Each of the bit lines BL may be electrically connected to the first dopant region SD1 of the vertically stacked semiconductor pattern SP.

[0045] The bit line BL may include a conductive material, and the conductive material may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. The bit line BL may be a reference Figure 1 The vertical bit line BL.

[0046] As a representative example, the first layer L1 among the first to third layers L1, L2, and L3 will be described in detail. The semiconductor patterns SP of the first layer L1 may be arranged along a first direction D1. The semiconductor patterns SP of the first layer L1 may be located at the same level. The gate electrode GE of the first layer L1 may intersect with the semiconductor patterns SP of the first layer L1 and may extend along the first direction D1. For example, the gate electrode GE of the first layer L1 may be disposed on the top surface of the semiconductor pattern SP (above the semiconductor pattern SP).

[0047] Even though not shown in the drawings, a gate insulating layer may be provided between the gate electrode GE and the channel region CH. The gate insulating layer may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. For example, the high-k dielectric layer may include at least one of hafnium oxide, hafnium-silicon oxide, lanthanum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, lithium oxide, aluminum oxide, lead-scandium-tantalum oxide, or lead zinc niobate.

[0048] The bit lines BL may be connected to (e.g., directly connected to) first ends of the semiconductor pattern SP of the first layer L1, respectively. In some example embodiments, the bit lines BL may be directly connected to the first dopant region SD1. In some example embodiments, the bit lines BL may be electrically connected to the first dopant region SD1 via a metal silicide. For example, the metal silicide may correspond to a passive component between the first dopant region SD1 and the bit lines BL. The second layer L2 and the third layer L3 may be substantially the same as the first layer L1 described above.

[0049] Although not shown in the drawings, the hollow space in the stacked structure SS may be filled with an insulating material. For example, the insulating material may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. An interconnect layer electrically connected to the subcell array SCA may be provided on the stacked structure SS. The interconnect layer may be electrically connected to the peripheral circuit region PER via a through contact.

[0050] exist Figures 3 to 6 In the following example embodiments, for the purpose of ease and convenience of description, reference to Figure 1 and Figure 2 In other words, the following will mainly describe in detail Figures 3 to 6 Example embodiments of Figure 2 The differences between the example embodiments.

[0051] refer to Figure 1 and Figure 3The gate electrode GE may include a first gate electrode GE1 on the top surface of the semiconductor pattern SP (e.g., above the semiconductor pattern SP) and a second gate electrode GE2 on the bottom surface of the semiconductor pattern SP (e.g., below the semiconductor pattern SP). For example, the memory cell transistor according to some example embodiments may be a dual-gate transistor in which the gate electrodes GE are provided on both surfaces of the channel region CH.

[0052] refer to Figure 1 and Figure 4 The gate electrode GE may surround the channel region CH of the semiconductor pattern SP. The gate electrode GE may be disposed on the top surface, the bottom surface, and both sidewalls of the channel region CH. For example, the memory cell transistor according to some example embodiments may be a gate-all-around (GAA) transistor in which the gate electrode GE surrounds the channel region CH.

[0053] refer to Figure 1 and Figure 5 The gate electrode GE may penetrate the channel region CH of the semiconductor pattern SP and may extend in the first direction D1. The channel region CH may surround the gate electrode GE. For example, the memory cell transistor according to some example embodiments may be a surround channel (CAA) transistor in which the channel region CH surrounds the gate electrode GE.

[0054] refer to Figure 1 and Figure 6 The subcell array SCA may be disposed on or above (e.g., directly above) the substrate SUB. The peripheral circuit region PER may be disposed on or above (e.g., directly above) the subcell array SCA. As described above, the peripheral circuit region PER may include circuits for operating the subcell array SCA and may include planar transistors.

[0055] Figure 7 are plan views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts. Figure 8A 、 8B and 8C are respectively along Figure 7 In the example embodiment, for the purpose of ease and convenience of description, the cross-sectional view taken along the lines AA′, BB′ and CC′ will be omitted or briefly mentioned. Figure 1 and Figure 2 In other words, the following will mainly describe in detail the exemplary embodiment and the Figure 1 and Figure 2 The differences between the example embodiments.

[0056] refer to Figure 7 and Figures 8A to 8CThe stacked structure SS may be disposed on or above the substrate SUB. For example, the stacked structure SS may extend along the first direction D1 together with the gate electrode GE. Even though not shown in the drawings, a plurality of stacked structures SS may be provided, and the plurality of stacked structures SS may be arranged along the second direction D2.

[0057] refer to Figure 8A The stacked structure SS may include first to fourth layers L1 to L4 sequentially stacked on a substrate SUB. The stacked structure SS may include more than four layers. Example embodiments are not limited thereto. Each of the first to fourth layers L1 to L4 may include a first insulating layer IL1, a horizontal portion BLh of a bit line BL, a semiconductor pattern SP, and a gate electrode GE. Each of the first to fourth layers L1 to L4 may further include a data storage element DS electrically connected to the semiconductor pattern SP. As an example, the first to fourth layers L1 to L4 according to some example embodiments are shown. In certain example embodiments, additional layers may be repeatedly stacked on the fourth layer L4.

[0058] The horizontal portion BLh, the semiconductor pattern SP, and the gate electrode GE may be disposed on the first insulating layer IL1. The first insulating layer IL1 may vertically separate the upper horizontal portion BLh from the lower horizontal portion BLh. In other words / for example, the upper horizontal portion BLh may be separated from the lower horizontal portion BLh along the third direction D3 by the first insulating layer IL1. The first insulating layer IL1 may separate the upper gate electrode GE from the lower gate electrode GE along the third direction D3.

[0059] The gate electrode GE may include at least one of a doped semiconductor material (e.g., doped polysilicon), a conductive metal nitride, a metal, or a metal-semiconductor compound. The semiconductor pattern SP may include a semiconductor material, such as silicon, germanium, or silicon germanium. The first insulating layer IL1 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer.

[0060] The gate electrode GE of each of the first to fourth layers L1 to L4 may include a first gate electrode GE1 on the first surface SPa of the semiconductor pattern SP (e.g., above the semiconductor pattern SP) and a second gate electrode GE2 on the second surface SPb of the semiconductor pattern SP (e.g., below the semiconductor pattern SP). The second surface SPb may be opposite to the first surface SPa along the third direction D3. For example, the first surface SPa may be the top surface of the semiconductor pattern SP, and the second surface SPb may be the bottom surface of the semiconductor pattern SP.

[0061] The first gate electrode GE1 and the second gate electrode GE2 may be vertically spaced apart from each other, with the semiconductor pattern SP interposed therebetween. In other words / for example, the semiconductor pattern SP may be sandwiched between the first gate electrode GE1 and the second gate electrode GE2 disposed thereon and below, respectively. The first gate electrode GE1 and the second gate electrode GE2 may extend along the first direction D1 and may be parallel to each other. For example, the gate electrode GE of each of the first to fourth layers L1 to L4 may be parallel to the first gate electrode GE1 and the second gate electrode GE2. Figure 1 corresponds to one of the word lines WL.

[0062] The gate insulating layer GI may be disposed between the semiconductor pattern SP and the first and second gate electrodes GE1 and GE2. The gate insulating layer GI may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The gate insulating layer GI may surround the gate electrodes GE1 and GE2.

[0063] The memory cell transistor according to some example embodiments may have a dual-gate structure in which the first gate electrode GE1 and the second gate electrode GE2 are respectively disposed above and below the body (eg, semiconductor pattern SP) of the transistor. In other words / for example, the memory cell transistor according to some example embodiments may be the above reference Figure 3 Since the memory cell transistor according to some example embodiments has a dual-gate structure, channel controllability of the gate electrode GE may be improved.

[0064] refer to Figure 7 and Figure 8B , a plurality of vertical insulators VIP may be provided to penetrate the stacked structure SS. Each of the vertical insulators VIP may extend along the second direction D2. The vertical insulators VIP may be arranged along the first direction D1. The vertical insulators VIP may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer.

[0065] Each of the vertical insulators VIP may include a first vertical insulator VIP1, a second vertical insulator VIP2, and an extension portion EP. Each of the first vertical insulator VIP1 and the second vertical insulator VIP2 may penetrate the stacked structure SS. The extension portion EP may extend horizontally and may connect (e.g., directly connect) adjacent first and second vertical insulators VIP1 and VIP2. When viewed in a plan view, the first and second vertical insulators VIP1 and VIP2 may have a strip shape extending along the second direction D2. The first vertical insulator VIP1 may not be aligned with the second vertical insulator VIP2 along the second direction D2, but may be offset relative to the second vertical insulator VIP2 along the first direction D1.

[0066] refer to Figure 8B The extension portion EP may be provided at the same level as the semiconductor pattern SP of each of the first to fourth layers L1 to L4. The extension portion EP may not be provided at the level where the first insulating layer IL1 is provided. The extension portion EP may not be provided at the level where the first gate electrode GE1 is provided. The extension portion EP may not be provided at the level where the second gate electrode GE2 is provided.

[0067] The semiconductor pattern SP in one layer may be divided into a plurality of semiconductor patterns SP, for example, a plurality of semiconductor sub-patterns SP, by the first vertical insulator VIP1, the second vertical insulator VIP2, and the extension EP. For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be disposed in the fourth layer L4. The second semiconductor pattern SP2 may be adjacent to the first semiconductor pattern SP1 along the first direction D1. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be spaced apart from each other along the first direction D1 by the first vertical insulator VIP1, the second vertical insulator VIP2, and the extension EP.

[0068] As described above, since the extension portion EP is not provided around the first gate electrode GE1, a portion of the first gate electrode GE1 can be provided between the first vertical insulator VIP1 and the second vertical insulator VIP2. Since the extension portion EP is not provided around the second gate electrode GE2, a portion of the second gate electrode GE2 can be provided between the first vertical insulator VIP1 and the second vertical insulator VIP2. The portion of the first gate electrode GE1 between the first vertical insulator VIP1 and the second vertical insulator VIP2 and the portion of the second gate electrode GE2 between the first vertical insulator VIP1 and the second vertical insulator VIP2 can each form a connection portion CNP.

[0069] For example, reference Figure 7 and Figure 8B The connection portion CNP of the first gate electrode GE1 may connect (eg, electrically connect) the first gate electrode GE1 on the first semiconductor pattern SP1 to the first gate electrode GE1 on the second semiconductor pattern SP2. Figure 7 As shown, the first gate electrode GE1 on the first semiconductor pattern SP1 and the first gate electrode GE1 on the second semiconductor pattern SP2 may be connected to each other through a path PAT.

[0070] As described above, the semiconductor patterns SP in one partition layer may be spaced apart from each other by the vertical insulator VIP. However, due to the connection portion CNP disposed between the first and second vertical insulators VIP1 and VIP2, the gate electrode GE in one layer may not be divided but may extend along the first direction D1.

[0071] Therefore, the gate electrode GE according to some example embodiments may continuously intersect the semiconductor pattern SP arranged along the first direction D1 in one layer, as described above with reference to FIG. Figure 1 and Figure 2 The gate electrode GE. The gate electrode GE according to some example embodiments may be or correspond to the reference Figure 1 The horizontal word line WL.

[0072] refer to Figure 7 、 Figure 8A and Figure 8B , the semiconductor patterns SP of each of the first to fourth layers L1 to L4 may be spaced apart from each other by the vertical insulator VIP and may be arranged along the first direction D1. The semiconductor pattern SP may have a strip shape extending from the bit line BL along the second direction D2 (see Figure 8A Even though not shown in the drawings, each of the semiconductor patterns SP may include a channel region, a first dopant region, and a second dopant region. The channel region may be provided between the first dopant region and the second dopant region.

[0073] The semiconductor pattern SP may have a first end SPe1 and a second end SPe2 opposite to the first end SPe1 along a second direction D2. A first dopant region may be provided at the first end SPe1, and a second dopant region may be provided at the second end SPe2. A bit line BL may be electrically connected to the first end SPe1 of the semiconductor pattern SP. A data storage element DS may be electrically connected to the second end SPe2 of the semiconductor pattern SP.

[0074] refer to Figure 7 、 8A 8C, each of the data storage elements DS may include a first electrode EL1, a dielectric layer DL, and a second electrode EL2. The data storage elements DS of the stacked structure SS may share a single dielectric layer DL and a single second electrode EL2. In other words / for example, a plurality of first electrodes EL1 may be provided in the stacked structure SS, and a single dielectric layer DL may cover the surface of the first electrode EL1. A single second electrode EL2 may be provided on the single dielectric layer DL. Each of the first electrodes EL1 may have a solid cylindrical shape. The second electrode EL2 may be provided on the outer surface of the cylinder of the first electrode EL1.

[0075] The first electrodes EL1 may be connected to the semiconductor patterns SP in one layer, respectively. Figure 8C , the first electrodes EL1 in one layer may be spaced apart from each other by the second vertical insulator VIP2 .The first electrodes EL1 in one layer may be arranged along the first direction D1 .

[0076] The first electrode EL1 may be directly connected to the second end SPe2 of the semiconductor pattern SP. For example, the first electrode EL1 may include a metal silicide (e.g., cobalt silicide). The second electrode EL2 may include at least one of a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a doped semiconductor material (e.g., doped silicon (e.g., doped polysilicon) and / or doped germanium). The dielectric layer DL may include a high-K dielectric material, such as hafnium oxide, hafnium-silicon oxide, lanthanum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, lithium oxide, aluminum oxide, lead-scandium-tantalum oxide, lead zinc niobate, or any combination thereof.

[0077] refer to Figure 7 and Figure 8A The bit lines BL may be arranged to penetrate the stack structure SS. The bit lines BL may be separated from each other by a vertical insulator VIP. The bit lines BL may be arranged along a first direction D1.

[0078] Each of the bit lines BL may include a horizontal portion BLh stacked on the substrate SUB and a vertical portion BLv extending along the third direction D3. The vertical portion BLv may connect the stacked horizontal portions BLh. In other words / for example, the bit line BL according to some example embodiments may be or correspond to a reference Figure 1 The vertical bit line BL.

[0079] The horizontal portions BLh of the bit lines BL may be electrically connected to the stacked semiconductor patterns SP, respectively. A silicide pattern SC may be disposed between the horizontal portions BLh and the first end SPe1 of the semiconductor pattern SP. In other words, or for example, the bit lines BL may be electrically connected to the semiconductor pattern SP through the horizontal portions BLh and the silicide pattern SC. The silicide pattern SC may include a metal silicide (e.g., cobalt silicide). A spacer SPC may be disposed between the horizontal portions BLh and the gate electrode GE. The spacer SPC may electrically insulate the horizontal portions BLh and the gate electrode GE from each other.

[0080] refer to Figure 7 When viewed in a plan view, the horizontal portion BLh of the bit line BL may not be aligned with the first electrode EL1 of the data storage element DS in the second direction D2. The horizontal portion BLh may be offset relative to the first electrode EL1 in the first direction D1.

[0081] The insulating structure ISS may be provided to cover the sidewall of the vertical portion BLv of the bit line BL. The insulating structure ISS may extend along the first direction D1. The insulating structure ISS may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0082] Figure 9 、 11 , 13 , 15 , 17 and 19 are plan views illustrating methods for manufacturing / fabricating a 3D semiconductor memory device according to some example embodiments of the inventive concepts. Figure 10 、 12 , 14A, 16A, 18A and 20A are respectively along Figure 9 、 11 , 13, 15, 17 and 19 are cross-sectional views taken along line AA′. Figure 14B 、 16B , 18B and 20B are respectively along Figure 13 、 15 , 17 and 19 are cross-sectional views taken along line BB′.

[0083] refer to Figure 9 and Figure 10 , a stacked structure SS may be formed on the substrate SUB. The formation of the stacked structure SS may include sequentially stacking first to fourth layers L1 to L4. In particular, the formation of each of the first to fourth layers L1 to L4 may include: forming a first insulating layer IL1; forming a second insulating layer IL2 on the first insulating layer IL1; forming a semiconductor layer SL on the second insulating layer IL2; and forming a third insulating layer IL3 on the semiconductor layer SL. In other words / for example, each of the first to fourth layers L1 to L4 may include a first insulating layer IL1, a second insulating layer IL2, a semiconductor layer SL, and a third insulating layer IL3 stacked sequentially. In some example embodiments, each of the first to fourth layers L1 to L4 may be formed in one manufacturing step (e.g., within one tool and / or within one process chamber); however, example embodiments are not limited thereto.

[0084] In some example embodiments, forming the stacked structure SS may include forming alternately stacked first and second semiconductor layers; and replacing each of the second semiconductor layers with a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3. The remaining first semiconductor layer may correspond to the semiconductor layer SL. Here, the first semiconductor layer may be a silicon layer such as a single crystal silicon layer, and the second semiconductor layer may be a silicon germanium layer such as a single crystal silicon germanium layer.

[0085] Each of the first to third insulating layers IL1, IL2, and IL3 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. The second insulating layer IL2 and the third insulating layer IL3 may include the same material; however, example embodiments are not limited thereto. The second insulating layer IL2 and the third insulating layer IL3 may include a material having an etch selectivity relative to the first insulating layer IL1. For example, the first insulating layer IL1 may include a silicon oxide layer, and the second insulating layer IL2 and the third insulating layer IL3 may include a silicon nitride layer. The semiconductor layer SL may include a semiconductor material, such as silicon, germanium, or silicon germanium.

[0086] The stack structure SS may be patterned to form first and second holes HO1 and HO2 penetrating the stack structure SS. The first and second holes HO1 and HO2 may expose the top surface of the substrate SUB. The first and second holes HO1 and HO2 may have a stripe shape extending in the second direction D2.

[0087] The second hole HO2 may be formed adjacent to the first hole HO1 along the second direction D2. The second hole HO2 may not be aligned with the first hole HO1 along the second direction D2. The second hole HO2 may alternate with the first hole HO1. For example, the first hole HO1 may be formed to be offset relative to the second hole HO2 along the first direction D1.

[0088] The first holes HO1 may be arranged at a constant interval along the first direction D1. The second holes HO2 may be arranged at a constant interval along the first direction D1. The interval of the first holes HO1 may be substantially equal to the interval of the second holes HO2.

[0089] refer to Figure 11 and Figure 12 The semiconductor layer SL exposed by the first and second holes HO1 and HO2 may be partially etched (e.g., partially isotropically etched). For example, a wet etching process may be performed to selectively etch the semiconductor layer SL through the first and second holes HO1 and HO2. The first to third insulating layers IL1, IL2, and IL3 may remain during the wet etching process. The semiconductor layer SL may be partially etched during the wet etching process, thereby forming a recessed region DR. The recessed region DR may connect the first and second holes HO1 and HO2, which are adjacent to each other.

[0090] A plurality of vertical insulators VIP may be formed by filling the first and second holes HO1 and HO2 and the recessed region DR with an insulating material (e.g., by using a chemical vapor deposition (CVD) process). Each of the vertical insulators VIP may include a first vertical insulator VIP1 filling the first hole HO1, a second vertical insulator VIP2 filling the second hole HO2, and an extension EP filling the recessed region DR. Adjacent first and second vertical insulators VIP1 and VIP2 may be connected to each other via the extension EP. The extension EP may be provided at the same level as the semiconductor layer SL.

[0091] The vertical insulator VIP may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. The vertical insulator VIP may include a material having an etching selectivity relative to the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3.

[0092] A portion of the first insulating layer IL1 may be disposed between the first and second vertical insulators VIP1 and VIP2, which are adjacent to each other. A portion of the second insulating layer IL2 may be disposed between the first and second vertical insulators VIP1 and VIP2, which are adjacent to each other. A portion of the third insulating layer IL3 may be disposed between the first and second vertical insulators VIP1 and VIP2, which are adjacent to each other.

[0093] The vertical insulators VIP may be arranged at a constant interval along the first direction D1. The semiconductor layer SL between adjacent vertical insulators VIP may be defined as a semiconductor pattern SP. In other words / for example, the vertical insulators VIP may divide the semiconductor layer SL into a plurality of semiconductor patterns SP. The semiconductor patterns SP may be arranged at a constant interval along the first direction D1 via the vertical insulators VIP.

[0094] refer to Figure 13 、 Figure 14A and Figure 14B The stacked structure SS may be patterned to form a first trench TR1 extending in the first direction D1. The first trench TR1 may expose the top surface of the substrate SUB. A first sidewall of the stacked structure SS extending in the first direction D1 may be defined by the first trench TR1. The first to third insulating layers IL1, IL2, and IL3 and the semiconductor layer SL of the stacked structure SS may be exposed through the first trench TR1.

[0095] The second insulating layer IL2 and the third insulating layer IL3 exposed by the first trench TR1 may be partially etched, for example, using an isotropic etching process. For example, a wet etching process may be performed through the first trench TR1 to selectively etch the second insulating layer IL2 and the third insulating layer IL3. The semiconductor layer SL and the first insulating layer IL1 may remain during the wet etching process.

[0096] Since the second insulating layer IL2 and the third insulating layer IL3 are partially removed, a first groove RS1 may be formed. The first groove RS1 may extend from the first trench TR1 along the second direction D2. Each of the first grooves RS1 may be deeper than the first vertical insulator VIP1 in the second direction D2. One end of each of the first grooves RS1 may be formed between one end of the first vertical insulator VIP1 and one end of the second vertical insulator VIP2. Each of the first grooves RS1 may expose the semiconductor pattern SP defined between adjacent vertical insulators VIP. In particular, the first surface SPa and the second surface SPb of the semiconductor pattern SP between adjacent vertical insulators VIP may be exposed through the first groove RS1.

[0097] refer to Figure 15 、 Figure 16A and Figure 16B , a gate insulating layer GI may be conformally formed in the first groove RS1. The gate insulating layer GI may cover the exposed first and second surfaces SPa and SPb of the semiconductor pattern SP. The gate insulating layer GI may not completely fill the first groove RS1 but may partially fill the first groove RS1. The gate insulating layer GI may be formed using a CVD process (e.g., a plasma enhanced CVD (PECVD) process and / or a low pressure CVD (LPCVD) process).

[0098] Gate electrodes GE filling the first grooves RS1 , respectively, may be formed on the gate insulating layer GI. The gate electrodes GE may include a first gate electrode GE1 on the first surface SPa of the semiconductor pattern SP and a second gate electrode GE2 on the second surface SPb of the semiconductor pattern SP.

[0099] A portion CNP1 of the first gate electrode GE1 may be disposed between the first vertical insulator VIP1 and the second vertical insulator VIP2. A portion CNP2 of the second gate electrode GE2 may be disposed between the first vertical insulator VIP1 and the second vertical insulator VIP2. A portion of the gate electrode GE disposed between the first vertical insulator VIP1 and the second vertical insulator VIP2 may be defined as a connecting portion CNP (i.e., CNP1 and CNP2).

[0100] The gate insulating layer GI and the gate electrode GE may be recessed through the first trench TR1 . A spacer SPC may be formed in the recessed region of the gate electrode GE . The formation of the spacer SPC may include forming a spacer layer in the first groove RS1 and wet-etching the spacer layer.

[0101] Subsequently, the semiconductor layer SL exposed by the first trench TR1 may be partially etched. Due to the etching of the semiconductor layer SL, a second groove RS2 may be formed in each of the first to fourth layers L1 to L4. The second groove RS2 may be formed so that one end of each of the semiconductor layers SL is adjacent to the isolation member SPC. A plurality of second grooves RS2 may be formed in a single layer. The second grooves RS2 in a single layer may be spaced apart from each other along the first direction D1 by the vertical insulator VIP.

[0102] refer to Figure 17 、 18A 18B, horizontal portions BLh of the bit lines BL can be formed in the second grooves RS2. For example, the horizontal portions BLh can be formed by depositing a conductive material in the second grooves RS2. Thereafter, the first insulating layer IL1 can be partially removed through the first trenches TR1. Conductive material can be further deposited in the region formed by removing the first insulating layer IL1, thereby forming vertical portions BLv of the bit lines BL. The vertical portions BLv can extend along the third direction D3 and can connect the stacked horizontal portions BLh to each other.

[0103] A silicide pattern SC may be formed between the bit line BL and each of the semiconductor patterns SP. The formation of the silicide pattern SC may include performing a silicidation reaction on the semiconductor pattern SP exposed by the second groove RS2.

[0104] Even though not shown in the drawings, a first dopant region may be formed in the semiconductor pattern SP. The formation of the first dopant region may include doping the semiconductor pattern SP exposed through the second groove RS2 with a dopant such as boron, phosphorus, and / or arsenic before forming the silicide pattern SC.

[0105] refer to Figure 19 、 Figure 20A and Figure 20B , an insulating structure ISS may be formed to fill the first trench TR1. The insulating structure ISS may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0106] The stacked structure SS may be patterned to form a second trench TR2 extending in the first direction D1. The second trench TR2 may be formed on a side of the stacked structure SS opposite the first trench TR1. The second trench TR2 may expose the top surface of the substrate SUB. A second sidewall of the stacked structure SS extending in the first direction D1 may be defined by the second trench TR2. The first to third insulating layers IL1, IL2, and IL3 and the semiconductor layer SL of the stacked structure SS may be exposed through the second trench TR2.

[0107] The second insulating layer IL2 and the third insulating layer IL3 exposed by the second trench TR2 may be completely removed. For example, a wet etching process may be performed to selectively etch the second insulating layer IL2 and the third insulating layer IL3 through the second trench TR2. The semiconductor layer SL and the first insulating layer IL1 may remain during the wet etching process.

[0108] Since the remaining second and third insulating layers IL2 and IL3 are completely removed, a third recess RS3 may be formed The third recess RS3 may horizontally extend from the second trench TR2 toward the gate electrode GE.

[0109] Reference again Figure 7 and Figures 8A to 8C A silicidation reaction may be performed on the semiconductor layer SL exposed by the third recess RS3, thereby forming the first electrode EL1. Since the first electrode EL1 is formed by silicided exposed portions of the semiconductor layer SL, the first electrodes EL1 may be directly connected to the semiconductor patterns SP. The first electrodes EL1 in a layer may be separated from each other along the first direction D1 by the second vertical insulator VIP2. Each of the first electrodes EL1 may have a solid cylindrical shape.

[0110] Even though not shown in the drawings, a second dopant region may be formed in the semiconductor pattern SP before forming the first electrode EL1. Forming the second dopant region may include doping the semiconductor layer SL exposed by the third recess RS3 with a dopant before forming the first electrode EL1. The dopant used to form the second dopant region may be the same as or different from the dopant used to form the first dopant region.

[0111] A dielectric layer DL may be conformally formed on the first electrode EL1 , cover the exposed outer surface of the first electrode EL1 , and partially fill the third groove RS3 .

[0112] The second electrode EL2 may be formed on the dielectric layer DL. The second electrode EL2 may be formed to completely fill the second trench TR2 and the third recess RS3. The first electrode EL1, the dielectric layer DL, and the second electrode EL2 may constitute / correspond to the data storage element DS.

[0113] Figure 21 It is along Figure 7 A cross-sectional view taken along line BB' is provided to illustrate a 3D semiconductor memory device according to some example embodiments of the present invention. In some example embodiments, for ease of explanation, the description of the 3D semiconductor memory device will be omitted. Figure 7 and Figures 8A to 8C In other words / for example, the following will mainly describe in detail the exemplary embodiment and the Figure 7 and Figures 8A to 8C The differences between the example embodiments.

[0114] refer to Figure 7 and Figure 21 The vertical insulator VIP may not include the extension EP. The gate electrode GE may surround the first surface SPa, the second surface SPb, the first sidewall SPw1, and the second sidewall SPw2 of the semiconductor pattern SP. The first sidewall SPw1 and the second sidewall SPw2 may be both sidewalls of the semiconductor pattern SP.

[0115] The memory cell transistor according to some example embodiments may have a gate-all-around (GAA) structure in which the gate electrode GE surrounds the body of the transistor (ie, the semiconductor pattern SP). For example, the memory cell transistor according to some example embodiments may be the above reference Figure 4 Since the memory cell transistor according to some example embodiments has a gate-all-around structure, channel controllability of the gate electrode GE may be improved.

[0116] In a method for manufacturing a semiconductor memory device according to some example embodiments, the above reference Figure 11 and Figure 12 The extension EP of the vertical insulator VIP can be formed of the same insulating material as the second insulating layer IL2 and the third insulating layer IL3. Therefore, when the second insulating layer IL2 and the third insulating layer IL3 are replaced by the gate electrode GE in a subsequent process, the extension EP and the second insulating layer IL2 and the third insulating layer IL3 can be replaced by the gate electrode GE. Thus, a gate-all-around structure can be realized.

[0117] Figure 22 and Figure 23 It is along Figure 7 A cross-sectional view taken along line AA' is provided to illustrate a 3D semiconductor memory device according to some example embodiments of the present invention. Figure 7 and Figures 8A to 8C In other words, the following will mainly describe in detail the exemplary embodiment and the exemplary embodiment. Figure 7and Figures 8A to 8C The differences between the example embodiments.

[0118] refer to Figure 7 and Figure 22 ,refer to Figure 1 The cell array CA may be disposed on a substrate SUB. The cell array CA may include a stacked structure SS. A peripheral circuit region PER may be disposed between the cell array CA and the substrate SUB. The peripheral circuit region PER may include circuits for operating the cell array CA, such as row driver circuits, address decoding circuits, and / or sense amplifier circuits.

[0119] In some example embodiments, the peripheral circuit region PER may include a peripheral transistor PTR, a peripheral interconnection line PIL, and a peripheral contact PCNT vertically connected to the peripheral interconnection line PIL. Although not shown in the drawings, the peripheral interconnection line PIL may be electrically connected to the cell array CA through a through contact. An etch stop layer ESL may be additionally provided between the cell array CA and the peripheral circuit region PER.

[0120] As mentioned above Figure 1 and Figure 2 As described above, the semiconductor memory device according to some example embodiments may have a cell-on-peripheral-circuit (COP) structure, in which memory cells are arranged on a peripheral circuit region. Since the peripheral circuit region PER and the cell array CA are three-dimensionally stacked, the area of ​​the semiconductor memory device can be reduced, and a high integration density of the circuit can be achieved.

[0121] refer to Figure 7 and Figure 23 The cell array CA may be disposed on a first substrate SUB1. A second substrate SUB2 may be disposed on the cell array CA. A peripheral circuit region PER may be disposed on the second substrate SUB2. The peripheral circuit region PER may include circuits for operating the cell array CA.

[0122] A method for manufacturing a semiconductor memory device according to some example embodiments may include forming a cell array CA on a first substrate SUB1 ; forming a peripheral circuit region PER on a second substrate SUB2 ; and bonding the second substrate SUB2 to the cell array CA by a wafer bonding method.

[0123] As mentioned above Figure 1 and Figure 6 As described above, the semiconductor memory device according to some example embodiments may have an on-cell peripheral circuit (POC) structure, in which the peripheral circuit region is provided on the memory cell. Since the cell array CA and the peripheral circuit region PER are three-dimensionally stacked, the area of ​​the semiconductor memory device can be reduced, and a high integration density of the circuit can be achieved.

[0124] Figure 24 are plan views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts. Figure 25A and Figure 25B are along Figure 24 In some example embodiments, for the purpose of ease and convenience of description, the cross-sectional view taken along the lines BB' and DD' will be omitted. Figure 7 and Figures 8A to 8C In other words, the following will mainly describe in detail some exemplary embodiments and Figure 7 and Figures 8A to 8C The differences between the example embodiments. Figure 24 The cross-sectional views taken along the lines AA' and CC' can be respectively Figure 8A and 8C The cross-sectional views are essentially the same.

[0125] refer to Figure 24 、 25A , 25B, 8A, and 8C, the first vertical insulator VIP1 and the second vertical insulator VIP2 of each of the vertical insulators VIP may be aligned with each other along the second direction D2. The second vertical insulator VIP2 may be spaced apart from the first vertical insulator VIP1 along the second direction D2. A connection portion CNP of the gate electrode GE may be provided between the first vertical insulator VIP1 and the second vertical insulator VIP2. Due to the connection portion CNP between the first vertical insulator VIP1 and the second vertical insulator VIP2, the gate electrode GE may not be divided but may extend continuously along the first direction D1.

[0126] In addition to the shape of the vertical insulator VIP described above, other features of the semiconductor memory device according to some example embodiments may be the same as those described above. Figure 7 and Figures 8A to 8C The corresponding features of the semiconductor memory devices are substantially the same.

[0127] Figure 26 are plan views illustrating 3D semiconductor memory devices according to some example embodiments of the inventive concepts. Figure 27A 、 27B and 27C are respectively along Figure 26 In some example embodiments, for the purpose of ease and convenience of description, the cross-sectional view taken along the lines A-A', BB' and DD' will be omitted. Figure 7 and Figures 8A to 8C In other words, the following will mainly describe in detail some exemplary embodiments and Figure 7 and Figures 8A to 8C The differences between the example embodiments. Figure 26 The cross-sectional view taken along the line CC' can be compared with Figure 8C The cross-sectional views are essentially the same.

[0128] refer to Figure 26 、 27A 27C to 8C, third holes HO3 penetrating the stacked structure SS may be defined. Each of the third holes HO3 may penetrate a central portion of the stacked semiconductor pattern SP. When viewed in a plan view, the third holes HO3 may be arranged at a constant pitch along the first direction D1. The planar shape of the third holes HO3 may be a circular shape. Insulating pillars VPL may be respectively disposed in the third holes HO3. The insulating pillars VPL may penetrate the gate electrode GE extending along the first direction D1 and may be arranged along the gate electrode GE in the first direction D1. For example, the insulating pillars VPL may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer.

[0129] refer to Figure 26 The gate electrode GE may have a first side wall SW1 and a second side wall SW2 that are opposite to each other along the second direction D2. The first side wall SW1 and the second side wall SW2 may have a curved profile. The first side wall SW1 may have a shape that protrudes toward the bit line BL, and the second side wall SW2 may have a shape that protrudes toward the first electrode EL1. For example, the center of curvature of the first side wall SW1 and the center of curvature of the second side wall SW2 may substantially coincide with the center of the insulating pillar VPL. The spacer SPC may be provided on each of the first side wall SW1 and the second side wall SW2 of the gate electrode GE.

[0130] The first vertical insulator VIP1 and the second vertical insulator VIP2 of each of the vertical insulators VIP may be aligned with each other along the second direction D2. A connection portion CNP of the gate electrode GE may be provided between the first vertical insulator VIP1 and the second vertical insulator VIP2. Due to the connection portion CNP between the first vertical insulator VIP1 and the second vertical insulator VIP2, the gate electrode GE may not be divided but may extend continuously along the first direction D1.

[0131] Figure 28 、 30 , 32 and 34 are plan views illustrating methods for fabricating a 3D semiconductor memory device according to some example embodiments of the inventive concept. Figure 29 、 31 , 33A and 35A are respectively along Figure 28 、 30 , 32 and 34 are cross-sectional views taken along line AA′. Figure 33B and Figure 35B are along Figure 32 and Figure 34 A cross-sectional view taken along line BB′.

[0132] refer to Figure 28 and Figure 29 A stacked structure SS may be formed on a substrate SUB. The stacked structure SS may include sequentially stacking first to fourth layers L1 to L4. Each of the first to fourth layers L1 to L4 may include: a first insulating layer IL1; a second insulating layer IL2 on the first insulating layer IL1; a semiconductor layer SL on the second insulating layer IL2; and a third insulating layer IL3 on the semiconductor layer SL.

[0133] The first hole HO1 and the second hole HO2 may be formed to penetrate the stack structure SS. The second hole HO2 may be formed adjacent to the first hole HO1 along the second direction D2. The second hole HO2 may be aligned with the first hole HO1 along the second direction D2.

[0134] refer to Figure 30 and Figure 31 The semiconductor layer SL exposed by the first and second holes HO1 and HO2 may be partially etched to form a recessed region DR. A plurality of vertical insulators VIP may be formed by filling the first and second holes HO1 and HO2 and the recessed region DR with an insulating material. The vertical insulators VIP may be arranged at a constant interval along the first direction D1. The semiconductor layer SL between adjacent vertical insulators VIP may be defined as a semiconductor pattern SP.

[0135] refer to Figure 32 、 Figure 33A and Figure 33B , a third hole HO3 penetrating the stack structure SS may be formed. The third hole HO3 may be formed between adjacent vertical insulators VIP. The third hole HO3 may penetrate the center of the semiconductor pattern SP. The third holes HO3 may be arranged at a constant interval along the first direction D1.

[0136] The second and third insulating layers IL2 and IL3 exposed through the third hole HO3 may be partially etched to form a fourth recess RS4. For example, a wet etching process may be performed through the third hole HO3 to selectively etch the second and third insulating layers IL2 and IL3. The semiconductor layer SL and the first insulating layer IL1 may remain during the wet etching process.

[0137] Etching may be isotropically performed from the third hole HO3 in the wet etching process, and thus the fourth groove RS4 may extend horizontally from the third hole HO3. Figure 32 , when viewed in a plan view, a sidewall of the fourth groove RS4 may have a curved profile.

[0138] refer to Figure 34、 Figure 35A and Figure 35B , a spacer SPC may be formed in the fourth groove RS4. The spacer SPC may partially fill the fourth groove RS4. A gate insulating layer GI and a gate electrode GE may be formed in the fourth groove RS4. Thereafter, an anisotropic etching process may be performed through the third hole HO3 to completely remove the material filling the third hole HO3. Therefore, the stacked gate electrodes GE may not be vertically connected to each other.

[0139] Subsequently, you can perform the same Figures 17 to 20B and Figures 7 to 8C The manufacturing process is substantially the same as the manufacturing process. For example, the bit line BL extending along the third direction D3 may be formed at one side of the stack structure SS. The data storage element DS may be formed at the opposite side of the stack structure SS.

[0140] In a 3D semiconductor memory device according to example embodiments of the present inventive concept, a gate electrode may be three-dimensionally disposed on a body of a memory cell transistor, thereby improving channel controllability of the gate electrode.

[0141] In a 3D semiconductor memory device according to an exemplary embodiment of the present inventive concept, bit lines can be formed vertically and word lines can be formed horizontally. Therefore, when a memory cell array is three-dimensionally implemented, process defects can be reduced and device reliability can be improved.

[0142] Although the present invention has been described with reference to certain exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. It should be understood, therefore, that the exemplary embodiments described above are illustrative rather than restrictive. The scope of the present invention is therefore to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A semiconductor memory device comprising: A stacked structure comprising a plurality of layers vertically stacked on a substrate, wherein each of the plurality of layers comprises a semiconductor pattern, a gate electrode extending along a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern; a plurality of vertical insulators penetrating the stack structure, at least one of the plurality of vertical insulators being arranged along the first direction; and A bit line extending vertically on one side of the stack structure, wherein the bit lines electrically connect the semiconductor patterns. Each of the plurality of vertical insulators includes a first vertical insulator and a second vertical insulator adjacent to the first vertical insulator, and The gate electrode includes a connection portion between the first vertical insulator and the second vertical insulator.

2. The semiconductor memory device according to claim 1, wherein The plurality of vertical insulators divide the semiconductor pattern into a plurality of sub-patterns, and Wherein, the plurality of sub-patterns are arranged along the first direction.

3. The semiconductor memory device according to claim 2, wherein Each of the plurality of vertical insulators further comprises: an extension portion connecting the first vertical insulator and the second vertical insulator, The plurality of sub-patterns adjacent to each other are spaced apart from each other along the first direction by the first vertical insulator, the second vertical insulator, and the extending portion.

4. The semiconductor memory device according to claim 1, wherein The data storage element comprises: a first electrode electrically connected to the semiconductor pattern; a second electrode on the first electrode; and A dielectric layer is between the first electrode and the second electrode.

5. The semiconductor memory device according to claim 1, wherein The gate electrode includes: a first gate electrode on a first surface of the semiconductor pattern; and A second gate electrode is disposed on a second surface of the semiconductor pattern, the second surface being opposite to the first surface.

6. The semiconductor memory device according to claim 1, wherein The gate electrode is on a top surface, a bottom surface, a first sidewall, and a second sidewall of the semiconductor pattern.

7. The semiconductor memory device according to claim 1, wherein The bit line includes: stacked horizontal portions, each electrically connected to the stacked semiconductor patterns; and A vertical portion connects the stacked horizontal portions and extends vertically.

8. The semiconductor memory device according to claim 1, wherein The second vertical insulator is offset relative to the first vertical insulator along the first direction.

9. The semiconductor memory device according to claim 1, wherein The second vertical insulator is aligned with the first vertical insulator along a second direction, the second direction intersecting the first direction.

10. The semiconductor memory device according to claim 1, wherein The gate electrode has a first side wall and a second side wall facing each other along a second direction intersecting the first direction, and Wherein, each of the first side wall and the second side wall is curved.

11. A semiconductor memory device comprising: A stacked structure comprising a plurality of layers vertically stacked on a substrate, wherein each of the plurality of layers comprises a semiconductor pattern, a gate electrode extending along a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern; a vertical insulator penetrating the stack structure, the vertical insulator extending along a second direction intersecting the first direction; and A bit line extending vertically on one side of the stack structure, wherein the semiconductor pattern includes a first semiconductor sub-pattern and a second semiconductor sub-pattern spaced apart from each other along the first direction, wherein the vertical insulator is interposed between the first semiconductor sub-pattern and the second semiconductor sub-pattern, The vertical insulator includes a first vertical insulator and a second vertical insulator adjacent to the first vertical insulator, The gate electrode includes a connection portion between the first vertical insulator and the second vertical insulator, and The gate electrode on the first semiconductor sub-pattern is connected to the gate electrode on the second semiconductor sub-pattern through the connection portion.

12. The semiconductor memory device according to claim 11, wherein The bit line includes: horizontal portions of the stack electrically connected to corresponding ones of the semiconductor patterns; and A vertical portion connects the stacked horizontal portions and extends vertically.

13. The semiconductor memory device according to claim 11, wherein The gate electrode includes: a first gate electrode on a first surface of the semiconductor pattern; and A second gate electrode is disposed on a second surface of the semiconductor pattern, the second surface being opposite to the first surface.

14. The semiconductor memory device according to claim 11, wherein The gate electrode is on a top surface, a bottom surface, a first sidewall, and a second sidewall of the semiconductor pattern.

15. The semiconductor memory device according to claim 11, wherein The data storage element comprises: a first electrode electrically connected to the semiconductor pattern; a second electrode on the first electrode; and A dielectric layer is between the first electrode and the second electrode.

16. A semiconductor memory device comprising: a bit line extending on the substrate along a first direction, the first direction being perpendicular to a top surface of the substrate; a semiconductor pattern extending from the bit line in a second direction, the second direction being parallel to the top surface of the substrate, the semiconductor pattern having a first surface and a second surface opposite to each other in the first direction; a first gate electrode and a second gate electrode, respectively on the first surface and the second surface of the semiconductor pattern, the first gate electrode and the second gate electrode extending along a third direction, the first gate electrode and the second gate electrode being parallel to each other, the third direction being parallel to the top surface of the substrate and intersecting the second direction; a data storage element electrically connected to the semiconductor pattern; as well as a peripheral circuit region on the substrate, wherein the bit line, the semiconductor pattern, the first gate electrode, the second gate electrode, and the data storage element correspond to a memory cell of a cell array, and The memory cells and the peripheral circuit region are stacked along the first direction.

17. The semiconductor memory device according to claim 16, wherein The first gate electrode and the second gate electrode are spaced apart from each other along the first direction.

18. The semiconductor memory device according to claim 16, further comprising: an insulating pillar penetrating the semiconductor pattern and the first gate electrode and the second gate electrode, wherein each of the first gate electrode and the second gate electrode has a first side wall and a second side wall opposite to each other along the second direction, and Each of the first sidewall and the second sidewall is curved.

19. The semiconductor memory device according to claim 16, wherein The data storage element comprises: a first electrode electrically connected to the semiconductor pattern; a second electrode on the first electrode; and A dielectric layer is between the first electrode and the second electrode.

Images