Electronic device and method of manufacturing the same

Abstract

The semiconductor memory comprises: a substrate, which comprises: a first region in which a plurality of variable resistance elements are arranged; a second region and a third region on different sides of the first region; a plurality of first lines arranged above the substrate and extending across the first region and the second region; a plurality of second lines arranged above the first lines and extending across the first region and the third region. The variable resistance element is located at the intersection of the first line and the second line and between the first line and the second line, a contact plug is arranged in the third region, an upper end of which is coupled to the second line, a resistance material layer is inserted between the second line and the variable resistance element in the first region, but does not exist between the contact plug and the second line in the third region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0165497, filed on Dec. 12, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This patent document relates to a memory circuit or a memory device and its application in an electronic device or a system. Background Art

[0004] Recently, as electronic devices develop toward miniaturization, low power consumption, high performance, multi-functions, etc., semiconductor devices capable of storing information in various electronic devices such as computers, portable communication devices, etc. have been required in the art, and research has been conducted on semiconductor devices. Such semiconductor devices include semiconductor devices that can store data using a characteristic of switching between different resistance states according to an applied voltage or current, such as RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electrically programmable fuses (E-fuse), etc. Summary of the invention

[0005] The technology disclosed in this patent document includes various embodiments of electronic devices and methods for manufacturing the same that can reduce process difficulty and process cost while improving reliability and performance characteristics.

[0006] In one embodiment, an electronic device includes a semiconductor memory, which includes: a substrate, which includes a first region in which a plurality of variable resistance elements are arranged, a second region arranged on one side of the first region in a first direction, and a third region arranged on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines arranged on the substrate and extending across the first region and the second region in the first direction; a plurality of second lines arranged above the first lines and extending across the first region and the third region in the second direction; a variable resistance element located between the first line and the second line at the intersection of the first line and the second line; a contact plug, which is arranged in the third region and whose upper end is coupled to the second line; a material layer inserted between the second line and the variable resistance element in the first region but not present in a position between the second line and the contact plug in the third region, the material layer increasing the resistance of the variable resistance element.

[0007] In another embodiment, an electronic device includes a semiconductor memory, which includes: a substrate, which includes a first region in which a plurality of variable resistance elements are arranged, a second region arranged on one side of the first region in a first direction, and a third region arranged on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines arranged on the substrate and extending across the first region and the second region in the first direction; a plurality of second lines arranged above the first lines and extending across the first region and the third region in the second direction; a variable resistance element located between the first line and the second line at the intersection of the first line and the second line; a contact plug, which is arranged in the third region and whose upper end is coupled to the second line; a material layer inserted between the second line and the variable resistance element in the first region and extending to the third region, the material layer increasing the resistance of the variable resistance element, wherein the thickness of the material layer in the first region is constant and the thickness of the material layer in the third region varies.

[0008] In another embodiment, a method for manufacturing an electronic device including a semiconductor memory includes: providing a substrate including a first region, a second region arranged on one side of the first region in a first direction, and a third region arranged on the other side of the first region in a second direction intersecting the first direction; forming a plurality of first lines extending across the first region and the second region in the first direction above the substrate; forming a plurality of variable resistance elements above the first lines in the first region; forming an interlayer insulating layer filling the space between the variable resistance elements; forming a contact plug passing through the interlayer insulating layer in the third region; forming a material layer covering the variable resistance element, the interlayer insulating layer and the contact plug, the material layer increasing the resistance of the variable resistance element; removing a portion of the material layer arranged above the contact plug to form a material layer pattern; forming a plurality of second lines above the material layer pattern and the contact plug, the plurality of second lines extending across the first region and the third region in the second direction.

[0009] These and other aspects, embodiments and associated advantages are described in more detail in the drawings, the description and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 , 2A -2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, and 7A to 7B are views illustrating a semiconductor memory and a method of manufacturing the same according to an embodiment of the present disclosure.

[0011] Figure 8 is a view showing a semiconductor memory according to another embodiment of the present disclosure.

[0012] Figures 9A-9B10A-10B, 11A-11B, and 12A to 12B are views illustrating a semiconductor memory and a method of manufacturing the same according to another embodiment of the present disclosure.

[0013] Fig.13 is an example of a configuration diagram of a microprocessor that implements a memory circuit based on the disclosed technology.

[0014] Fig.14 is an example of a configuration diagram of a processor that implements a memory circuit based on the disclosed technology.

[0015] Fig.15 is an example of a configuration diagram of a system that implements a memory circuit based on the disclosed technology.

[0016] Fig.16 is an example of a configuration diagram of a memory system that implements a memory circuit based on the disclosed technology. DETAILED DESCRIPTION

[0017] Various examples and implementations of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0018] The drawings may not necessarily be drawn to scale, and in some cases the proportions of at least some of the structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example in a drawing or specification having two or more layers is shown in a multilayer structure, the relative positional relationship of such layers or the arrangement order of these layers as shown reflects the described or shown examples and the specific embodiments of the examples, and different relative positioning relationships or arrangement orders of layers are possible. In addition, the described or shown examples of multilayer structures may not reflect all the layers present in the particular multilayer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in the described or shown multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly on the second layer or substrate, or may represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0019] Figures 1 to 7B is a view showing a semiconductor memory and a method of manufacturing the same according to an embodiment of the present disclosure. Figure 1 is a plan view showing a semiconductor memory, Fig. 7A is along Figure 1 A cross-sectional view taken along line A-A', Figure 7B is along Figure 1 A cross-sectional view taken along line BB'. FIG. 2A to FIG. 6B is shown for manufacturing Figure 1 , 7Aand a cross-sectional view of an intermediate process step of a semiconductor memory device of FIG. 7B . Figure 2A , 3A , 4A, 5A and 6A are from along Figure 1 A perspective view of a cross section taken along line AA'. Figure 2B , 3B , 4B, 5B and 6B are from along Figure 1 Perspective view of a cross section taken along line BB'.

[0020] First, the manufacturing method will be described.

[0021] Reference Figure 1 , 2A 2B, a substrate 100 including a semiconductor material such as silicon may be provided. In the substrate 100, a predetermined lower structure (not shown) may be formed. For example, a transistor or the like constituting an integrated circuit may be formed in the substrate 100.

[0022] The cell area CA and the peripheral circuit areas PA1 and PA2 may be defined in the substrate 100. The cell area CA may be an area in which a memory cell is arranged, and the peripheral circuit areas PA1 and PA2 may be areas in which various components constituting a peripheral circuit other than a memory cell are arranged. In the present embodiment, the four cell areas CA are spaced apart from each other and arranged in a 2×2 array along a first direction parallel to the line B-B' and a second direction parallel to the line A-A', and the peripheral circuit areas PA1 and PA2 are located between the cell areas CA. For ease of description, the area between the two cell areas CA arranged in the first direction may be referred to as the first peripheral circuit area PA1, and the area between the two cell areas CA arranged in the second direction may be referred to as the second peripheral circuit area PA2. In the present embodiment, the area of ​​the second peripheral circuit area PA2 may be greater than the area of ​​the first peripheral circuit area PA1. However, the embodiments of the present disclosure are not limited to this configuration, and the arrangement or size of the cell areas CA and the peripheral circuit areas PA1 and PA2 may vary.

[0023] Subsequently, a first interlayer insulating layer 105 may be formed over the substrate 100. The first interlayer insulating layer 105 may include various insulating materials such as silicon oxide, silicon nitride, or a combination thereof.

[0024] Subsequently, a first contact plug 110 may be formed in the first interlayer insulating layer 105 to penetrate the first interlayer insulating layer 105 and be connected to a portion of the substrate 100. The first contact plug 110 may be formed to be connected to the first line 120 in the first peripheral area PA1. A plurality of first contact plugs 110 may be connected to the plurality of first lines 120 in a one-to-one correspondence. The first contact plugs 110 may be arranged in a zigzag or alternating pattern along the second direction. This is to provide a gap between adjacent first contact plugs 110 in the second direction. However, in other embodiments, the arrangement of the first contact plug 110 may be different. The first contact plug 110 may be formed of a conductive material such as a metal, a metal nitride, or a combination thereof, the metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) and tantalum (Ta), the metal nitride such as titanium nitride (TiN) and tantalum nitride (TaN).

[0025] Subsequently, the first wire 120 may be formed by depositing a conductive layer on the first interlayer insulating layer 105 formed with the first contact plug 110 and selectively etching the conductive layer. Each first wire 120 may have a line shape extending in the first direction. In the present embodiment, the first wire 120 may span two cell areas CA arranged along the first direction and the first peripheral circuit area PA1 therebetween. Therefore, the first wire 120 may contact the upper end of the first contact plug 110. The first wire 120 may be formed of various conductive materials such as metals, metal nitrides, or combinations thereof, such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), and the metal nitrides, such as titanium nitride (TiN) and tantalum nitride (TaN).

[0026] Subsequently, a second interlayer insulating layer 125 may be formed to fill the space between the first lines 120 .

[0027] Reference Figure 1 , 3A 3B, the variable resistance element 130 may be formed by forming a material layer of the variable resistance element on the first line 120 and the second interlayer insulating layer 125 and selectively etching the material layer.

[0028] Each variable resistance element 130 may have an island shape in a plan view, and adjacent variable resistance elements 130 may be separated from each other. The variable resistance element 130 may be located at the intersection between the first line 120 and the second line 170. For reference, in the present embodiment, the second line 170 may extend in the second direction to cross two unit regions CA arranged along the second direction and the second peripheral circuit region PA2 therebetween. Therefore, the first line 120 and the second line 170 may cross only in the unit region CA. As a result, the variable resistance element 130 may be arranged in a matrix form along the first direction and the second direction in the unit region CA.

[0029] The variable resistance element 130 may have a variable resistance characteristic that switches between different resistance states to store data. That is, the variable resistance element 130 may be used as a memory cell.

[0030] In addition, the variable resistance element 130 may have a multilayer structure. As an example, the variable resistance element 130 may include a stacked structure of a lower electrode layer 131 , a selection element layer 133 , an intermediate electrode layer 135 , a variable resistance layer 137 , and an upper electrode layer 139 .

[0031] The lower electrode layer 131 and the upper electrode layer 139 can be located at the ends of the variable resistance element 130, for example, at the lower end and the upper end thereof, respectively, and a voltage can be applied to operate the variable resistance element 130. The intermediate electrode layer 135 can physically separate the selection element layer 133 and the variable resistance layer 137, but electrically connect them. The lower electrode layer 131, the intermediate electrode layer 135, or the upper electrode layer 139 can be formed of various conductive materials such as metals, metal nitrides, or combinations thereof, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), and metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN). Alternatively, the lower electrode layer 131, the intermediate electrode layer 135, or the upper electrode layer 139 can be a carbon electrode. In some embodiments, at least one of the lower electrode layer 131, the intermediate electrode layer 135, and the upper electrode layer 139 can be omitted.

[0032] The selection element layer 133 can prevent current leakage between the variable resistance elements 130. Since the variable resistance elements 130 share the first line 120 or the second line 170, current leakage may occur. To this end, the selection element layer 133 may have a threshold switching characteristic for blocking or substantially limiting the current when the amplitude of the applied voltage is less than a predetermined threshold, and for allowing the current to suddenly increase above the threshold. The threshold may be referred to as a threshold voltage, and the selection element layer 133 may be implemented in an on state or an off state based on the threshold voltage. The selection element layer 133 may include a diode; an OTS (bidirectional threshold switching) material such as a chalcogenide material; a MIEC (mixed ion electron conduction) material such as a metal containing a chalcogenide; a MIT (metal insulator transition) material such as NbO2, VO2, etc., or a tunneling insulating material with a wider band gap such as SiO2, Al2O3, etc.

[0033] The variable resistance layer 137 may be a portion of the variable resistance element 130 for storing data. To this end, the variable resistance layer 137 may have a variable resistance characteristic that switches between different resistance states according to an applied voltage or current. The variable resistance layer 137 may have a single-layer structure or a multi-layer structure including at least one of materials for RRAM, PRAM, MRAM, FRAM, etc., that is, metal oxides such as perovskite-based oxides, transition metal oxides, etc., phase change materials such as chalcogenide-based materials, ferromagnetic materials, ferroelectric materials, etc. As an example, the resistance of the variable resistance layer 137 may change due to the generation or disappearance of a conductive path therein. That is, when a conductive path through the variable resistance layer 137 is generated in the variable resistance layer 137, the variable resistance layer 137 may have a low resistance state. On the contrary, when the conductive path disappears, the variable resistance layer 137 may have a high resistance state. When the variable resistance layer 137 includes a metal oxide containing a large number of oxygen vacancies, the conductive path caused by the characteristics of the oxygen vacancies may be generated or disappeared in the variable resistance layer 137. The conductive path may be formed in various ways according to the type, film structure, or operating characteristics of the variable resistance layer 137 .

[0034] Subsequently, a third interlayer insulating layer 140 may be formed to fill the space between the variable resistance elements 130 .

[0035] Reference Figure 1 , Figure 4A and Figure 4B, a second contact plug 150 may be formed in the first to third interlayer insulating layers 105, 125, and 140 to pass through the first to third interlayer insulating layers 105, 125, and 140 and be connected to a portion of the substrate 100. The second contact plug 150 may be formed in the second peripheral circuit region PA2 to be connected to the second line 170 described later. A plurality of second contact plugs 150 may be connected to the second line 170 in a one-to-one correspondence. The second contact plug 150 may be arranged in a zigzag pattern along the first direction. This is to ensure a gap between adjacent second contact plugs 150 in the first direction. However, the present disclosure is not limited thereto, and the arrangement of the second contact plug 150 may be different in other embodiments. The second contact plug 150 may be formed of various conductive materials such as metals, metal nitrides, or combinations thereof, such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), and the metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN).

[0036] Reference Figure 1 , Figure 5A and Figure 5B , you can Figure 4A and Figure 4B A material layer 160 is formed on the resulting structure shown. The material layer may serve as a resistance component that increases the resistance of the variable resistance element 130. The material layer 160 may be formed using a deposition method to cover the entire surface of the substrate 100. The reason for forming the material layer 160 is as follows.

[0037] The variable resistance element 130 can be switched between a high resistance state and a low resistance state. The operation of changing the variable resistance element 130 from the high resistance state to the low resistance state may be referred to as a set operation, and the operation of changing the variable resistance element 130 from the low resistance state to the high resistance state may be referred to as a reset operation.

[0038] The initial set operation may be referred to as a forming operation. The voltage applied in the forming operation may be greater than the voltage applied in the set operation. This is because the voltage required to generate the first or initial conductive path in the variable resistance layer 137 is greater than the voltage required to generate the conductive path in subsequent operations. After the forming operation, the set voltage and reset voltage applied in the set operation and the reset operation may be substantially constant. However, there is such a problem: when the variable resistance element 130 becomes a low resistance state in the forming operation and / or the set operation, an overshoot current or a spike current occurs. Such an overshoot current may damage the variable resistance element 130. For example, the overshoot current may increase the size of the conductive path formed in the variable resistance layer 137, thereby causing the turn-off current of the variable resistance element 130 to increase. When the turn-off current of the variable resistance element 130 increases, the current leakage through the variable resistance element 130 may increase, and due to the reduction of the difference with the on-current, the data reading margin may be reduced. In order to prevent these problems, the resistance of the variable resistance element 130 may be increased. In the present embodiment, a material layer 160 having a relatively high resistance may be formed on the variable resistance element 130 to increase the resistance of the variable resistance element 130 .

[0039] The material layer 160 may include a material having a higher resistance than the conductive material. The material layer 160 may have a higher resistance than the first line 120, the second line 170, or the electrode layers 131, 135, and 139. For example, the material layer 160 may include various insulating materials, such as insulating metal oxides, insulating metal nitrides, silicon oxide, silicon nitride, or a combination thereof. For example, the material layer 160 may include WSiN, WN, TiN, etc.

[0040] Even if the material layer 160 includes an insulating material, the material layer 160 should not block the voltage applied to the variable resistance element 130. Therefore, the material layer 160 can be relatively thin to exhibit an ohmic-like characteristic. This is because regardless of the type of the material layer 160, if the thickness of the material layer 160 is reduced, the resistance of the material layer 160 is reduced, thereby having a leakage property. For example, the material layer 160 can have a thickness of several angstroms to tens of angstroms, such as 5 to 50 angstroms or 10 to 30 angstroms. For reference, an ohmic-like characteristic can refer to a characteristic in which a current increases as an applied voltage increases.

[0041] However, since the material layer 160 is a resistance component, the operation characteristics of the semiconductor memory may be deteriorated, such as interruption of current transmission in a certain area. For example, the material layer 160 on the second contact plug 150 may increase the contact resistance between the second contact plug 150 and the second line 170. In order to solve this problem, it is possible to perform Fig. 6A and 6B The subsequent process shown.

[0042] Reference Figure 1 , 6A 6B, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the material layer 160 to form a material layer pattern 160A. The material layer pattern 160A may cover the cell area CA, while at least a portion above the second contact plug 150 in the second peripheral circuit area PA2 is omitted or does not exist. At least a portion of the material layer 160 of the second peripheral circuit area PA2 may be selectively removed even without a mask for the following reasons.

[0043] In the cell area CA, since the first line 120 and the second line 170 cross each other and a plurality of memory cells, i.e., the variable resistance element 130, are disposed between the first line 120 and the second line 170 at the intersection of the first line 120 and the second line 170, the density of the pattern formed in the cell area CA is high. On the other hand, in the second peripheral circuit area PA2 where the second line 170 and the second contact plug 150 connected to the second line 170 are disposed, the density of the pattern formed in the second peripheral circuit area PA2 is lower than the density of the pattern formed in the cell area CA. Because the pattern density is low in the second peripheral circuit area PA2, the material layer 160 of the second peripheral circuit area PA2 is removed much faster than the material layer 160 from the cell area CA in the planarization process. As a result, the material layer 160 can remain in the cell area CA, while at least a portion of the material layer 160 of the second peripheral circuit area PA2 can be removed.

[0044] The removal rate of the material layer 160 in the second peripheral circuit area PA2 may gradually decrease as it approaches the cell area CA, i.e., gradually decreases toward the two edges of the second peripheral circuit area PA2 in the second direction. In other words, the removal rate of the material layer 160 in the second peripheral circuit area PA2 may increase as the distance from the cell area CA, i.e., toward the center of the second peripheral circuit area PA2 in the second direction. In addition, a planarization process may be performed until the upper ends of all second contact plugs 150 of the second peripheral circuit area PA2 are exposed. That is, over-polishing may be performed in the second peripheral circuit area PA2 to remove not only a portion of the material layer 160, but also a portion of the third interlayer insulating layer 140 and / or the second contact plug 150. Therefore, as shown in the figure, a depression phenomenon (see "D1") may occur in the second peripheral circuit area PA2, in which the upper surface of the resulting structure is concave from the edge of the area toward the center in the second direction. In the cell area CA, the thickness of the material layer pattern 160A may be substantially constant. On the other hand, the thickness of the material layer pattern 160A of the second peripheral circuit area PA2 may gradually decrease from the outer edge of the second peripheral circuit area PA2 toward the center of the second peripheral circuit area PA2 in the second direction.

[0045] As can be seen in this embodiment, when the area of ​​the second peripheral circuit area PA2 is larger than the area of ​​the first peripheral circuit area PA1, some parts of the second peripheral circuit area PA2 are farther from the higher density cell area CA than the first peripheral circuit area PA1. In this case, the degree of removal of the material layer 160 in the first peripheral circuit area PA1 can be lower than that in the second peripheral circuit area PA2. In other words, the amount of depression in the peripheral area is proportional to the distance from the cell area CA.

[0046] In the present embodiment, a portion of the material layer pattern 160A disposed above the first peripheral circuit area PA1 is retained, and its thickness is less than the thickness of the portion of the material layer pattern 160A disposed above the cell area CA. However, the present disclosure is not limited to this embodiment. In another embodiment, the material layer 160 in the first peripheral circuit area PA1 may be removed to an extent that the third interlayer insulating layer 140 is exposed. In this case, the material layer patterns 160A covering the cell areas CA spaced from each other in the first direction may also be separated from each other. Alternatively, in another embodiment, when the pattern density of the first peripheral circuit area PA1 is high, for example, when it is similar to the pattern density of the cell area CA, the material layer pattern 160A of the first peripheral circuit area PA1 may have substantially the same thickness as the material layer pattern 160A of the cell area CA.

[0047] Reference Figure 1 , Fig. 7A and Figure 7B , can be achieved by Fig. 6A and 6B A conductive layer is deposited on the resulting structure, and the conductive layer is selectively etched to form a second line 170. The second line 170 may have a line shape extending in the second direction. In the present embodiment, the second line 170 may span two unit areas CA arranged in the second direction and the second peripheral circuit area PA2 therebetween. The second line 170 may not be in direct contact with the variable resistance element 130 in the unit area CA, but may be connected thereto through the material layer pattern 160A. On the other hand, the second line 170 may directly contact the upper end of the second contact plug 150 in the second peripheral circuit area PA2. The second line 170 may be formed of various conductive materials such as metals, metal nitrides, or combinations thereof, such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) and tantalum (Ta), and the metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN).

[0048] The second line 170 may have a constant thickness in the cell area CA. On the other hand, a portion of the second line 170 in the second peripheral circuit area PA2 may have a greater thickness than a portion of the second line in the cell area CA.

[0049] In the present embodiment, when the second line 170 is formed, the material layer pattern 160A is not etched. Therefore, the material layer pattern 160A may have a substantially uniform thickness in the portion covering the cell area CA, and have a thickness that decreases as the pattern extends over the peripheral area. In addition, the material layer patterns 160A may be spaced apart from each other, with the second peripheral circuit area PA2 disposed therebetween in the second direction. However, the present disclosure is not limited thereto, and when the conductive layer is etched to form the second line 170, the material layer pattern 160A may be etched simultaneously, which will be described later with reference to FIG. Figure 8 Give a description.

[0050] As a result, it is possible to produce Figure 1 , 7A and the semiconductor memory shown in 7B.

[0051] Refer again Figure 1 , 7A7B, the semiconductor memory of the present embodiment may include: a substrate 100, which includes a cell region CA in which a plurality of variable resistance elements 130 are arranged; a first peripheral circuit region PA1 and a second peripheral circuit region PA2 adjacent to the cell region CA; a first line 120 disposed above the substrate 100 and extending across the cell region CA and the first peripheral circuit region PA1 in a first direction; a second line 170 disposed above and separated from the first line 120 and extending across the cell region CA and the second peripheral circuit region PA2 in a second direction; and a second line 170 disposed between the first line 120 and the second peripheral circuit region PA2. The variable resistance element 130 at the intersection of the first line 120 and the second line 170 in the cell area CA where the lines 170 cross each other; the first contact plug 110 disposed in the first peripheral circuit area PA1 and connected to the first line 120 through the lower surface of the first line 120; the second contact plug 150 disposed in the second peripheral circuit area PA2 and connected to the second line 170 through the lower surface of the second line 170; and the material layer 160 interposed between the second line 170 and the variable resistance element 130 and not present in the portion between the second line 170 and the second contact plug 150. The material layer 160 can increase the resistance of the variable resistance element 130.

[0052] The components of the semiconductor memory have been described in detail in the description of the embodiment of the manufacturing method.

[0053] The following effects can be obtained in the semiconductor memory manufactured according to the above-described embodiments.

[0054] First, since the material layer pattern 160A serving as a resistance member is formed on the variable resistance element 130 and increases the resistance of the variable resistance element, damage to the variable resistance element 130 due to overshoot current can be prevented. As a result, the reliability of the variable resistance element 130 and the semiconductor memory including it can be improved.

[0055] In addition, since the material layer pattern 160A is formed by depositing the material layer 160 on the entire surface of the substrate 100 and performing a planarization process that affects the thickness using a difference in pattern density, an additional mask process may not be performed. Therefore, the process may be relatively easy to perform and the cost of the process may be reduced.

[0056] Furthermore, by providing direct contact between the second line 170 and the second contact plug 150 in the second peripheral circuit region PA2 using the above process, it is possible to improve the operation characteristics of the semiconductor memory.

[0057] Figure 8 is a view showing a semiconductor memory according to another embodiment of the present disclosure. Figure 8 is along Figure 1The differences from the above-described embodiment will now be described.

[0058] Reference Figure 8 , after etching the conductive layer for forming the second line 170, a portion of the material layer pattern 160A exposed by the second line 170 may also be etched. The remaining portion of the additionally etched material layer pattern is denoted by reference numeral 160B.

[0059] In the present embodiment, the material layer pattern 160B may have the same pattern as the second line 170 in the cell area CA. That is, the material layer pattern 160B may have a line shape overlapping the second line 170 in the cell area CA while extending in the second direction.

[0060] On the other hand, the cutting of the material layer pattern 160B in the second peripheral circuit region PA2 may be substantially the same as in the above-mentioned embodiment. That is, the cross-sectional shape of the material layer pattern 160B along the line AA' may be the same as that of the embodiment described above. Fig. 7A The material layer patterns 160A are substantially the same.

[0061] 9A to 12B is a view showing a semiconductor memory and a method of manufacturing the same according to another embodiment of the present disclosure. Fig.9A , 10A , 11A and 12A are based on Figure 1 A cross section of line AA' is shown. Fig. 9B , 10B , 11B and 12B are based on Figure 1 In the following description, it will be emphasized that Figure 2A-7B The differences between the described embodiments.

[0062] Reference Fig.9A and 9B After forming a first interlayer insulating layer 205 over the substrate 200 in which the cell area CA and the peripheral circuit areas PA1 and PA2 are defined, a first contact plug 210 may be formed to extend through the first interlayer insulating layer 205 and may be connected to a portion of the substrate 200. The first contact plug 210 may be disposed in one-to-one correspondence with the first line 220 in the first peripheral circuit area PA1.

[0063] Subsequently, after a material layer and a conductive layer for forming a variable resistance element are deposited over the first interlayer insulating layer 205 in which the first contact plug 210 is formed, the conductive layer and the material layer are jointly etched to form a first line 220 and a preliminary variable resistance element 230 .

[0064] The first line 220 may have a line shape extending in the first direction. Also, the first line 220 may cross two cell areas CA arranged in the first direction and the first peripheral circuit area PA1 between the cell areas.

[0065] The initial variable resistance element 230 may have the same pattern as the first line 220 and overlap the first line 220. Therefore, the initial variable resistance element 230 may also have a line shape extending in the first direction. The initial variable resistance element 230 may include an initial lower electrode layer 231, an initial selection element layer 233, an initial intermediate electrode layer 235, an initial variable resistance layer 237, and an initial upper electrode layer 239.

[0066] In this process, since the conductive layer and the material layer are etched together using one mask, both sidewalls of the preliminary variable resistance element 230 may be aligned with both sidewalls of the first line 220 in the second direction.

[0067] Reference Fig. 10A and Fig. 10B , the second interlayer insulating layer 240 may fill a space between adjacent stack structures in which the first lines 220 and the preliminary variable resistance elements 230 are stacked.

[0068] Subsequently, second contact plugs 250 may be formed in the first and second interlayer insulating layers 205 and 240 to penetrate the first and second interlayer insulating layers 205 and 240 and be connected to a portion of the substrate 200. The second contact plugs 250 may be formed to correspond one-to-one to second lines 270 (to be described later) in the second peripheral circuit region PA2.

[0069] Reference Fig.11A and 11B ,exist Fig. 10A and 10B After forming a resistive material layer on the resultant structure, a planarization process may be performed to form a material layer pattern 260A that covers the cell area CA while exposing an upper end of the second contact plug 250 .

[0070] Reference Fig. 12A and 12B , can be achieved by Fig.11A and 11B A conductive layer is deposited on the resulting structure and the conductive layer is selectively etched to form a second line 270. The second line 270 may have a line shape extending in the second direction. In addition, the second line 270 may be formed to cross the two cell regions CA arranged in the second direction and the second peripheral circuit region PA2 between the cell regions.

[0071] Subsequently, the preliminary variable resistance element 230 and the material layer pattern 260A exposed by the second line 270 may be etched to form an etched material layer pattern 260B and the variable resistance element 230A.

[0072] The etch material layer pattern 260B may have a line shape overlapping the second line 270 , but may be separated from each other in the second direction with the second peripheral circuit area PA2 therebetween.

[0073] The variable resistance element 230A may have an island shape in a plan view. Both side walls of the variable resistance element 230A may be aligned with both side walls of the second line 270 in the first direction. The variable resistance element 230A may include a lower electrode layer 231A, a selection element layer 233A, an intermediate electrode layer 235A, a variable resistance layer 237A, and an upper electrode layer 239A.

[0074] In the present embodiment, the material layer for forming the variable resistance element 230A is first etched in the etching process for forming the first line 220, and is secondly etched in the etching process for forming the second line 270. Therefore, the sidewalls of the variable resistance element 230A may be aligned with the first line 220 and the second line 270. Figure 2A-7B In the embodiment, no additional mask is used to form the variable resistance element 230A, which further simplifies the process.

[0075] In the present embodiment, since the material layer pattern 260A is etched after the second line 270 is etched, the material layer pattern 260A may have a line shape. Figure 2A-7B In various embodiments, the material layer pattern 260A does not cover the cell area CA. Therefore, in various embodiments, a portion of the material layer pattern 260A disposed over the cell area CA may be substantially continuous or have a line pattern over the cell area.

[0076] Embodiments of the present disclosure can improve the reliability and performance characteristics of semiconductor memory while simplifying the production process.

[0077] Memory circuits and other semiconductor devices based on the disclosed technology can be used in a range of devices or systems. Figure 13-16 Some examples are provided of devices or systems that may implement the memory circuits disclosed herein.

[0078] Fig.13 is an example of a configuration diagram of a microprocessor that implements a storage circuit based on the disclosed technology.

[0079] Reference Fig.13, the microprocessor 1000 may perform tasks for controlling and adjusting a series of processes of receiving data from various external devices, processing the data, and outputting the processing results to the external devices. The microprocessor 1000 may include a storage unit 1010, an operation unit 1020, a control unit 1030, etc. The microprocessor 1000 may be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0080] The storage unit 1010 is a component that stores data in the microprocessor 1000 as a processor register, a register, etc. The storage unit 1010 may include various registers such as a data register, an address register, a floating point register, etc. The storage unit 1010 may perform functions of temporarily storing data to be operated on by the operation unit 1020, result data of the operation, and storing addresses of data used to perform the operation.

[0081] According to an embodiment, the memory cell 1010 may include one or more of the above-mentioned semiconductor devices. For example, the memory cell 1010 may include a substrate, which includes: a first region in which a plurality of variable resistance elements are arranged, a second region arranged on one side of the first region in a first direction, and a third region arranged on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines arranged on the substrate and extending across the first region and the second region in the first direction; a plurality of second lines arranged above the first line and extending across the first region and the third region in the second direction; a variable resistance element located at the intersection of the first line and the second line and between the first line and the second line; a contact plug, which is arranged in the third region and its upper end is coupled to the second line; and a material layer inserted between the second line and the variable resistance element in the first region and not present at a position between the second line and the contact plug in the third region, the material layer increasing the resistance of the variable resistance element. Thus, in the memory cell 1010, reliability and manufacturing process can be improved. As a result, the operating characteristics of the microprocessor 1000 are improved.

[0082] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and the like.

[0083] The control unit 1030 may receive signals from external devices of the microprocessor 1000 , the storage unit 1010 , and the operation unit 1020 , perform extraction, decoding of commands, and control input and output of signals of the microprocessor 1000 , and execute processing represented by a program.

[0084] The microprocessor 1000 according to the present embodiment may further include a cache memory unit 1040 that can temporarily store data to be input from or output to an external device other than the storage unit 1010. In this case, the cache memory unit 1040 can exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0085] Fig.14 is an example of a configuration diagram of a processor that implements a storage circuit based on the disclosed technology.

[0086] Reference Fig.14 , the processor 1100 may improve performance and realize multi-functions by including various functions in addition to the above-mentioned microprocessor 1000. The processor 1100 may include a core unit 1110 used as a microprocessor, a cache memory unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs) such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0087] The core unit 1110 of the present embodiment is a part that performs arithmetic logic operations on data input from an external device, and may include a storage unit 1111, an operation unit 1112, and a control unit 1113. The storage unit 1111, the operation unit 1112, and the control unit 1113 may be substantially the same as the storage unit 1010, the operation unit 1020, and the control unit 1030.

[0088] The cache memory unit 1120 is a part that temporarily stores data to compensate for the difference in data processing speed between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache memory unit 1120 may include a primary storage part 1121 and a secondary storage part 1122. In addition, in the case where a high storage capacity is required, the cache memory unit 1120 may include a tertiary storage part 1123. The cache memory unit 1120 may include a larger number of storage parts as required by the occasion. That is, the number of storage parts included in the cache memory unit 1120 may be changed according to the design. The speeds at which the primary, secondary, and tertiary storage parts 1121, 1122, and 1123 store and distinguish data may be the same or different. In the case where the speeds of the respective storage parts 1121, 1122, and 1123 are different, the speed of the primary storage part 1121 may be the largest. At least one storage part among the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit 1120 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the cache memory unit 1120 may include a substrate including a first region in which a plurality of variable resistance elements are arranged, a second region disposed on one side of the first region in a first direction, and a third region disposed on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines disposed on the substrate and extending across the first region and the second region in the first direction; a plurality of second lines disposed above the first lines and extending across the first region and the third region in the second direction; a variable resistance element located at an intersection of the first line and the second line and between the first line and the second line; a contact plug disposed in the third region and coupled to the second line at an upper end thereof; and a material layer inserted between the second line and the variable resistance element in the first region and not present at a location between the second line and the contact plug in the third region, the material layer increasing the resistance of the variable resistance element. Thus, reliability and manufacturing processes may be improved in the cache memory unit 1120. As a result, the operating characteristics of the processor 1100 are improved.

[0089] Although all of the primary, secondary and tertiary storage parts 1121, 1122 and 1123 are shown as being configured inside the high-speed cache memory unit 1120 in this embodiment, at least one of the primary, secondary and tertiary storage parts 1121, 1122 and 1123 of the high-speed cache memory unit 1120 can be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device can be compensated.

[0090] The bus interface 1130 is a portion that connects the core unit 1110 , the cache unit 1120 , and external devices and allows data to be efficiently transferred.

[0091] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the above-described core units 1110. The storage portion in each core unit 1110 may be configured to be shared with a storage portion outside the core unit 1110 through the bus interface 1130.

[0092] The processor 1100 according to the present embodiment may further include an embedded storage unit 1140 for storing data, a communication module unit 1150 that can send data to and receive data from an external device in a wired or wireless manner, a memory control unit 1160 that drives an external storage device, and a media processing unit 1170 that processes data processed in the processor 1100 or data input from an external input device and outputs the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of various modules and devices. In this case, the added plurality of modules may exchange data with the core unit 1110 and the cache memory unit 1120 and exchange data with each other through the bus interface 1130.

[0093] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), and memory having functions similar to the above memory, etc. Non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memory having similar functions.

[0094] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), etc., such as various devices that send and receive data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), etc., such as various devices that can send and receive data without a transmission line.

[0095] The memory control unit 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, for example, devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (International Personal Computer Memory Card Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC), Compact Flash (CF) Card, etc.

[0096] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external input device in the form of images, voices, and other forms, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), a high-definition multimedia interface (HDMI) controller, and the like.

[0097] Fig.15 is an example of a configuration diagram of a system that implements a storage circuit based on the disclosed technology.

[0098] Reference Fig.15, the system 1200 as a device for processing data can perform a series of operations on data by performing input, processing, output, communication, storage, etc. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems that use a processor to operate, such as computers, servers, PDAs (personal digital assistants), portable computers, web tablets, wireless phones, mobile phones, smart phones, digital music players, PMPs (portable multimedia players), cameras, global positioning systems (GPS), video cameras, voice recorders, telematics, audio-visual (AV) systems, smart TVs, etc.

[0099] The processor 1210 can decode input commands, perform operations such as calculations and comparisons on data stored in the system 1200, and control these operations. The processor 1210 can be substantially the same as the microprocessor 1000 or the processor 1100 described above.

[0100] The main memory device 1220 is a storage device that can temporarily store, call and execute program codes or data from the auxiliary memory device 1230 when executing a program, and can save the stored content even when the power is cut off. The auxiliary memory device 1230 is a storage device for storing program codes or data. Although the speed of the auxiliary memory device 1230 is slower than that of the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. According to the embodiment, the main memory device 1220 or the auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices. For example, the main memory device 1220 or the auxiliary memory device 1230 may include a substrate including a first region in which a plurality of variable resistance elements are arranged, a second region disposed on one side of the first region in a first direction, and a third region disposed on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines disposed on the substrate and extending across the first region and the second region in the first direction; a plurality of second lines disposed above the first lines and extending across the first region and the third region in the second direction; a variable resistance element located at an intersection of the first line and the second line and between the first line and the second line; a contact plug disposed in the third region and coupled to the second line at its upper end; and a material layer inserted between the second line and the variable resistance element in the first region and not present at a location between the second line and the contact plug in the third region, the material layer increasing the resistance of the variable resistance element. Thus, reliability and manufacturing processes may be improved in the main memory device 1220 or the auxiliary memory device 1230. As a result, the operating characteristics of the system 1200 may be improved.

[0101] In addition, the main memory device 1220 or the auxiliary memory device 1230 may include a memory system other than or excluding the above-mentioned semiconductor device (see Fig.16 1300).

[0102] The interface device 1240 can be used to execute commands and data exchanges between the system 1200 of this embodiment and external devices. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human interface devices (HIDs), a communication device, etc. The communication device can be substantially the same as the above-mentioned communication module unit 1150.

[0103] Fig.16 is an example of a configuration diagram of a memory system that implements a memory circuit based on the disclosed technology.

[0104] Reference Fig.16 , the storage system 1300 may include a memory 1310 having a non-volatile characteristic as a component for storing data, a controller 1320 for controlling the memory 1310, an interface 1330 for connecting with an external device, and a cache memory 1340 for temporarily storing data in order to effectively transfer data between the interface 1330 and the memory 1310. The storage system 1300 may simply represent a memory for storing data, and may also represent a data storage device for long-term preservation of stored data. The storage system 1300 may be a disk type and a card type, the disk type being such as a solid state drive (SSD), etc., and the card type being such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like.

[0105] According to an embodiment, the memory 1310 or the cache memory 1340 may include one or more of the above-mentioned semiconductor devices. For example, the memory 1310 or the cache memory 1340 may include a substrate including a first region in which a plurality of variable resistance elements are arranged, a second region disposed on one side of the first region in a first direction, and a third region disposed on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines disposed on the substrate and extending across the first region and the second region in the first direction; a plurality of second lines disposed above the first lines and extending across the first region and the third region in the second direction; a variable resistance element located at an intersection of the first line and the second line and between the first line and the second line; a contact plug disposed in the third region and coupled to the second line at its upper end; and a material layer inserted between the second line and the variable resistance element in the first region and not present at a location between the second line and the contact plug in the third region, the material layer increasing the resistance of the variable resistance element. Thus, reliability and manufacturing processes may be improved in the memory 1310 or the cache memory 1340. As a result, the operating characteristics of the memory system 1300 may be improved.

[0106] The memory 1310 or the cache memory 1340 may include various memories such as a nonvolatile memory or a volatile memory in addition to or without the above-mentioned semiconductor device.

[0107] The controller 1320 may control data exchange between the memory 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing an operation for processing a command input through the interface 1330 from the outside of the memory system 1300 or the like.

[0108] The interface 1330 will perform the exchange of commands and data between the memory system 1300 and the external device. In the case where the memory system 1300 is a card type or a disk type, the interface 1330 may be compatible with an interface used in a device having a card type or a disk type, or with an interface used in a device similar to the above devices. The interface 1330 may be compatible with one or more interfaces of different types from each other.

[0109] Based on the storage device disclosed in this document Figure 13-16 The features in the above examples of electronic devices or systems in the present invention can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebooks or laptop computers, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0110] Although the patent document contains many details, these details should not be interpreted as limitations on any invention or the scope of protection that can be claimed, but should be interpreted as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in the patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed, in some cases, one or more features in the claimed combination may be removed from the combination, and the claimed combination may be used for a sub-combination or a variation of the sub-combination.

[0111] Similarly, although operations are depicted in a particular order in the drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed to achieve the desired effect. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0112] Only some embodiments and examples are described. Other embodiments, enhancements, and variations may be made based on what is described and shown in this patent document.

Claims

1. An electronic device, comprising a semiconductor memory, wherein the semiconductor memory comprises: a substrate including a first region in which a plurality of variable resistance elements are arranged, a second region disposed on one side of the first region in a first direction, and a third region disposed on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines disposed over the substrate and extending across the first region and the second region in a first direction; a plurality of second lines disposed above the first lines and extending across the first region and the third region in a second direction; a variable resistance element located at an intersection of the first line and the second line and between the first line and the second line; a contact plug disposed in the third region and having an upper end coupled to the second line; a material layer interposed between the second line and the variable resistance element in the first region and not present in a portion between the second line and the contact plug in the third region, the material layer increasing the resistance of the variable resistance element; an interlayer insulating layer, the contact plug passing through the interlayer insulating layer, and The upper surface of the interlayer insulating layer in the third region decreases in height as it moves away from the first region.

2. The electronic device according to claim 1, wherein: The resistance of the material layer is greater than the resistance of the first line or the second line.

3. The electronic device according to claim 1, wherein: The material layer includes an insulating material, and As the applied voltage increases, the current flow through the material layer increases.

4. The electronic device according to claim 1, wherein: The material layer has a thickness of 5 angstroms to 50 angstroms.

5. The electronic device according to claim 1, wherein: A portion of the material layer covers the first region, and the portion of the material layer covering the first region has a substantially uniform thickness.

6. The electronic device according to claim 5, wherein: The material layer also covers an edge portion of the third region adjacent to the first region, and a middle portion of the third region is not covered by the material layer.

7. The electronic device according to claim 1, wherein: In the first region, the material layer has a line shape overlapping the second line.

8. The electronic device according to claim 7, wherein: The material layer also extends to an edge portion of the third region adjacent to the first region, and the material layer does not exist in a middle portion of the third region.

9. The electronic device according to claim 1, wherein: The second line and the contact plug are in direct contact with each other.

10. The electronic device according to claim 1, wherein: The thickness of the material layer in the first region is constant, and The thickness of the material layer in the third region is not uniform.

11. The electronic device according to claim 1, wherein: A thickness of at least a portion of the second line in the third region is greater than a thickness of the second line in the first region.

12. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: a substrate including a first region in which a plurality of variable resistance elements are arranged, a second region disposed on one side of the first region in a first direction, and a third region disposed on the other side of the first region in a second direction intersecting the first direction; a plurality of first lines disposed above the substrate and extending across the first region and the second region in a first direction; a plurality of second lines disposed above the first lines and extending across the first region and the third region in a second direction; a variable resistance element located at an intersection of the first line and the second line and between the first line and the second line; a contact plug disposed in the third region and having an upper end coupled to the second line; as well as a material layer, which is interposed between the second line and the variable resistance element in the first region and extends to the third region, the material layer increasing the resistance of the variable resistance element, The thickness of the material layer in the first region is constant, and the thickness of the material layer in the third region is inconsistent.

13. The electronic device according to claim 12, wherein: The resistance of the material layer is greater than the resistance of the first line and the resistance of the second line.

14. The electronic device according to claim 12, wherein: The material layer includes an insulating material, and As the applied voltage increases, the current flow through the material layer increases.

15. The electronic device according to claim 12, wherein: The material layer has a thickness of 5 angstroms to 50 angstroms.

16. The electronic device according to claim 12, wherein: A portion of the material layer covers the first region, and the portion of the material layer covering the first region has a substantially uniform thickness.

17. The electronic device according to claim 16, wherein: The material layer also covers an edge portion of the third region adjacent to the first region, and a middle portion of the third region is not covered by the material layer.

18. The electronic device according to claim 12, wherein: In the first region, the material layer has a line shape overlapping the second line.

19. The electronic device according to claim 18, wherein: The material layer extends to an edge portion of the third region adjacent to the first region, and the material layer does not exist in a middle portion of the third region.

20. The electronic device according to claim 12, wherein: The semiconductor memory further comprises: an interlayer insulating layer, the contact plug passing through the interlayer insulating layer, and The upper surface of the interlayer insulating layer in the third region decreases in height as it moves away from the first region.

21. The electronic device according to claim 12, wherein: The second line and the contact plug are in direct contact with each other.

22. The electronic device according to claim 12, wherein: A thickness of a thinnest portion of the second line in the third region is greater than a thickness of a thinnest portion of the second line in the first region.

23. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: providing a substrate including a first region, a second region disposed on one side of the first region in a first direction, and a third region disposed on the other side of the first region in a second direction intersecting the first direction; forming a plurality of first lines extending across the first region and the second region in a first direction over the substrate; forming a plurality of variable resistance elements over the first line in the first region; forming an interlayer insulating layer filling a space between the variable resistance elements; forming a contact plug passing through the interlayer insulating layer in the third region; forming a material layer covering the variable resistance element, the interlayer insulating layer and the contact plug, the material layer increasing the resistance of the variable resistance element; removing a portion of the material layer disposed above the contact plug to form a material layer pattern; as well as forming a plurality of second lines over the material layer pattern and the contact plugs, the plurality of second lines extending across the first region and the third region in a second direction; The upper surface of the interlayer insulating layer in the third region decreases in height as it moves away from the first region.

24. The method according to claim 23, wherein: Removing a portion of the material layer is performed by a planarization process.

25. The method according to claim 24, wherein the planarization process is a chemical mechanical polishing process (CMP).

26. The method according to claim 24, wherein: The pattern density of the first region is greater than the pattern density of the third region, and The removal rate of the material layer in the third region is greater than the removal rate of the material layer in the first region.

27. The method according to claim 24, wherein: When a portion of the material layer is removed, a portion of the interlayer insulating layer and a portion of the contact plug in the third region are removed.

28. The method of claim 23, wherein: The variable resistance element has a line shape overlapping the first line, and the method further includes: After forming the second line, the variable resistance element and the portion of the material layer pattern exposed by the second line are etched.

29. The method of claim 23, wherein: The variable resistance elements are located at intersections of the first line and the second line, and each of the variable resistance elements has an island shape.

30. The method of claim 23, further comprising: After forming the second line, a portion of the material layer pattern exposed by the second line is etched.

31. The method of claim 23, wherein: The material layer includes an insulating material, and As the applied voltage increases, the current flow through the material layer increases.

32. The method of claim 23, wherein: The material layer has a thickness of 5 angstroms to 50 angstroms.

33. The method of claim 23, wherein: A portion of the material layer pattern covers the first region, and the portion of the material layer pattern covering the first region has a substantially uniform thickness.

34. The method of claim 33, wherein: The material layer pattern covers an edge portion of the third region adjacent to the first region, and a middle portion of the third region is not covered by the material layer pattern.

35. The method of claim 23, wherein: In the first region, the material layer pattern has a line shape overlapping the second line.

36. The method of claim 23, wherein: The material layer pattern extends to an edge portion of the third region adjacent to the first region, and the material layer pattern does not exist in a middle portion of the third region.

37. The method of claim 23, further comprising: Before forming the first line, another contact plug disposed under the first line and coupled to the first line is formed.

38. The method of claim 23, wherein: The second line and the contact plug are in direct contact with each other.

39. The method of claim 23, wherein: The third region occupies a larger area than the second region.

40. The method of claim 23, wherein: The thickness of the material layer pattern in the first region is constant, and The thickness of the material layer pattern in the third region is not uniform.

41. The method of claim 23, wherein: A thickness of a thinnest portion of the second line in the third region is greater than a thickness of a thinnest portion of the second line in the first region.

42. The method of claim 23, wherein: The variable resistance element includes a variable resistance layer and a selection element layer electrically coupled to the variable resistance layer.

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