Methods for forming doped semiconductor layers

Abstract

The present invention relates to a method for obtaining a doped semiconductor layer, comprising the following sequential steps: a) implanting ions of a first dopant element B and a second undoped element C of a semiconductor alloy, which is made of at least a first element A1 and a second element A2, into a first single crystal layer to amorphize the upper part of the first layer and maintain the crystal structure of the lower part of the first layer; and b) subjecting the upper part of the first layer to solid-state recrystallization annealing, thereby transforming the upper part of the first layer into a doped single crystal layer of the alloy.

Description

Technical Field

[0001] This disclosure relates to a method for obtaining a doped semiconductor layer, and more particularly to a method for forming a light-emitting device. Background Technology

[0002] Light-emitting devices typically include one or more light-emitting cells capable of converting electrical signals into light radiation. Each light-emitting cell may comprise a stack of a P-type semiconductor layer (called the anode layer), an active layer, and an N-type doped semiconductor layer (called the cathode layer). The anode semiconductor layer is electrically connected to the anode of the cell, and the cathode semiconductor layer is electrically connected to the cathode of the cell. During operation, a current is applied between the semiconductor anode and cathode layers of the cell via the anode and cathode layers. Under the influence of this current, the active layer emits light within a certain wavelength range, which is substantially dependent on its composition.

[0003] On the one hand, to limit the contact resistance between the anode and the anode semiconductor layer, and / or on the other hand, to limit the contact resistance between the cathode and the cathode semiconductor layer, it is desirable to dope the anode and / or cathode semiconductor layers to a relatively high level. However, depending on the type of semiconductor material used to form the anode and cathode layers, doping can be difficult. In particular, it is difficult to implant semiconductor materials with large band gaps, especially III-V type semiconductor materials, into the anode and / or cathode layers, which are also very suitable for forming light-emitting cells.

[0004] A method for obtaining a doped semiconductor layer is desired, which overcomes all or part of the drawbacks of known doping methods. Summary of the Invention

[0005] To achieve this goal, the embodiment provides a method for obtaining a doped semiconductor layer, comprising the following sequential steps:

[0006] a) In a first single-crystal layer made of a semiconductor alloy having at least a first element A1 and a second element A2, ion implantation is performed on a first dopant element B and a second undoped element C of the alloy, thereby amorphizing the upper part of the first layer while maintaining the crystal structure of the lower part of the first layer; and

[0007] b) Perform solid-state recrystallization annealing on the upper part of the first layer to transform the upper part of the first layer into a doped single-crystal layer of the alloy.

[0008] In this process, dopant element B and undoped element C replace atoms of element A1.

[0009] According to one embodiment, during step a), the protective layer covers the upper surface of the first layer.

[0010] According to one embodiment, during step a), the injection conditions are selected such that the lower part of the first layer has a thickness less than one-fifth of the thickness of the first layer.

[0011] According to one embodiment, during step a), the injection conditions are selected such that the lower portion of the first layer has a thickness in the range of 2 to 10 nm.

[0012] According to one embodiment, during step a), a supplementary injection of element A2 is performed to compensate for the addition of elements B and C.

[0013] According to one embodiment, while selecting the undoped element C, the ratio of the covalent radius of element A1 to the covalent radius of the doped element B is considered, and at the end of step b), a generally stress-free unit cell is obtained.

[0014] According to one embodiment, when the covalent radius of dopant element B is greater than the covalent radius of element A1, an undoped element C with a covalent radius less than or equal to the covalent radius of element A1 is selected; and when the covalent radius of dopant element B is less than the covalent radius of element A1, an undoped element C with a covalent radius greater than or equal to the covalent radius of element A1 is selected.

[0015] According to one embodiment, elements A1 and A2 are Group III and Group V elements, respectively, and element B is a Group II or Group IV element, and element C is a Group III element.

[0016] According to the embodiment, element A1 and element A2 are gallium and nitrogen, respectively.

[0017] According to the embodiment, element B and element C are magnesium and aluminum, respectively.

[0018] According to the embodiment, element B and element C are silicon and indium, respectively.

[0019] According to the embodiments, elements A1 and A2 are silicon and carbon, respectively, and elements B and C are boron and germanium, respectively, or elements B and C are arsenic and carbon, respectively.

[0020] According to an embodiment, in step b), the solid-phase recrystallization annealing is carried out in a temperature range of 300 to 1200°C.

[0021] According to an example, solid-phase recrystallization annealing is performed at approximately 400°C. Attached Figure Description

[0022] The above features and advantages, as well as others, will be described in detail with reference to the specific embodiments given in the accompanying drawings, which are illustrated but not limited in scope, wherein:

[0023] Figure 1A The steps of a method for obtaining a doped semiconductor layer according to an embodiment are illustrated schematically;

[0024] Figure 1B The illustration schematically shows another step in the method for obtaining a doped semiconductor layer according to an embodiment; and

[0025] Figure 1C A method for obtaining a doped semiconductor layer according to an embodiment is illustrated schematically. Detailed Implementation

[0026] In the various illustrations, similar features are designated by similar reference numerals. In particular, features of common structure and / or function in various embodiments may have the same reference numerals and may deal with the same structural, dimensional, and material properties.

[0027] For clarity, only the steps and elements useful for understanding the embodiments described herein are detailed and described. In particular, the following description relates primarily to obtaining a doped semiconductor layer. Different structures that can be used for this layer have not been described in detail. Furthermore, the steps that can be performed before or after the formation of the doped layer to obtain such a structure have not been described in detail.

[0028] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements may be connected, or they may be coupled through one or more other elements.

[0029] In the following disclosure, unless otherwise specified, when referring to absolute positional qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative positional qualifiers such as “above,” “below,” “higher than,” “lower than,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc., it refers to the orientation shown in the attached figure.

[0030] Unless otherwise specified, the terms “approximately,” “about,” “generally,” and “roughly” indicate within 10%, and preferably within 5%.

[0031] Figures 1A to 1C This is a cross-sectional view illustrating the sequential steps of an example method for obtaining a doped semiconductor layer according to an embodiment.

[0032] In this example, consider forming a light-emitting cell stack, which includes: a first semiconductor layer 101 of a first conductivity type forming an anode or cathode layer of the cell, an active layer 103, and a second doped semiconductor layer 105 of a second conductivity type forming a cathode or anode layer of the cell. For example, layers 101 and 105 are example layers of a III-V semiconductor material, such as gallium nitride layers. For example, active layer 103 includes confinement devices corresponding to a plurality of quantum wells. As an example, active layer 103 is formed by alternating semiconductor layers of a first material and semiconductor layers of a second material, each layer of the first material sandwiched between two layers of the second material, the first material having a narrower bandgap than the second material to define a plurality of quantum wells. For example, layers 101, 103, and 105 are formed epitaxially. The stack of layers 101, 103, and 105 is arranged on a support substrate 107, for example, made of sapphire or silicon. A stack 109 of one or more buffer layers may form an interface between the substrate 107 and the stack of layers 101, 103, and 105. In the example shown, stack 109 is disposed on and in contact with the upper surface of substrate 107, layer 101 is disposed on and in contact with the upper surface of stack 109, layer 103 is disposed on and in contact with the upper surface of layer 101, and layer 105 is disposed on and in contact with the upper surface of layer 103.

[0033] The doping of the stacked upper semiconductor layer 105 is given special consideration here.

[0034] Figure 1A The diagram illustrates an insulating protective layer 111 (e.g., made of silicon nitride (Si3N4)) deposited on the upper surface side of layer 105, for example, at the end of a step that contacts the upper surface of layer 105. For example, layer 111 extends over the entire surface of layer 105. For example, the thickness of layer 111 is in the range of 5 to 500 nm, and preferably in the range of 10 to 50 nm, for example, approximately 20 nm. At this stage, layer 105 can be an undoped layer. As a variation, layer 105 may have been previously doped in situ during its epitaxial growth. In this case, it is desirable to increase the doping level of layer 105.

[0035] Figure 1B The step of ion implantation in semiconductor layer 105 via protective layer 111 for a material in layer 105 that is a dopant element is illustrated. During this step, as will be explained in further detail later, the material implanted into layer 105 is not a dopant element, and preferably no intermediate annealing step is performed to limit the stress introduced by the dopant element at the unit cell level.

[0036] The implantation energy and dose of dopant and undoped elements are selected based on the desired doping distribution. The implantation energy and dose are further selected to achieve complete amorphization of the upper portion 105a of layer 105 while maintaining the original crystal reference in the lower portion 105b of layer 105. Preferably, the thickness of the lower reference single-crystal layer 105b is relatively small to allow for the elimination of possible dislocations or other crystal defects in a subsequent recrystallization annealing step of layer 105a. In one example, the thickness of the lower reference single-crystal layer 105b is less than half the thickness of the original layer 105, for example, less than one-fifth of the thickness of the original layer 105. In one example, the thickness of the lower reference single-crystal layer 105b is between 2 and 100 nm, preferably between 2 and 10 nm. For example, layer 105 has a thickness ranging from 10 to 500 nm, for example, from 100 to 400 nm.

[0037] The protective layer 111 is particularly capable of protecting the layer 105 from sputtering during ion implantation of doped and undoped elements.

[0038] Figure 1C It shows in Figure 1A and 1B The final step of the process involves annealing the structure obtained, resulting in solid-state recrystallization of the upper layer 105a of the first layer 105. For example, the annealing is performed at a temperature range of 300 to 1200°C. The duration of the recrystallization annealing is, for example, between 1 minute and 10 hours. Preferably, the annealing is performed at a low temperature, for example, at approximately 400°C for approximately 1 hour. During this step, the recrystallization of layer 105a is obtained. A crystal reference is provided by the underlying single-crystal layer 105b. At the end of this step, a doped crystalline semiconductor layer 105a is obtained. The doping level of layer 105a depends on… Figure 1B The dose of dopant injected into the sample.

[0039] The 111 protective layer can be removed after annealing. Alternatively, the 111 layer can be removed before annealing. Subsequent steps (not detailed) can then be performed to form one or more light-emitting unit cells from the resulting structure. Specifically, an electrode deposition step on and in contact with the 105a layer can be provided.

[0040] Figures 1A to 1C The doping method described herein is particularly advantageous for the doping of III-V type semiconductor materials. However, this method is applicable to the doping of other semiconductor alloys, and especially to semiconductor alloys with large band gaps, such as greater than 1.5 eV and preferably greater than 3 eV.

[0041] Generally, layer 105 can be a single-crystal layer of an alloy having at least one first element (hereinafter referred to as element A1, such as a group III element) and one second element (hereinafter referred to as element A2, such as a group V element). Figure 1B The dopant element injected in this step, hereinafter referred to as element B, can be a p-type or n-type dopant element. In one example, dopant element B is intended to replace an atom of element A1 in the initial alloy to obtain p-type or n-type doping. When alloying element A1 is a group III element, dopant element B can be a group II element to obtain p-type doping or a group IV element to obtain n-type doping. The covalent radius of dopant element B can be different from the covalent radius of the substituted element A1. The choice of... Figure 1B In this step, an undoped element (hereinafter referred to as element C) is injected to compensate for the stress introduced at the unit cell level by the dopant level B. In one example, if the dopant element B has a covalent radius smaller than that of the substituted element A1, then an element belonging to the same group as element A1 with a covalent radius greater than or equal to that of element A1, and preferably greater than that of element A1, can be selected as the undoped element C. Conversely, if the dopant element B has a covalent radius larger than that of the substituted element A1, then an element belonging to the same group as element A1 with a covalent radius less than or equal to that of element A1, and preferably less than that of element A1, can be selected as the undoped element C.

[0042] exist Figure 1B During the injection step, atoms of element A2 from the initial alloy, in addition to elements B and C, can be injected. Preferably, there is no intermediate annealing step to compensate for the addition of elements B and C and to maintain the general stoichiometry of the material.

[0043] Figure 1B The implantation dose of dopant element B during the step is preferably relatively high, for example, greater than 10. 20 atoms / cm 3 This facilitates the amorphization of the upper part 105a of layer 105.

[0044] Now will describe Figures 1A to 1C The method is applied to an example of gallium nitride (GaN) layer doping. In this case, the initial semiconductor layer 105 is a single-crystal GaN layer. The elements A1 and A2 of the semiconductor alloy forming the initial layer 105 are gallium (Ga) and nitrogen (N), respectively. The layer 105 desired at the end of the process is C. y B x Ga 1-x-yN layers are defined, where x and y define the concentrations of dopant element B and undoped element C in the final layer, respectively. Dopant element B must replace gallium (Ga). The concentration x of dopant element B is chosen to obtain the desired doping level. Based on the covalent radius of dopant element B and the concentration x of dopant element B, the concentrations y of undoped element C and undoped element C are chosen to finally obtain a general unstressed layer 105a.

[0045] As an example, choose concentrations x and y to follow the mixing rules below:

[0046] [Formula 1]

[0047] a*x+b*y=0

[0048] in:

[0049] [Formula 2]

[0050]

[0051] as well as:

[0052] [Formula 3]

[0053]

[0054] RB, RC, and Rh refer to the covalent radii of elements B, C, and Al (Ga in this example), respectively, while S refers to the site concentration in the main matrix, i.e., the number of gallium atoms in the initial unit cell of layer 105.

[0055] More generally, in order to constrain the concentration y of the undoped element C, other mixing rules can be constrained based on stress modeling of crystalline semiconductor alloys.

[0056] exist Figure 1C In the co-implantation step, in addition to elements B and C, nitrogen (element A2) is also injected (preferably without an intermediate annealing step) to compensate for the addition of elements B and C and to maintain the general stoichiometry of the material. Without the co-implantation of nitrogen, the stoichiometry of the final layer 105a would be C. y B x Ga 1-x-y N 1-x-y To compensate for the injection of elements B and C, a co-injection of nitrogen at a concentration of z = x + y is provided.

[0057] P-doping case:

[0058] To obtain the p-type doped layer 105a, in Figure 1BThe dopant element B implanted in this step can be a group II element, such as magnesium (Mg), beryllium (Be), zinc (Zn), or calcium (Ca). The undoped element C can be an element from the same group as gallium, i.e., a group III element, such as aluminum or indium. Magnesium is preferred as the dopant element B. When magnesium is the dopant element B, aluminum is preferred as the undoped element C. In fact, magnesium has a larger covalent radius than gallium, while aluminum has a smaller covalent radius than gallium, which allows for stress balance within the unit cell.

[0059] As an example, the injected magnesium dose is approximately 3 x 10⁻⁶. 15 atoms / cm 2 The injection energy was approximately 23 keV, and the aluminum injection dose was approximately 4.6 × 10⁻⁶. 15 atoms / cm 2 The injected energy was approximately 120 keV, and the nitrogen injection dose was approximately 9.6 × 10⁻⁶. 15 atoms / cm 2 The injected energy is approximately 15 keV.

[0060] N-doped case:

[0061] To obtain the N-type doped layer 105, in Figure 1B The dopant element B implanted in this step can be a group IV element, such as silicon (Si), germanium (Ge), or carbon (C), while the undoped element C can be an element from the same group as gallium, i.e., a group III element, such as aluminum or indium. Dopant element B is preferably silicon. When dopant element B is silicon, the undoped element C is preferably indium. In fact, silicon has a smaller covalent radius than gallium, while indium has a larger covalent radius than gallium, which allows for stress balance within the unit cell.

[0062] Those skilled in the art will be able to apply the above methods to the doping of other semiconductor alloys. For example, in the case where layer 105 is made of silicon carbide (SiC), elements A1 and A2 are silicon (Si) and carbon (C), respectively. To obtain P-type doping, the dopant element B can be a group II element, such as boron (B), and the undoped element C can be a group III element, such as germanium. To obtain N-type doping, the dopant element B can be a group IV element, such as arsenic, and the undoped element C can be a group III element, such as carbon.

[0063] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will be readily available to those skilled in the art. In particular, the described embodiments are not limited to examples of the materials or numerical values ​​mentioned in the specification.

[0064] Furthermore, although examples of applying doping methods to the formation of light-emitting unit cells have been described above, these embodiments are not limited to this particular application. As a variation, the method for obtaining the doped semiconductor layer described above can be used in other applications, such as for forming semiconductor power devices (transistors, diodes, etc.).

[0065] The changes, modifications, and improvements described herein will become part of this disclosure and are intended to conform to the spirit and scope of the invention. Therefore, the above description is by way of example only and is not intended to be limiting. The invention is limited to what is defined in the claims and their equivalents.

Claims

1. A method for obtaining a doped semiconductor layer, comprising the following sequential steps: a) Ion implantation of a first dopant element B and a second undoped element C of a semiconductor alloy made of at least a first element A1 and a second element A2 into a first single crystal layer, thereby amorphizing the upper part of the first single crystal layer while maintaining the crystal structure of the lower part of the first single crystal layer; and b) Perform solid-state recrystallization annealing on the upper part of the first single crystal layer, thereby transforming the upper part of the first single crystal layer into a doped single crystal layer of the alloy. Wherein, the first dopant element B and the second undoped element C replace atoms of the first element A1. in, During step a), a supplemental implantation of the second element A2 is performed to compensate for the addition of the first dopant element B and the second undoped element C. The second undoped element C is in the same group as the first element A1. Wherein, when the covalent radius of the first dopant element B is greater than the covalent radius of the first element A1, the second undoped element C with a covalent radius less than the covalent radius of the first element A1 is selected; and when the covalent radius of the first dopant element B is less than the covalent radius of the first element A1, the second undoped element C with a covalent radius greater than the covalent radius of the first element A1 is selected.

2. The method according to claim 1, wherein, During step a), a protective layer covers the upper surface of the first monocrystalline layer.

3. The method according to claim 1, wherein, During step a), the implantation conditions are selected such that the lower part of the first single crystal layer has a thickness less than one-fifth of the thickness of the first single crystal layer.

4. The method according to claim 1, wherein, During step a), the implantation conditions are selected such that the lower part of the first single crystal layer has a thickness in the range of 2 to 10 nm.

5. The method according to claim 1, wherein, The second undoped element C is selected, while taking into account the ratio of the covalent radius of the first element A1 to the covalent radius of the first doped element B, so that a stress-free unit cell is obtained at the end of step b).

6. The method according to claim 1, wherein, The first element A1 and the second element A2 are respectively a group III element and a group V element, wherein the first dopant element B is a group II element or a group IV element, and the second undoped element C is a group III element.

7. The method according to claim 6, wherein the first element A1 and the second element A2 are gallium and nitrogen, respectively.

8. The method according to claim 7, wherein the first dopant element B and the second undoped element C are magnesium and aluminum, respectively.

9. The method according to claim 7, wherein the first dopant element B and the second undoped element C are silicon and indium, respectively.

10. The method according to claim 1, wherein the first element A1 and the second element A2 are silicon and carbon, respectively, and wherein the first dopant element B and the second undoped element C are boron or germanium, respectively, or wherein the first dopant element B and the second undoped element C are arsenic and carbon, respectively.

11. The method according to claim 1, wherein, In step b), the solid-phase recrystallization annealing is carried out in a temperature range of 300 to 1200°C.

12. The method according to claim 1, wherein, The solid-state recrystallization annealing is carried out at approximately 400°C.

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