Semiconductor device including variable resistance element

Abstract

The present disclosure provides a semiconductor device including a variable resistance device. The variable resistance element according to one embodiment of the present disclosure includes: an ion receiving layer having a top, a bottom, and a side wall connecting the top and the bottom; an ion supply layer having an inner side wall connected to at least a portion of the side wall of the ion receiving layer; a gate pattern connected to the outer side wall of the ion supply layer; and a source pattern connected to one of the top or the bottom of the ion receiving layer, and a drain pattern connected to the other of the top or the bottom of the ion receiving layer, wherein the resistance of the ion receiving layer changes according to the amount of ions supplied from the ion supply layer based on the voltage applied to the gate pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0165406, filed on December 12, 2019, which is hereby incorporated by reference in its entirety into this application. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to a variable resistance element and a semiconductor device including the variable resistance element. Background Art

[0004] As electronic devices develop towards miniaturization, low power consumption, high performance, and diversification, technologies that can efficiently process large amounts of information are needed. In particular, there is growing interest in neuromorphic technology that mimics the human nervous system in electronic devices. The human nervous system contains hundreds of billions of neurons and synapses, and synapses are the connections between neurons. Neuromorphic technology aims to realize neuromorphic devices by designing neuronal circuits and synaptic circuits that correspond to biological neurons and synapses. The neuromorphic device can be used in a variety of applications, including data classification, pattern recognition, etc. Summary of the invention

[0005] Various embodiments relate to a variable resistance element having characteristics suitable for use as a synapse in a neuromorphic device, and a semiconductor device including the variable resistance element.

[0006] In one embodiment, a semiconductor device includes at least one variable resistance element, the variable resistance element including: an ion receiving layer having a top, a bottom, and a sidewall connecting the top and the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the sidewall of the ion receiving layer; a gate pattern connected to the outer sidewall of the ion supply layer; and a source pattern connected to one of the top or the bottom of the ion receiving layer, and a drain pattern connected to the other of the top or the bottom of the ion receiving layer, wherein the resistance of the ion receiving layer changes according to the amount of ions supplied from the ion supply layer based on a voltage applied to the gate pattern.

[0007] In another embodiment, a semiconductor device includes at least one variable resistance element, the variable resistance element comprising: an ion supply layer having a top, a bottom, and a sidewall connecting the top and the bottom; an ion receiving layer having an inner sidewall connected to at least a portion of the sidewall of the ion supply layer; a gate pattern connected to the outer sidewall of the ion receiving layer; and a source pattern connected to one of the top or the bottom of the ion supply layer, and a drain pattern connected to the other of the top or the bottom of the ion supply layer, wherein the resistance of the ion supply layer changes according to the amount of ions supplied from the ion supply layer to the ion receiving layer in response to a voltage applied to the gate pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 The conductivity of a synapse according to the number of electrical pulses input to the synapse of a neuromorphic device is shown.

[0009] Figure 2A and Figure 2B are a cross-sectional view and a plan view illustrating a variable resistance element according to an embodiment of the present disclosure.

[0010] Figure 3 is an example Figure 2A and Figure 2B A view showing the operating method of the variable resistance element.

[0011] Figure 4A and Figure 4B are a plan view and a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5 is a plan view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0013] Fig. 6A is a cross-sectional view illustrating a variable resistance element according to another embodiment of the present disclosure.

[0014] Figure 6B is a cross-sectional view illustrating a variable resistance element according to still another embodiment of the present disclosure.

[0015] Figure 7 is a cross-sectional view illustrating a variable resistance element according to still another embodiment of the present disclosure.

[0016] Figure 8 is an example Figure 7 A view of the operating method of the variable resistance element.

[0017] Fig. 9 is a cross-sectional view illustrating a variable resistance element according to still another embodiment of the present disclosure.

[0018] Fig.10 is an example illustrating a pattern recognition system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Various embodiments will be described in detail below with reference to the accompanying drawings.

[0020] The drawings are not necessarily drawn to scale, and in some cases, the proportions of at least some of the structures in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments. When a multilayer structure is disclosed in the drawings or detailed description, the relative positional relationship of the layers shown or the arrangement order of the layers reflects the specific implementation of the described or illustrated example, and therefore, the present disclosure is not limited thereto, and the relative positional relationship or arrangement order of the layers may be changed. In addition, the described or illustrated examples of multilayer structures may not reflect all the layers present in a specific multilayer structure (for example, one or more additional layers may exist between two illustrated layers). For example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, it may not only represent a structure in which the first layer can be directly formed on the second layer or substrate, but also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or between the first layer and the substrate.

[0021] Embodiments of the present disclosure are intended to provide a variable resistance element having characteristics suitable for use as a synapse in a neuromorphic device. However, it should be understood that the variable resistance element according to embodiments of the present disclosure can be used not only in neuromorphic devices, but also in various semiconductor devices, such as memory devices. Before describing the variable resistance element according to embodiments of the present disclosure, the characteristics of the device suitable for use as a synapse in a neuromorphic device will be described.

[0022] In general, a variable resistance element used as a storage element in a memory device can switch between a high resistance state and a low resistance state through a set operation and a reset operation. The variable resistance element may preferably have a low resistance state and a high resistance state, and since a sudden resistance change occurs during the set operation and the reset operation, the low resistance state and the high resistance state can be clearly distinguished from each other. Even if an electric pulse is repeatedly applied to the variable resistance element, the element can maintain its own resistance state until the set operation and the reset operation are performed. The variable resistance element can use these characteristics to store different data.

[0023] In contrast, the variable resistance element preferably used as a synapse in a neuromorphic device does not undergo an abrupt resistance change between a set operation and a reset operation, but rather exhibits an analog behavior in which the conductivity and / or resistance gradually changes according to the number of input electrical pulses. This analog behavior improves various operational characteristics of the neuromorphic device, such as improving the accuracy of learning and recognition. In the following, reference will be made to Figure 1 A more detailed description is given.

[0024] Figure 1 The conductivity of a synapse according to the number of electrical pulses input to the synapse of a neuromorphic device is shown.

[0025] refer to Figure 1 When a first polarity voltage pulse (e.g., a negative voltage pulse having a voltage equal to or higher than a certain critical value) is repeatedly applied to a synapse in a low resistance state, the conductivity (G) of the synapse may gradually increase. The direction in which the conductivity (G) of the synapse increases may be referred to as a G+ direction or a potentiation direction.

[0026] When a second polarity voltage pulse (eg, a positive voltage pulse having a voltage equal to or higher than the reset voltage) is applied to the synapse, a reset operation may be performed in which the resistance state of the synapse changes to a high resistance state.

[0027] When the second polarity voltage pulse is repeatedly applied to the synapse in the high resistance state, the conductivity (G) of the synapse may gradually decrease. The direction in which the conductivity (G) of the synapse decreases may be referred to as the G-direction or the depression direction.

[0028] When a first polarity voltage pulse having a voltage equal to or higher than the set voltage is applied to the synapse again, a set operation may be performed, and the resistance state of the synapse changes to a low resistance state.

[0029] Preferably, the rate of change of the synaptic conductivity (G) is substantially constant during both the potentiation and inhibition operations, and Figure 1 As shown, the synapse exhibits essentially symmetric conductivity (G) characteristics around the set or reset point.

[0030] In summary, compared with a variable resistance element that switches suddenly between a high resistance state and a low resistance state, it may be preferable that the conductivity (G) of the synapse changes gradually (i.e., has three or more multiple levels). The conductivity (G) of the synapse in the enhancement operation and the inhibition operation may preferably have linearity and symmetry.

[0031] In the following, reference will be made to Figure 2A , Figure 2B and Figure 3 A variable resistance element having a structure suitable for use as a synapse having the above-described characteristics, and a method of operating the variable resistance element will be described.

[0032] Figure 2A and Figure 2B are a cross-sectional view and a plan view illustrating a variable resistance element according to an embodiment of the present disclosure. Figure 2B is along Figure 2A A plan view taken along line H1-H1'.

[0033] refer to Figure 2A and Figure 2B According to an embodiment of the present disclosure, the variable resistance element may include: a columnar ion receiving layer 120 extending in a vertical direction; an ion supply layer 130 surrounding the sidewalls of the ion receiving layer 120; a gate pattern 140 surrounding the sidewalls of the ion supply layer 130; a source pattern 110 connected to the bottom of the ion receiving layer 120; and a drain pattern 150 connected to the top of the ion receiving layer 120.

[0034] The ion receiving layer 120 may include a material that, when receiving cations (particularly metal cations) from the ion supply layer 130, may enter an oxygen-deficient state to form oxygen vacancies. For example, the ion receiving layer 120 may include an electrolyte material, an electrochromic material, a lithium (Li)-based oxide, a transition metal oxide (such as LiPON, LiCoO2, LiFePO4, LiMn2O4, and M2O4). x ), perovskite materials (such as WO3, MoO3 and SrTiO3), etc. Oxygen vacancies act as donor defects. Therefore, as the amount of oxygen vacancies increases, the conductivity of the ion receiving layer 120 may increase, and as the amount of oxygen vacancies decreases, the conductivity of the ion receiving layer 120 may decrease. That is, the resistance of the ion receiving layer 120 may vary according to the amount of oxygen vacancies in the ion receiving layer 120.

[0035] The ion supply layer 130 may include a material that supplies cations (particularly metal cations) to the ion receiving layer 120. For example, the ion supply layer 130 may include a Li-based oxide, a transition metal oxide (such as LiPON, LiCoO2, LiFePO4, LiMn2O4, and M2O4). x ), perovskite materials (such as WO3, MoO3 and SrTiO3), etc. Specifically, the ion supply layer 130 may be formed of a material different from the ion receiving layer 120, and may include a material having a greater metal ion content than the ion receiving layer 120. In one embodiment, the ion supply layer 130 may have a shape of an outer sidewall surrounding the ion receiving layer 120. However, the present disclosure is not limited thereto, and the shape of the ion supply layer 130 may be variously modified so that the ion supply layer 130 contacts at least a portion of the sidewall of the ion receiving layer 120 and provides a smooth or uninterrupted ion supply to the ion receiving layer 120.

[0036] The gate pattern 140 may be used to control the movement of ions from the ion supply layer 130 to the ion receiving layer 120 in response to certain received voltages. The gate pattern 140 may include various conductive materials, such as metals, metal nitrides, or combinations thereof. In one embodiment, the gate pattern 140 may have a shape that surrounds the outer sidewall of the ion supply layer 130; the inner sidewall of the ion supply layer 130 may refer to a sidewall that contacts the sidewall of the ion receiving layer 120, and the outer sidewall of the ion supply layer 130 may refer to a sidewall opposite to the inner sidewall. However, the present disclosure is not limited thereto, and in other embodiments, the shape of the gate pattern 140 may be variously modified so that the gate pattern 140 contacts at least a portion of the outer sidewall of the ion supply layer 130, and the gate pattern 140 controls the movement of ions from the ion supply layer 130 to the ion receiving layer 120 to allow a smooth transition between multiple resistance states.

[0037] The source pattern 110 and the drain pattern 150 are connected to the bottom and top of the ion receiving layer 120, respectively, and the resistance change of the ion receiving layer 120 can be read by these patterns. The source pattern 110 and the drain pattern 150 may include various conductive materials, such as metals, metal nitrides, or a combination thereof. In one embodiment, the source pattern 110 and the drain pattern 150 are shown to have a rectangular cross-sectional shape, but in other embodiments, the shapes of the drain pattern and the source pattern may be variously modified. The source pattern 110 and the drain pattern 150 may be connected to the bottom and top of the ion receiving layer 120, respectively, through a source contact 115 and a drain contact 155. As will be described later, for ease of processing, etc., the source contact 115 and the drain contact 155 may be respectively between the source pattern 110 and the ion receiving layer 120, and between the drain pattern 150 and the ion receiving layer 120. The source contact 115 and the drain contact 155 may have a columnar shape. However, the present disclosure is not limited thereto, and in other embodiments, the source contact 115 and the drain contact 155 may be omitted, and the source pattern 110 and the drain pattern 150 may directly contact the bottom and the top of the ion receiving layer 120, respectively. In addition, although the present embodiment illustrates a case where the source pattern 110 is located below the ion receiving layer 120 and the drain pattern 150 is located above the ion receiving layer 120, in other embodiments, the positions of the source pattern 110 and the drain pattern 150 may be reversed or positioned in a different configuration relative to each other.

[0038] The following will refer to Figure 3 The operating method of the above-mentioned variable resistance element is described in detail.

[0039] Figure 3 is an example such as Figure 2A and Figure 2B2 is a view of the operation method of the variable resistance element illustrated in FIG. 1 , that is, a view illustrating the program method. Figure 3 Only shown Figure 2A A portion of a variable resistance element is shown.

[0040] refer to Figure 3 In one embodiment, the ion supply layer 130 may include LiCoO 2 , and the ion receiving layer 120 may include WO 3 .

[0041] When a positive programming voltage is applied to the gate pattern 140, the metal cations (ie, Li + ions) can move to the ion receiving layer 120. The Li that has moved to the ion receiving layer 120 + The ions may encounter electrons supplied from the source pattern 110 and / or the drain pattern 150 and react with WO 3 as shown in the following chemical reaction equation 1, thereby forming oxygen vacancies in the ion receiving layer 120 .

[0042] Chemical reaction equation 1

[0043] x + +xe - +WO3→Li x WO 3-x

[0044] In order to make the source pattern 110 and / or the drain pattern 150 supply electrons, a ground voltage may be applied to at least one of these patterns. As an example, a ground voltage may be applied to the source pattern 110, and the drain pattern 150 may be in a floating state without applying a voltage. Alternatively, the source pattern 110 may be in a floating state, and a ground voltage may be applied to the drain pattern 150. Alternatively, a ground voltage may be applied to both the source pattern 110 and the drain pattern 150.

[0045] As described above, the oxygen vacancies act as donor defects. Therefore, when a positive programming voltage is applied, the conductivity of the ion receiving layer 120 may increase, that is, the resistance may decrease.

[0046] Herein, as the number of programming voltage pulses increases, the Li moving from the ion supply layer 130 to the ion receiving layer 120 + The number of ions may gradually increase, and accordingly, the amount of oxygen vacancies in the ion receiving layer 120 may gradually increase.

[0047] Therefore, the conductivity of the ion receiving layer 120 may gradually increase, that is, the resistance may gradually decrease.

[0048] On the contrary, although not shown in the figure, when a negative erase voltage is applied to the gate pattern 140, Li+ Ions may return from the ion receiving layer 120 to the ion supply layer 130, so the conductivity of the ion receiving layer 120 may decrease, that is, the resistance may increase. This decrease in conductivity and / or increase in resistance may be gradual depending on the number of erase voltage pulses. In addition, a positive voltage may be applied to at least one of the source pattern 110 and the drain pattern 150. As an example, a positive voltage may be applied to the source pattern 110, and the drain pattern 150 may be in a floating state. Alternatively, the source pattern 110 may be in a floating state, and a positive voltage may be applied to the drain pattern 150. Alternatively, a positive voltage may be applied to both the source pattern 110 and the drain pattern 150.

[0049] Therefore, the variable resistance element including the ion receiving layer 120, the ion supply layer 130 and the gate pattern 140 is characterized in that its resistance gradually changes according to the amount of ions moving between the ion receiving layer 120 and the ion supply layer 130, and thus such a variable resistance element is suitable for use as a synapse in a neuromorphic device.

[0050] The resistance state of the variable resistance element can be read by using the source pattern 110 and the drain pattern 150. That is, the resistance state of the variable resistance element can be read or determined by applying a predetermined read voltage between the source pattern 110 and the drain pattern 150 and reading the current flowing therebetween (i.e., the current flowing in the ion receiving layer 120).

[0051] At the same time, a plurality of variable resistance elements may be arranged to form an array. Figure 4A , Figure 4B and Figure 5 This is described by way of example.

[0052] Figure 4A and Figure 4B are a plan view and a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 4B is along Figure 4A A cross-sectional view taken along line X2-X2′.

[0053] refer to Figure 4A and Figure 4B, a semiconductor device according to an embodiment of the present disclosure may include: a substrate 200; a source line 210 formed on the substrate 200 and extending in a first direction; a bit line 250 extending in a second direction intersecting the first direction; an ion receiving layer 220, which is arranged between the source line 210 and the bit line 250 and is located at an intersection between the source line 210 and the bit line 250; an ion supply layer 230, which surrounds the side wall of the ion receiving layer 220; and a word line 240, which surrounds the side wall of the ion supply layer 230 and extends in the second direction.

[0054] The substrate 200 may include certain necessary underlying structures (not shown), for example, transistors for controlling the source lines 210 , the word lines 240 , and / or the bit lines 250 .

[0055] A plurality of source lines 210 may be arranged to extend along a first direction on the substrate 200 while being spaced apart from each other in a second direction angled to the first direction. Although not shown in the drawings, an interlayer dielectric layer may fill the space between the source lines 210. The source lines 210 may include various conductive materials such as metal, metal nitride, or a combination thereof.

[0056] On the interlayer dielectric layer (not shown) between the source line 210 and the ion receiving layer 220, a columnar source line contact 215 may be provided. The source line contact 215 may be provided at each intersection between the source line 210 and the bit line 250 and may have a columnar shape. The space between the source line contacts 215 may be filled with a first interlayer dielectric layer ILD1.

[0057] On the first layer including the source line contact 215 and the first interlayer dielectric layer ILD1 , an ion receiving layer 220 , an ion supply layer 230 , and a word line 240 may be disposed.

[0058] The ion receiving layer 220 may be disposed at each intersection between the source line 210 and the bit line 250, and may have a columnar shape. The bottom of the ion receiving layer 220 may be connected to the source line contact 215. The width of the ion receiving layer 220 in a horizontal direction parallel to the surface of the substrate 200 may be equal to or greater than the width of the source line contact 215 in the same direction. Therefore, the source line contact 215 is not accidentally connected to the ion supply layer 230 and / or the word line 240.

[0059] The ion supply layer 230 may completely surround the side wall of the ion receiving layer 220. In other embodiments, the ion supply layer 230 may contact a portion of the outer side wall of the ion receiving layer 220, as long as the contact area ensures a smooth supply of ions to the ion receiving layer 220. As used herein, "a portion of the side wall of the ion receiving layer 220" may refer to a portion of the side wall in the horizontal direction and / or the vertical direction. That is, the ion supply layer 230 may have a shape in which it contacts a portion of the ion receiving layer 220 in the horizontal direction, but does not surround the ion receiving layer 220 in the plan view. Alternatively, in the plan view, the ion supply layer 230 may completely surround the side wall of the ion receiving layer 220, but only surround a portion of the ion receiving layer 220 in the cross-sectional view, that is, the ion supply layer 230 may have a smaller thickness in the vertical direction than the ion receiving layer 220. Alternatively, both are possible. That is, the ion supply layer 230 may partially contact the ion receiving layer 220 in the horizontal direction and the vertical direction. The sidewall of the ion supply layer 230 in contact with the sidewall of the ion receiving layer 220 will be referred to as an inner sidewall, and the sidewall of the ion supply layer 230 opposite to the inner sidewall of the ion supply layer 230 will be referred to as an outer sidewall.

[0060] The word line 240 may completely surround the outer sidewall of the ion supply layer 230. However, in other embodiments, the word line 240 may contact a portion of the outer sidewall of the ion supply layer 230 as long as the contact area has a size that ensures that a sufficient voltage is provided to the ion supply layer 230. As used herein, "a portion of the outer sidewall of the ion supply layer 230" may refer to a portion of the outer sidewall in the horizontal direction and / or the vertical direction. That is, the word line 240 may have a shape in which it contacts a portion of the outer sidewall of the ion supply layer 230 in the horizontal direction, but does not surround the ion supply layer 230 in a plan view. Alternatively, the word line 240 may contact a portion of the outer sidewall of the ion supply layer 230 in the vertical direction, and its thickness in the vertical direction is less than the thickness of the ion supply layer 230, while surrounding the outer sidewall of the ion supply layer 230 in a plan view. Alternatively, both are possible. That is, the word line 240 may partially contact the ion supply layer 230 in the horizontal direction and the vertical direction. In addition, the word line 240 may be formed to extend in the second direction and surround the plurality of ion supply layers 230 arranged in the second direction. However, the extending direction of the word line 240 may be variable. For example, the word line 240 may extend in one direction and be connected to the plurality of ion supply layers 230 arranged in the same direction. For example, the word line 240 may extend in the first direction and surround the plurality of ion supply layers 230 arranged in the first direction.

[0061] Return to reference Figure 4B, a space between the ion receiving layer 220 , the ion supply layer 230 , and the word line 240 may be filled with a second interlayer dielectric layer ILD2 .

[0062] The ion receiving layer 220, the ion supply layer 230, the word line 240 and the second interlayer dielectric layer ILD2 may be included in the second layer. The bit line contact 255 may be provided at each intersection between the source line 210 and the bit line 250, and may have a columnar or columnar shape. The bottom of the bit line contact 255 may be connected to the top of the ion receiving layer 220. The width of the ion receiving layer 220 in the horizontal direction parallel to the surface of the substrate 200 may be equal to or greater than the width of the bit line contact 255 in the same direction. The space between the bit line contacts 255 may be filled with a third interlayer dielectric layer ILD3.

[0063] The bit line contacts 255 and the third interlayer dielectric layer ILD3 may form a third layer on which the bit lines 250 may be disposed and arranged to be spaced apart from each other in the first direction while extending in the second direction.

[0064] In the semiconductor device of the above-described embodiment, at each intersection point between the source line 210 and the bit line 250 (see Figure 4A The variable resistance element can be formed by the dotted line in the figure. Figure 2A and 2B In other words, the variable resistance element included in Figure 4A The source line 210, the source line contact 215, the ion receiving layer 220, the ion supply layer 230, the word line 240, the bit line contact 255 and the bit line 250 in the dotted line area may correspond to Figure 2A and 2B 1 , the source pattern 110, the source contact 115, the ion receiving layer 120, the ion supply layer 130, the gate pattern 140, the drain contact 155, and the drain pattern 150 are shown in FIG. Accordingly, each variable resistance element in the semiconductor device of the present embodiment can be formed in the same manner as in the above reference. Figure 3 Operate as an example.

[0065] A method for manufacturing a semiconductor device of the present invention will be described below by way of example.

[0066] First, a conductive material may be formed on the substrate 200 and patterned to form the source line 210. Then, a dielectric material covering the source line 210 may be deposited and planarized until the upper surface of the source line 210 is exposed, thereby forming an interlayer dielectric layer (not shown) that fills the space between the source lines 210. Next, a first interlayer dielectric layer ILD1 covering the source line 210 and the interlayer dielectric layer therebetween may be formed, and then the first interlayer dielectric layer ILD1 may be selectively etched to provide a space in which a source line contact 215 is to be formed. The space may be filled with a conductive material to form the source line contact 215. Then, a conductive material may be formed on the first interlayer dielectric layer ILD1 and the source line contact 215 and patterned to form the word line 240, and a second interlayer dielectric layer ILD2 filling the space between the word lines 240 may be formed. Then, the word line 240 may be selectively etched to form a hole H1 in the word line 240, the hole H1 providing a space in which the ion receiving layer 220 and the ion supply layer 230 are to be formed. The hole H1 may be formed to have a width greater than the width of each source line contact 215 while exposing each source line contact 215. Next, a material layer for forming the ion supply layer 230 may be formed along the sidewall and bottom surface of the hole H1 until the thickness of the hole H1 cannot be completely filled, and then the material layer may be blanket-etched to form the ion supply layer 230 on the sidewall of the hole H1. By this blanket etching, the bottom surface of the hole H1 may be exposed. The thickness and degree of the blanket-etched material layer may be adjusted so that the width of the exposed bottom surface of the hole H1 is equal to or greater than the width of the source line contact 215. Next, an ion receiving layer 220 may be formed, and the ion receiving layer 220 may fill the remaining space of the hole H1 in which the ion supply layer 230 is formed. Next, a third interlayer dielectric layer ILD3 may be formed on the ion receiving layer 220, the ion supply layer 230, the word line 240, and the second interlayer dielectric layer ILD2, and then the third interlayer dielectric layer ILD3 may be selectively etched to provide a space in which a bit line contact 255 is to be formed, and the space may be filled with a conductive material to form the bit line contact 255. Thereafter, a conductive material may be formed on the bit line contact 255 and the third interlayer dielectric layer ILD3, and the conductive material may be patterned to form a bit line 250.

[0067] Figure 5 is a plan view illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 4A and Figure 4B This embodiment is described with reference to the differences between the embodiments of FIG.

[0068] refer to Figure 5 The semiconductor device of this embodiment may include: a source line 310 extending in a first direction; a bit line 350 extending in a second direction intersecting the first direction; an ion receiving layer 320 arranged between the source line 310 and the bit line 350 and located at the intersection between the source line 310 and the bit line 350; an ion supply layer 330 surrounding the side wall of the ion receiving layer 320; and a word line 340 extending in a third direction and surrounding the side wall of the ion supply layer 330.

[0069] This embodiment may be substantially the same as the above embodiment, except that the extending directions of the source line 310 , the bit line 350 , and the word line 340 are different.

[0070] Source line 310, bit line 350, and word line 340 extend in directions that intersect each other at certain angles, which need not be perpendicular. Figure 5 , a region having a substantially triangular shape is defined by the source line 310, the bit line 350, and the word line 340. As an example, the angle formed by the source line 310 and the bit line 350 may be about 60°, the angle formed by the bit line 350 and the word line 340 may be about 60°, and the angle formed by the word line 340 and the source line 310 may be about 60°. In this example, the region defined by the source line 310, the bit line 350, and the word line 340 has an equilateral triangle shape.

[0071] The ion receiving layer 320 and the ion supply layer 330 may be provided at each intersection of the source line 310, the bit line 350, and the word line 340. Therefore, a variable resistance element may be formed at each intersection of the source line 310, the bit line 350, and the word line 340.

[0072] According to this embodiment, Figure 4A and Figure 4B Compared with the described embodiments, the integration level of the semiconductor device can be further improved.

[0073] Fig. 6A is a cross-sectional view illustrating a variable resistance element according to another embodiment of the present disclosure, and Figure 6B FIG. 1 is a cross-sectional view illustrating a variable resistance element according to another embodiment of the present disclosure. Figure 2A and Figure 2B These embodiments are described with reference to the differences between the embodiments described above.

[0074] refer to Fig. 6A ,Apart from Figure 2A and 2B In addition to the components of the variable resistance element shown, the variable resistance element of one embodiment may further include a selection element pattern 160 .

[0075] although Fig. 6A The selection element pattern 160 is illustrated as being interposed between the drain pattern 150 and the drain contact 155, but the present disclosure is not limited thereto. The selection element pattern 160 may be located between the drain pattern 150 and the ion receiving layer 120, and / or between the source pattern 110 and the ion receiving layer 120. The selection element pattern 160 may control access from the drain pattern 150 to the ion receiving layer 120 or from the source pattern 110 to the ion receiving layer 120. For example, the selection element pattern 160 may be interposed between the drain contact 155 and the ion receiving layer 120, between the source pattern 110 and the source contact 115, and / or between the source contact 115 and the ion receiving layer 120.

[0076] In addition, despite Fig. 6A The selection element pattern 160 is shown to have the same shape as the drain pattern 150, but the present disclosure is not limited thereto, and the selection element pattern 160 may have various shapes. For example, when viewed in a plan view, the selection element pattern 160 may have the same outline, outer contour, or island shape as the drain contact 155 and / or the source contact 115. Alternatively, or in addition, the selection element pattern 160 may also have the same shape as the source pattern 110. In other embodiments, the selection element pattern 160 may also have a linear shape overlapping a bit line or a source line when viewed in a plan view.

[0077] The selection element pattern 160 may have a selection element characteristic, wherein when the magnitude of the voltage or current applied thereto is equal to or lower than a certain critical value, the current passing through the selection element pattern 160 is small or does not pass, and when the magnitude of the voltage or current applied thereto is higher than a certain critical value, the current passing through the selection element pattern 160 increases rapidly in proportion to the magnitude of the applied voltage or current. The selection element pattern 160 may include, for example, a MIT (metal insulator transition) element such as NbO2 or TiO2; a MIEC (mixed ion electron conduction) element such as ZrO2 (Y2O3), Bi2O3-BaO or (La2O3)x(CeO2)1-x; an OTS (bidirectional threshold switch) element including a chalcogenide-based material such as Ge2Sb2Te5, As2Te3, As2 or As2Se3; a rectifying element such as a diode; or a tunnel dielectric layer composed of various dielectric materials such as silicon oxide, silicon nitride or metal oxide. The tunnel dielectric layer may have a small or minimum thickness to allow electrons to tunnel under a certain voltage or current.

[0078] The selection element pattern 160 may have a single-layer structure or a multi-layer structure, wherein the selection element pattern 160 may be composed of a combination of two or more layers and exhibit the characteristics of a selection element.

[0079] When the selection element pattern 160 is used in a variable resistance element, leakage current between adjacent variable resistance elements can be reduced and / or blocked, wherein the variable resistance elements are arranged such as Figure 4A , Figure 4B and Figure 5 Those array structures shown in .

[0080] refer to Figure 6B ,Apart from Figure 2A and Figure 2B In addition to the components of the variable resistance element shown, the variable resistance element of one embodiment may further include an isolation layer interposed between the ion receiving layer 120 and the ion supply layer 130 to physically isolate them from each other.

[0081] The isolation layer 170 may be used to prevent the unnecessary formation of a mixed layer due to the movement of ions at the interface between the ion receiving layer 120 and the ion supply layer 130. In addition, when an operating voltage (such as a programming voltage or an erase voltage) is applied to the gate pattern 140, the isolation layer 170 may allow the metal ions to move. On the other hand, at other voltages, the isolation layer 170 may block the movement of electrons. An electrolyte material may be used in the isolation layer 170.

[0082] When the isolation layer 170 is used, the movement of metal ions between the ion supply layer 130 and the ion receiving layer 120 can be effectively controlled and a mixed layer can be prevented from being formed between the ion supply layer 130 and the ion receiving layer 120. Therefore, the isolation layer 170 contributes to the reliability of the variable resistance element.

[0083] Figure 7 is a cross-sectional view illustrating a variable resistance element according to still another embodiment of the present disclosure.

[0084] refer to Figure 7 , a variable resistance element of an embodiment may include: a columnar ion supply layer 420 extending in a vertical direction; an ion receiving layer 430 surrounding a sidewall of the ion supply layer 420; a gate pattern 440 surrounding a sidewall of the ion receiving layer 430; a source pattern 410 connected to the bottom of the ion supply layer 420; and a drain pattern 450 connected to the top of the ion supply layer 420. A source contact 415 may be interposed between the source pattern 410 and the ion supply layer 420, and a drain contact 455 may be interposed between the drain pattern 450 and the ion supply layer 420.

[0085] Figure 7 The embodiments shown in Figure 2A and Figure 2B The difference between the embodiments shown in FIG. 1 is that the positions of the ion supply layer and the ion receiving layer are different in different embodiments. Figure 2A and 2BThe illustrated embodiment exemplifies a variable resistance element in which the ion supply layer 130 surrounds the outer side wall of the columnar ion receiving layer 120, but Figure 7 A variable resistance element is shown in which the ion receiving layer 430 surrounds the outer side wall of the columnar ion supply layer 420. Although in various embodiments, only the positions of the ion receiving layer and the ion supply layer are reversed, the material forming the ion supply layer 420 may be the same as the material forming the ion supply layer 130, and the material forming the ion receiving layer 430 may be the same as the material forming the ion receiving layer 120.

[0086] In the present embodiment, the ion supply layer 420 may show a state of insufficient metal ions by supplying cations (particularly metal cations) to the ion receiving layer 430, thereby forming holes. The holes in the ion supply layer 420 act as acceptor defects. Therefore, as the amount of holes increases, the conductivity of the ion supply layer 420 may increase, and as the amount of holes decreases, the conductivity of the ion supply layer 420 may decrease. That is, the resistance of the ion supply layer 420 may vary according to the amount of holes in the ion supply layer 420. Accordingly, in accordance with Figure 2A and 2B In the variable resistance element of the illustrated embodiment, the ion receiving layer 120 serves as the resistance change element, but in this embodiment, the ion supply layer 420 may serve as the resistance change element.

[0087] The ion receiving layer 430 may receive cations, particularly metal cations, from the ion supply layer 420. In the present embodiment, the ion receiving layer 430 may have a shape of an outer sidewall surrounding the ion supply layer 420. However, the present disclosure is not limited thereto, and the shape of the ion receiving layer 430 may be variously modified so that the ion receiving layer 430 contacts at least a portion of the sidewall of the ion supply layer 420 to provide a smooth or uninterrupted supply of ions from the ion supply layer 420 to the ion receiving layer 430.

[0088] The gate pattern 440 may be used to control the movement of ions from the ion supply layer 420 to the ion receiving layer 430 in response to receiving a predetermined voltage. The gate pattern 440 may have a shape that surrounds the outer sidewall of the ion receiving layer 430. However, the present disclosure is not limited thereto, and in other embodiments, the shape of the gate pattern 440 may be variously modified so that the gate pattern 440 contacts at least a portion of the outer sidewall of the ion receiving layer 430, and the movement of ions from the ion supply layer 420 to the ion receiving layer 430 is smooth and uninterrupted.

[0089] The source pattern 410 and the drain pattern 450 may be connected to the bottom and the top of the ion supply layer 420 , respectively, and a resistance change of the ion supply layer 420 may be read through the patterns.

[0090] The following will refer to Figure 8 Detailed Description Figure 7 The operation method of the variable resistance element is shown.

[0091] Figure 8 is an example Figure 7 A view of an operating method (particularly a programming method) of a variable resistance element is shown. Figure 8 Only shown Figure 7 A portion of a variable resistance element is shown.

[0092] refer to Figure 8 , the ion supply layer 420 may include LiCoO 2 , and the ion receiving layer 430 may include WO 3 .

[0093] When a negative programming voltage is applied to the gate pattern 440, the metal cations (ie, Li + ions) can move to the ion receiving layer 430. + When ions are released from the ion supply layer 420, holes may be formed in the ion supply layer 420, as shown in the following chemical reaction equation 2:

[0094] Chemical reaction equation 2

[0095] LiCoO2→Li 1-x CoO2+xLi+ + xh

[0096] In this case, a ground voltage may be applied to at least one of the source pattern 410 and the drain pattern 450. As an example, a ground voltage may be applied to the source pattern 410, and the drain pattern 450 may be in a floating state. Alternatively, the source pattern 410 may be in a floating state, and a ground voltage may be applied to the drain pattern 450. Alternatively, a ground voltage may be applied to both the source pattern 410 and the drain pattern 450.

[0097] As described above, holes act as acceptor defects. Therefore, when a negative programming voltage is applied, the conductivity of the ion supply layer 420 may be increased, that is, the resistance may be reduced.

[0098] Here, as the number of programming voltage pulses increases, the Li moving from the ion supply layer 420 to the ion receiving layer 430 + The number of ions may gradually increase, and accordingly, the number of holes in the ion supply layer 420 may gradually increase.

[0099] Therefore, the conductivity of the ion supply layer 420 may gradually increase, that is, the resistance may gradually decrease.

[0100] On the contrary, although not shown in the figure, when a positive erase voltage is applied to the gate pattern 440, Li + Ions can be returned from the ion receiving layer 430 to the ion supply layer 420, so the conductivity of the ion supply layer 420 can be reduced, that is, the resistance can be increased. This reduction in conductivity and / or increase in resistance can be gradual depending on the number of erase voltage pulses. In addition, a negative voltage can be applied to at least one of the source pattern 410 and the drain pattern 450. As an example, a negative voltage can be applied to the source pattern 410, and the drain pattern 450 can be in a floating state. Alternatively, the source pattern 410 can be in a floating state, and a negative voltage can be applied to the drain pattern 450. Alternatively, a negative voltage can be applied to both the source pattern 410 and the drain pattern 450.

[0101] Therefore, the variable resistance element including the ion supply layer 420, the ion receiving layer 430 and the gate pattern 440 is characterized in that the resistance of the variable resistance element can be gradually changed according to the amount of ions moving between the ion supply layer 420 and the ion receiving layer 430, and thus the variable resistance element is suitable for use as a synapse in a neuromorphic device. In the above-mentioned embodiment, it is possible to change the resistance of the variable resistance element by the change of oxygen vacancies in the layer, but the present embodiment is different from the above-mentioned embodiment in that the resistance change of the variable resistance element is caused by the change in the number of holes.

[0102] The resistance state of the variable resistance element may be read using the source pattern 410 and the drain pattern 450. That is, the resistance state of the variable resistance element may be understood or determined by reading the current difference or voltage difference between the source pattern 410 and the drain pattern 450.

[0103] At the same time, it should be understood that the variable resistance element of this embodiment can be used in the above Figure 4A , Figure 4B and Figure 5 The semiconductor device shown, or similar to Fig. 6A The variable resistance element shown may also include a selection element pattern, and / or a similar Figure 6B The variable resistance element shown may further include an isolation layer.

[0104] Fig. 9 FIG. 1 is a cross-sectional view illustrating a variable resistance element according to another embodiment of the present disclosure. Figure 2A and Figure 2B The present embodiment is described with reference to the differences of the illustrated embodiment.

[0105] refer to Fig. 9 The ion receiving layer 120' of the variable resistance element according to the embodiment may have a hollow columnar shape, such as a cylindrical shape, which is similar to Figure 2A and Figure 2B The ion receiving layer 120 of the variable resistance element shown, which has a solid columnar shape, is different. The space in the ion receiving layer 120' may be filled with the dielectric pattern 180. In other words, a columnar dielectric pattern 180 may be further formed, and the ion receiving layer 120' may have a shape surrounding the dielectric pattern 180.

[0106] The ion receiving layer 120' needs to be electrically connected to the source pattern 110 and the drain pattern 150. Therefore, a portion of the bottom of the ion receiving layer 120' may contact the source contact 115 (or the source pattern 110 if the source contact 115 is omitted), and a portion of the top of the ion receiving layer 120' may contact the drain contact 155 (or the drain pattern 150 if the drain contact 155 is omitted). In addition, the width of the dielectric pattern 180 in the horizontal direction may be smaller than the width of each of the source contact 115 (or the source pattern 110 if the source contact 115 is omitted) and the drain contact 155 (or the drain pattern 150 if the drain contact 155 is omitted).

[0107] According to the present embodiment, the total width of the ion receiving layer 120' in the horizontal direction can be reduced due to the inclusion of the dielectric pattern 180. As a result, the path of the metal ion movement can be shortened in the horizontal direction, so the formation rate of oxygen vacancies in the ion receiving layer 120' can be increased. Therefore, the resistance change rate of the ion receiving layer 120' can be increased, so that the operation speed of the variable resistance element can also be improved.

[0108] Similarly, although not shown in the figure, Figure 7 The shape of the ion supply layer 420 in the variable resistance element shown may be modified into a hollow columnar shape, and the empty space in the ion supply layer 420 may be filled with a dielectric material. Such an embodiment also supports an increased operating speed.

[0109] The variable resistance element and / or semiconductor device according to the above-described embodiments may be used in various devices or systems, for example, a neuromorphic device. Fig.10 Describe by way of example.

[0110] Fig.10 An example of a pattern recognition system 1000 according to an embodiment of the present disclosure is shown. The pattern recognition system according to the present embodiment may be a system for recognizing various patterns, such as a speech recognition system or an image recognition system. The pattern recognition system according to the present embodiment may be configured with a neuromorphic device including an embodiment of the above-mentioned variable resistance element and / or semiconductor device.

[0111] refer to Fig.10 According to the present embodiment, the pattern recognition system 1000 may include a central processing unit (CPU) 1010, a storage device 1020, a communication control device 1030, a network 1040, a pattern output device 1050, a pattern input device 1060, an analog-to-digital converter (ADC) 1070, a neuromorphic device 1080, a bus 1090, and the like.

[0112] The central processing unit 1010 may generate and transmit various signals used in the learning operation of the neuromorphic device 1080, and may perform various processing operations and functions based on the output from the neuromorphic device 1080 to recognize patterns of sounds, images, etc. The central processing unit 1010 may be connected to the storage device 1020, the communication control device 1030, the pattern output device 1050, the analog-to-digital converter (ADC) 1070, and the neuromorphic device 1080 via the bus 1090.

[0113] The memory device 1020 may store various information required by the pattern recognition system 1000. To this end, the memory device 1020 may include different types of memory devices. For example, the memory device 1020 may include a ROM device 1022, a RAM device 1023, and the like. The ROM device 1022 may be used to store various programs or data, which are used in the central processing unit 1010 to perform learning operations, pattern recognition, and the like of the neuromorphic device 1080. The RAM device 1023 may store programs or data downloaded from the ROM device 1022, or store data converted and analyzed by the analog-to-digital converter (ADC) 1070, such as sound or images.

[0114] The communication control device 1030 can exchange recognized data (for example, sound or image) with other communication control devices through the network 1040 .

[0115] The pattern output device 1050 may output the recognized data (eg, sound or image) in various ways. For example, the pattern output device 1050 may include a printer, a display unit, etc., and may output a sound waveform or display an image.

[0116] The mode input device 1060 may receive analog sounds, images, etc., and may include a microphone, a camera, etc.

[0117] An analog-to-digital converter (ADC) 1070 may convert analog data provided by the mode input device 1060 into digital data, and may also analyze the digital data.

[0118] The neuromorphic device 1080 can use the data provided by the analog-to-digital converter (ADC) 1070 to perform learning, recognition, etc., and can output data corresponding to the recognized pattern. The neuromorphic device 1080 may include one or more variable resistance elements and semiconductor devices according to the above-mentioned embodiments. For example, the neuromorphic device 1080 may include a plurality of synapses, and each of the plurality of synapses may include: an ion receiving layer having a top, a bottom, and a sidewall connecting the top and the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the outer sidewall of the ion receiving layer; a gate pattern connected to the outer sidewall of the ion supply layer; and a source pattern connected to one of the top or bottom of the ion receiving layer, and a drain pattern connected to the other of the top or bottom of the ion receiving layer, wherein the resistance of the ion receiving layer varies according to the amount of ions supplied from the ion supply layer based on the voltage applied to the gate pattern. By this configuration, the symmetry and linearity of the synapse can be guaranteed. Accordingly, the operating characteristics of the neuromorphic device 1080 can be improved, and thus the operating characteristics of the pattern recognition system 1000 can also be improved.

[0119] In addition, the pattern recognition system 1000 may also include other components required to correctly perform its functions. For example, the pattern recognition system 1000 may also include a keyboard, a mouse, etc. as an input unit to receive various parameters or setting conditions for the operation of the pattern recognition system 1000.

[0120] According to the above-described embodiments, a variable resistance element having characteristics suitable for use as a synapse in a neuromorphic device, and a semiconductor device including the variable resistance element can be provided.

[0121] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A semiconductor device comprising at least one variable resistance element, wherein the variable resistance element comprises: an ion receiving layer having a top, a bottom, and a sidewall connecting the top and the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the sidewall of the ion receiving layer; a gate pattern connected to an outer side wall of the ion supply layer; and a source pattern connected to one of the top or the bottom of the ion receiving layer, and a drain pattern connected to the other of the top or the bottom of the ion receiving layer, wherein the resistance of the ion receiving layer varies according to the amount of metal ions supplied from the ion supply layer based on a voltage applied to the gate pattern, The ion supply layer includes a material that supplies metal cations to the ion receiving layer serving as a channel.

2. The semiconductor device according to claim 1, wherein The resistance state of the ion receiving layer is read using a difference in current or voltage supplied between the source pattern and the drain pattern.

3. The semiconductor device according to claim 1, wherein The ion receiving layer includes a material that uses received metal cations to form oxygen vacancies.

4. The semiconductor device according to claim 3, wherein: When the metal cations are supplied from the ion supply layer to the ion reception layer, a positive voltage is applied to the gate pattern.

5. The semiconductor device according to claim 1, wherein As the number of pulses of the voltage applied to the gate pattern increases, the amount of the ions supplied from the ion supply layer to the ion receiving layer gradually increases.

6. The semiconductor device according to claim 1, wherein The ion receiving layer has a columnar shape, an inner sidewall of the ion supply layer surrounds a sidewall of the ion receiving layer, and the gate pattern surrounds an outer sidewall of the ion supply layer.

7. The semiconductor device according to claim 1, wherein The ion receiving layer has a hollow columnar shape, the ion supply layer surrounds an outer side wall of the ion receiving layer, the gate pattern surrounds the outer side wall of the ion supply layer, and the variable resistance element further includes a dielectric pattern filling the ion receiving layer.

8. The semiconductor device according to claim 1 further includes a selection element layer, which is located between the ion receiving layer and the drain pattern, between the ion receiving layer and the source pattern, or between the ion receiving layer and the drain pattern and between the ion receiving layer and the source pattern.

9. The semiconductor device according to claim 1, further comprising a separation layer provided between the ion receiving layer and the ion supply layer, wherein The isolation layer allows ions to move between the ion supply layer and the ion receiving layer when a voltage is applied to the gate pattern.

10. The semiconductor device according to claim 9, wherein The separator includes an electrolyte material.

11. The semiconductor device according to claim 1, further comprising: a plurality of source lines extending in a first direction and connected to the source patterns; a plurality of bit lines extending in a second direction crossing the first direction and connected to the drain pattern; as well as a plurality of word lines extending in one direction and connected to the gate pattern, The variable resistance element is arranged at each intersection between the source line, the bit line and the word line.

12. The semiconductor device according to claim 11, wherein The word line extends in the first direction or the second direction.

13. The semiconductor device according to claim 11, wherein The word line extends in a third direction different from the first direction and the second direction.

14. The semiconductor device according to claim 13, wherein: The angle formed between the first direction and the second direction, the angle formed between the second direction and the third direction, and the angle formed between the third direction and the first direction are each 60°, and the ion receiving layer is located at each vertex of an equilateral triangle defined by the source line, the bit line, and the word line.

15. A semiconductor device comprising at least one variable resistance element, wherein the variable resistance element comprises: an ion supply layer having a top, a bottom, and a sidewall connecting the top and the bottom; an ion receiving layer having an inner sidewall connected to at least a portion of the sidewall of the ion supply layer; a grid pattern connected to an outer side wall of the ion receiving layer; as well as a source pattern connected to one of the top or the bottom of the ion supply layer, and a drain pattern connected to the other of the top or the bottom of the ion supply layer, wherein the resistance of the ion supply layer varies according to the amount of metal ions supplied from the ion supply layer to the ion receiving layer in response to a voltage applied to the gate pattern, The ion supply layer as a channel includes a material that supplies metal cations to the ion receiving layer.

16. The semiconductor device according to claim 15, wherein: The resistance state of the ion supply layer is read using a difference in current or voltage applied between the source pattern and the drain pattern.

17. The semiconductor device according to claim 15, wherein: When the metal cations are supplied from the ion supply layer to the ion reception layer, a negative voltage is applied to the gate pattern.

18. The semiconductor device according to claim 15, wherein: As the number of pulses of the voltage applied to the gate pattern increases, the amount of the ions supplied from the ion supply layer to the ion receiving layer gradually increases.

19. The semiconductor device according to claim 15, wherein: The ion supply layer has a columnar shape, an inner sidewall of the ion receiving layer surrounds a sidewall of the ion supply layer, and the gate pattern surrounds an outer sidewall of the ion receiving layer.

20. The semiconductor device according to claim 15, wherein The ion supply layer has a hollow columnar shape, the ion receiving layer surrounds an outer sidewall of the ion supply layer, the gate pattern surrounds the outer sidewall of the ion receiving layer, and the variable resistance element further includes a dielectric pattern filling the ion supply layer.

21. The semiconductor device according to claim 15 further comprises a selection element layer, which is located between the ion supply layer and the drain pattern, between the ion supply layer and the source pattern, or between the ion supply layer and the drain pattern and between the ion supply layer and the source pattern.

22. The semiconductor device according to claim 15, further comprising a separation layer provided between the ion receiving layer and the ion supply layer, wherein The isolation layer allows ions to move between the ion supply layer and the ion receiving layer when a voltage is applied to the gate pattern.

23. The semiconductor device according to claim 22, wherein: The separator includes an electrolyte material.

24. The semiconductor device according to claim 15, further comprising: a plurality of source lines extending in a first direction and connected to the source patterns; a plurality of bit lines extending in a second direction crossing the first direction and connected to the drain pattern; as well as a plurality of word lines extending in one direction and connected to the gate pattern, The variable resistance element is arranged at each intersection between the source line, the bit line and the word line.

25. The semiconductor device according to claim 24, wherein: The word line extends in the first direction or the second direction.

26. The semiconductor device according to claim 24, wherein: The word line extends in a third direction different from the first direction and the second direction.

27. The semiconductor device according to claim 26, wherein: The angle formed between the first direction and the second direction, the angle formed between the second direction and the third direction, and the angle formed between the third direction and the first direction are each 60°, and the ion supply layer is located at each vertex of an equilateral triangle defined by the source line, the bit line, and the word line.

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