Capacitor structure and semiconductor device including the same

Abstract

Disclosed is a capacitor structure and a semiconductor device including the same, the capacitor structure including: a lower electrode on a substrate; a seed layer on the lower electrode; a dielectric layer on the seed layer; and an upper electrode on the dielectric layer, wherein the dielectric layer includes a ternary metal oxide of a chemical formula ABO3, wherein each of A and B is independently a metal, and the seed layer includes a ternary metal oxide of a chemical formula ABO 3‑x , each of A and B in the ternary metal oxide of the chemical formula ABO 3‑x is the same metal as A and B in the ternary metal oxide of the chemical formula ABO3, 0

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0166401, filed on December 13, 2019, and entitled “Capacitor Structure and Semiconductor Device Including the Same,” the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Embodiments relate to a capacitor structure and a semiconductor device including the same. BACKGROUND

[0003] In a manufacturing process of a dynamic random access memory (DRAM) device, a capacitor structure including a lower electrode, a dielectric layer, and an upper electrode sequentially stacked can be formed on a substrate. SUMMARY

[0004] Embodiments can be implemented by providing a capacitor structure including a lower electrode on a substrate, a seed layer on the lower electrode, a dielectric layer on the seed layer, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a ternary metal oxide of a chemical formula ABO3, wherein each of A and B is independently a metal, and the seed layer includes a ternary metal oxide of a chemical formula ABO3-x, wherein each of A and B is the same metal as A and B in the ternary metal oxide of the chemical formula ABO3, 0 < x < 3, and x is a real number. 3-x 3-x Each of A and B in the ternary metal oxide of the chemical formula ABO3-x is the same metal as A and B in the ternary metal oxide of the chemical formula ABO3, 0 < x < 3, and x is a real number.

[0005] Embodiments can be implemented by providing a capacitor structure including a lower electrode on a substrate, a seed layer on the lower electrode, a dielectric layer on the seed layer, and an upper electrode on the dielectric layer, wherein the dielectric layer includes SrTiO3, BaTiO3, or CaTiO3, the seed layer includes SrTiO3-x, BaTiO3-x, or CaTiO3-x, wherein 0 < x < 3 and x is a real number, and the dielectric layer has a perovskite structure. 3-x 3-x 3-x Each of A and B in the ternary metal oxide of the chemical formula ABO3-x is the same metal as A and B in the ternary metal oxide of the chemical formula ABO3, 0 < x < 3, and x is a real number.

[0006] ​​​Embodiments can be realized by providing a semiconductor device including: gate structures each extending at an upper portion of a substrate in a first direction parallel to an upper surface of the substrate, the gate structures being spaced apart from each other along a second direction parallel to the upper surface of the substrate and intersecting the first direction; bit line structures each extending on the gate structures in the second direction, the bit line structures being spaced apart from each other along the first direction; contact plug structures adjacent to the bit line structures, the contact plug structures including a lower contact plug, a metal silicide pattern, and an upper contact plug stacked in sequence along a vertical direction perpendicular to the upper surface of the substrate; and a capacitor structure contacting an upper surface of the contact plug structure, wherein the capacitor structure includes a lower electrode, a seed layer, a dielectric layer, and an upper electrode stacked in sequence, the dielectric layer including a ternary metal oxide of a chemical formula ABO3, where each of A and B is independently a metal, and the seed layer including a ternary metal oxide of a chemical formula ABO3, where each of A and B is a same metal as in the ternary metal oxide of the chemical formula ABO3, 0 < x < 3, and x is a real number. 3-x 3-x 3-x BRIEF DESCRIPTION OF DRAWINGS

[0007] Features will become apparent to those of ordinary skill in the art upon examination of the following details. It is also intended that all such embodiments can be obtained and practiced within the scope of the application.

[0008] Figures 1 to 6 is a cross-sectional view of a stage in a method of forming a capacitor structure according to an example embodiment.

[0009] Figures 7 to 24 is a plan view and a cross-sectional view of a stage in a method of manufacturing a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0010] Hereinafter, two directions substantially parallel to the upper surface of the substrate and substantially perpendicular to each other can be defined as the first direction and the second direction, respectively. A direction orthogonal to the first direction and the second direction is defined as the vertical direction.

[0011] Figures 1 to 6 is a cross-sectional view of a stage in a method of forming a capacitor structure according to an example embodiment.

[0012] Referring to Figure 1 After the contact plug 20 is formed on the substrate 10, a first insulating interlayer 30 can be formed on the substrate 10 to surround the sidewall of the contact plug 20.

[0013] ​The substrate 10 can include silicon, germanium, silicon-germanium, or a Group III-V compound semiconductor (e.g., GaP, GaAs, or GaSb). In an embodiment, the substrate 10 can be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GOI) wafer.

[0014] Various types of elements, such as an active pattern, a gate structure, a bit line structure, a source / drain layer, etc., can be formed on the substrate 10. The elements can be covered by the first insulating interlayer 30, and the contact plug 20 can be electrically connected to the source / drain layer. The first insulating interlayer 30 can include, for example, an oxide such as silicon oxide.

[0015] In an embodiment, the contact plug 20 can be formed by sequentially forming a contact plug layer on the substrate 10 and an etching mask partially covering the contact plug layer, and performing an etching process on the contact plug layer using the etching mask. The first insulating interlayer 30 can be formed on the substrate 10 to cover sidewalls of the contact plug 20.

[0016] In an embodiment, the contact plug 20 can be formed by forming the first insulating interlayer 30 having a hole exposing the substrate 10, forming a contact plug layer filling the recess to a sufficient height, and planarizing an upper portion of the contact plug layer until an upper surface (e.g., a surface facing away from the substrate 10 in a vertical direction) of the first insulating interlayer 30 is exposed.

[0017] In an embodiment, a plurality of contact plugs 20 can be spaced apart from each other in each of the first direction and the second direction.

[0018] Referring to Figure 2 A preliminary lower electrode structure 50 can be formed to contact an upper surface of the contact plug 20.

[0019] The preliminary lower electrode structure 50 can be formed by sequentially stacking a first oxide layer, a preliminary lower electrode layer, and a second oxide layer on (e.g., in a vertical direction) the contact plug 20 and the first insulating interlayer 30, and patterning the first oxide layer, the preliminary lower electrode layer, and the second oxide layer. In an embodiment, the first oxide layer, the preliminary lower electrode layer, and the second oxide layer can be patterned into a first oxide pattern 43, a preliminary lower electrode 45, and a second oxide pattern 47, respectively, which can form the preliminary lower electrode structure 50.

[0020] Each of the sequentially stacked first oxide layer, the preliminary lower electrode layer, and the second oxide layer can be formed by, for example, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process.

[0021] In an embodiment, as shown in the drawings, the preliminary lower electrode structure 50 can cover a portion of the upper surface of the contact plug 20 and the upper surface of the first insulating interlayer 30. In an embodiment, the preliminary lower electrode structure 50 can be formed to cover only the upper surface of the contact plug 20.

[0022] The first oxide pattern 43 and the second oxide pattern 47 can include the same material, and the preliminary lower electrode 45 can include a material different from that of the first oxide pattern 43 and the second oxide pattern 47. Each of the first oxide pattern 43 and the second oxide pattern 47 can include, for example, an oxide such as strontium oxide (SrO), and the preliminary lower electrode 45 can include, for example, a metal such as ruthenium (Ru), molybdenum (Mo), cobalt (Co), iridium (Ir), or the like. In an embodiment, each of the first oxide pattern 43 and the second oxide pattern 47 can include an oxide such as barium oxide (BaO) or calcium oxide (CaO).

[0023] In an embodiment, the first oxide pattern 43, the preliminary lower electrode 45, and the second oxide pattern 47 can be formed to have the same thickness (e.g., a thickness measured in a vertical direction). In an embodiment, the first oxide pattern 43 and the second oxide pattern 47 can be formed to have the same thickness as each other, and the first oxide pattern 43 and the second oxide pattern 47 can be formed to have a thickness (e.g., a thickness measured in a vertical direction) smaller than that of the preliminary lower electrode 45.

[0024] Referring to Figure 3 The cap layer 60 can be formed conformally to cover the upper surface of the first insulating interlayer 30 and the upper surface and the sidewall of the preliminary lower electrode structure 50.

[0025] The cap layer 60 can include, for example, an oxide such as titanium oxide (TiO2).

[0026] Referring to Figure 4 An annealing process can be performed on the cap layer 60 and the preliminary lower electrode structure 50 to form the lower electrode 55 and the seed layer 65 stacked in sequence.

[0027] In an embodiment, when the annealing process is performed, the first oxide pattern 43 and the second oxide pattern 47 can provide oxygen (O) to the preliminary lower electrode 45, and the preliminary lower electrode 45 can provide ruthenium (Ru), molybdenum (Mo), cobalt (Co), or iridium (Ir) to the first oxide pattern 43 and the second oxide pattern 47. The first oxide pattern 43, the preliminary lower electrode 45, and the second oxide pattern 47 can react to form the lower electrode 55 including a ternary metal oxide. As a result of the annealing process, the first oxide pattern 43, the preliminary lower electrode 45, and the second oxide pattern 47 can react to form the lower electrode 55.

[0028] In an embodiment, the lower electrode 55 can include a ternary metal oxide having a chemical formula of ABO3 (where each of A and B is independently a metal). In an embodiment, the ternary metal oxide can include a first element A (e.g., a first metal element), a second element B (e.g., a second metal element different from the first metal element), and a third element (e.g., oxygen). In an embodiment, the ternary metal oxide can have a perovskite structure. In an embodiment, the ternary metal oxide can include, for example, strontium ruthenate (SrRuO3), strontium molybdate (SrMoO3), strontium cobaltate (SrCoO3), strontium iridate (SrIrO3), barium ruthenate (BaRuO3), barium molybdate (BaMoO3), barium cobaltate (BaCoO3), barium iridate (BaIrO3), calcium ruthenate (CaRuO3), calcium molybdate (CaMoO3), calcium cobaltate (CaCoO3), or calcium iridate (CaIrO3).

[0029] In an embodiment, the oxygen concentration at the central portion of the lower electrode 55 can be greater than the oxygen concentration at the upper portion of the lower electrode 55 (e.g., the portion of the lower electrode 55 that is distal from the substrate 10 in the vertical direction) or the oxygen concentration at the lower portion of the lower electrode 55 (e.g., the portion of the lower electrode 55 that is proximal to the substrate 10 in the vertical direction). In an embodiment, the oxygen concentration at the upper portion of the lower electrode 55 can be greater than the oxygen concentration at the lower portion of the lower electrode 55.

[0030] In an embodiment, as shown in the drawings, the lower electrode 55 can have a cylindrical shape. In an embodiment, the lower electrode 55 having a cylindrical shape can be formed.

[0031] The first oxide pattern 43 and the second oxide pattern 47 can provide strontium (Sr), barium (Ba), or calcium (Ca) to the cap layer 60, and thus the cap layer 60 can react (e.g., during an annealing process) to form a seed layer 65 including another ternary metal oxide. When the annealing process is performed, the oxygen (O) component included in the cap layer 60 can diffuse into the first oxide pattern 43 and the second oxide pattern 47, and the seed layer 65 can have an oxygen concentration that is less than the oxygen concentration of the ternary metal oxide having a chemical formula of ABO3 that forms a perovskite structure.

[0032] In an embodiment, the seed layer 65 can include a material having an oxygen concentration that is less than the oxygen concentration of the ternary metal oxide (ABO3) that forms a perovskite structure. In an embodiment, the seed layer 65 can include, for example, SrTiO 3-x , BaTiO 3-x , or CaTiO 3-x , where 0 < x < 3, x is a real number.

[0033] In an embodiment, the oxygen concentration at a portion of the seed layer 65 proximate to the lower electrode 55 can be less than the oxygen concentration at a portion of the seed layer 65 distal from the lower electrode 55.

[0034] Referring to Figure 5 The dielectric layer 70 can be formed conformally on the seed layer 65.

[0035] In an embodiment, the dielectric layer 70 can include a further ternary metal oxide forming or having a perovskite structure. In an embodiment, the dielectric layer 70 can include, for example, strontium titanate (SrTiO3), barium titanate (BaTiO3), or calcium titanate (CaTiO3).

[0036] The dielectric layer 70 can be formed on the seed layer 65 including substantially the same material (e.g., including the same elements), and thus can be more efficiently formed than if the dielectric layer 70 is to be formed on a layer containing a different material (e.g., containing different elements) therefrom. In an embodiment, the dielectric layer 70 can be formed by performing only a deposition process (e.g., a CVD process, an ALD process, or a PVD process) without performing an annealing process on the seed layer 65 or performing an annealing process only at a relatively low temperature.

[0037] In an embodiment, the dielectric layer 70 can be formed to have substantially the same thickness as the seed layer 65, as shown in the drawings. In an embodiment, the dielectric layer 70 can be formed to have a different thickness than the seed layer 65.

[0038] Referring to Figure 6 The upper electrode 80 can be formed on the dielectric layer 70 to complete the fabrication of the capacitor structure 90 including the lower electrode 55, the seed layer 65, the dielectric layer 70, and the upper electrode 80 sequentially stacked on the substrate 10. The second insulating interlayer 95 can be formed to cover the capacitor structure 90.

[0039] The upper electrode 80 can be formed of, for example, doped polysilicon and / or metal, and the second insulating interlayer 95 can be formed of, for example, an oxide of silicon oxide.

[0040] As described above, the capacitor structure 90 can include the lower electrode 55, the seed layer 65, the dielectric layer 70, and the upper electrode 80 sequentially stacked on the substrate 10, and the lower electrode 55 and the seed layer 65 can be formed by sequentially forming the preliminary lower electrode structure 50 and the cap layer 60 and performing an annealing process on the cap layer 60 and the preliminary lower electrode structure 50. The preliminary lower electrode structure 50 can be covered by the cap layer 60, the preliminary lower electrode structure 50 can not be volatilized by the annealing process, and the lower electrode 55 can be more efficiently formed.

[0041] The preliminary lower electrode structure 50 can include the first oxide pattern 43, the preliminary lower electrode 45, and the second oxide pattern 47 sequentially stacked. The first oxide pattern 43 and the second oxide pattern 47 can provide oxygen (O) to the preliminary lower electrode 45 when an annealing process is performed, and the preliminary lower electrode 45 can provide (Ru), molybdenum (Mo), cobalt (Co), or iridium (Ir) to each of the first oxide pattern 43 and the second oxide pattern 47, and thus the preliminary lower electrode 45 and the first oxide pattern 43 and the second oxide pattern 47 can effectively react to form a lower electrode 55 including a ternary metal oxide. For example, different oxygen concentrations at different portions of the lower electrode 55 can be a result of the annealing process.

[0042] In an embodiment, the first oxide pattern 43 and the second oxide pattern 47 can provide strontium (Sr), barium (Ba), or calcium (Ca) to the cap layer 60, and the cap layer 60 can react to form a seed layer 65 including another ternary metal oxide. Thus, the dielectric layer 70 can be formed on the seed layer 65 including substantially the same material (e.g., including the same elements), and thus the dielectric layer 70 can be more effectively formed than if the dielectric layer 70 were to be formed on a layer including a different material (e.g., including different elements) therefrom.

[0043] In an embodiment, the seed layer 65 and the dielectric layer 70 can include substantially the same ternary metal oxide (e.g., can include the same elements), and the lower electrode 55 can include a different ternary metal oxide (e.g., can include at least one different element) than the seed layer 65 and the dielectric layer 70. In an embodiment, the ternary metal oxide included in the seed layer 65 can have a smaller oxygen concentration than an oxygen concentration of the ternary metal oxide included in the dielectric layer 70.

[0044] Figures 7 to 24 are plan views and sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment. Figure 7 、 Figure 9 、 Figure 17 and Figure 23 are plan views, Figure 8 、 Figures 10 to 16 、 Figures 18 to 22 and Figure 24 are sectional views. Figure 8 、 Figures 10 to 16 、 Figures 18 to 22 and Figure 24 each include a sectional view taken along line A-A' and line B-B' of the corresponding plan view, respectively.

[0045] The method includes substantially the same or similar processes as those described with reference to Figures 1 to 6 , and thus a repeated description thereof can be omitted here.

[0046] Referring to Figure 7 and Figure 8 The active pattern 105 can be formed on the substrate 100, and the isolation pattern 110 can be formed to cover sidewalls of the active pattern 105.

[0047] The substrate 100 can include silicon, germanium, silicon-germanium, or a group III-V compound such as GaP, GaAs, GaSb, etc. In an embodiment, the substrate 100 can be an SOI substrate or a GOI substrate.

[0048] In an embodiment, a plurality of active patterns 105 can be formed to be spaced apart from each other in each of a first direction and a second direction parallel to the upper surface of the substrate 100 and orthogonal to each other, and each of the active patterns 105 can extend along a third direction that is parallel to the upper surface of the substrate 100 and that is acute to the first direction and the second direction.

[0049] The active pattern 105 can be formed by removing an upper portion of the substrate 100 to form a first recess, and the isolation pattern 110 can be formed by forming an isolation layer on the substrate 100 to fill the first recess and planarizing the isolation layer until an upper surface of the active pattern 105 is exposed. In an embodiment, the planarization process can include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0050] An impurity region can be formed at the upper portion of the substrate 100 by, for example, an ion implantation process, and the active pattern 105 and the isolation pattern 110 can be partially etched to form a second recess extending in the first direction.

[0051] Referring to Figure 9 and Figure 10 A gate structure 160 can be formed in the second recess, and an insulating layer structure 200, a first conductive layer 210, and a first etching mask 220 can be sequentially formed on the active pattern 105, the isolation pattern 110, and the gate structure 160.

[0052] The first conductive layer 210 and the insulating layer structure 200 can be etched using the first etching mask 220 to form a first opening 230 exposing an upper surface of the active pattern 105.

[0053] The gate structure 160 can be formed to include a gate insulating layer 130 on the active pattern 105 exposed by the second recess, a gate electrode 140 on the gate insulating layer 130 that can fill a lower portion of the second recess, and a gate mask 150 on the gate electrode 140 that can fill an upper portion of the second recess. The gate structure 160 can extend along the first direction, and a plurality of gate structures 160 can be formed to be spaced apart from each other along the second direction.

[0054] In an embodiment, the gate insulating layer 130 can be formed on the active pattern 105 exposed by the second recess by a thermal oxidation process, and can be formed to include an oxide, for example, silicon oxide.

[0055] The gate electrode 140 can be formed by forming a gate electrode layer on the gate insulating layer 130 and the isolation pattern 110 to fill the second recess and removing an upper portion of the gate electrode layer by a CMP process and / or an etch-back process. Accordingly, the gate electrode 140 can be formed in a lower portion of the second recess. The gate electrode layer can be formed of, for example, a metal such as tungsten (W), titanium (Ti), or tantalum (Ta) or a metal nitride such as tungsten nitride, titanium nitride, or tantalum nitride.

[0056] The gate mask 150 can be formed by forming a gate mask layer on the gate electrode 140, the gate insulating layer 130, and the isolation pattern 110 to fill a remaining portion of the second recess and planarize an upper portion of the gate mask layer until an upper surface of the isolation pattern 110 is exposed. Accordingly, the gate mask 150 can be formed in an upper portion of the second recess. The gate mask layer can be formed to include a nitride, for example, silicon nitride.

[0057] In an embodiment, the insulating layer structure 200 can include first to third insulating layers 170, 180, and 190 which are sequentially stacked. The first insulating layer 170 can be formed of, for example, an oxide such as silicon oxide, the second insulating layer 180 can be formed of, for example, a nitride such as silicon nitride, and the third insulating layer 190 can be formed of, for example, an oxide such as silicon oxide.

[0058] The first conductive layer 210 can be formed to include, for example, polysilicon doped with an impurity, and the first etching mask 220 can be formed to include, for example, a nitride such as silicon nitride.

[0059] During the etching process, an upper portion of the active pattern 105 exposed by the first opening 230 and an upper portion of the isolation pattern 110 adjacent to the upper portion of the active pattern 105, as well as an upper portion of the gate mask 150, can be etched to form a third recess 230. In an embodiment, a bottom of the first opening 230 can also be referred to as the third recess 230.

[0060] In an embodiment, the first opening 230 can expose an upper surface of a central portion of each active pattern 105 extending in a third direction, and a plurality of first openings 230 can be formed in each of the first direction and the second direction.

[0061] The second conductive layer 240 can be formed to fill the first opening 230.

[0062] In an embodiment, the second conductive layer 240 can be formed by forming a preliminary second conductive layer to fill the first openings 230 on the active pattern 105, the isolation pattern 110, the gate mask 150, and the first etching mask 220, and removing an upper portion of the preliminary second conductive layer by a CMP process and / or an etch-back process. Accordingly, the second conductive layer 240 can be formed to have an upper surface that is substantially coplanar with an upper surface of the first conductive layer 210.

[0063] In an embodiment, the plurality of second conductive layers 240 can be formed to be spaced apart from each other in each of the first direction and the second direction. The second conductive layer 240 can be formed to include, for example, polysilicon doped with impurities. In an embodiment, the second conductive layer 240 can be merged with the first conductive layer 210.

[0064] Referring to Figure 11 After the first etching mask 220 is removed, a third conductive layer 250, a barrier layer 270, a first metal layer 280, and a first cap layer 290 can be sequentially formed on the first conductive layer 210 and the second conductive layer 240.

[0065] In an embodiment, the third conductive layer 250 can be formed to include substantially the same material as that of the first conductive layer 210 and the second conductive layer 240. That is, the third conductive layer 250 can be formed to include polysilicon doped with impurities, and in some embodiments, the third conductive layer 250 can be merged with the first conductive layer 210 and the second conductive layer 240.

[0066] The barrier layer 270 can be formed to include, for example, a metal such as titanium (Ti), tantalum (Ta), or the like, and / or a metal nitride such as titanium nitride, tantalum nitride, or the like. The first metal layer 280 can be formed to include, for example, a metal such as tungsten (W). The first cap layer 290 can be formed to include, for example, a nitride such as silicon nitride.

[0067] Referring to Figure 12 The first cap layer 290 can be etched to form a first cap pattern 295, and the first metal layer 280, the barrier layer 270, the third conductive layer 250, and the first conductive layer 210 and the second conductive layer 240 can be sequentially etched using the first cap pattern 295 as an etching mask. During the etching process, the third insulating layer 190 at the uppermost level of the insulating layer structure 200 can also be etched.

[0068] Accordingly, the second conductive pattern 245, the third conductive pattern 255, the barrier pattern 275, the first metal pattern 285, and the first cap pattern 295 can be sequentially stacked on the active pattern 105, the isolation pattern 110, and the gate mask 150 in the first opening 230, and the third insulating pattern 195, the first conductive pattern 215, the third conductive pattern 255, the barrier pattern 275, the first metal pattern 285, and the first cap pattern 295 can be sequentially stacked on the second insulating layer 180 of the insulating layer structure 200 at the outside of the first opening 230.

[0069] In an embodiment, the first to third conductive layers 210, 240, and 250 can be merged with each other, and the second conductive pattern 245 and the third conductive pattern 255 sequentially stacked can form a conductive pattern structure 265, and the first conductive pattern 215 and the third conductive pattern 255 sequentially stacked can also form the conductive pattern structure 265. Hereinafter, the conductive pattern structure 265, the barrier pattern 275, the first metal pattern 285, and the first cap pattern 295 sequentially stacked can be referred to as a bit line structure 305.

[0070] In an embodiment, the bit line structure 305 can extend in the second direction, and a plurality of bit line structures 305 can be formed in the first direction.

[0071] Referring to Figure 13 The first spacer layer 310 can be formed on the upper surfaces of the active pattern 105, the isolation pattern 110, and the gate mask 150 exposed by the first opening 230, the sidewalls of the first opening 230, and the upper surface of the second insulating layer 180 to cover the bit line structure 305, and the fourth and fifth insulating layers can be sequentially formed on the first spacer layer 310.

[0072] The first spacer layer 310 can also cover the sidewalls of the third insulating pattern 195 under the portions of the bit line structure 305 on the second insulating layer 180. The first spacer layer 310 can be formed to include, for example, a nitride such as silicon nitride.

[0073] The fourth insulating layer can be formed to include, for example, an oxide such as silicon oxide. The fifth insulating layer can be formed to include, for example, a nitride such as silicon nitride. The fifth insulating layer can be formed to fill the entire portion of the first opening 230.

[0074] The fourth and fifth insulating layers can be etched by an etching process. In an embodiment, the etching process can be performed by a wet etching process, and all remaining portions of the fourth and fifth insulating layers except for portions thereof in the first openings 230 can be removed. Accordingly, almost the entire surface of the first spacer layer 310 (e.g., the entire portion of the first spacer layer 310 except for the portions thereof in the first openings 230) can be exposed. The portions of the fourth and fifth insulating layers remaining in the first openings 230 can form fourth and fifth insulating patterns 320 and 330, respectively.

[0075] Referring to Figure 14 A second spacer layer can be formed on the exposed surface of the first spacer layer 310 and the fourth and fifth insulating patterns 320 and 330 located in the first openings 230, and the second spacer layer can be anisotropically etched to form second spacers 340 covering the sidewalls of the bit line structure 305 on the surface of the first spacer layer 310 and the fourth and fifth insulating patterns 320 and 330.

[0076] The second spacers 340 can be formed to include an oxide such as silicon oxide, for example.

[0077] A second opening 350 can be formed to expose the upper surface of the active pattern 105 by a dry etching process using the first cap pattern 295 and the second spacers 340 as etching masks, and the upper surfaces of the isolation pattern 110 and the gate mask 150 can also be exposed by the second opening 350.

[0078] By the dry etching process, portions of the first spacer layer 310 located on the upper surface of the first cap pattern 295 and the upper surface of the second insulating layer 180 can be removed to form first spacers 315 covering the sidewalls of the bit line structure 305. During the dry etching process, the first and second insulating layers 170 and 180 can also be partially removed to remain as first and second insulating patterns 175 and 185, respectively. The first through third insulating patterns 175, 185, and 195 sequentially stacked under the bit line structure 305 can form an insulating pattern structure.

[0079] Referring to Figure 15 A third spacer layer can be formed on the upper surface of the first cap pattern 295, the upper surface of the first spacers 315, the outer sidewalls of the second spacers 340, a portion of the upper surface of the fourth insulating pattern 320, a portion of the upper surface of the fifth insulating pattern 330, and the upper surfaces of the active pattern 105, the isolation pattern 110, and the gate mask 150 exposed by the second opening 350, and the third spacer layer can be anisotropically etched to form third spacers 375 covering the sidewalls of the bit line structure 305.

[0080] The first to third spacers 315, 340, and 375 stacked in sequence on the sidewalls of the bit line structure 305 along a horizontal direction parallel to the upper surface of the substrate 100 can be referred to as a preliminary spacer structure.

[0081] The upper portion of the active pattern 105 can be etched by an additional etching process to form a fourth recess 390 connected with the second opening 350.

[0082] In an embodiment, the etching process can be performed by a wet etching process. In the wet etching process, an upper portion of the isolation pattern 110 adjacent to the upper portion of the active pattern 105 can also be etched, and the third spacer 375, the first cap pattern 295, and the gate mask 150 including a material (e.g., nitride) having etching selectivity with respect to the active pattern 105 and the isolation pattern 110 can be hardly etched.

[0083] Referring to Figure 16 The lower contact plug layer 400 can be formed to a sufficient height to fill the second opening 350 and the fourth recess 390, and the lower contact plug layer 400 can be planarized until the upper surface of the first cap pattern 295 is exposed.

[0084] In an embodiment, the lower contact plug layer 400 can extend in the second direction, and a plurality of lower contact plug layers 400 can be formed to be spaced apart from each other along the first direction through the bit line structure 305.

[0085] Referring to Figure 17 and Figure 18 A fourth mask including a plurality of third openings spaced apart from each other in the second direction, each of which can extend in the first direction, can be formed on the first cap pattern 295 and the lower contact plug layer 400, and the lower contact plug layer 400 can be etched by an etching process using the fourth mask as an etching mask.

[0086] In an embodiment, each of the third openings can be superposed with the gate structure 160 in a vertical direction perpendicular to the upper surface of the substrate 100. When the etching process is performed, a fourth opening exposing the upper surface of the gate mask 150 of the gate structure 160 between the bit line structures 305 can be formed, and after the fourth mask is removed, a second cap pattern 410 can be formed to fill the fourth opening. In an example embodiment, the second cap pattern 410 can extend in the first direction between the bit line structures 305, and a plurality of second cap patterns 410 can be formed along the second direction.

[0087] Accordingly, the lower contact plug layer 400 extending in the second direction between the bit line structures 305 can be transformed into a plurality of lower contact plugs 405 spaced apart from each other along the second direction by the second cap pattern 410.

[0088] Referring to Figure 19 An upper portion of the lower contact plug 405 can be removed to expose an upper portion of the preliminary spacer structure on sidewalls of the bit line structure 305, and an upper portion of the second spacer 340 and an upper portion of the third spacer 375 of the exposed preliminary spacer structure can be removed. The upper portion of the lower contact plug 405 can be further removed.

[0089] In an embodiment, an upper surface of the lower contact plug 405 can be lower than uppermost surfaces of the second spacer 340 and the third spacer 375.

[0090] Referring to Figure 20 A fourth spacer layer can be formed on the bit line structure 305, the preliminary spacer structure, the second cap pattern 410, and the lower contact plug 405, and the fourth spacer layer can be anisotropically etched to form a fourth spacer 425 covering the first to third spacers 315, 340, and 375 on each of opposite sidewalls of the bit line structure 305 in the first direction, and thus an upper surface of the lower contact plug 405 can be exposed.

[0091] A metal silicide pattern 435 can be formed on the exposed upper surface of the lower contact plug 405. In an example embodiment, the metal silicide pattern 435 can be formed by forming a second metal layer on the first cap pattern 295 and the second cap pattern 410, the fourth spacer 425, and the lower contact plug 405, performing a heat treatment on the second metal layer, and removing unreacted portions of the second metal layer.

[0092] Referring to Figure 21 An upper contact plug layer 450 can be formed on the first cap pattern 295 and the second cap pattern 410, the first to fourth spacers 315, 340, 375, and 425, the metal silicide pattern 435, and the lower contact plug 405, and an upper portion of the upper contact plug layer 450 can be planarized.

[0093] In an example embodiment, an upper surface of the upper contact plug layer 450 can be higher than upper surfaces of the first cap pattern 295 and the second cap pattern 410.

[0094] Referring to Figure 22 The upper contact plug layer 450 can be patterned to form a fifth recess, and a first inter-insulating layer structure including a sixth insulating layer 480 and a seventh insulating layer 490 sequentially stacked can be formed in the fifth recess. The first inter-insulating layer structure can also be formed on the second cap pattern 410.

[0095] The fifth recess can be formed by removing upper portions of the upper contact plug layer 450, the upper portion of the first cap pattern 295, and upper portions of the first spacer 315, the third spacer 375, and the fourth spacer 425. Accordingly, an upper surface of the second spacer 340 can be exposed.

[0096] When the fifth recess is formed, the upper contact plug layer 450 can be transformed into an upper contact plug 455. In an embodiment, a plurality of upper contact plugs 455 can be formed to be spaced apart from each other in each of the first direction and the second direction, and can be arranged in a honeycomb shape in a plan view. Each of the upper contact plugs 455 can have a circular, elliptical, or polygonal shape in a plan view.

[0097] The sequentially stacked lower contact plug 405, the metal silicide pattern 435, and the upper contact plug 455 can form a contact plug structure.

[0098] The exposed second spacer 340 can be removed to form an air gap 345 connected with the fifth recess. The second spacer 340 can be removed, for example, by a wet etching process.

[0099] The sixth insulating layer 480 can be formed using a material having a low gap filling property, such that the air gap 345 under the fifth recess can not be filled but remain. The air gap 345 can also be referred to as an air spacer 345, and can form a spacer structure together with the first spacer 315, the third spacer 375, and the fourth spacer 425. In an embodiment, the air gap 345 can be a spacer including air.

[0100] Referring to Figure 23 and Figure 24 A process substantially the same as or similar to the process shown in Figures 1 to 6 can be performed to complete the manufacturing of the semiconductor device.

[0101] In an embodiment, a preliminary lower electrode structure including sequentially stacked first oxide patterns, a preliminary lower electrode, and second oxide patterns can be formed on the upper contact plug 455, as well as the sixth insulating layer 480 and the seventh insulating layer 490, a cap layer can be conformally formed on the preliminary lower electrode structure, and an annealing process can be performed on the cap layer and the preliminary lower electrode structure to form a sequentially stacked lower electrode 500 and a seed layer 510.

[0102] A dielectric layer 520 and an upper electrode 530 can be sequentially formed on the seed layer 510 to form a capacitor structure 540 including the lower electrode 500, the seed layer 510, the dielectric layer 520, and the upper electrode 530. A second insulating interlayer 550 can be formed to cover the capacitor structure 540, such that the manufacturing of the semiconductor device can be completed.

[0103] By summarizing and reviewing, in order to help improve the electrical characteristics of the capacitor structure, an annealing process can be performed on the lower electrode layer including different types of metal oxides, so that the lower electrode can be formed to include a ternary metal oxide from the lower electrode layer. The lower electrode layer can be evaporated due to the annealing process, so that the lower electrode can be formed inappropriately.

[0104] One or more embodiments can provide a capacitor structure having improved electrical characteristics.

[0105] One or more embodiments can provide a semiconductor device having improved electrical characteristics.

[0106] In a manufacturing process of a capacitor structure according to an example embodiment, the capacitor structure can be formed to include a lower electrode, a seed layer, a dielectric layer, and an upper electrode sequentially stacked on a substrate. The lower electrode can be formed by sequentially forming a preliminary lower electrode structure and a cap layer, and performing an annealing process on the cap layer and the preliminary lower electrode structure. The preliminary lower electrode structure can be covered by the cap layer, the preliminary lower electrode structure can not be evaporated due to the annealing process, and the lower electrode can be more effectively formed.

[0107] Example embodiments have been disclosed herein and, although a specific terminology is employed, it is understood that the use of such terminology is merely for the purpose of general and descriptive reference and is not intended to limit the spirit and scope of the present application. In some instances, characteristics, features and / or elements described in connection with a specific example embodiment can be used singularly or in combination with features, characteristics and / or elements described in connection with other example embodiments, unless specifically stated otherwise, as would be apparent to one of ordinary skill in the art from this disclosure, as filed. It will be understood by those within the art that, in light of the preceding disclosure, various changes can be made in form and detail without departing from the spirit and scope of the application, as set forth in the appended claims.

Claims

1. A capacitor structure, the capacitor structure comprising: a lower electrode on a substrate; a seed layer on the lower electrode; a dielectric layer on the seed layer; and an upper electrode on the dielectric layer, wherein: the dielectric layer comprises SrTiO 3, BaTiO 3, or CaTiO 3, and the lower electrode comprises a ternary metal oxide. The seed layer comprises SrTiO 3-x , BaTiO 3-x or CaTiO 3-x where 0 < x < 3 and x is a real number such that when the dielectric layer comprises SrTiO3, the seed layer comprises SrTiO 3-x , when the dielectric layer comprises BaTiO3, the seed layer comprises BaTiO 3-x , and when the dielectric layer comprises CaTiO3, the seed layer comprises CaTiO 3-x , and SrTiO3, BaTiO3, or CaTiO3of the dielectric layer directly contacts the SrTiO 3-x , BaTiO 3-x , or CaTiO 3-x of the seed layer.

2. The capacitor structure of claim 1, wherein, the lower electrode comprises:

3. The capacitor structure of claim 2, wherein, one of Ru, Mo, Co, and Ir; and O； one of Sr, Ba, and Ca. the lower electrode comprises SrRuO 3, SrMoO 3, SrCoO 3, SrIrO 3, BaRuO 3, BaMoO 3, BaCoO 3, BaIrO 3, CaRuO 3, CaMoO 3, CaCoO 3, or CaIrO 3.

4. The capacitor structure of claim 3, wherein, an oxygen concentration at a portion of the seed layer closer to the lower electrode is less than an oxygen concentration at a portion of the seed layer farther from the lower electrode.

5. The capacitor structure according to any one of claims 1 to 4, wherein, an oxygen concentration at a central portion of the lower electrode is greater than an oxygen concentration at a portion of the lower electrode farther from the substrate, and greater than an oxygen concentration at a portion of the lower electrode closer to the substrate.

6. The capacitor structure of any one of claims 1 to 4, wherein, 7.A capacitor structure, the capacitor structure comprising: a lower electrode on a substrate; a seed layer on the lower electrode; a dielectric layer on the seed layer; and an upper electrode on the dielectric layer, wherein: the dielectric layer comprises SrTiO 3, BaTiO 3, or CaTiO 3, the dielectric layer has a perovskite structure. the seed layer does not have a perovskite structure. The seed layer comprises SrTiO 3-x , BaTiO 3-x , or CaTiO 3-x , where 0 < x < 3 and x is a real number such that when the dielectric layer comprises SrTiO3, the seed layer comprises SrTiO 3-x , when the dielectric layer comprises BaTiO3, the seed layer comprises BaTiO 3-x , and when the dielectric layer comprises CaTiO3, the seed layer comprises CaTiO 3-x , SrTiO3, BaTiO3or CaTiO3of the dielectric layer directly contacts the SrTiO 3-x , BaTiO 3-x or CaTiO 3-x of the seed layer, and the lower electrode comprises SrRuO 3, SrMoO 3, SrCoO 3, SrIrO 3, BaRuO 3, BaMoO 3, BaCoO 3, BaIrO 3, CaRuO 3, CaMoO 3, CaCoO 3, or CaIrO 3.

8. The capacitor structure of claim 7, wherein, an oxygen concentration at a central portion of the lower electrode is greater than an oxygen concentration at a portion of the lower electrode farther from the substrate, and greater than an oxygen concentration at a portion of the lower electrode closer to the substrate.

9. The capacitor structure of claim 7, wherein, an oxygen concentration at a portion of the lower electrode closer to the substrate is less than an oxygen concentration at a portion of the lower electrode farther from the substrate.

10. The capacitor structure according to any one of claims 7 to 9, wherein, 12.A semiconductor device, the semiconductor device comprising:

11. The capacitor structure of any one of claims 7-9, wherein, gate structures each extending in a first direction parallel to an upper surface of a substrate at an upper portion of the substrate, the gate structures being spaced apart from each other along a second direction parallel to the upper surface of the substrate and intersecting the first direction; bit line structures each extending on the gate structures in the second direction, the bit line structures being spaced apart from each other along the first direction; a contact plug structure adjacent to the bit line structures, the contact plug structure comprising a lower contact plug, a metal silicide pattern, and an upper contact plug stacked in sequence along a vertical direction perpendicular to the upper surface of the substrate; and a capacitor structure contacting an upper surface of the contact plug structure, wherein: the capacitor structure comprises a lower electrode, a seed layer, a dielectric layer, and an upper electrode stacked in sequence, the dielectric layer comprises SrTiO 3, BaTiO 3, or CaTiO 3, and 13.The semiconductor device according to claim 12, wherein: the dielectric layer has a perovskite structure, and The seed layer comprises SrTiO 3-x , BaTiO 3-x , or CaTiO 3-x , where 0 < x < 3 and x is a real number such that when the dielectric layer comprises SrTiO3, the seed layer comprises SrTiO 3-x , when the dielectric layer comprises BaTiO3, the seed layer comprises BaTiO 3-x , and when the dielectric layer comprises CaTiO3, the seed layer comprises CaTiO 3-x , SrTiO3, BaTiO3, or CaTiO3of the dielectric layer directly contacts the SrTiO 3-x , BaTiO 3-x , or CaTiO 3-x of the seed layer. the seed layer does not have a perovskite structure. an oxygen concentration at a portion of the seed layer closer to the lower electrode is less than an oxygen concentration at a portion of the seed layer farther from the lower electrode. ​ 14. The semiconductor device according to any one of Claims 12 to 13, wherein ​ 15. The semiconductor device according to any one of Claims 12 to 13, wherein The lower electrode includes SrRuO3, SrMoO3, SrCoO3, SrIrO3, BaRuO3, BaMoO3, BaCoO3, BaIrO3, CaRuO3, CaMoO3, CaCoO3, or CaIrO3.

16. The semiconductor device according to any one of Claims 12 to 13, wherein The oxygen concentration at the central portion of the lower electrode is greater than the oxygen concentration at the portion of the lower electrode distal from the substrate, and greater than the oxygen concentration at the portion of the lower electrode proximal to the substrate.

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